1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 5 */ 6 7#include <linux/kernel.h> 8#include <linux/irq.h> 9 10#include "mt76x02.h" 11#include "mt76x02_mcu.h" 12#include "trace.h" 13 14static void mt76x02_pre_tbtt_tasklet(unsigned long arg) 15{ 16 struct mt76x02_dev *dev = (struct mt76x02_dev *)arg; 17 struct mt76_queue *q = dev->mt76.q_tx[MT_TXQ_PSD]; 18 struct beacon_bc_data data = {}; 19 struct sk_buff *skb; 20 int i; 21 22 if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL) 23 return; 24 25 mt76x02_resync_beacon_timer(dev); 26 27 /* Prevent corrupt transmissions during update */ 28 mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff); 29 dev->beacon_data_count = 0; 30 31 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 32 IEEE80211_IFACE_ITER_RESUME_ALL, 33 mt76x02_update_beacon_iter, dev); 34 35 mt76_wr(dev, MT_BCN_BYPASS_MASK, 36 0xff00 | ~(0xff00 >> dev->beacon_data_count)); 37 38 mt76_csa_check(&dev->mt76); 39 40 if (dev->mt76.csa_complete) 41 return; 42 43 mt76x02_enqueue_buffered_bc(dev, &data, 8); 44 45 if (!skb_queue_len(&data.q)) 46 return; 47 48 for (i = 0; i < ARRAY_SIZE(data.tail); i++) { 49 if (!data.tail[i]) 50 continue; 51 52 mt76_skb_set_moredata(data.tail[i], false); 53 } 54 55 spin_lock_bh(&q->lock); 56 while ((skb = __skb_dequeue(&data.q)) != NULL) { 57 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 58 struct ieee80211_vif *vif = info->control.vif; 59 struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv; 60 61 mt76_tx_queue_skb(dev, MT_TXQ_PSD, skb, &mvif->group_wcid, 62 NULL); 63 } 64 spin_unlock_bh(&q->lock); 65} 66 67static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en) 68{ 69 if (en) 70 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 71 else 72 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 73} 74 75static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en) 76{ 77 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); 78 if (en) 79 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 80 else 81 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 82} 83 84void mt76x02e_init_beacon_config(struct mt76x02_dev *dev) 85{ 86 static const struct mt76x02_beacon_ops beacon_ops = { 87 .nslots = 8, 88 .slot_size = 1024, 89 .pre_tbtt_enable = mt76x02e_pre_tbtt_enable, 90 .beacon_enable = mt76x02e_beacon_enable, 91 }; 92 93 dev->beacon_ops = &beacon_ops; 94 95 /* Fire a pre-TBTT interrupt 8 ms before TBTT */ 96 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT, 97 8 << 4); 98 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER, 99 MT_DFS_GP_INTERVAL); 100 mt76_wr(dev, MT_INT_TIMER_EN, 0); 101 102 mt76x02_init_beacon_config(dev); 103} 104EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config); 105 106static int 107mt76x02_init_tx_queue(struct mt76x02_dev *dev, int qid, int idx, int n_desc) 108{ 109 struct mt76_queue *hwq; 110 int err; 111 112 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL); 113 if (!hwq) 114 return -ENOMEM; 115 116 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); 117 if (err < 0) 118 return err; 119 120 dev->mt76.q_tx[qid] = hwq; 121 122 mt76x02_irq_enable(dev, MT_INT_TX_DONE(idx)); 123 124 return 0; 125} 126 127static int 128mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q, 129 int idx, int n_desc, int bufsize) 130{ 131 int err; 132 133 err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize, 134 MT_RX_RING_BASE); 135 if (err < 0) 136 return err; 137 138 mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx)); 139 140 return 0; 141} 142 143static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev) 144{ 145 struct mt76x02_tx_status stat; 146 u8 update = 1; 147 148 while (kfifo_get(&dev->txstatus_fifo, &stat)) 149 mt76x02_send_tx_status(dev, &stat, &update); 150} 151 152static void mt76x02_tx_worker(struct mt76_worker *w) 153{ 154 struct mt76x02_dev *dev; 155 156 dev = container_of(w, struct mt76x02_dev, mt76.tx_worker); 157 158 mt76x02_mac_poll_tx_status(dev, false); 159 mt76x02_process_tx_status_fifo(dev); 160 161 mt76_txq_schedule_all(&dev->mphy); 162} 163 164static int mt76x02_poll_tx(struct napi_struct *napi, int budget) 165{ 166 struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev, 167 mt76.tx_napi); 168 int i; 169 170 mt76x02_mac_poll_tx_status(dev, false); 171 172 for (i = MT_TXQ_MCU; i >= 0; i--) 173 mt76_queue_tx_cleanup(dev, i, false); 174 175 if (napi_complete_done(napi, 0)) 176 mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL); 177 178 for (i = MT_TXQ_MCU; i >= 0; i--) 179 mt76_queue_tx_cleanup(dev, i, false); 180 181 mt76_worker_schedule(&dev->mt76.tx_worker); 182 183 return 0; 184} 185 186int mt76x02_dma_init(struct mt76x02_dev *dev) 187{ 188 struct mt76_txwi_cache __maybe_unused *t; 189 int i, ret, fifo_size; 190 struct mt76_queue *q; 191 void *status_fifo; 192 193 BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM); 194 195 fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status)); 196 status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL); 197 if (!status_fifo) 198 return -ENOMEM; 199 200 dev->mt76.tx_worker.fn = mt76x02_tx_worker; 201 tasklet_init(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet, 202 (unsigned long)dev); 203 204 spin_lock_init(&dev->txstatus_fifo_lock); 205 kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size); 206 207 mt76_dma_attach(&dev->mt76); 208 209 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 210 211 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 212 ret = mt76x02_init_tx_queue(dev, i, mt76_ac_to_hwq(i), 213 MT76x02_TX_RING_SIZE); 214 if (ret) 215 return ret; 216 } 217 218 ret = mt76x02_init_tx_queue(dev, MT_TXQ_PSD, 219 MT_TX_HW_QUEUE_MGMT, MT76x02_PSD_RING_SIZE); 220 if (ret) 221 return ret; 222 223 ret = mt76x02_init_tx_queue(dev, MT_TXQ_MCU, 224 MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE); 225 if (ret) 226 return ret; 227 228 ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 229 MT_MCU_RING_SIZE, MT_RX_BUF_SIZE); 230 if (ret) 231 return ret; 232 233 q = &dev->mt76.q_rx[MT_RXQ_MAIN]; 234 q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi); 235 ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE, 236 MT_RX_BUF_SIZE); 237 if (ret) 238 return ret; 239 240 ret = mt76_init_queues(dev); 241 if (ret) 242 return ret; 243 244 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 245 mt76x02_poll_tx, NAPI_POLL_WEIGHT); 246 napi_enable(&dev->mt76.tx_napi); 247 248 return 0; 249} 250EXPORT_SYMBOL_GPL(mt76x02_dma_init); 251 252void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 253{ 254 struct mt76x02_dev *dev; 255 256 dev = container_of(mdev, struct mt76x02_dev, mt76); 257 mt76x02_irq_enable(dev, MT_INT_RX_DONE(q)); 258} 259EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete); 260 261irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance) 262{ 263 struct mt76x02_dev *dev = dev_instance; 264 u32 intr, mask; 265 266 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 267 intr &= dev->mt76.mmio.irqmask; 268 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 269 270 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 271 return IRQ_NONE; 272 273 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 274 275 mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER); 276 if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT)) 277 mask |= MT_INT_TX_DONE_ALL; 278 279 mt76x02_irq_disable(dev, mask); 280 281 if (intr & MT_INT_RX_DONE(0)) 282 napi_schedule(&dev->mt76.napi[0]); 283 284 if (intr & MT_INT_RX_DONE(1)) 285 napi_schedule(&dev->mt76.napi[1]); 286 287 if (intr & MT_INT_PRE_TBTT) 288 tasklet_schedule(&dev->mt76.pre_tbtt_tasklet); 289 290 /* send buffered multicast frames now */ 291 if (intr & MT_INT_TBTT) { 292 if (dev->mt76.csa_complete) 293 mt76_csa_finish(&dev->mt76); 294 else 295 mt76_queue_kick(dev, dev->mt76.q_tx[MT_TXQ_PSD]); 296 } 297 298 if (intr & MT_INT_TX_STAT) 299 mt76x02_mac_poll_tx_status(dev, true); 300 301 if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL)) 302 napi_schedule(&dev->mt76.tx_napi); 303 304 if (intr & MT_INT_GPTIMER) 305 tasklet_schedule(&dev->dfs_pd.dfs_tasklet); 306 307 return IRQ_HANDLED; 308} 309EXPORT_SYMBOL_GPL(mt76x02_irq_handler); 310 311static void mt76x02_dma_enable(struct mt76x02_dev *dev) 312{ 313 u32 val; 314 315 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 316 mt76x02_wait_for_wpdma(&dev->mt76, 1000); 317 usleep_range(50, 100); 318 319 val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | 320 MT_WPDMA_GLO_CFG_TX_DMA_EN | 321 MT_WPDMA_GLO_CFG_RX_DMA_EN; 322 mt76_set(dev, MT_WPDMA_GLO_CFG, val); 323 mt76_clear(dev, MT_WPDMA_GLO_CFG, 324 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 325} 326 327void mt76x02_dma_disable(struct mt76x02_dev *dev) 328{ 329 u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); 330 331 val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE | 332 MT_WPDMA_GLO_CFG_BIG_ENDIAN | 333 MT_WPDMA_GLO_CFG_HDR_SEG_LEN; 334 val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE; 335 mt76_wr(dev, MT_WPDMA_GLO_CFG, val); 336} 337EXPORT_SYMBOL_GPL(mt76x02_dma_disable); 338 339void mt76x02_mac_start(struct mt76x02_dev *dev) 340{ 341 mt76x02_mac_reset_counters(dev); 342 mt76x02_dma_enable(dev); 343 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 344 mt76_wr(dev, MT_MAC_SYS_CTRL, 345 MT_MAC_SYS_CTRL_ENABLE_TX | 346 MT_MAC_SYS_CTRL_ENABLE_RX); 347 mt76x02_irq_enable(dev, 348 MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 349 MT_INT_TX_STAT); 350} 351EXPORT_SYMBOL_GPL(mt76x02_mac_start); 352 353static bool mt76x02_tx_hang(struct mt76x02_dev *dev) 354{ 355 u32 dma_idx, prev_dma_idx; 356 struct mt76_queue *q; 357 int i; 358 359 for (i = 0; i < 4; i++) { 360 q = dev->mt76.q_tx[i]; 361 362 if (!q->queued) 363 continue; 364 365 prev_dma_idx = dev->mt76.tx_dma_idx[i]; 366 dma_idx = readl(&q->regs->dma_idx); 367 dev->mt76.tx_dma_idx[i] = dma_idx; 368 369 if (prev_dma_idx == dma_idx) 370 break; 371 } 372 373 return i < 4; 374} 375 376static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 377 struct ieee80211_sta *sta, 378 struct ieee80211_key_conf *key, void *data) 379{ 380 struct mt76x02_dev *dev = hw->priv; 381 struct mt76_wcid *wcid; 382 383 if (!sta) 384 return; 385 386 wcid = (struct mt76_wcid *)sta->drv_priv; 387 388 if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv) 389 return; 390 391 mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key); 392} 393 394static void mt76x02_reset_state(struct mt76x02_dev *dev) 395{ 396 int i; 397 398 lockdep_assert_held(&dev->mt76.mutex); 399 400 clear_bit(MT76_STATE_RUNNING, &dev->mphy.state); 401 402 rcu_read_lock(); 403 ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL); 404 rcu_read_unlock(); 405 406 for (i = 0; i < MT76x02_N_WCIDS; i++) { 407 struct ieee80211_sta *sta; 408 struct ieee80211_vif *vif; 409 struct mt76x02_sta *msta; 410 struct mt76_wcid *wcid; 411 void *priv; 412 413 wcid = rcu_dereference_protected(dev->mt76.wcid[i], 414 lockdep_is_held(&dev->mt76.mutex)); 415 if (!wcid) 416 continue; 417 418 rcu_assign_pointer(dev->mt76.wcid[i], NULL); 419 420 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 421 sta = container_of(priv, struct ieee80211_sta, drv_priv); 422 423 priv = msta->vif; 424 vif = container_of(priv, struct ieee80211_vif, drv_priv); 425 426 __mt76_sta_remove(&dev->mt76, vif, sta); 427 memset(msta, 0, sizeof(*msta)); 428 } 429 430 dev->mphy.vif_mask = 0; 431 dev->mt76.beacon_mask = 0; 432} 433 434static void mt76x02_watchdog_reset(struct mt76x02_dev *dev) 435{ 436 u32 mask = dev->mt76.mmio.irqmask; 437 bool restart = dev->mt76.mcu_ops->mcu_restart; 438 int i; 439 440 ieee80211_stop_queues(dev->mt76.hw); 441 set_bit(MT76_RESET, &dev->mphy.state); 442 443 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 444 mt76_worker_disable(&dev->mt76.tx_worker); 445 napi_disable(&dev->mt76.tx_napi); 446 447 mt76_for_each_q_rx(&dev->mt76, i) { 448 napi_disable(&dev->mt76.napi[i]); 449 } 450 451 mutex_lock(&dev->mt76.mutex); 452 453 dev->mcu_timeout = 0; 454 if (restart) 455 mt76x02_reset_state(dev); 456 457 if (dev->mt76.beacon_mask) 458 mt76_clear(dev, MT_BEACON_TIME_CFG, 459 MT_BEACON_TIME_CFG_BEACON_TX | 460 MT_BEACON_TIME_CFG_TBTT_EN); 461 462 mt76x02_irq_disable(dev, mask); 463 464 /* perform device reset */ 465 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 466 mt76_wr(dev, MT_MAC_SYS_CTRL, 0); 467 mt76_clear(dev, MT_WPDMA_GLO_CFG, 468 MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN); 469 usleep_range(5000, 10000); 470 mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff); 471 472 /* let fw reset DMA */ 473 mt76_set(dev, 0x734, 0x3); 474 475 if (restart) 476 mt76_mcu_restart(dev); 477 478 for (i = 0; i < __MT_TXQ_MAX; i++) 479 mt76_queue_tx_cleanup(dev, i, true); 480 481 mt76_for_each_q_rx(&dev->mt76, i) { 482 mt76_queue_rx_reset(dev, i); 483 } 484 485 mt76x02_mac_start(dev); 486 487 if (dev->ed_monitor) 488 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 489 490 if (dev->mt76.beacon_mask && !restart) 491 mt76_set(dev, MT_BEACON_TIME_CFG, 492 MT_BEACON_TIME_CFG_BEACON_TX | 493 MT_BEACON_TIME_CFG_TBTT_EN); 494 495 mt76x02_irq_enable(dev, mask); 496 497 mutex_unlock(&dev->mt76.mutex); 498 499 clear_bit(MT76_RESET, &dev->mphy.state); 500 501 mt76_worker_enable(&dev->mt76.tx_worker); 502 napi_enable(&dev->mt76.tx_napi); 503 napi_schedule(&dev->mt76.tx_napi); 504 505 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 506 507 mt76_for_each_q_rx(&dev->mt76, i) { 508 napi_enable(&dev->mt76.napi[i]); 509 napi_schedule(&dev->mt76.napi[i]); 510 } 511 512 if (restart) { 513 set_bit(MT76_RESTART, &dev->mphy.state); 514 mt76x02_mcu_function_select(dev, Q_SELECT, 1); 515 ieee80211_restart_hw(dev->mt76.hw); 516 } else { 517 ieee80211_wake_queues(dev->mt76.hw); 518 mt76_txq_schedule_all(&dev->mphy); 519 } 520} 521 522void mt76x02_reconfig_complete(struct ieee80211_hw *hw, 523 enum ieee80211_reconfig_type reconfig_type) 524{ 525 struct mt76x02_dev *dev = hw->priv; 526 527 if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART) 528 return; 529 530 clear_bit(MT76_RESTART, &dev->mphy.state); 531} 532EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete); 533 534static void mt76x02_check_tx_hang(struct mt76x02_dev *dev) 535{ 536 if (test_bit(MT76_RESTART, &dev->mphy.state)) 537 return; 538 539 if (mt76x02_tx_hang(dev)) { 540 if (++dev->tx_hang_check >= MT_TX_HANG_TH) 541 goto restart; 542 } else { 543 dev->tx_hang_check = 0; 544 } 545 546 if (dev->mcu_timeout) 547 goto restart; 548 549 return; 550 551restart: 552 mt76x02_watchdog_reset(dev); 553 554 dev->tx_hang_reset++; 555 dev->tx_hang_check = 0; 556 memset(dev->mt76.tx_dma_idx, 0xff, 557 sizeof(dev->mt76.tx_dma_idx)); 558} 559 560void mt76x02_wdt_work(struct work_struct *work) 561{ 562 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 563 wdt_work.work); 564 565 mt76x02_check_tx_hang(dev); 566 567 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work, 568 MT_WATCHDOG_TIME); 569} 570