1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc.
3 *
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 */
6
7#ifndef __MT76S_H
8#define __MT76S_H
9
10#define MT_PSE_PAGE_SZ			128
11
12#define MCR_WCIR			0x0000
13#define MCR_WHLPCR			0x0004
14#define WHLPCR_FW_OWN_REQ_CLR		BIT(9)
15#define WHLPCR_FW_OWN_REQ_SET		BIT(8)
16#define WHLPCR_IS_DRIVER_OWN		BIT(8)
17#define WHLPCR_INT_EN_CLR		BIT(1)
18#define WHLPCR_INT_EN_SET		BIT(0)
19
20#define MCR_WSDIOCSR			0x0008
21#define MCR_WHCR			0x000C
22#define W_INT_CLR_CTRL			BIT(1)
23#define RECV_MAILBOX_RD_CLR_EN		BIT(2)
24#define MAX_HIF_RX_LEN_NUM		GENMASK(13, 8)
25#define RX_ENHANCE_MODE			BIT(16)
26
27#define MCR_WHISR			0x0010
28#define MCR_WHIER			0x0014
29#define WHIER_D2H_SW_INT		GENMASK(31, 8)
30#define WHIER_FW_OWN_BACK_INT_EN	BIT(7)
31#define WHIER_ABNORMAL_INT_EN		BIT(6)
32#define WHIER_RX1_DONE_INT_EN		BIT(2)
33#define WHIER_RX0_DONE_INT_EN		BIT(1)
34#define WHIER_TX_DONE_INT_EN		BIT(0)
35#define WHIER_DEFAULT			(WHIER_RX0_DONE_INT_EN	| \
36					 WHIER_RX1_DONE_INT_EN	| \
37					 WHIER_TX_DONE_INT_EN	| \
38					 WHIER_ABNORMAL_INT_EN	| \
39					 WHIER_D2H_SW_INT)
40
41#define MCR_WASR			0x0020
42#define MCR_WSICR			0x0024
43#define MCR_WTSR0			0x0028
44#define TQ0_CNT				GENMASK(7, 0)
45#define TQ1_CNT				GENMASK(15, 8)
46#define TQ2_CNT				GENMASK(23, 16)
47#define TQ3_CNT				GENMASK(31, 24)
48
49#define MCR_WTSR1			0x002c
50#define TQ4_CNT				GENMASK(7, 0)
51#define TQ5_CNT				GENMASK(15, 8)
52#define TQ6_CNT				GENMASK(23, 16)
53#define TQ7_CNT				GENMASK(31, 24)
54
55#define MCR_WTDR1			0x0034
56#define MCR_WRDR0			0x0050
57#define MCR_WRDR1			0x0054
58#define MCR_WRDR(p)			(0x0050 + 4 * (p))
59#define MCR_H2DSM0R			0x0070
60#define H2D_SW_INT_READ			BIT(16)
61#define H2D_SW_INT_WRITE		BIT(17)
62
63#define MCR_H2DSM1R			0x0074
64#define MCR_D2HRM0R			0x0078
65#define MCR_D2HRM1R			0x007c
66#define MCR_D2HRM2R			0x0080
67#define MCR_WRPLR			0x0090
68#define RX0_PACKET_LENGTH		GENMASK(15, 0)
69#define RX1_PACKET_LENGTH		GENMASK(31, 16)
70
71#define MCR_WTMDR			0x00b0
72#define MCR_WTMCR			0x00b4
73#define MCR_WTMDPCR0			0x00b8
74#define MCR_WTMDPCR1			0x00bc
75#define MCR_WPLRCR			0x00d4
76#define MCR_WSR				0x00D8
77#define MCR_CLKIOCR			0x0100
78#define MCR_CMDIOCR			0x0104
79#define MCR_DAT0IOCR			0x0108
80#define MCR_DAT1IOCR			0x010C
81#define MCR_DAT2IOCR			0x0110
82#define MCR_DAT3IOCR			0x0114
83#define MCR_CLKDLYCR			0x0118
84#define MCR_CMDDLYCR			0x011C
85#define MCR_ODATDLYCR			0x0120
86#define MCR_IDATDLYCR1			0x0124
87#define MCR_IDATDLYCR2			0x0128
88#define MCR_ILCHCR			0x012C
89#define MCR_WTQCR0			0x0130
90#define MCR_WTQCR1			0x0134
91#define MCR_WTQCR2			0x0138
92#define MCR_WTQCR3			0x013C
93#define MCR_WTQCR4			0x0140
94#define MCR_WTQCR5			0x0144
95#define MCR_WTQCR6			0x0148
96#define MCR_WTQCR7			0x014C
97#define MCR_WTQCR(x)                   (0x130 + 4 * (x))
98#define TXQ_CNT_L			GENMASK(15, 0)
99#define TXQ_CNT_H			GENMASK(31, 16)
100
101#define MCR_SWPCDBGR			0x0154
102
103struct mt76s_intr {
104	u32 isr;
105	struct {
106		u32 wtqcr[8];
107	} tx;
108	struct {
109		u16 num[2];
110		u16 len[2][16];
111	} rx;
112	u32 rec_mb[2];
113} __packed;
114
115#endif
116