1// SPDX-License-Identifier: ISC 2/* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Roy Luo <royluo@google.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8#include <linux/firmware.h> 9#include "mt7615.h" 10#include "mcu.h" 11#include "mac.h" 12#include "eeprom.h" 13 14static bool prefer_offload_fw = true; 15module_param(prefer_offload_fw, bool, 0644); 16MODULE_PARM_DESC(prefer_offload_fw, 17 "Prefer client mode offload firmware (MT7663)"); 18 19struct mt7615_patch_hdr { 20 char build_date[16]; 21 char platform[4]; 22 __be32 hw_sw_ver; 23 __be32 patch_ver; 24 __be16 checksum; 25} __packed; 26 27struct mt7615_fw_trailer { 28 __le32 addr; 29 u8 chip_id; 30 u8 feature_set; 31 u8 eco_code; 32 char fw_ver[10]; 33 char build_date[15]; 34 __le32 len; 35} __packed; 36 37#define FW_V3_COMMON_TAILER_SIZE 36 38#define FW_V3_REGION_TAILER_SIZE 40 39#define FW_START_OVERRIDE BIT(0) 40#define FW_START_DLYCAL BIT(1) 41#define FW_START_WORKING_PDA_CR4 BIT(2) 42 43struct mt7663_fw_trailer { 44 u8 chip_id; 45 u8 eco_code; 46 u8 n_region; 47 u8 format_ver; 48 u8 format_flag; 49 u8 reserv[2]; 50 char fw_ver[10]; 51 char build_date[15]; 52 __le32 crc; 53} __packed; 54 55struct mt7663_fw_buf { 56 __le32 crc; 57 __le32 d_img_size; 58 __le32 block_size; 59 u8 rsv[4]; 60 __le32 img_dest_addr; 61 __le32 img_size; 62 u8 feature_set; 63}; 64 65#define MT7615_PATCH_ADDRESS 0x80000 66#define MT7622_PATCH_ADDRESS 0x9c000 67#define MT7663_PATCH_ADDRESS 0xdc000 68 69#define N9_REGION_NUM 2 70#define CR4_REGION_NUM 1 71 72#define IMG_CRC_LEN 4 73 74#define FW_FEATURE_SET_ENCRYPT BIT(0) 75#define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 76 77#define DL_MODE_ENCRYPT BIT(0) 78#define DL_MODE_KEY_IDX GENMASK(2, 1) 79#define DL_MODE_RESET_SEC_IV BIT(3) 80#define DL_MODE_WORKING_PDA_CR4 BIT(4) 81#define DL_MODE_VALID_RAM_ENTRY BIT(5) 82#define DL_MODE_NEED_RSP BIT(31) 83 84#define FW_START_OVERRIDE BIT(0) 85#define FW_START_WORKING_PDA_CR4 BIT(2) 86 87void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb, 88 int cmd, int *wait_seq) 89{ 90 int txd_len, mcu_cmd = cmd & MCU_CMD_MASK; 91 struct mt7615_uni_txd *uni_txd; 92 struct mt7615_mcu_txd *mcu_txd; 93 u8 seq, q_idx, pkt_fmt; 94 __le32 *txd; 95 u32 val; 96 97 seq = ++dev->mt76.mcu.msg_seq & 0xf; 98 if (!seq) 99 seq = ++dev->mt76.mcu.msg_seq & 0xf; 100 if (wait_seq) 101 *wait_seq = seq; 102 103 txd_len = cmd & MCU_UNI_PREFIX ? sizeof(*uni_txd) : sizeof(*mcu_txd); 104 txd = (__le32 *)skb_push(skb, txd_len); 105 106 if (cmd != MCU_CMD_FW_SCATTER) { 107 q_idx = MT_TX_MCU_PORT_RX_Q0; 108 pkt_fmt = MT_TX_TYPE_CMD; 109 } else { 110 q_idx = MT_TX_MCU_PORT_RX_FWDL; 111 pkt_fmt = MT_TX_TYPE_FW; 112 } 113 114 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) | 115 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) | 116 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 117 txd[0] = cpu_to_le32(val); 118 119 val = MT_TXD1_LONG_FORMAT | 120 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) | 121 FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt); 122 txd[1] = cpu_to_le32(val); 123 124 if (cmd & MCU_UNI_PREFIX) { 125 uni_txd = (struct mt7615_uni_txd *)txd; 126 uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd)); 127 uni_txd->option = MCU_CMD_UNI_EXT_ACK; 128 uni_txd->cid = cpu_to_le16(mcu_cmd); 129 uni_txd->s2d_index = MCU_S2D_H2N; 130 uni_txd->pkt_type = MCU_PKT_ID; 131 uni_txd->seq = seq; 132 133 return; 134 } 135 136 mcu_txd = (struct mt7615_mcu_txd *)txd; 137 mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd)); 138 mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx)); 139 mcu_txd->s2d_index = MCU_S2D_H2N; 140 mcu_txd->pkt_type = MCU_PKT_ID; 141 mcu_txd->seq = seq; 142 143 switch (cmd & ~MCU_CMD_MASK) { 144 case MCU_FW_PREFIX: 145 mcu_txd->set_query = MCU_Q_NA; 146 mcu_txd->cid = mcu_cmd; 147 break; 148 case MCU_CE_PREFIX: 149 if (cmd & MCU_QUERY_MASK) 150 mcu_txd->set_query = MCU_Q_QUERY; 151 else 152 mcu_txd->set_query = MCU_Q_SET; 153 mcu_txd->cid = mcu_cmd; 154 break; 155 default: 156 mcu_txd->cid = MCU_CMD_EXT_CID; 157 if (cmd & MCU_QUERY_PREFIX) 158 mcu_txd->set_query = MCU_Q_QUERY; 159 else 160 mcu_txd->set_query = MCU_Q_SET; 161 mcu_txd->ext_cid = mcu_cmd; 162 mcu_txd->ext_cid_ack = 1; 163 break; 164 } 165} 166EXPORT_SYMBOL_GPL(mt7615_mcu_fill_msg); 167 168static int __mt7615_mcu_msg_send(struct mt7615_dev *dev, struct sk_buff *skb, 169 int cmd, int *wait_seq) 170{ 171 enum mt76_txq_id qid; 172 173 mt7615_mcu_fill_msg(dev, skb, cmd, wait_seq); 174 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state)) 175 qid = MT_TXQ_MCU; 176 else 177 qid = MT_TXQ_FWDL; 178 179 return mt76_tx_queue_skb_raw(dev, qid, skb, 0); 180} 181 182static int 183mt7615_mcu_parse_response(struct mt7615_dev *dev, int cmd, 184 struct sk_buff *skb, int seq) 185{ 186 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 187 int ret = 0; 188 189 if (seq != rxd->seq) { 190 ret = -EAGAIN; 191 goto out; 192 } 193 194 switch (cmd) { 195 case MCU_CMD_PATCH_SEM_CONTROL: 196 skb_pull(skb, sizeof(*rxd) - 4); 197 ret = *skb->data; 198 break; 199 case MCU_EXT_CMD_GET_TEMP: 200 skb_pull(skb, sizeof(*rxd)); 201 ret = le32_to_cpu(*(__le32 *)skb->data); 202 break; 203 case MCU_EXT_CMD_RF_REG_ACCESS | MCU_QUERY_PREFIX: 204 skb_pull(skb, sizeof(*rxd)); 205 ret = le32_to_cpu(*(__le32 *)&skb->data[8]); 206 break; 207 case MCU_UNI_CMD_DEV_INFO_UPDATE: 208 case MCU_UNI_CMD_BSS_INFO_UPDATE: 209 case MCU_UNI_CMD_STA_REC_UPDATE: 210 case MCU_UNI_CMD_HIF_CTRL: 211 case MCU_UNI_CMD_OFFLOAD: 212 case MCU_UNI_CMD_SUSPEND: { 213 struct mt7615_mcu_uni_event *event; 214 215 skb_pull(skb, sizeof(*rxd)); 216 event = (struct mt7615_mcu_uni_event *)skb->data; 217 ret = le32_to_cpu(event->status); 218 break; 219 } 220 case MCU_CMD_REG_READ: { 221 struct mt7615_mcu_reg_event *event; 222 223 skb_pull(skb, sizeof(*rxd)); 224 event = (struct mt7615_mcu_reg_event *)skb->data; 225 ret = (int)le32_to_cpu(event->val); 226 break; 227 } 228 default: 229 break; 230 } 231out: 232 dev_kfree_skb(skb); 233 234 return ret; 235} 236 237int mt7615_mcu_wait_response(struct mt7615_dev *dev, int cmd, int seq) 238{ 239 unsigned long expires = jiffies + 20 * HZ; 240 struct sk_buff *skb; 241 int ret = 0; 242 243 while (true) { 244 skb = mt76_mcu_get_response(&dev->mt76, expires); 245 if (!skb) { 246 dev_err(dev->mt76.dev, "Message %ld (seq %d) timeout\n", 247 cmd & MCU_CMD_MASK, seq); 248 return -ETIMEDOUT; 249 } 250 251 ret = mt7615_mcu_parse_response(dev, cmd, skb, seq); 252 if (ret != -EAGAIN) 253 break; 254 } 255 256 return ret; 257} 258EXPORT_SYMBOL_GPL(mt7615_mcu_wait_response); 259 260static int 261mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, 262 int cmd, bool wait_resp) 263{ 264 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 265 int ret, seq; 266 267 mutex_lock(&mdev->mcu.mutex); 268 269 ret = __mt7615_mcu_msg_send(dev, skb, cmd, &seq); 270 if (ret) 271 goto out; 272 273 if (wait_resp) 274 ret = mt7615_mcu_wait_response(dev, cmd, seq); 275 276out: 277 mutex_unlock(&mdev->mcu.mutex); 278 279 return ret; 280} 281 282int mt7615_mcu_msg_send(struct mt76_dev *mdev, int cmd, const void *data, 283 int len, bool wait_resp) 284{ 285 struct sk_buff *skb; 286 287 skb = mt76_mcu_msg_alloc(mdev, data, len); 288 if (!skb) 289 return -ENOMEM; 290 291 return __mt76_mcu_skb_send_msg(mdev, skb, cmd, wait_resp); 292} 293EXPORT_SYMBOL_GPL(mt7615_mcu_msg_send); 294 295u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg) 296{ 297 struct { 298 __le32 wifi_stream; 299 __le32 address; 300 __le32 data; 301 } req = { 302 .wifi_stream = cpu_to_le32(wf), 303 .address = cpu_to_le32(reg), 304 }; 305 306 return __mt76_mcu_send_msg(&dev->mt76, 307 MCU_EXT_CMD_RF_REG_ACCESS | MCU_QUERY_PREFIX, 308 &req, sizeof(req), true); 309} 310 311int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val) 312{ 313 struct { 314 __le32 wifi_stream; 315 __le32 address; 316 __le32 data; 317 } req = { 318 .wifi_stream = cpu_to_le32(wf), 319 .address = cpu_to_le32(reg), 320 .data = cpu_to_le32(val), 321 }; 322 323 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RF_REG_ACCESS, &req, 324 sizeof(req), false); 325} 326 327static void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en) 328{ 329 if (!is_mt7622(&dev->mt76)) 330 return; 331 332 regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC, 333 MT_INFRACFG_MISC_AP2CONN_WAKE, 334 !en * MT_INFRACFG_MISC_AP2CONN_WAKE); 335} 336 337static int mt7615_mcu_drv_pmctrl(struct mt7615_dev *dev) 338{ 339 struct mt76_phy *mphy = &dev->mt76.phy; 340 struct mt76_dev *mdev = &dev->mt76; 341 u32 addr; 342 int err; 343 344 if (is_mt7663(mdev)) { 345 /* Clear firmware own via N9 eint */ 346 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN); 347 mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); 348 349 addr = MT_CONN_HIF_ON_LPCTL; 350 } else { 351 addr = MT_CFG_LPCR_HOST; 352 } 353 354 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN); 355 356 mt7622_trigger_hif_int(dev, true); 357 358 err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); 359 360 mt7622_trigger_hif_int(dev, false); 361 362 if (err) { 363 dev_err(mdev->dev, "driver own failed\n"); 364 return -ETIMEDOUT; 365 } 366 367 clear_bit(MT76_STATE_PM, &mphy->state); 368 369 return 0; 370} 371 372static int mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev *dev) 373{ 374 struct mt76_phy *mphy = &dev->mt76.phy; 375 int i; 376 377 if (!test_and_clear_bit(MT76_STATE_PM, &mphy->state)) 378 goto out; 379 380 for (i = 0; i < MT7615_DRV_OWN_RETRY_COUNT; i++) { 381 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN); 382 if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL, 383 MT_CFG_LPCR_HOST_FW_OWN, 0, 50)) 384 break; 385 } 386 387 if (i == MT7615_DRV_OWN_RETRY_COUNT) { 388 dev_err(dev->mt76.dev, "driver own failed\n"); 389 set_bit(MT76_STATE_PM, &mphy->state); 390 return -EIO; 391 } 392 393out: 394 dev->pm.last_activity = jiffies; 395 396 return 0; 397} 398 399static int mt7615_mcu_fw_pmctrl(struct mt7615_dev *dev) 400{ 401 struct mt76_phy *mphy = &dev->mt76.phy; 402 int err = 0; 403 u32 addr; 404 405 if (test_and_set_bit(MT76_STATE_PM, &mphy->state)) 406 return 0; 407 408 mt7622_trigger_hif_int(dev, true); 409 410 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST; 411 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN); 412 413 if (is_mt7622(&dev->mt76) && 414 !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 415 MT_CFG_LPCR_HOST_FW_OWN, 3000)) { 416 dev_err(dev->mt76.dev, "Timeout for firmware own\n"); 417 clear_bit(MT76_STATE_PM, &mphy->state); 418 err = -EIO; 419 } 420 421 mt7622_trigger_hif_int(dev, false); 422 423 return err; 424} 425 426static void 427mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif) 428{ 429 if (vif->csa_active) 430 ieee80211_csa_finish(vif); 431} 432 433static void 434mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb) 435{ 436 struct mt76_phy *mphy = &dev->mt76.phy; 437 struct mt7615_mcu_rdd_report *r; 438 439 r = (struct mt7615_mcu_rdd_report *)skb->data; 440 441 if (r->idx && dev->mt76.phy2) 442 mphy = dev->mt76.phy2; 443 444 ieee80211_radar_detected(mphy->hw); 445 dev->hw_pattern++; 446} 447 448static void 449mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb) 450{ 451 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 452 const char *data = (char *)&rxd[1]; 453 const char *type; 454 455 switch (rxd->s2d_index) { 456 case 0: 457 type = "N9"; 458 break; 459 case 2: 460 type = "CR4"; 461 break; 462 default: 463 type = "unknown"; 464 break; 465 } 466 467 wiphy_info(mt76_hw(dev)->wiphy, "%s: %s", type, data); 468} 469 470static void 471mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb) 472{ 473 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 474 475 switch (rxd->ext_eid) { 476 case MCU_EXT_EVENT_RDD_REPORT: 477 mt7615_mcu_rx_radar_detected(dev, skb); 478 break; 479 case MCU_EXT_EVENT_CSA_NOTIFY: 480 ieee80211_iterate_active_interfaces_atomic(dev->mt76.hw, 481 IEEE80211_IFACE_ITER_RESUME_ALL, 482 mt7615_mcu_csa_finish, dev); 483 break; 484 case MCU_EXT_EVENT_FW_LOG_2_HOST: 485 mt7615_mcu_rx_log_message(dev, skb); 486 break; 487 default: 488 break; 489 } 490} 491 492static void 493mt7615_mcu_scan_event(struct mt7615_dev *dev, struct sk_buff *skb) 494{ 495 u8 *seq_num = skb->data + sizeof(struct mt7615_mcu_rxd); 496 struct mt7615_phy *phy; 497 struct mt76_phy *mphy; 498 499 if (*seq_num & BIT(7) && dev->mt76.phy2) 500 mphy = dev->mt76.phy2; 501 else 502 mphy = &dev->mt76.phy; 503 504 phy = (struct mt7615_phy *)mphy->priv; 505 506 spin_lock_bh(&dev->mt76.lock); 507 __skb_queue_tail(&phy->scan_event_list, skb); 508 spin_unlock_bh(&dev->mt76.lock); 509 510 ieee80211_queue_delayed_work(mphy->hw, &phy->scan_work, 511 MT7615_HW_SCAN_TIMEOUT); 512} 513 514static void 515mt7615_mcu_roc_event(struct mt7615_dev *dev, struct sk_buff *skb) 516{ 517 struct mt7615_roc_tlv *event; 518 struct mt7615_phy *phy; 519 struct mt76_phy *mphy; 520 int duration; 521 522 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 523 event = (struct mt7615_roc_tlv *)skb->data; 524 525 if (event->dbdc_band && dev->mt76.phy2) 526 mphy = dev->mt76.phy2; 527 else 528 mphy = &dev->mt76.phy; 529 530 ieee80211_ready_on_channel(mphy->hw); 531 532 phy = (struct mt7615_phy *)mphy->priv; 533 phy->roc_grant = true; 534 wake_up(&phy->roc_wait); 535 536 duration = le32_to_cpu(event->max_interval); 537 mod_timer(&phy->roc_timer, 538 round_jiffies_up(jiffies + msecs_to_jiffies(duration))); 539} 540 541static void 542mt7615_mcu_beacon_loss_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 543{ 544 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 545 struct mt7615_beacon_loss_event *event = priv; 546 547 if (mvif->idx != event->bss_idx) 548 return; 549 550 if (!(vif->driver_flags & IEEE80211_VIF_BEACON_FILTER)) 551 return; 552 553 ieee80211_beacon_loss(vif); 554} 555 556static void 557mt7615_mcu_beacon_loss_event(struct mt7615_dev *dev, struct sk_buff *skb) 558{ 559 struct mt7615_beacon_loss_event *event; 560 struct mt76_phy *mphy; 561 u8 band_idx = 0; /* DBDC support */ 562 563 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 564 event = (struct mt7615_beacon_loss_event *)skb->data; 565 if (band_idx && dev->mt76.phy2) 566 mphy = dev->mt76.phy2; 567 else 568 mphy = &dev->mt76.phy; 569 570 ieee80211_iterate_active_interfaces_atomic(mphy->hw, 571 IEEE80211_IFACE_ITER_RESUME_ALL, 572 mt7615_mcu_beacon_loss_iter, event); 573} 574 575static void 576mt7615_mcu_bss_event(struct mt7615_dev *dev, struct sk_buff *skb) 577{ 578 struct mt7615_mcu_bss_event *event; 579 struct mt76_phy *mphy; 580 u8 band_idx = 0; /* DBDC support */ 581 582 event = (struct mt7615_mcu_bss_event *)(skb->data + 583 sizeof(struct mt7615_mcu_rxd)); 584 585 if (band_idx && dev->mt76.phy2) 586 mphy = dev->mt76.phy2; 587 else 588 mphy = &dev->mt76.phy; 589 590 if (event->is_absent) 591 ieee80211_stop_queues(mphy->hw); 592 else 593 ieee80211_wake_queues(mphy->hw); 594} 595 596static void 597mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb) 598{ 599 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 600 601 switch (rxd->eid) { 602 case MCU_EVENT_EXT: 603 mt7615_mcu_rx_ext_event(dev, skb); 604 break; 605 case MCU_EVENT_BSS_BEACON_LOSS: 606 mt7615_mcu_beacon_loss_event(dev, skb); 607 break; 608 case MCU_EVENT_ROC: 609 mt7615_mcu_roc_event(dev, skb); 610 break; 611 case MCU_EVENT_SCHED_SCAN_DONE: 612 case MCU_EVENT_SCAN_DONE: 613 mt7615_mcu_scan_event(dev, skb); 614 return; 615 case MCU_EVENT_BSS_ABSENCE: 616 mt7615_mcu_bss_event(dev, skb); 617 break; 618 default: 619 break; 620 } 621 dev_kfree_skb(skb); 622} 623 624void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb) 625{ 626 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 627 628 if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT || 629 rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST || 630 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP || 631 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC || 632 rxd->eid == MCU_EVENT_BSS_BEACON_LOSS || 633 rxd->eid == MCU_EVENT_SCHED_SCAN_DONE || 634 rxd->eid == MCU_EVENT_BSS_ABSENCE || 635 rxd->eid == MCU_EVENT_SCAN_DONE || 636 rxd->eid == MCU_EVENT_ROC || 637 !rxd->seq) 638 mt7615_mcu_rx_unsolicited_event(dev, skb); 639 else 640 mt76_mcu_rx_event(&dev->mt76, skb); 641} 642 643static int mt7615_mcu_init_download(struct mt7615_dev *dev, u32 addr, 644 u32 len, u32 mode) 645{ 646 struct { 647 __le32 addr; 648 __le32 len; 649 __le32 mode; 650 } req = { 651 .addr = cpu_to_le32(addr), 652 .len = cpu_to_le32(len), 653 .mode = cpu_to_le32(mode), 654 }; 655 656 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_TARGET_ADDRESS_LEN_REQ, 657 &req, sizeof(req), true); 658} 659 660static int 661mt7615_mcu_add_dev(struct mt7615_dev *dev, struct ieee80211_vif *vif, 662 bool enable) 663{ 664 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 665 struct { 666 struct req_hdr { 667 u8 omac_idx; 668 u8 band_idx; 669 __le16 tlv_num; 670 u8 is_tlv_append; 671 u8 rsv[3]; 672 } __packed hdr; 673 struct req_tlv { 674 __le16 tag; 675 __le16 len; 676 u8 active; 677 u8 band_idx; 678 u8 omac_addr[ETH_ALEN]; 679 } __packed tlv; 680 } data = { 681 .hdr = { 682 .omac_idx = mvif->omac_idx, 683 .band_idx = mvif->band_idx, 684 .tlv_num = cpu_to_le16(1), 685 .is_tlv_append = 1, 686 }, 687 .tlv = { 688 .tag = cpu_to_le16(DEV_INFO_ACTIVE), 689 .len = cpu_to_le16(sizeof(struct req_tlv)), 690 .active = enable, 691 .band_idx = mvif->band_idx, 692 }, 693 }; 694 695 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN); 696 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DEV_INFO_UPDATE, 697 &data, sizeof(data), true); 698} 699 700static int 701mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev, 702 struct ieee80211_hw *hw, 703 struct ieee80211_vif *vif, bool enable) 704{ 705 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 706 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 707 struct ieee80211_mutable_offsets offs; 708 struct ieee80211_tx_info *info; 709 struct req { 710 u8 omac_idx; 711 u8 enable; 712 u8 wlan_idx; 713 u8 band_idx; 714 u8 pkt_type; 715 u8 need_pre_tbtt_int; 716 __le16 csa_ie_pos; 717 __le16 pkt_len; 718 __le16 tim_ie_pos; 719 u8 pkt[512]; 720 u8 csa_cnt; 721 /* bss color change */ 722 u8 bcc_cnt; 723 __le16 bcc_ie_pos; 724 } __packed req = { 725 .omac_idx = mvif->omac_idx, 726 .enable = enable, 727 .wlan_idx = wcid->idx, 728 .band_idx = mvif->band_idx, 729 }; 730 struct sk_buff *skb; 731 732 skb = ieee80211_beacon_get_template(hw, vif, &offs); 733 if (!skb) 734 return -EINVAL; 735 736 if (skb->len > 512 - MT_TXD_SIZE) { 737 dev_err(dev->mt76.dev, "Bcn size limit exceed\n"); 738 dev_kfree_skb(skb); 739 return -EINVAL; 740 } 741 742 if (mvif->band_idx) { 743 info = IEEE80211_SKB_CB(skb); 744 info->hw_queue |= MT_TX_HW_QUEUE_EXT_PHY; 745 } 746 747 mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL, 748 0, NULL, true); 749 memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len); 750 req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 751 req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 752 if (offs.cntdwn_counter_offs[0]) { 753 u16 csa_offs; 754 755 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4; 756 req.csa_ie_pos = cpu_to_le16(csa_offs); 757 req.csa_cnt = skb->data[offs.cntdwn_counter_offs[0]]; 758 } 759 dev_kfree_skb(skb); 760 761 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_BCN_OFFLOAD, 762 &req, sizeof(req), true); 763} 764 765static int 766mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 767{ 768#define ENTER_PM_STATE 1 769#define EXIT_PM_STATE 2 770 struct { 771 u8 pm_number; 772 u8 pm_state; 773 u8 bssid[ETH_ALEN]; 774 u8 dtim_period; 775 u8 wlan_idx; 776 __le16 bcn_interval; 777 __le32 aid; 778 __le32 rx_filter; 779 u8 band_idx; 780 u8 rsv[3]; 781 __le32 feature; 782 u8 omac_idx; 783 u8 wmm_idx; 784 u8 bcn_loss_cnt; 785 u8 bcn_sp_duration; 786 } __packed req = { 787 .pm_number = 5, 788 .pm_state = state ? ENTER_PM_STATE : EXIT_PM_STATE, 789 .band_idx = band, 790 }; 791 792 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PM_STATE_CTRL, 793 &req, sizeof(req), true); 794} 795 796static struct sk_buff * 797mt7615_mcu_alloc_sta_req(struct mt7615_dev *dev, struct mt7615_vif *mvif, 798 struct mt7615_sta *msta) 799{ 800 struct sta_req_hdr hdr = { 801 .bss_idx = mvif->idx, 802 .wlan_idx = msta ? msta->wcid.idx : 0, 803 .muar_idx = msta ? mvif->omac_idx : 0, 804 .is_tlv_append = 1, 805 }; 806 struct sk_buff *skb; 807 808 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, MT7615_STA_UPDATE_MAX_SIZE); 809 if (!skb) 810 return ERR_PTR(-ENOMEM); 811 812 skb_put_data(skb, &hdr, sizeof(hdr)); 813 814 return skb; 815} 816 817static struct wtbl_req_hdr * 818mt7615_mcu_alloc_wtbl_req(struct mt7615_dev *dev, struct mt7615_sta *msta, 819 int cmd, void *sta_wtbl, struct sk_buff **skb) 820{ 821 struct tlv *sta_hdr = sta_wtbl; 822 struct wtbl_req_hdr hdr = { 823 .wlan_idx = msta->wcid.idx, 824 .operation = cmd, 825 }; 826 struct sk_buff *nskb = *skb; 827 828 if (!nskb) { 829 nskb = mt76_mcu_msg_alloc(&dev->mt76, NULL, 830 MT7615_WTBL_UPDATE_BA_SIZE); 831 if (!nskb) 832 return ERR_PTR(-ENOMEM); 833 834 *skb = nskb; 835 } 836 837 if (sta_hdr) 838 sta_hdr->len = cpu_to_le16(sizeof(hdr)); 839 840 return skb_put_data(nskb, &hdr, sizeof(hdr)); 841} 842 843static struct tlv * 844mt7615_mcu_add_nested_tlv(struct sk_buff *skb, int tag, int len, 845 void *sta_ntlv, void *sta_wtbl) 846{ 847 struct sta_ntlv_hdr *ntlv_hdr = sta_ntlv; 848 struct tlv *sta_hdr = sta_wtbl; 849 struct tlv *ptlv, tlv = { 850 .tag = cpu_to_le16(tag), 851 .len = cpu_to_le16(len), 852 }; 853 u16 ntlv; 854 855 ptlv = skb_put(skb, len); 856 memcpy(ptlv, &tlv, sizeof(tlv)); 857 858 ntlv = le16_to_cpu(ntlv_hdr->tlv_num); 859 ntlv_hdr->tlv_num = cpu_to_le16(ntlv + 1); 860 861 if (sta_hdr) { 862 u16 size = le16_to_cpu(sta_hdr->len); 863 864 sta_hdr->len = cpu_to_le16(size + len); 865 } 866 867 return ptlv; 868} 869 870static struct tlv * 871mt7615_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 872{ 873 return mt7615_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 874} 875 876static int 877mt7615_mcu_bss_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 878 struct ieee80211_sta *sta, bool enable) 879{ 880 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 881 u32 type = vif->p2p ? NETWORK_P2P : NETWORK_INFRA; 882 struct bss_info_basic *bss; 883 u8 wlan_idx = mvif->sta.wcid.idx; 884 struct tlv *tlv; 885 886 tlv = mt7615_mcu_add_tlv(skb, BSS_INFO_BASIC, sizeof(*bss)); 887 888 switch (vif->type) { 889 case NL80211_IFTYPE_MESH_POINT: 890 case NL80211_IFTYPE_AP: 891 break; 892 case NL80211_IFTYPE_STATION: 893 /* TODO: enable BSS_INFO_UAPSD & BSS_INFO_PM */ 894 if (enable && sta) { 895 struct mt7615_sta *msta; 896 897 msta = (struct mt7615_sta *)sta->drv_priv; 898 wlan_idx = msta->wcid.idx; 899 } 900 break; 901 case NL80211_IFTYPE_ADHOC: 902 type = NETWORK_IBSS; 903 break; 904 default: 905 WARN_ON(1); 906 break; 907 } 908 909 bss = (struct bss_info_basic *)tlv; 910 memcpy(bss->bssid, vif->bss_conf.bssid, ETH_ALEN); 911 bss->bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int); 912 bss->network_type = cpu_to_le32(type); 913 bss->dtim_period = vif->bss_conf.dtim_period; 914 bss->bmc_tx_wlan_idx = wlan_idx; 915 bss->wmm_idx = mvif->wmm_idx; 916 bss->active = enable; 917 918 return 0; 919} 920 921static void 922mt7615_mcu_bss_omac_tlv(struct sk_buff *skb, struct ieee80211_vif *vif) 923{ 924 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 925 struct bss_info_omac *omac; 926 struct tlv *tlv; 927 u32 type = 0; 928 u8 idx; 929 930 tlv = mt7615_mcu_add_tlv(skb, BSS_INFO_OMAC, sizeof(*omac)); 931 932 switch (vif->type) { 933 case NL80211_IFTYPE_MESH_POINT: 934 case NL80211_IFTYPE_AP: 935 if (vif->p2p) 936 type = CONNECTION_P2P_GO; 937 else 938 type = CONNECTION_INFRA_AP; 939 break; 940 case NL80211_IFTYPE_STATION: 941 if (vif->p2p) 942 type = CONNECTION_P2P_GC; 943 else 944 type = CONNECTION_INFRA_STA; 945 break; 946 case NL80211_IFTYPE_ADHOC: 947 type = CONNECTION_IBSS_ADHOC; 948 break; 949 default: 950 WARN_ON(1); 951 break; 952 } 953 954 omac = (struct bss_info_omac *)tlv; 955 idx = mvif->omac_idx > EXT_BSSID_START ? HW_BSSID_0 : mvif->omac_idx; 956 omac->conn_type = cpu_to_le32(type); 957 omac->omac_idx = mvif->omac_idx; 958 omac->band_idx = mvif->band_idx; 959 omac->hw_bss_idx = idx; 960} 961 962/* SIFS 20us + 512 byte beacon tranmitted by 1Mbps (3906us) */ 963#define BCN_TX_ESTIMATE_TIME (4096 + 20) 964static void 965mt7615_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt7615_vif *mvif) 966{ 967 struct bss_info_ext_bss *ext; 968 int ext_bss_idx, tsf_offset; 969 struct tlv *tlv; 970 971 ext_bss_idx = mvif->omac_idx - EXT_BSSID_START; 972 if (ext_bss_idx < 0) 973 return; 974 975 tlv = mt7615_mcu_add_tlv(skb, BSS_INFO_EXT_BSS, sizeof(*ext)); 976 977 ext = (struct bss_info_ext_bss *)tlv; 978 tsf_offset = ext_bss_idx * BCN_TX_ESTIMATE_TIME; 979 ext->mbss_tsf_offset = cpu_to_le32(tsf_offset); 980} 981 982static void 983mt7615_mcu_sta_ba_tlv(struct sk_buff *skb, 984 struct ieee80211_ampdu_params *params, 985 bool enable, bool tx) 986{ 987 struct sta_rec_ba *ba; 988 struct tlv *tlv; 989 990 tlv = mt7615_mcu_add_tlv(skb, STA_REC_BA, sizeof(*ba)); 991 992 ba = (struct sta_rec_ba *)tlv; 993 ba->ba_type = tx ? MT_BA_TYPE_ORIGINATOR : MT_BA_TYPE_RECIPIENT, 994 ba->winsize = cpu_to_le16(params->buf_size); 995 ba->ssn = cpu_to_le16(params->ssn); 996 ba->ba_en = enable << params->tid; 997 ba->amsdu = params->amsdu; 998 ba->tid = params->tid; 999} 1000 1001static void 1002mt7615_mcu_sta_basic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 1003 struct ieee80211_sta *sta, bool enable) 1004{ 1005 struct sta_rec_basic *basic; 1006 struct tlv *tlv; 1007 int conn_type; 1008 1009 tlv = mt7615_mcu_add_tlv(skb, STA_REC_BASIC, sizeof(*basic)); 1010 1011 basic = (struct sta_rec_basic *)tlv; 1012 basic->extra_info = cpu_to_le16(EXTRA_INFO_VER); 1013 1014 if (enable) { 1015 basic->extra_info |= cpu_to_le16(EXTRA_INFO_NEW); 1016 basic->conn_state = CONN_STATE_PORT_SECURE; 1017 } else { 1018 basic->conn_state = CONN_STATE_DISCONNECT; 1019 } 1020 1021 if (!sta) { 1022 basic->conn_type = cpu_to_le32(CONNECTION_INFRA_BC); 1023 eth_broadcast_addr(basic->peer_addr); 1024 return; 1025 } 1026 1027 switch (vif->type) { 1028 case NL80211_IFTYPE_MESH_POINT: 1029 case NL80211_IFTYPE_AP: 1030 if (vif->p2p) 1031 conn_type = CONNECTION_P2P_GC; 1032 else 1033 conn_type = CONNECTION_INFRA_STA; 1034 basic->conn_type = cpu_to_le32(conn_type); 1035 basic->aid = cpu_to_le16(sta->aid); 1036 break; 1037 case NL80211_IFTYPE_STATION: 1038 if (vif->p2p) 1039 conn_type = CONNECTION_P2P_GO; 1040 else 1041 conn_type = CONNECTION_INFRA_AP; 1042 basic->conn_type = cpu_to_le32(conn_type); 1043 basic->aid = cpu_to_le16(vif->bss_conf.aid); 1044 break; 1045 case NL80211_IFTYPE_ADHOC: 1046 basic->conn_type = cpu_to_le32(CONNECTION_IBSS_ADHOC); 1047 basic->aid = cpu_to_le16(sta->aid); 1048 break; 1049 default: 1050 WARN_ON(1); 1051 break; 1052 } 1053 1054 memcpy(basic->peer_addr, sta->addr, ETH_ALEN); 1055 basic->qos = sta->wme; 1056} 1057 1058static void 1059mt7615_mcu_sta_ht_tlv(struct sk_buff *skb, struct ieee80211_sta *sta) 1060{ 1061 struct tlv *tlv; 1062 1063 if (sta->ht_cap.ht_supported) { 1064 struct sta_rec_ht *ht; 1065 1066 tlv = mt7615_mcu_add_tlv(skb, STA_REC_HT, sizeof(*ht)); 1067 ht = (struct sta_rec_ht *)tlv; 1068 ht->ht_cap = cpu_to_le16(sta->ht_cap.cap); 1069 } 1070 if (sta->vht_cap.vht_supported) { 1071 struct sta_rec_vht *vht; 1072 1073 tlv = mt7615_mcu_add_tlv(skb, STA_REC_VHT, sizeof(*vht)); 1074 vht = (struct sta_rec_vht *)tlv; 1075 vht->vht_rx_mcs_map = sta->vht_cap.vht_mcs.rx_mcs_map; 1076 vht->vht_tx_mcs_map = sta->vht_cap.vht_mcs.tx_mcs_map; 1077 vht->vht_cap = cpu_to_le32(sta->vht_cap.cap); 1078 } 1079} 1080 1081static void 1082mt7615_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 1083 struct ieee80211_sta *sta) 1084{ 1085 struct sta_rec_uapsd *uapsd; 1086 struct tlv *tlv; 1087 1088 if (vif->type != NL80211_IFTYPE_AP || !sta->wme) 1089 return; 1090 1091 tlv = mt7615_mcu_add_tlv(skb, STA_REC_APPS, sizeof(*uapsd)); 1092 uapsd = (struct sta_rec_uapsd *)tlv; 1093 1094 if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_VO) { 1095 uapsd->dac_map |= BIT(3); 1096 uapsd->tac_map |= BIT(3); 1097 } 1098 if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_VI) { 1099 uapsd->dac_map |= BIT(2); 1100 uapsd->tac_map |= BIT(2); 1101 } 1102 if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_BE) { 1103 uapsd->dac_map |= BIT(1); 1104 uapsd->tac_map |= BIT(1); 1105 } 1106 if (sta->uapsd_queues & IEEE80211_WMM_IE_STA_QOSINFO_AC_BK) { 1107 uapsd->dac_map |= BIT(0); 1108 uapsd->tac_map |= BIT(0); 1109 } 1110 uapsd->max_sp = sta->max_sp; 1111} 1112 1113static void 1114mt7615_mcu_wtbl_ba_tlv(struct sk_buff *skb, 1115 struct ieee80211_ampdu_params *params, 1116 bool enable, bool tx, void *sta_wtbl, 1117 void *wtbl_tlv) 1118{ 1119 struct wtbl_ba *ba; 1120 struct tlv *tlv; 1121 1122 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_BA, sizeof(*ba), 1123 wtbl_tlv, sta_wtbl); 1124 1125 ba = (struct wtbl_ba *)tlv; 1126 ba->tid = params->tid; 1127 1128 if (tx) { 1129 ba->ba_type = MT_BA_TYPE_ORIGINATOR; 1130 ba->sn = enable ? cpu_to_le16(params->ssn) : 0; 1131 ba->ba_winsize = cpu_to_le16(params->buf_size); 1132 ba->ba_en = enable; 1133 } else { 1134 memcpy(ba->peer_addr, params->sta->addr, ETH_ALEN); 1135 ba->ba_type = MT_BA_TYPE_RECIPIENT; 1136 ba->rst_ba_tid = params->tid; 1137 ba->rst_ba_sel = RST_BA_MAC_TID_MATCH; 1138 ba->rst_ba_sb = 1; 1139 } 1140 1141 if (enable && tx) { 1142 u8 ba_range[] = { 4, 8, 12, 24, 36, 48, 54, 64 }; 1143 int i; 1144 1145 for (i = 7; i > 0; i--) { 1146 if (params->buf_size >= ba_range[i]) 1147 break; 1148 } 1149 ba->ba_winsize_idx = i; 1150 } 1151} 1152 1153static void 1154mt7615_mcu_wtbl_generic_tlv(struct sk_buff *skb, struct ieee80211_vif *vif, 1155 struct ieee80211_sta *sta, void *sta_wtbl, 1156 void *wtbl_tlv) 1157{ 1158 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1159 struct wtbl_generic *generic; 1160 struct wtbl_rx *rx; 1161 struct wtbl_spe *spe; 1162 struct tlv *tlv; 1163 1164 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_GENERIC, sizeof(*generic), 1165 wtbl_tlv, sta_wtbl); 1166 1167 generic = (struct wtbl_generic *)tlv; 1168 1169 if (sta) { 1170 if (vif->type == NL80211_IFTYPE_STATION) 1171 generic->partial_aid = cpu_to_le16(vif->bss_conf.aid); 1172 else 1173 generic->partial_aid = cpu_to_le16(sta->aid); 1174 memcpy(generic->peer_addr, sta->addr, ETH_ALEN); 1175 generic->muar_idx = mvif->omac_idx; 1176 generic->qos = sta->wme; 1177 } else { 1178 eth_broadcast_addr(generic->peer_addr); 1179 generic->muar_idx = 0xe; 1180 } 1181 1182 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_RX, sizeof(*rx), 1183 wtbl_tlv, sta_wtbl); 1184 1185 rx = (struct wtbl_rx *)tlv; 1186 rx->rca1 = sta ? vif->type != NL80211_IFTYPE_AP : 1; 1187 rx->rca2 = 1; 1188 rx->rv = 1; 1189 1190 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_SPE, sizeof(*spe), 1191 wtbl_tlv, sta_wtbl); 1192 spe = (struct wtbl_spe *)tlv; 1193 spe->spe_idx = 24; 1194} 1195 1196static void 1197mt7615_mcu_wtbl_ht_tlv(struct sk_buff *skb, struct ieee80211_sta *sta, 1198 void *sta_wtbl, void *wtbl_tlv) 1199{ 1200 struct tlv *tlv; 1201 struct wtbl_ht *ht = NULL; 1202 u32 flags = 0; 1203 1204 if (sta->ht_cap.ht_supported) { 1205 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_HT, sizeof(*ht), 1206 wtbl_tlv, sta_wtbl); 1207 ht = (struct wtbl_ht *)tlv; 1208 ht->ldpc = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING); 1209 ht->af = sta->ht_cap.ampdu_factor; 1210 ht->mm = sta->ht_cap.ampdu_density; 1211 ht->ht = 1; 1212 1213 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) 1214 flags |= MT_WTBL_W5_SHORT_GI_20; 1215 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 1216 flags |= MT_WTBL_W5_SHORT_GI_40; 1217 } 1218 1219 if (sta->vht_cap.vht_supported) { 1220 struct wtbl_vht *vht; 1221 u8 af; 1222 1223 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_VHT, sizeof(*vht), 1224 wtbl_tlv, sta_wtbl); 1225 vht = (struct wtbl_vht *)tlv; 1226 vht->ldpc = !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 1227 vht->vht = 1; 1228 1229 af = (sta->vht_cap.cap & 1230 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK) >> 1231 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 1232 1233 if (ht) 1234 ht->af = max(ht->af, af); 1235 1236 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) 1237 flags |= MT_WTBL_W5_SHORT_GI_80; 1238 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160) 1239 flags |= MT_WTBL_W5_SHORT_GI_160; 1240 } 1241 1242 /* wtbl smps */ 1243 if (sta->smps_mode == IEEE80211_SMPS_DYNAMIC) { 1244 struct wtbl_smps *smps; 1245 1246 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_SMPS, sizeof(*smps), 1247 wtbl_tlv, sta_wtbl); 1248 smps = (struct wtbl_smps *)tlv; 1249 smps->smps = 1; 1250 } 1251 1252 if (sta->ht_cap.ht_supported) { 1253 /* sgi */ 1254 u32 msk = MT_WTBL_W5_SHORT_GI_20 | MT_WTBL_W5_SHORT_GI_40 | 1255 MT_WTBL_W5_SHORT_GI_80 | MT_WTBL_W5_SHORT_GI_160; 1256 struct wtbl_raw *raw; 1257 1258 tlv = mt7615_mcu_add_nested_tlv(skb, WTBL_RAW_DATA, 1259 sizeof(*raw), wtbl_tlv, 1260 sta_wtbl); 1261 raw = (struct wtbl_raw *)tlv; 1262 raw->val = cpu_to_le32(flags); 1263 raw->msk = cpu_to_le32(~msk); 1264 raw->wtbl_idx = 1; 1265 raw->dw = 5; 1266 } 1267} 1268 1269static int 1270mt7615_mcu_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1271 struct ieee80211_sta *sta, bool enable) 1272{ 1273 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1274 struct mt7615_dev *dev = phy->dev; 1275 struct sk_buff *skb; 1276 1277 skb = mt7615_mcu_alloc_sta_req(dev, mvif, NULL); 1278 if (IS_ERR(skb)) 1279 return PTR_ERR(skb); 1280 1281 if (enable) 1282 mt7615_mcu_bss_omac_tlv(skb, vif); 1283 1284 mt7615_mcu_bss_basic_tlv(skb, vif, sta, enable); 1285 1286 if (enable && mvif->omac_idx > EXT_BSSID_START) 1287 mt7615_mcu_bss_ext_tlv(skb, mvif); 1288 1289 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1290 MCU_EXT_CMD_BSS_INFO_UPDATE, true); 1291} 1292 1293static int 1294mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev, 1295 struct ieee80211_ampdu_params *params, 1296 bool enable) 1297{ 1298 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1299 struct mt7615_vif *mvif = msta->vif; 1300 struct wtbl_req_hdr *wtbl_hdr; 1301 struct sk_buff *skb = NULL; 1302 int err; 1303 1304 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, NULL, &skb); 1305 if (IS_ERR(wtbl_hdr)) 1306 return PTR_ERR(wtbl_hdr); 1307 1308 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, true, NULL, wtbl_hdr); 1309 1310 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1311 MCU_EXT_CMD_WTBL_UPDATE, true); 1312 if (err < 0) 1313 return err; 1314 1315 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1316 if (IS_ERR(skb)) 1317 return PTR_ERR(skb); 1318 1319 mt7615_mcu_sta_ba_tlv(skb, params, enable, true); 1320 1321 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1322 MCU_EXT_CMD_STA_REC_UPDATE, true); 1323} 1324 1325static int 1326mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev, 1327 struct ieee80211_ampdu_params *params, 1328 bool enable) 1329{ 1330 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1331 struct mt7615_vif *mvif = msta->vif; 1332 struct wtbl_req_hdr *wtbl_hdr; 1333 struct sk_buff *skb; 1334 int err; 1335 1336 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1337 if (IS_ERR(skb)) 1338 return PTR_ERR(skb); 1339 1340 mt7615_mcu_sta_ba_tlv(skb, params, enable, false); 1341 1342 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1343 MCU_EXT_CMD_STA_REC_UPDATE, true); 1344 if (err < 0 || !enable) 1345 return err; 1346 1347 skb = NULL; 1348 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, NULL, &skb); 1349 if (IS_ERR(wtbl_hdr)) 1350 return PTR_ERR(wtbl_hdr); 1351 1352 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, false, NULL, wtbl_hdr); 1353 1354 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1355 MCU_EXT_CMD_WTBL_UPDATE, true); 1356} 1357 1358static int 1359mt7615_mcu_wtbl_sta_add(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1360 struct ieee80211_sta *sta, bool enable) 1361{ 1362 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1363 struct sk_buff *skb, *sskb, *wskb = NULL; 1364 struct wtbl_req_hdr *wtbl_hdr; 1365 struct mt7615_sta *msta; 1366 int cmd, err; 1367 1368 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta; 1369 1370 sskb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1371 if (IS_ERR(sskb)) 1372 return PTR_ERR(sskb); 1373 1374 mt7615_mcu_sta_basic_tlv(sskb, vif, sta, enable); 1375 if (enable && sta) { 1376 mt7615_mcu_sta_ht_tlv(sskb, sta); 1377 mt7615_mcu_sta_uapsd(sskb, vif, sta); 1378 } 1379 1380 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_RESET_AND_SET, 1381 NULL, &wskb); 1382 if (IS_ERR(wtbl_hdr)) 1383 return PTR_ERR(wtbl_hdr); 1384 1385 if (enable) { 1386 mt7615_mcu_wtbl_generic_tlv(wskb, vif, sta, NULL, wtbl_hdr); 1387 if (sta) 1388 mt7615_mcu_wtbl_ht_tlv(wskb, sta, NULL, wtbl_hdr); 1389 } 1390 1391 cmd = enable ? MCU_EXT_CMD_WTBL_UPDATE : MCU_EXT_CMD_STA_REC_UPDATE; 1392 skb = enable ? wskb : sskb; 1393 1394 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1395 if (err < 0) { 1396 skb = enable ? sskb : wskb; 1397 dev_kfree_skb(skb); 1398 1399 return err; 1400 } 1401 1402 cmd = enable ? MCU_EXT_CMD_STA_REC_UPDATE : MCU_EXT_CMD_WTBL_UPDATE; 1403 skb = enable ? sskb : wskb; 1404 1405 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1406} 1407 1408static const struct mt7615_mcu_ops wtbl_update_ops = { 1409 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1410 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1411 .add_dev_info = mt7615_mcu_add_dev, 1412 .add_bss_info = mt7615_mcu_add_bss, 1413 .add_tx_ba = mt7615_mcu_wtbl_tx_ba, 1414 .add_rx_ba = mt7615_mcu_wtbl_rx_ba, 1415 .sta_add = mt7615_mcu_wtbl_sta_add, 1416 .set_drv_ctrl = mt7615_mcu_drv_pmctrl, 1417 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1418}; 1419 1420static int 1421mt7615_mcu_sta_ba(struct mt7615_dev *dev, 1422 struct ieee80211_ampdu_params *params, 1423 bool enable, bool tx) 1424{ 1425 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1426 struct mt7615_vif *mvif = msta->vif; 1427 struct wtbl_req_hdr *wtbl_hdr; 1428 struct tlv *sta_wtbl; 1429 struct sk_buff *skb; 1430 1431 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1432 if (IS_ERR(skb)) 1433 return PTR_ERR(skb); 1434 1435 mt7615_mcu_sta_ba_tlv(skb, params, enable, tx); 1436 1437 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1438 1439 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, sta_wtbl, 1440 &skb); 1441 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, tx, sta_wtbl, wtbl_hdr); 1442 1443 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1444 MCU_EXT_CMD_STA_REC_UPDATE, true); 1445} 1446 1447static int 1448mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev, 1449 struct ieee80211_ampdu_params *params, 1450 bool enable) 1451{ 1452 return mt7615_mcu_sta_ba(dev, params, enable, true); 1453} 1454 1455static int 1456mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev, 1457 struct ieee80211_ampdu_params *params, 1458 bool enable) 1459{ 1460 return mt7615_mcu_sta_ba(dev, params, enable, false); 1461} 1462 1463static int 1464mt7615_mcu_add_sta_cmd(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1465 struct ieee80211_sta *sta, bool enable, int cmd) 1466{ 1467 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1468 struct wtbl_req_hdr *wtbl_hdr; 1469 struct mt7615_sta *msta; 1470 struct tlv *sta_wtbl; 1471 struct sk_buff *skb; 1472 1473 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta; 1474 1475 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1476 if (IS_ERR(skb)) 1477 return PTR_ERR(skb); 1478 1479 mt7615_mcu_sta_basic_tlv(skb, vif, sta, enable); 1480 if (enable && sta) { 1481 mt7615_mcu_sta_ht_tlv(skb, sta); 1482 mt7615_mcu_sta_uapsd(skb, vif, sta); 1483 } 1484 1485 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1486 1487 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_RESET_AND_SET, 1488 sta_wtbl, &skb); 1489 if (enable) { 1490 mt7615_mcu_wtbl_generic_tlv(skb, vif, sta, sta_wtbl, wtbl_hdr); 1491 if (sta) 1492 mt7615_mcu_wtbl_ht_tlv(skb, sta, sta_wtbl, wtbl_hdr); 1493 } 1494 1495 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 1496} 1497 1498static int 1499mt7615_mcu_add_sta(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1500 struct ieee80211_sta *sta, bool enable) 1501{ 1502 return mt7615_mcu_add_sta_cmd(dev, vif, sta, enable, 1503 MCU_EXT_CMD_STA_REC_UPDATE); 1504} 1505 1506static const struct mt7615_mcu_ops sta_update_ops = { 1507 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1508 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1509 .add_dev_info = mt7615_mcu_add_dev, 1510 .add_bss_info = mt7615_mcu_add_bss, 1511 .add_tx_ba = mt7615_mcu_sta_tx_ba, 1512 .add_rx_ba = mt7615_mcu_sta_rx_ba, 1513 .sta_add = mt7615_mcu_add_sta, 1514 .set_drv_ctrl = mt7615_mcu_drv_pmctrl, 1515 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1516}; 1517 1518static int 1519mt7615_mcu_uni_add_dev(struct mt7615_dev *dev, 1520 struct ieee80211_vif *vif, bool enable) 1521{ 1522 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1523 struct { 1524 struct { 1525 u8 omac_idx; 1526 u8 band_idx; 1527 __le16 pad; 1528 } __packed hdr; 1529 struct req_tlv { 1530 __le16 tag; 1531 __le16 len; 1532 u8 active; 1533 u8 pad; 1534 u8 omac_addr[ETH_ALEN]; 1535 } __packed tlv; 1536 } dev_req = { 1537 .hdr = { 1538 .omac_idx = mvif->omac_idx, 1539 .band_idx = mvif->band_idx, 1540 }, 1541 .tlv = { 1542 .tag = cpu_to_le16(DEV_INFO_ACTIVE), 1543 .len = cpu_to_le16(sizeof(struct req_tlv)), 1544 .active = enable, 1545 }, 1546 }; 1547 struct { 1548 struct { 1549 u8 bss_idx; 1550 u8 pad[3]; 1551 } __packed hdr; 1552 struct mt7615_bss_basic_tlv basic; 1553 } basic_req = { 1554 .hdr = { 1555 .bss_idx = mvif->idx, 1556 }, 1557 .basic = { 1558 .tag = cpu_to_le16(UNI_BSS_INFO_BASIC), 1559 .len = cpu_to_le16(sizeof(struct mt7615_bss_basic_tlv)), 1560 .omac_idx = mvif->omac_idx, 1561 .band_idx = mvif->band_idx, 1562 .wmm_idx = mvif->wmm_idx, 1563 .active = enable, 1564 .bmc_tx_wlan_idx = cpu_to_le16(mvif->sta.wcid.idx), 1565 .sta_idx = cpu_to_le16(mvif->sta.wcid.idx), 1566 .conn_state = 1, 1567 }, 1568 }; 1569 int err, idx, cmd, len; 1570 void *data; 1571 1572 switch (vif->type) { 1573 case NL80211_IFTYPE_MESH_POINT: 1574 case NL80211_IFTYPE_AP: 1575 basic_req.basic.conn_type = cpu_to_le32(CONNECTION_INFRA_AP); 1576 break; 1577 case NL80211_IFTYPE_STATION: 1578 basic_req.basic.conn_type = cpu_to_le32(CONNECTION_INFRA_STA); 1579 break; 1580 case NL80211_IFTYPE_ADHOC: 1581 basic_req.basic.conn_type = cpu_to_le32(CONNECTION_IBSS_ADHOC); 1582 break; 1583 default: 1584 WARN_ON(1); 1585 break; 1586 } 1587 1588 idx = mvif->omac_idx > EXT_BSSID_START ? HW_BSSID_0 : mvif->omac_idx; 1589 basic_req.basic.hw_bss_idx = idx; 1590 1591 memcpy(dev_req.tlv.omac_addr, vif->addr, ETH_ALEN); 1592 1593 cmd = enable ? MCU_UNI_CMD_DEV_INFO_UPDATE : MCU_UNI_CMD_BSS_INFO_UPDATE; 1594 data = enable ? (void *)&dev_req : (void *)&basic_req; 1595 len = enable ? sizeof(dev_req) : sizeof(basic_req); 1596 1597 err = __mt76_mcu_send_msg(&dev->mt76, cmd, data, len, true); 1598 if (err < 0) 1599 return err; 1600 1601 cmd = enable ? MCU_UNI_CMD_BSS_INFO_UPDATE : MCU_UNI_CMD_DEV_INFO_UPDATE; 1602 data = enable ? (void *)&basic_req : (void *)&dev_req; 1603 len = enable ? sizeof(basic_req) : sizeof(dev_req); 1604 1605 return __mt76_mcu_send_msg(&dev->mt76, cmd, data, len, true); 1606} 1607 1608static int 1609mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 1610{ 1611 return 0; 1612} 1613 1614static int 1615mt7615_mcu_uni_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1616 struct ieee80211_sta *sta, bool enable) 1617{ 1618 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1619 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 1620 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2; 1621 struct mt7615_dev *dev = phy->dev; 1622 struct { 1623 struct { 1624 u8 bss_idx; 1625 u8 pad[3]; 1626 } __packed hdr; 1627 struct mt7615_bss_basic_tlv basic; 1628 struct mt7615_bss_qos_tlv qos; 1629 } basic_req = { 1630 .hdr = { 1631 .bss_idx = mvif->idx, 1632 }, 1633 .basic = { 1634 .tag = cpu_to_le16(UNI_BSS_INFO_BASIC), 1635 .len = cpu_to_le16(sizeof(struct mt7615_bss_basic_tlv)), 1636 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int), 1637 .dtim_period = vif->bss_conf.dtim_period, 1638 .omac_idx = mvif->omac_idx, 1639 .band_idx = mvif->band_idx, 1640 .wmm_idx = mvif->wmm_idx, 1641 .active = true, /* keep bss deactivated */ 1642 .phymode = 0x38, 1643 }, 1644 .qos = { 1645 .tag = cpu_to_le16(UNI_BSS_INFO_QBSS), 1646 .len = cpu_to_le16(sizeof(struct mt7615_bss_qos_tlv)), 1647 .qos = vif->bss_conf.qos, 1648 }, 1649 }; 1650 struct { 1651 struct { 1652 u8 bss_idx; 1653 u8 pad[3]; 1654 } __packed hdr; 1655 struct rlm_tlv { 1656 __le16 tag; 1657 __le16 len; 1658 u8 control_channel; 1659 u8 center_chan; 1660 u8 center_chan2; 1661 u8 bw; 1662 u8 tx_streams; 1663 u8 rx_streams; 1664 u8 short_st; 1665 u8 ht_op_info; 1666 u8 sco; 1667 u8 pad[3]; 1668 } __packed rlm; 1669 } __packed rlm_req = { 1670 .hdr = { 1671 .bss_idx = mvif->idx, 1672 }, 1673 .rlm = { 1674 .tag = cpu_to_le16(UNI_BSS_INFO_RLM), 1675 .len = cpu_to_le16(sizeof(struct rlm_tlv)), 1676 .control_channel = chandef->chan->hw_value, 1677 .center_chan = ieee80211_frequency_to_channel(freq1), 1678 .center_chan2 = ieee80211_frequency_to_channel(freq2), 1679 .tx_streams = hweight8(phy->mt76->antenna_mask), 1680 .rx_streams = phy->chainmask, 1681 .short_st = true, 1682 }, 1683 }; 1684 int err, conn_type; 1685 u8 idx; 1686 1687 idx = mvif->omac_idx > EXT_BSSID_START ? HW_BSSID_0 : mvif->omac_idx; 1688 basic_req.basic.hw_bss_idx = idx; 1689 1690 switch (vif->type) { 1691 case NL80211_IFTYPE_MESH_POINT: 1692 case NL80211_IFTYPE_AP: 1693 if (vif->p2p) 1694 conn_type = CONNECTION_P2P_GO; 1695 else 1696 conn_type = CONNECTION_INFRA_AP; 1697 basic_req.basic.conn_type = cpu_to_le32(conn_type); 1698 break; 1699 case NL80211_IFTYPE_STATION: 1700 if (vif->p2p) 1701 conn_type = CONNECTION_P2P_GC; 1702 else 1703 conn_type = CONNECTION_INFRA_STA; 1704 basic_req.basic.conn_type = cpu_to_le32(conn_type); 1705 break; 1706 case NL80211_IFTYPE_ADHOC: 1707 basic_req.basic.conn_type = cpu_to_le32(CONNECTION_IBSS_ADHOC); 1708 break; 1709 default: 1710 WARN_ON(1); 1711 break; 1712 } 1713 1714 memcpy(basic_req.basic.bssid, vif->bss_conf.bssid, ETH_ALEN); 1715 basic_req.basic.bmc_tx_wlan_idx = cpu_to_le16(mvif->sta.wcid.idx); 1716 basic_req.basic.sta_idx = cpu_to_le16(mvif->sta.wcid.idx); 1717 basic_req.basic.conn_state = !enable; 1718 1719 err = __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_BSS_INFO_UPDATE, 1720 &basic_req, sizeof(basic_req), true); 1721 if (err < 0) 1722 return err; 1723 1724 switch (chandef->width) { 1725 case NL80211_CHAN_WIDTH_40: 1726 rlm_req.rlm.bw = CMD_CBW_40MHZ; 1727 break; 1728 case NL80211_CHAN_WIDTH_80: 1729 rlm_req.rlm.bw = CMD_CBW_80MHZ; 1730 break; 1731 case NL80211_CHAN_WIDTH_80P80: 1732 rlm_req.rlm.bw = CMD_CBW_8080MHZ; 1733 break; 1734 case NL80211_CHAN_WIDTH_160: 1735 rlm_req.rlm.bw = CMD_CBW_160MHZ; 1736 break; 1737 case NL80211_CHAN_WIDTH_5: 1738 rlm_req.rlm.bw = CMD_CBW_5MHZ; 1739 break; 1740 case NL80211_CHAN_WIDTH_10: 1741 rlm_req.rlm.bw = CMD_CBW_10MHZ; 1742 break; 1743 case NL80211_CHAN_WIDTH_20_NOHT: 1744 case NL80211_CHAN_WIDTH_20: 1745 default: 1746 rlm_req.rlm.bw = CMD_CBW_20MHZ; 1747 break; 1748 } 1749 1750 if (rlm_req.rlm.control_channel < rlm_req.rlm.center_chan) 1751 rlm_req.rlm.sco = 1; /* SCA */ 1752 else if (rlm_req.rlm.control_channel > rlm_req.rlm.center_chan) 1753 rlm_req.rlm.sco = 3; /* SCB */ 1754 1755 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_BSS_INFO_UPDATE, 1756 &rlm_req, sizeof(rlm_req), true); 1757} 1758 1759static int 1760mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev, 1761 struct ieee80211_hw *hw, 1762 struct ieee80211_vif *vif, 1763 bool enable) 1764{ 1765 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1766 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 1767 struct ieee80211_mutable_offsets offs; 1768 struct { 1769 struct req_hdr { 1770 u8 bss_idx; 1771 u8 pad[3]; 1772 } __packed hdr; 1773 struct bcn_content_tlv { 1774 __le16 tag; 1775 __le16 len; 1776 __le16 tim_ie_pos; 1777 __le16 csa_ie_pos; 1778 __le16 bcc_ie_pos; 1779 /* 0: enable beacon offload 1780 * 1: disable beacon offload 1781 * 2: update probe respond offload 1782 */ 1783 u8 enable; 1784 /* 0: legacy format (TXD + payload) 1785 * 1: only cap field IE 1786 */ 1787 u8 type; 1788 __le16 pkt_len; 1789 u8 pkt[512]; 1790 } __packed beacon_tlv; 1791 } req = { 1792 .hdr = { 1793 .bss_idx = mvif->idx, 1794 }, 1795 .beacon_tlv = { 1796 .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT), 1797 .len = cpu_to_le16(sizeof(struct bcn_content_tlv)), 1798 .enable = enable, 1799 }, 1800 }; 1801 struct sk_buff *skb; 1802 1803 skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs); 1804 if (!skb) 1805 return -EINVAL; 1806 1807 if (skb->len > 512 - MT_TXD_SIZE) { 1808 dev_err(dev->mt76.dev, "beacon size limit exceed\n"); 1809 dev_kfree_skb(skb); 1810 return -EINVAL; 1811 } 1812 1813 mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb, 1814 wcid, NULL, 0, NULL, true); 1815 memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len); 1816 req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 1817 req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 1818 1819 if (offs.cntdwn_counter_offs[0]) { 1820 u16 csa_offs; 1821 1822 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4; 1823 req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs); 1824 } 1825 dev_kfree_skb(skb); 1826 1827 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_BSS_INFO_UPDATE, 1828 &req, sizeof(req), true); 1829} 1830 1831static int 1832mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev, 1833 struct ieee80211_ampdu_params *params, 1834 bool enable) 1835{ 1836 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1837 struct mt7615_vif *mvif = msta->vif; 1838 struct wtbl_req_hdr *wtbl_hdr; 1839 struct tlv *sta_wtbl; 1840 struct sk_buff *skb; 1841 int err; 1842 1843 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1844 if (IS_ERR(skb)) 1845 return PTR_ERR(skb); 1846 1847 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1848 1849 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, sta_wtbl, 1850 &skb); 1851 if (IS_ERR(wtbl_hdr)) 1852 return PTR_ERR(wtbl_hdr); 1853 1854 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, true, sta_wtbl, 1855 wtbl_hdr); 1856 1857 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1858 MCU_UNI_CMD_STA_REC_UPDATE, true); 1859 if (err < 0) 1860 return err; 1861 1862 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1863 if (IS_ERR(skb)) 1864 return PTR_ERR(skb); 1865 1866 mt7615_mcu_sta_ba_tlv(skb, params, enable, true); 1867 1868 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1869 MCU_UNI_CMD_STA_REC_UPDATE, true); 1870} 1871 1872static int 1873mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev, 1874 struct ieee80211_ampdu_params *params, 1875 bool enable) 1876{ 1877 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1878 struct mt7615_vif *mvif = msta->vif; 1879 struct wtbl_req_hdr *wtbl_hdr; 1880 struct tlv *sta_wtbl; 1881 struct sk_buff *skb; 1882 int err; 1883 1884 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1885 if (IS_ERR(skb)) 1886 return PTR_ERR(skb); 1887 1888 mt7615_mcu_sta_ba_tlv(skb, params, enable, false); 1889 1890 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1891 MCU_UNI_CMD_STA_REC_UPDATE, true); 1892 if (err < 0 || !enable) 1893 return err; 1894 1895 skb = mt7615_mcu_alloc_sta_req(dev, mvif, msta); 1896 if (IS_ERR(skb)) 1897 return PTR_ERR(skb); 1898 1899 sta_wtbl = mt7615_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 1900 1901 wtbl_hdr = mt7615_mcu_alloc_wtbl_req(dev, msta, WTBL_SET, sta_wtbl, 1902 &skb); 1903 if (IS_ERR(wtbl_hdr)) 1904 return PTR_ERR(wtbl_hdr); 1905 1906 mt7615_mcu_wtbl_ba_tlv(skb, params, enable, false, sta_wtbl, 1907 wtbl_hdr); 1908 1909 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 1910 MCU_UNI_CMD_STA_REC_UPDATE, true); 1911} 1912 1913static int 1914mt7615_mcu_uni_add_sta(struct mt7615_dev *dev, struct ieee80211_vif *vif, 1915 struct ieee80211_sta *sta, bool enable) 1916{ 1917 return mt7615_mcu_add_sta_cmd(dev, vif, sta, enable, 1918 MCU_UNI_CMD_STA_REC_UPDATE); 1919} 1920 1921static const struct mt7615_mcu_ops uni_update_ops = { 1922 .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload, 1923 .set_pm_state = mt7615_mcu_uni_ctrl_pm_state, 1924 .add_dev_info = mt7615_mcu_uni_add_dev, 1925 .add_bss_info = mt7615_mcu_uni_add_bss, 1926 .add_tx_ba = mt7615_mcu_uni_tx_ba, 1927 .add_rx_ba = mt7615_mcu_uni_rx_ba, 1928 .sta_add = mt7615_mcu_uni_add_sta, 1929 .set_drv_ctrl = mt7615_mcu_lp_drv_pmctrl, 1930 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1931}; 1932 1933static int mt7615_mcu_send_firmware(struct mt7615_dev *dev, const void *data, 1934 int len) 1935{ 1936 int ret = 0, cur_len; 1937 1938 while (len > 0) { 1939 cur_len = min_t(int, 4096 - dev->mt76.mcu_ops->headroom, len); 1940 1941 ret = __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_FW_SCATTER, 1942 data, cur_len, false); 1943 if (ret) 1944 break; 1945 1946 data += cur_len; 1947 len -= cur_len; 1948 1949 if (mt76_is_mmio(&dev->mt76)) 1950 mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false); 1951 } 1952 1953 return ret; 1954} 1955 1956static int mt7615_mcu_start_firmware(struct mt7615_dev *dev, u32 addr, 1957 u32 option) 1958{ 1959 struct { 1960 __le32 option; 1961 __le32 addr; 1962 } req = { 1963 .option = cpu_to_le32(option), 1964 .addr = cpu_to_le32(addr), 1965 }; 1966 1967 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_FW_START_REQ, 1968 &req, sizeof(req), true); 1969} 1970 1971int mt7615_mcu_restart(struct mt76_dev *dev) 1972{ 1973 return __mt76_mcu_send_msg(dev, MCU_CMD_RESTART_DL_REQ, NULL, 1974 0, true); 1975} 1976EXPORT_SYMBOL_GPL(mt7615_mcu_restart); 1977 1978static int mt7615_mcu_patch_sem_ctrl(struct mt7615_dev *dev, bool get) 1979{ 1980 struct { 1981 __le32 op; 1982 } req = { 1983 .op = cpu_to_le32(get ? PATCH_SEM_GET : PATCH_SEM_RELEASE), 1984 }; 1985 1986 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_PATCH_SEM_CONTROL, 1987 &req, sizeof(req), true); 1988} 1989 1990static int mt7615_mcu_start_patch(struct mt7615_dev *dev) 1991{ 1992 struct { 1993 u8 check_crc; 1994 u8 reserved[3]; 1995 } req = { 1996 .check_crc = 0, 1997 }; 1998 1999 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_PATCH_FINISH_REQ, 2000 &req, sizeof(req), true); 2001} 2002 2003static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name) 2004{ 2005 const struct mt7615_patch_hdr *hdr; 2006 const struct firmware *fw = NULL; 2007 int len, ret, sem; 2008 2009 sem = mt7615_mcu_patch_sem_ctrl(dev, 1); 2010 switch (sem) { 2011 case PATCH_IS_DL: 2012 return 0; 2013 case PATCH_NOT_DL_SEM_SUCCESS: 2014 break; 2015 default: 2016 dev_err(dev->mt76.dev, "Failed to get patch semaphore\n"); 2017 return -EAGAIN; 2018 } 2019 2020 ret = firmware_request_nowarn(&fw, name, dev->mt76.dev); 2021 if (ret) 2022 goto out; 2023 2024 if (!fw || !fw->data || fw->size < sizeof(*hdr)) { 2025 dev_err(dev->mt76.dev, "Invalid firmware\n"); 2026 ret = -EINVAL; 2027 goto out; 2028 } 2029 2030 hdr = (const struct mt7615_patch_hdr *)(fw->data); 2031 2032 dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n", 2033 be32_to_cpu(hdr->hw_sw_ver), hdr->build_date); 2034 2035 len = fw->size - sizeof(*hdr); 2036 2037 ret = mt7615_mcu_init_download(dev, addr, len, DL_MODE_NEED_RSP); 2038 if (ret) { 2039 dev_err(dev->mt76.dev, "Download request failed\n"); 2040 goto out; 2041 } 2042 2043 ret = mt7615_mcu_send_firmware(dev, fw->data + sizeof(*hdr), len); 2044 if (ret) { 2045 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 2046 goto out; 2047 } 2048 2049 ret = mt7615_mcu_start_patch(dev); 2050 if (ret) 2051 dev_err(dev->mt76.dev, "Failed to start patch\n"); 2052 2053out: 2054 release_firmware(fw); 2055 2056 sem = mt7615_mcu_patch_sem_ctrl(dev, 0); 2057 switch (sem) { 2058 case PATCH_REL_SEM_SUCCESS: 2059 break; 2060 default: 2061 ret = -EAGAIN; 2062 dev_err(dev->mt76.dev, "Failed to release patch semaphore\n"); 2063 break; 2064 } 2065 2066 return ret; 2067} 2068 2069static u32 mt7615_mcu_gen_dl_mode(u8 feature_set, bool is_cr4) 2070{ 2071 u32 ret = 0; 2072 2073 ret |= (feature_set & FW_FEATURE_SET_ENCRYPT) ? 2074 (DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV) : 0; 2075 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 2076 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 2077 ret |= DL_MODE_NEED_RSP; 2078 ret |= is_cr4 ? DL_MODE_WORKING_PDA_CR4 : 0; 2079 2080 return ret; 2081} 2082 2083static int 2084mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev, 2085 const struct mt7615_fw_trailer *hdr, 2086 const u8 *data, bool is_cr4) 2087{ 2088 int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM; 2089 int err, i, offset = 0; 2090 u32 len, addr, mode; 2091 2092 for (i = 0; i < n_region; i++) { 2093 mode = mt7615_mcu_gen_dl_mode(hdr[i].feature_set, is_cr4); 2094 len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN; 2095 addr = le32_to_cpu(hdr[i].addr); 2096 2097 err = mt7615_mcu_init_download(dev, addr, len, mode); 2098 if (err) { 2099 dev_err(dev->mt76.dev, "Download request failed\n"); 2100 return err; 2101 } 2102 2103 err = mt7615_mcu_send_firmware(dev, data + offset, len); 2104 if (err) { 2105 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 2106 return err; 2107 } 2108 2109 offset += len; 2110 } 2111 2112 return 0; 2113} 2114 2115static const struct wiphy_wowlan_support mt7615_wowlan_support = { 2116 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT | 2117 WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | WIPHY_WOWLAN_NET_DETECT, 2118 .n_patterns = 1, 2119 .pattern_min_len = 1, 2120 .pattern_max_len = MT7615_WOW_PATTEN_MAX_LEN, 2121 .max_nd_match_sets = 10, 2122}; 2123 2124static int mt7615_load_n9(struct mt7615_dev *dev, const char *name) 2125{ 2126 const struct mt7615_fw_trailer *hdr; 2127 const struct firmware *fw; 2128 int ret; 2129 2130 ret = request_firmware(&fw, name, dev->mt76.dev); 2131 if (ret) 2132 return ret; 2133 2134 if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) { 2135 dev_err(dev->mt76.dev, "Invalid firmware\n"); 2136 ret = -EINVAL; 2137 goto out; 2138 } 2139 2140 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 2141 N9_REGION_NUM * sizeof(*hdr)); 2142 2143 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 2144 hdr->fw_ver, hdr->build_date); 2145 2146 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false); 2147 if (ret) 2148 goto out; 2149 2150 ret = mt7615_mcu_start_firmware(dev, le32_to_cpu(hdr->addr), 2151 FW_START_OVERRIDE); 2152 if (ret) { 2153 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 2154 goto out; 2155 } 2156 2157 snprintf(dev->mt76.hw->wiphy->fw_version, 2158 sizeof(dev->mt76.hw->wiphy->fw_version), 2159 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 2160 2161 if (!is_mt7615(&dev->mt76) && 2162 !strncmp(hdr->fw_ver, "2.0", sizeof(hdr->fw_ver))) { 2163 dev->fw_ver = MT7615_FIRMWARE_V2; 2164 dev->mcu_ops = &sta_update_ops; 2165 } else { 2166 dev->fw_ver = MT7615_FIRMWARE_V1; 2167 dev->mcu_ops = &wtbl_update_ops; 2168 } 2169 2170out: 2171 release_firmware(fw); 2172 return ret; 2173} 2174 2175static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name) 2176{ 2177 const struct mt7615_fw_trailer *hdr; 2178 const struct firmware *fw; 2179 int ret; 2180 2181 ret = request_firmware(&fw, name, dev->mt76.dev); 2182 if (ret) 2183 return ret; 2184 2185 if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) { 2186 dev_err(dev->mt76.dev, "Invalid firmware\n"); 2187 ret = -EINVAL; 2188 goto out; 2189 } 2190 2191 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 2192 CR4_REGION_NUM * sizeof(*hdr)); 2193 2194 dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n", 2195 hdr->fw_ver, hdr->build_date); 2196 2197 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true); 2198 if (ret) 2199 goto out; 2200 2201 ret = mt7615_mcu_start_firmware(dev, 0, FW_START_WORKING_PDA_CR4); 2202 if (ret) { 2203 dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n"); 2204 goto out; 2205 } 2206 2207out: 2208 release_firmware(fw); 2209 2210 return ret; 2211} 2212 2213static int mt7615_load_ram(struct mt7615_dev *dev) 2214{ 2215 int ret; 2216 2217 ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9); 2218 if (ret) 2219 return ret; 2220 2221 return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4); 2222} 2223 2224static int mt7615_load_firmware(struct mt7615_dev *dev) 2225{ 2226 int ret; 2227 u32 val; 2228 2229 val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE); 2230 2231 if (val != FW_STATE_FW_DOWNLOAD) { 2232 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 2233 return -EIO; 2234 } 2235 2236 ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH); 2237 if (ret) 2238 return ret; 2239 2240 ret = mt7615_load_ram(dev); 2241 if (ret) 2242 return ret; 2243 2244 if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE, 2245 FIELD_PREP(MT_TOP_MISC2_FW_STATE, 2246 FW_STATE_CR4_RDY), 500)) { 2247 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 2248 return -EIO; 2249 } 2250 2251 return 0; 2252} 2253 2254static int mt7622_load_firmware(struct mt7615_dev *dev) 2255{ 2256 int ret; 2257 u32 val; 2258 2259 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 2260 2261 val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE); 2262 if (val != FW_STATE_FW_DOWNLOAD) { 2263 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 2264 return -EIO; 2265 } 2266 2267 ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH); 2268 if (ret) 2269 return ret; 2270 2271 ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9); 2272 if (ret) 2273 return ret; 2274 2275 if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE, 2276 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE, 2277 FW_STATE_NORMAL_TRX), 1500)) { 2278 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 2279 return -EIO; 2280 } 2281 2282 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 2283 2284 return 0; 2285} 2286 2287int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl) 2288{ 2289 struct { 2290 u8 ctrl_val; 2291 u8 pad[3]; 2292 } data = { 2293 .ctrl_val = ctrl 2294 }; 2295 2296 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_FW_LOG_2_HOST, 2297 &data, sizeof(data), true); 2298} 2299 2300static int mt7663_load_n9(struct mt7615_dev *dev, const char *name) 2301{ 2302 u32 offset = 0, override_addr = 0, flag = FW_START_DLYCAL; 2303 const struct mt7663_fw_trailer *hdr; 2304 const struct mt7663_fw_buf *buf; 2305 const struct firmware *fw; 2306 const u8 *base_addr; 2307 int i, ret; 2308 2309 ret = request_firmware(&fw, name, dev->mt76.dev); 2310 if (ret) 2311 return ret; 2312 2313 if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) { 2314 dev_err(dev->mt76.dev, "Invalid firmware\n"); 2315 ret = -EINVAL; 2316 goto out; 2317 } 2318 2319 hdr = (const struct mt7663_fw_trailer *)(fw->data + fw->size - 2320 FW_V3_COMMON_TAILER_SIZE); 2321 2322 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 2323 hdr->fw_ver, hdr->build_date); 2324 dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region); 2325 2326 base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE; 2327 for (i = 0; i < hdr->n_region; i++) { 2328 u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE; 2329 u32 len, addr, mode; 2330 2331 dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i); 2332 2333 buf = (const struct mt7663_fw_buf *)(base_addr - shift); 2334 mode = mt7615_mcu_gen_dl_mode(buf->feature_set, false); 2335 addr = le32_to_cpu(buf->img_dest_addr); 2336 len = le32_to_cpu(buf->img_size); 2337 2338 ret = mt7615_mcu_init_download(dev, addr, len, mode); 2339 if (ret) { 2340 dev_err(dev->mt76.dev, "Download request failed\n"); 2341 goto out; 2342 } 2343 2344 ret = mt7615_mcu_send_firmware(dev, fw->data + offset, len); 2345 if (ret) { 2346 dev_err(dev->mt76.dev, "Failed to send firmware\n"); 2347 goto out; 2348 } 2349 2350 offset += le32_to_cpu(buf->img_size); 2351 if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) { 2352 override_addr = le32_to_cpu(buf->img_dest_addr); 2353 dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n", 2354 i, override_addr); 2355 } 2356 } 2357 2358 if (override_addr) 2359 flag |= FW_START_OVERRIDE; 2360 2361 dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n", 2362 override_addr, flag); 2363 2364 ret = mt7615_mcu_start_firmware(dev, override_addr, flag); 2365 if (ret) { 2366 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 2367 goto out; 2368 } 2369 2370 snprintf(dev->mt76.hw->wiphy->fw_version, 2371 sizeof(dev->mt76.hw->wiphy->fw_version), 2372 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 2373 2374out: 2375 release_firmware(fw); 2376 2377 return ret; 2378} 2379 2380static int 2381mt7663_load_rom_patch(struct mt7615_dev *dev, const char **n9_firmware) 2382{ 2383 const char *selected_rom, *secondary_rom = MT7663_ROM_PATCH; 2384 const char *primary_rom = MT7663_OFFLOAD_ROM_PATCH; 2385 int ret; 2386 2387 if (!prefer_offload_fw) { 2388 secondary_rom = MT7663_OFFLOAD_ROM_PATCH; 2389 primary_rom = MT7663_ROM_PATCH; 2390 } 2391 selected_rom = primary_rom; 2392 2393 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, primary_rom); 2394 if (ret) { 2395 dev_info(dev->mt76.dev, "%s not found, switching to %s", 2396 primary_rom, secondary_rom); 2397 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, 2398 secondary_rom); 2399 if (ret) { 2400 dev_err(dev->mt76.dev, "failed to load %s", 2401 secondary_rom); 2402 return ret; 2403 } 2404 selected_rom = secondary_rom; 2405 } 2406 2407 if (!strcmp(selected_rom, MT7663_OFFLOAD_ROM_PATCH)) { 2408 *n9_firmware = MT7663_OFFLOAD_FIRMWARE_N9; 2409 dev->fw_ver = MT7615_FIRMWARE_V3; 2410 dev->mcu_ops = &uni_update_ops; 2411 } else { 2412 *n9_firmware = MT7663_FIRMWARE_N9; 2413 dev->fw_ver = MT7615_FIRMWARE_V2; 2414 dev->mcu_ops = &sta_update_ops; 2415 } 2416 2417 return 0; 2418} 2419 2420int __mt7663_load_firmware(struct mt7615_dev *dev) 2421{ 2422 const char *n9_firmware; 2423 int ret; 2424 2425 ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY); 2426 if (ret) { 2427 dev_dbg(dev->mt76.dev, "Firmware is already download\n"); 2428 return -EIO; 2429 } 2430 2431 ret = mt7663_load_rom_patch(dev, &n9_firmware); 2432 if (ret) 2433 return ret; 2434 2435 ret = mt7663_load_n9(dev, n9_firmware); 2436 if (ret) 2437 return ret; 2438 2439 if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY, 2440 MT_TOP_MISC2_FW_N9_RDY, 1500)) { 2441 ret = mt76_get_field(dev, MT_CONN_ON_MISC, 2442 MT7663_TOP_MISC2_FW_STATE); 2443 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 2444 return -EIO; 2445 } 2446 2447#ifdef CONFIG_PM 2448 if (mt7615_firmware_offload(dev)) 2449 dev->mt76.hw->wiphy->wowlan = &mt7615_wowlan_support; 2450#endif /* CONFIG_PM */ 2451 2452 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 2453 2454 return 0; 2455} 2456EXPORT_SYMBOL_GPL(__mt7663_load_firmware); 2457 2458static int mt7663_load_firmware(struct mt7615_dev *dev) 2459{ 2460 int ret; 2461 2462 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 2463 2464 ret = __mt7663_load_firmware(dev); 2465 if (ret) 2466 return ret; 2467 2468 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 2469 2470 return 0; 2471} 2472 2473int mt7615_mcu_init(struct mt7615_dev *dev) 2474{ 2475 static const struct mt76_mcu_ops mt7615_mcu_ops = { 2476 .headroom = sizeof(struct mt7615_mcu_txd), 2477 .mcu_skb_send_msg = mt7615_mcu_send_message, 2478 .mcu_send_msg = mt7615_mcu_msg_send, 2479 .mcu_restart = mt7615_mcu_restart, 2480 }; 2481 int ret; 2482 2483 dev->mt76.mcu_ops = &mt7615_mcu_ops, 2484 2485 ret = mt7615_mcu_drv_pmctrl(dev); 2486 if (ret) 2487 return ret; 2488 2489 switch (mt76_chip(&dev->mt76)) { 2490 case 0x7622: 2491 ret = mt7622_load_firmware(dev); 2492 break; 2493 case 0x7663: 2494 ret = mt7663_load_firmware(dev); 2495 break; 2496 default: 2497 ret = mt7615_load_firmware(dev); 2498 break; 2499 } 2500 if (ret) 2501 return ret; 2502 2503 mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false); 2504 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 2505 set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 2506 mt7615_mcu_fw_log_2_host(dev, 0); 2507 2508 return 0; 2509} 2510EXPORT_SYMBOL_GPL(mt7615_mcu_init); 2511 2512void mt7615_mcu_exit(struct mt7615_dev *dev) 2513{ 2514 __mt76_mcu_restart(&dev->mt76); 2515 mt7615_mcu_set_fw_ctrl(dev); 2516 skb_queue_purge(&dev->mt76.mcu.res_q); 2517} 2518EXPORT_SYMBOL_GPL(mt7615_mcu_exit); 2519 2520int mt7615_mcu_set_eeprom(struct mt7615_dev *dev) 2521{ 2522 struct { 2523 u8 buffer_mode; 2524 u8 content_format; 2525 __le16 len; 2526 } __packed req_hdr = { 2527 .buffer_mode = 1, 2528 }; 2529 u8 *eep = (u8 *)dev->mt76.eeprom.data; 2530 struct sk_buff *skb; 2531 int eep_len, offset; 2532 2533 switch (mt76_chip(&dev->mt76)) { 2534 case 0x7622: 2535 eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0; 2536 offset = MT_EE_NIC_CONF_0; 2537 break; 2538 case 0x7663: 2539 eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID; 2540 req_hdr.content_format = 1; 2541 offset = MT_EE_CHIP_ID; 2542 break; 2543 default: 2544 eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0; 2545 offset = MT_EE_NIC_CONF_0; 2546 break; 2547 } 2548 2549 req_hdr.len = cpu_to_le16(eep_len); 2550 2551 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + eep_len); 2552 if (!skb) 2553 return -ENOMEM; 2554 2555 skb_put_data(skb, &req_hdr, sizeof(req_hdr)); 2556 skb_put_data(skb, eep + offset, eep_len); 2557 2558 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 2559 MCU_EXT_CMD_EFUSE_BUFFER_MODE, true); 2560} 2561EXPORT_SYMBOL_GPL(mt7615_mcu_set_eeprom); 2562 2563int mt7615_mcu_set_mac_enable(struct mt7615_dev *dev, int band, bool enable) 2564{ 2565 struct { 2566 u8 enable; 2567 u8 band; 2568 u8 rsv[2]; 2569 } __packed req = { 2570 .enable = enable, 2571 .band = band, 2572 }; 2573 2574 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_MAC_INIT_CTRL, 2575 &req, sizeof(req), true); 2576} 2577 2578int mt7615_mcu_set_rts_thresh(struct mt7615_phy *phy, u32 val) 2579{ 2580 struct mt7615_dev *dev = phy->dev; 2581 struct { 2582 u8 prot_idx; 2583 u8 band; 2584 u8 rsv[2]; 2585 __le32 len_thresh; 2586 __le32 pkt_thresh; 2587 } __packed req = { 2588 .prot_idx = 1, 2589 .band = phy != &dev->phy, 2590 .len_thresh = cpu_to_le32(val), 2591 .pkt_thresh = cpu_to_le32(0x2), 2592 }; 2593 2594 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_PROTECT_CTRL, 2595 &req, sizeof(req), true); 2596} 2597 2598int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue, 2599 const struct ieee80211_tx_queue_params *params) 2600{ 2601#define WMM_AIFS_SET BIT(0) 2602#define WMM_CW_MIN_SET BIT(1) 2603#define WMM_CW_MAX_SET BIT(2) 2604#define WMM_TXOP_SET BIT(3) 2605#define WMM_PARAM_SET (WMM_AIFS_SET | WMM_CW_MIN_SET | \ 2606 WMM_CW_MAX_SET | WMM_TXOP_SET) 2607 struct req_data { 2608 u8 number; 2609 u8 rsv[3]; 2610 u8 queue; 2611 u8 valid; 2612 u8 aifs; 2613 u8 cw_min; 2614 __le16 cw_max; 2615 __le16 txop; 2616 } __packed req = { 2617 .number = 1, 2618 .queue = queue, 2619 .valid = WMM_PARAM_SET, 2620 .aifs = params->aifs, 2621 .cw_min = 5, 2622 .cw_max = cpu_to_le16(10), 2623 .txop = cpu_to_le16(params->txop), 2624 }; 2625 2626 if (params->cw_min) 2627 req.cw_min = fls(params->cw_min); 2628 if (params->cw_max) 2629 req.cw_max = cpu_to_le16(fls(params->cw_max)); 2630 2631 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_EDCA_UPDATE, 2632 &req, sizeof(req), true); 2633} 2634 2635int mt7615_mcu_set_dbdc(struct mt7615_dev *dev) 2636{ 2637 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev); 2638 struct dbdc_entry { 2639 u8 type; 2640 u8 index; 2641 u8 band; 2642 u8 _rsv; 2643 }; 2644 struct { 2645 u8 enable; 2646 u8 num; 2647 u8 _rsv[2]; 2648 struct dbdc_entry entry[64]; 2649 } req = { 2650 .enable = !!ext_phy, 2651 }; 2652 int i; 2653 2654 if (!ext_phy) 2655 goto out; 2656 2657#define ADD_DBDC_ENTRY(_type, _idx, _band) \ 2658 do { \ 2659 req.entry[req.num].type = _type; \ 2660 req.entry[req.num].index = _idx; \ 2661 req.entry[req.num++].band = _band; \ 2662 } while (0) 2663 2664 for (i = 0; i < 4; i++) { 2665 bool band = !!(ext_phy->omac_mask & BIT(i)); 2666 2667 ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band); 2668 } 2669 2670 for (i = 0; i < 14; i++) { 2671 bool band = !!(ext_phy->omac_mask & BIT(0x11 + i)); 2672 2673 ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band); 2674 } 2675 2676 ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1); 2677 2678 for (i = 0; i < 3; i++) 2679 ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1); 2680 2681 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0); 2682 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0); 2683 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1); 2684 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1); 2685 2686 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0); 2687 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1); 2688 2689out: 2690 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_DBDC_CTRL, 2691 &req, sizeof(req), true); 2692} 2693 2694int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev) 2695{ 2696 struct wtbl_req_hdr req = { 2697 .operation = WTBL_RESET_ALL, 2698 }; 2699 2700 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_WTBL_UPDATE, 2701 &req, sizeof(req), true); 2702} 2703EXPORT_SYMBOL_GPL(mt7615_mcu_del_wtbl_all); 2704 2705int mt7615_mcu_rdd_cmd(struct mt7615_dev *dev, 2706 enum mt7615_rdd_cmd cmd, u8 index, 2707 u8 rx_sel, u8 val) 2708{ 2709 struct { 2710 u8 ctrl; 2711 u8 rdd_idx; 2712 u8 rdd_rx_sel; 2713 u8 val; 2714 u8 rsv[4]; 2715 } req = { 2716 .ctrl = cmd, 2717 .rdd_idx = index, 2718 .rdd_rx_sel = rx_sel, 2719 .val = val, 2720 }; 2721 2722 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_CTRL, 2723 &req, sizeof(req), true); 2724} 2725 2726int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val) 2727{ 2728 struct { 2729 __le16 tag; 2730 __le16 min_lpn; 2731 } req = { 2732 .tag = cpu_to_le16(0x1), 2733 .min_lpn = cpu_to_le16(val), 2734 }; 2735 2736 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, 2737 &req, sizeof(req), true); 2738} 2739 2740int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev, 2741 const struct mt7615_dfs_pulse *pulse) 2742{ 2743 struct { 2744 __le16 tag; 2745 __le32 max_width; /* us */ 2746 __le32 max_pwr; /* dbm */ 2747 __le32 min_pwr; /* dbm */ 2748 __le32 min_stgr_pri; /* us */ 2749 __le32 max_stgr_pri; /* us */ 2750 __le32 min_cr_pri; /* us */ 2751 __le32 max_cr_pri; /* us */ 2752 } req = { 2753 .tag = cpu_to_le16(0x3), 2754#define __req_field(field) .field = cpu_to_le32(pulse->field) 2755 __req_field(max_width), 2756 __req_field(max_pwr), 2757 __req_field(min_pwr), 2758 __req_field(min_stgr_pri), 2759 __req_field(max_stgr_pri), 2760 __req_field(min_cr_pri), 2761 __req_field(max_cr_pri), 2762#undef __req_field 2763 }; 2764 2765 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, 2766 &req, sizeof(req), true); 2767} 2768 2769int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index, 2770 const struct mt7615_dfs_pattern *pattern) 2771{ 2772 struct { 2773 __le16 tag; 2774 __le16 radar_type; 2775 u8 enb; 2776 u8 stgr; 2777 u8 min_crpn; 2778 u8 max_crpn; 2779 u8 min_crpr; 2780 u8 min_pw; 2781 u8 max_pw; 2782 __le32 min_pri; 2783 __le32 max_pri; 2784 u8 min_crbn; 2785 u8 max_crbn; 2786 u8 min_stgpn; 2787 u8 max_stgpn; 2788 u8 min_stgpr; 2789 } req = { 2790 .tag = cpu_to_le16(0x2), 2791 .radar_type = cpu_to_le16(index), 2792#define __req_field_u8(field) .field = pattern->field 2793#define __req_field_u32(field) .field = cpu_to_le32(pattern->field) 2794 __req_field_u8(enb), 2795 __req_field_u8(stgr), 2796 __req_field_u8(min_crpn), 2797 __req_field_u8(max_crpn), 2798 __req_field_u8(min_crpr), 2799 __req_field_u8(min_pw), 2800 __req_field_u8(max_pw), 2801 __req_field_u32(min_pri), 2802 __req_field_u32(max_pri), 2803 __req_field_u8(min_crbn), 2804 __req_field_u8(max_crbn), 2805 __req_field_u8(min_stgpn), 2806 __req_field_u8(max_stgpn), 2807 __req_field_u8(min_stgpr), 2808#undef __req_field_u8 2809#undef __req_field_u32 2810 }; 2811 2812 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH, 2813 &req, sizeof(req), true); 2814} 2815 2816int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev) 2817{ 2818 struct { 2819 u8 pulse_num; 2820 u8 rsv[3]; 2821 struct { 2822 __le32 start_time; 2823 __le16 width; 2824 __le16 power; 2825 } pattern[32]; 2826 } req = { 2827 .pulse_num = dev->radar_pattern.n_pulses, 2828 }; 2829 u32 start_time = ktime_to_ms(ktime_get_boottime()); 2830 int i; 2831 2832 if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern)) 2833 return -EINVAL; 2834 2835 /* TODO: add some noise here */ 2836 for (i = 0; i < dev->radar_pattern.n_pulses; i++) { 2837 u32 ts = start_time + i * dev->radar_pattern.period; 2838 2839 req.pattern[i].width = cpu_to_le16(dev->radar_pattern.width); 2840 req.pattern[i].power = cpu_to_le16(dev->radar_pattern.power); 2841 req.pattern[i].start_time = cpu_to_le32(ts); 2842 } 2843 2844 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_PATTERN, 2845 &req, sizeof(req), false); 2846} 2847 2848static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku) 2849{ 2850 struct mt76_phy *mphy = phy->mt76; 2851 struct ieee80211_hw *hw = mphy->hw; 2852 int n_chains = hweight8(mphy->antenna_mask); 2853 int tx_power; 2854 int i; 2855 2856 tx_power = hw->conf.power_level * 2 - 2857 mt76_tx_power_nss_delta(n_chains); 2858 mphy->txpower_cur = tx_power; 2859 2860 for (i = 0; i < MT_SKU_1SS_DELTA; i++) 2861 sku[i] = tx_power; 2862 2863 for (i = 0; i < 4; i++) { 2864 int delta = 0; 2865 2866 if (i < n_chains - 1) 2867 delta = mt76_tx_power_nss_delta(n_chains) - 2868 mt76_tx_power_nss_delta(i + 1); 2869 sku[MT_SKU_1SS_DELTA + i] = delta; 2870 } 2871} 2872 2873static u8 mt7615_mcu_chan_bw(struct cfg80211_chan_def *chandef) 2874{ 2875 static const u8 width_to_bw[] = { 2876 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 2877 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 2878 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 2879 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 2880 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 2881 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 2882 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 2883 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 2884 }; 2885 2886 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 2887 return 0; 2888 2889 return width_to_bw[chandef->width]; 2890} 2891 2892int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd) 2893{ 2894 struct mt7615_dev *dev = phy->dev; 2895 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2896 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2; 2897 struct { 2898 u8 control_chan; 2899 u8 center_chan; 2900 u8 bw; 2901 u8 tx_streams; 2902 u8 rx_streams_mask; 2903 u8 switch_reason; 2904 u8 band_idx; 2905 /* for 80+80 only */ 2906 u8 center_chan2; 2907 __le16 cac_case; 2908 u8 channel_band; 2909 u8 rsv0; 2910 __le32 outband_freq; 2911 u8 txpower_drop; 2912 u8 rsv1[3]; 2913 u8 txpower_sku[53]; 2914 u8 rsv2[3]; 2915 } req = { 2916 .control_chan = chandef->chan->hw_value, 2917 .center_chan = ieee80211_frequency_to_channel(freq1), 2918 .tx_streams = hweight8(phy->mt76->antenna_mask), 2919 .rx_streams_mask = phy->chainmask, 2920 .center_chan2 = ieee80211_frequency_to_channel(freq2), 2921 }; 2922 2923 if (dev->mt76.hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 2924 req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD; 2925 else if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) && 2926 chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 2927 req.switch_reason = CH_SWITCH_DFS; 2928 else 2929 req.switch_reason = CH_SWITCH_NORMAL; 2930 2931 req.band_idx = phy != &dev->phy; 2932 req.bw = mt7615_mcu_chan_bw(chandef); 2933 2934 if (mt76_testmode_enabled(&dev->mt76)) 2935 memset(req.txpower_sku, 0x3f, 49); 2936 else 2937 mt7615_mcu_set_txpower_sku(phy, req.txpower_sku); 2938 2939 return __mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true); 2940} 2941 2942int mt7615_mcu_get_temperature(struct mt7615_dev *dev, int index) 2943{ 2944 struct { 2945 u8 action; 2946 u8 rsv[3]; 2947 } req = { 2948 .action = index, 2949 }; 2950 2951 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_GET_TEMP, &req, 2952 sizeof(req), true); 2953} 2954 2955int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode, 2956 u32 val) 2957{ 2958 struct { 2959 u8 test_mode_en; 2960 u8 param_idx; 2961 u8 _rsv[2]; 2962 2963 __le32 value; 2964 2965 u8 pad[8]; 2966 } req = { 2967 .test_mode_en = test_mode, 2968 .param_idx = param, 2969 .value = cpu_to_le32(val), 2970 }; 2971 2972 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_ATE_CTRL, &req, 2973 sizeof(req), false); 2974} 2975 2976int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable) 2977{ 2978 struct mt7615_dev *dev = phy->dev; 2979 struct { 2980 u8 format_id; 2981 u8 sku_enable; 2982 u8 band_idx; 2983 u8 rsv; 2984 } req = { 2985 .format_id = 0, 2986 .band_idx = phy != &dev->phy, 2987 .sku_enable = enable, 2988 }; 2989 2990 return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_TX_POWER_FEATURE_CTRL, &req, 2991 sizeof(req), true); 2992} 2993 2994int mt7615_mcu_set_vif_ps(struct mt7615_dev *dev, struct ieee80211_vif *vif) 2995{ 2996 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 2997 struct { 2998 u8 bss_idx; 2999 u8 ps_state; /* 0: device awake 3000 * 1: static power save 3001 * 2: dynamic power saving 3002 */ 3003 } req = { 3004 .bss_idx = mvif->idx, 3005 .ps_state = vif->bss_conf.ps ? 2 : 0, 3006 }; 3007 3008 if (vif->type != NL80211_IFTYPE_STATION) 3009 return -ENOTSUPP; 3010 3011 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_PS_PROFILE, 3012 &req, sizeof(req), false); 3013} 3014 3015int mt7615_mcu_set_channel_domain(struct mt7615_phy *phy) 3016{ 3017 struct mt76_phy *mphy = phy->mt76; 3018 struct mt7615_dev *dev = phy->dev; 3019 struct mt7615_mcu_channel_domain { 3020 __le32 country_code; /* regulatory_request.alpha2 */ 3021 u8 bw_2g; /* BW_20_40M 0 3022 * BW_20M 1 3023 * BW_20_40_80M 2 3024 * BW_20_40_80_160M 3 3025 * BW_20_40_80_8080M 4 3026 */ 3027 u8 bw_5g; 3028 __le16 pad; 3029 u8 n_2ch; 3030 u8 n_5ch; 3031 __le16 pad2; 3032 } __packed hdr = { 3033 .bw_2g = 0, 3034 .bw_5g = 3, 3035 .n_2ch = mphy->sband_2g.sband.n_channels, 3036 .n_5ch = mphy->sband_5g.sband.n_channels, 3037 }; 3038 struct mt7615_mcu_chan { 3039 __le16 hw_value; 3040 __le16 pad; 3041 __le32 flags; 3042 } __packed; 3043 int i, n_channels = hdr.n_2ch + hdr.n_5ch; 3044 int len = sizeof(hdr) + n_channels * sizeof(struct mt7615_mcu_chan); 3045 struct sk_buff *skb; 3046 3047 if (!mt7615_firmware_offload(dev)) 3048 return 0; 3049 3050 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, len); 3051 if (!skb) 3052 return -ENOMEM; 3053 3054 skb_put_data(skb, &hdr, sizeof(hdr)); 3055 3056 for (i = 0; i < n_channels; i++) { 3057 struct ieee80211_channel *chan; 3058 struct mt7615_mcu_chan channel; 3059 3060 if (i < hdr.n_2ch) 3061 chan = &mphy->sband_2g.sband.channels[i]; 3062 else 3063 chan = &mphy->sband_5g.sband.channels[i - hdr.n_2ch]; 3064 3065 channel.hw_value = cpu_to_le16(chan->hw_value); 3066 channel.flags = cpu_to_le32(chan->flags); 3067 channel.pad = 0; 3068 3069 skb_put_data(skb, &channel, sizeof(channel)); 3070 } 3071 3072 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 3073 MCU_CMD_SET_CHAN_DOMAIN, false); 3074} 3075 3076#define MT7615_SCAN_CHANNEL_TIME 60 3077int mt7615_mcu_hw_scan(struct mt7615_phy *phy, struct ieee80211_vif *vif, 3078 struct ieee80211_scan_request *scan_req) 3079{ 3080 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3081 struct cfg80211_scan_request *sreq = &scan_req->req; 3082 int n_ssids = 0, err, i, duration = MT7615_SCAN_CHANNEL_TIME; 3083 int ext_channels_num = max_t(int, sreq->n_channels - 32, 0); 3084 struct ieee80211_channel **scan_list = sreq->channels; 3085 struct mt7615_dev *dev = phy->dev; 3086 bool ext_phy = phy != &dev->phy; 3087 struct mt7615_mcu_scan_channel *chan; 3088 struct mt7615_hw_scan_req *req; 3089 struct sk_buff *skb; 3090 3091 /* fall-back to sw-scan */ 3092 if (!mt7615_firmware_offload(dev)) 3093 return 1; 3094 3095 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(*req)); 3096 if (!skb) 3097 return -ENOMEM; 3098 3099 set_bit(MT76_HW_SCANNING, &phy->mt76->state); 3100 mvif->scan_seq_num = (mvif->scan_seq_num + 1) & 0x7f; 3101 3102 req = (struct mt7615_hw_scan_req *)skb_put(skb, sizeof(*req)); 3103 3104 req->seq_num = mvif->scan_seq_num | ext_phy << 7; 3105 req->bss_idx = mvif->idx; 3106 req->scan_type = sreq->n_ssids ? 1 : 0; 3107 req->probe_req_num = sreq->n_ssids ? 2 : 0; 3108 req->version = 1; 3109 3110 for (i = 0; i < sreq->n_ssids; i++) { 3111 if (!sreq->ssids[i].ssid_len) 3112 continue; 3113 3114 req->ssids[i].ssid_len = cpu_to_le32(sreq->ssids[i].ssid_len); 3115 memcpy(req->ssids[i].ssid, sreq->ssids[i].ssid, 3116 sreq->ssids[i].ssid_len); 3117 n_ssids++; 3118 } 3119 req->ssid_type = n_ssids ? BIT(2) : BIT(0); 3120 req->ssid_type_ext = n_ssids ? BIT(0) : 0; 3121 req->ssids_num = n_ssids; 3122 3123 /* increase channel time for passive scan */ 3124 if (!sreq->n_ssids) 3125 duration *= 2; 3126 req->timeout_value = cpu_to_le16(sreq->n_channels * duration); 3127 req->channel_min_dwell_time = cpu_to_le16(duration); 3128 req->channel_dwell_time = cpu_to_le16(duration); 3129 3130 req->channels_num = min_t(u8, sreq->n_channels, 32); 3131 req->ext_channels_num = min_t(u8, ext_channels_num, 32); 3132 for (i = 0; i < req->channels_num + req->ext_channels_num; i++) { 3133 if (i >= 32) 3134 chan = &req->ext_channels[i - 32]; 3135 else 3136 chan = &req->channels[i]; 3137 3138 chan->band = scan_list[i]->band == NL80211_BAND_2GHZ ? 1 : 2; 3139 chan->channel_num = scan_list[i]->hw_value; 3140 } 3141 req->channel_type = sreq->n_channels ? 4 : 0; 3142 3143 if (sreq->ie_len > 0) { 3144 memcpy(req->ies, sreq->ie, sreq->ie_len); 3145 req->ies_len = cpu_to_le16(sreq->ie_len); 3146 } 3147 3148 memcpy(req->bssid, sreq->bssid, ETH_ALEN); 3149 if (sreq->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { 3150 get_random_mask_addr(req->random_mac, sreq->mac_addr, 3151 sreq->mac_addr_mask); 3152 req->scan_func = 1; 3153 } 3154 3155 err = __mt76_mcu_skb_send_msg(&dev->mt76, skb, MCU_CMD_START_HW_SCAN, 3156 false); 3157 if (err < 0) 3158 clear_bit(MT76_HW_SCANNING, &phy->mt76->state); 3159 3160 return err; 3161} 3162 3163int mt7615_mcu_cancel_hw_scan(struct mt7615_phy *phy, 3164 struct ieee80211_vif *vif) 3165{ 3166 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3167 struct mt7615_dev *dev = phy->dev; 3168 struct { 3169 u8 seq_num; 3170 u8 is_ext_channel; 3171 u8 rsv[2]; 3172 } __packed req = { 3173 .seq_num = mvif->scan_seq_num, 3174 }; 3175 3176 if (test_and_clear_bit(MT76_HW_SCANNING, &phy->mt76->state)) { 3177 struct cfg80211_scan_info info = { 3178 .aborted = true, 3179 }; 3180 3181 ieee80211_scan_completed(phy->mt76->hw, &info); 3182 } 3183 3184 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_CANCEL_HW_SCAN, &req, 3185 sizeof(req), false); 3186} 3187 3188int mt7615_mcu_sched_scan_req(struct mt7615_phy *phy, 3189 struct ieee80211_vif *vif, 3190 struct cfg80211_sched_scan_request *sreq) 3191{ 3192 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3193 struct ieee80211_channel **scan_list = sreq->channels; 3194 struct mt7615_dev *dev = phy->dev; 3195 bool ext_phy = phy != &dev->phy; 3196 struct mt7615_mcu_scan_channel *chan; 3197 struct mt7615_sched_scan_req *req; 3198 struct cfg80211_match_set *match; 3199 struct cfg80211_ssid *ssid; 3200 struct sk_buff *skb; 3201 int i; 3202 3203 if (!mt7615_firmware_offload(dev)) 3204 return -ENOTSUPP; 3205 3206 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, 3207 sizeof(*req) + sreq->ie_len); 3208 if (!skb) 3209 return -ENOMEM; 3210 3211 mvif->scan_seq_num = (mvif->scan_seq_num + 1) & 0x7f; 3212 3213 req = (struct mt7615_sched_scan_req *)skb_put(skb, sizeof(*req)); 3214 req->version = 1; 3215 req->seq_num = mvif->scan_seq_num | ext_phy << 7; 3216 3217 if (sreq->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { 3218 get_random_mask_addr(req->random_mac, sreq->mac_addr, 3219 sreq->mac_addr_mask); 3220 req->scan_func = 1; 3221 } 3222 3223 req->ssids_num = sreq->n_ssids; 3224 for (i = 0; i < req->ssids_num; i++) { 3225 ssid = &sreq->ssids[i]; 3226 memcpy(req->ssids[i].ssid, ssid->ssid, ssid->ssid_len); 3227 req->ssids[i].ssid_len = cpu_to_le32(ssid->ssid_len); 3228 } 3229 3230 req->match_num = sreq->n_match_sets; 3231 for (i = 0; i < req->match_num; i++) { 3232 match = &sreq->match_sets[i]; 3233 memcpy(req->match[i].ssid, match->ssid.ssid, 3234 match->ssid.ssid_len); 3235 req->match[i].rssi_th = cpu_to_le32(match->rssi_thold); 3236 req->match[i].ssid_len = match->ssid.ssid_len; 3237 } 3238 3239 req->channel_type = sreq->n_channels ? 4 : 0; 3240 req->channels_num = min_t(u8, sreq->n_channels, 64); 3241 for (i = 0; i < req->channels_num; i++) { 3242 chan = &req->channels[i]; 3243 chan->band = scan_list[i]->band == NL80211_BAND_2GHZ ? 1 : 2; 3244 chan->channel_num = scan_list[i]->hw_value; 3245 } 3246 3247 req->intervals_num = sreq->n_scan_plans; 3248 for (i = 0; i < req->intervals_num; i++) 3249 req->intervals[i] = cpu_to_le16(sreq->scan_plans[i].interval); 3250 3251 if (sreq->ie_len > 0) { 3252 req->ie_len = cpu_to_le16(sreq->ie_len); 3253 memcpy(skb_put(skb, sreq->ie_len), sreq->ie, sreq->ie_len); 3254 } 3255 3256 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 3257 MCU_CMD_SCHED_SCAN_REQ, false); 3258} 3259 3260int mt7615_mcu_sched_scan_enable(struct mt7615_phy *phy, 3261 struct ieee80211_vif *vif, 3262 bool enable) 3263{ 3264 struct mt7615_dev *dev = phy->dev; 3265 struct { 3266 u8 active; /* 0: enabled 1: disabled */ 3267 u8 rsv[3]; 3268 } __packed req = { 3269 .active = !enable, 3270 }; 3271 3272 if (!mt7615_firmware_offload(dev)) 3273 return -ENOTSUPP; 3274 3275 if (enable) 3276 set_bit(MT76_HW_SCHED_SCANNING, &phy->mt76->state); 3277 else 3278 clear_bit(MT76_HW_SCHED_SCANNING, &phy->mt76->state); 3279 3280 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SCHED_SCAN_ENABLE, 3281 &req, sizeof(req), false); 3282} 3283 3284static int mt7615_find_freq_idx(const u16 *freqs, int n_freqs, u16 cur) 3285{ 3286 int i; 3287 3288 for (i = 0; i < n_freqs; i++) 3289 if (cur == freqs[i]) 3290 return i; 3291 3292 return -1; 3293} 3294 3295static int mt7615_dcoc_freq_idx(u16 freq, u8 bw) 3296{ 3297 static const u16 freq_list[] = { 3298 4980, 5805, 5905, 5190, 3299 5230, 5270, 5310, 5350, 3300 5390, 5430, 5470, 5510, 3301 5550, 5590, 5630, 5670, 3302 5710, 5755, 5795, 5835, 3303 5875, 5210, 5290, 5370, 3304 5450, 5530, 5610, 5690, 3305 5775, 5855 3306 }; 3307 static const u16 freq_bw40[] = { 3308 5190, 5230, 5270, 5310, 3309 5350, 5390, 5430, 5470, 3310 5510, 5550, 5590, 5630, 3311 5670, 5710, 5755, 5795, 3312 5835, 5875 3313 }; 3314 int offset_2g = ARRAY_SIZE(freq_list); 3315 int idx; 3316 3317 if (freq < 4000) { 3318 if (freq < 2427) 3319 return offset_2g; 3320 if (freq < 2442) 3321 return offset_2g + 1; 3322 if (freq < 2457) 3323 return offset_2g + 2; 3324 3325 return offset_2g + 3; 3326 } 3327 3328 switch (bw) { 3329 case NL80211_CHAN_WIDTH_80: 3330 case NL80211_CHAN_WIDTH_80P80: 3331 case NL80211_CHAN_WIDTH_160: 3332 break; 3333 default: 3334 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 3335 freq + 10); 3336 if (idx >= 0) { 3337 freq = freq_bw40[idx]; 3338 break; 3339 } 3340 3341 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 3342 freq - 10); 3343 if (idx >= 0) { 3344 freq = freq_bw40[idx]; 3345 break; 3346 } 3347 fallthrough; 3348 case NL80211_CHAN_WIDTH_40: 3349 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 3350 freq); 3351 if (idx >= 0) 3352 break; 3353 3354 return -1; 3355 3356 } 3357 3358 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq); 3359} 3360 3361int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy) 3362{ 3363 struct mt7615_dev *dev = phy->dev; 3364 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 3365 int freq2 = chandef->center_freq2; 3366 int ret; 3367 struct { 3368 u8 direction; 3369 u8 runtime_calibration; 3370 u8 _rsv[2]; 3371 3372 __le16 center_freq; 3373 u8 bw; 3374 u8 band; 3375 u8 is_freq2; 3376 u8 success; 3377 u8 dbdc_en; 3378 3379 u8 _rsv2; 3380 3381 struct { 3382 __le32 sx0_i_lna[4]; 3383 __le32 sx0_q_lna[4]; 3384 3385 __le32 sx2_i_lna[4]; 3386 __le32 sx2_q_lna[4]; 3387 } dcoc_data[4]; 3388 } req = { 3389 .direction = 1, 3390 3391 .bw = mt7615_mcu_chan_bw(chandef), 3392 .band = chandef->center_freq1 > 4000, 3393 .dbdc_en = !!dev->mt76.phy2, 3394 }; 3395 u16 center_freq = chandef->center_freq1; 3396 int freq_idx; 3397 u8 *eep = dev->mt76.eeprom.data; 3398 3399 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_RX_CAL)) 3400 return 0; 3401 3402 if (chandef->width == NL80211_CHAN_WIDTH_160) { 3403 freq2 = center_freq + 40; 3404 center_freq -= 40; 3405 } 3406 3407again: 3408 req.runtime_calibration = 1; 3409 freq_idx = mt7615_dcoc_freq_idx(center_freq, chandef->width); 3410 if (freq_idx < 0) 3411 goto out; 3412 3413 memcpy(req.dcoc_data, eep + MT7615_EEPROM_DCOC_OFFSET + 3414 freq_idx * MT7615_EEPROM_DCOC_SIZE, 3415 sizeof(req.dcoc_data)); 3416 req.runtime_calibration = 0; 3417 3418out: 3419 req.center_freq = cpu_to_le16(center_freq); 3420 ret = __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_RXDCOC_CAL, &req, 3421 sizeof(req), true); 3422 3423 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 || 3424 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) { 3425 req.is_freq2 = true; 3426 center_freq = freq2; 3427 goto again; 3428 } 3429 3430 return ret; 3431} 3432 3433static int mt7615_dpd_freq_idx(u16 freq, u8 bw) 3434{ 3435 static const u16 freq_list[] = { 3436 4920, 4940, 4960, 4980, 3437 5040, 5060, 5080, 5180, 3438 5200, 5220, 5240, 5260, 3439 5280, 5300, 5320, 5340, 3440 5360, 5380, 5400, 5420, 3441 5440, 5460, 5480, 5500, 3442 5520, 5540, 5560, 5580, 3443 5600, 5620, 5640, 5660, 3444 5680, 5700, 5720, 5745, 3445 5765, 5785, 5805, 5825, 3446 5845, 5865, 5885, 5905 3447 }; 3448 int offset_2g = ARRAY_SIZE(freq_list); 3449 int idx; 3450 3451 if (freq < 4000) { 3452 if (freq < 2432) 3453 return offset_2g; 3454 if (freq < 2457) 3455 return offset_2g + 1; 3456 3457 return offset_2g + 2; 3458 } 3459 3460 if (bw != NL80211_CHAN_WIDTH_20) { 3461 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), 3462 freq + 10); 3463 if (idx >= 0) 3464 return idx; 3465 3466 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), 3467 freq - 10); 3468 if (idx >= 0) 3469 return idx; 3470 } 3471 3472 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq); 3473} 3474 3475 3476int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy) 3477{ 3478 struct mt7615_dev *dev = phy->dev; 3479 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 3480 int freq2 = chandef->center_freq2; 3481 int ret; 3482 struct { 3483 u8 direction; 3484 u8 runtime_calibration; 3485 u8 _rsv[2]; 3486 3487 __le16 center_freq; 3488 u8 bw; 3489 u8 band; 3490 u8 is_freq2; 3491 u8 success; 3492 u8 dbdc_en; 3493 3494 u8 _rsv2; 3495 3496 struct { 3497 struct { 3498 u32 dpd_g0; 3499 u8 data[32]; 3500 } wf0, wf1; 3501 3502 struct { 3503 u32 dpd_g0_prim; 3504 u32 dpd_g0_sec; 3505 u8 data_prim[32]; 3506 u8 data_sec[32]; 3507 } wf2, wf3; 3508 } dpd_data; 3509 } req = { 3510 .direction = 1, 3511 3512 .bw = mt7615_mcu_chan_bw(chandef), 3513 .band = chandef->center_freq1 > 4000, 3514 .dbdc_en = !!dev->mt76.phy2, 3515 }; 3516 u16 center_freq = chandef->center_freq1; 3517 int freq_idx; 3518 u8 *eep = dev->mt76.eeprom.data; 3519 3520 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_TX_DPD)) 3521 return 0; 3522 3523 if (chandef->width == NL80211_CHAN_WIDTH_160) { 3524 freq2 = center_freq + 40; 3525 center_freq -= 40; 3526 } 3527 3528again: 3529 req.runtime_calibration = 1; 3530 freq_idx = mt7615_dpd_freq_idx(center_freq, chandef->width); 3531 if (freq_idx < 0) 3532 goto out; 3533 3534 memcpy(&req.dpd_data, eep + MT7615_EEPROM_TXDPD_OFFSET + 3535 freq_idx * MT7615_EEPROM_TXDPD_SIZE, 3536 sizeof(req.dpd_data)); 3537 req.runtime_calibration = 0; 3538 3539out: 3540 req.center_freq = cpu_to_le16(center_freq); 3541 ret = __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_TXDPD_CAL, &req, 3542 sizeof(req), true); 3543 3544 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 || 3545 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) { 3546 req.is_freq2 = true; 3547 center_freq = freq2; 3548 goto again; 3549 } 3550 3551 return ret; 3552} 3553 3554int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif, 3555 bool enable) 3556{ 3557 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3558 struct { 3559 u8 bss_idx; 3560 u8 dtim_period; 3561 __le16 aid; 3562 __le16 bcn_interval; 3563 __le16 atim_window; 3564 u8 uapsd; 3565 u8 bmc_delivered_ac; 3566 u8 bmc_triggered_ac; 3567 u8 pad; 3568 } req = { 3569 .bss_idx = mvif->idx, 3570 .aid = cpu_to_le16(vif->bss_conf.aid), 3571 .dtim_period = vif->bss_conf.dtim_period, 3572 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int), 3573 }; 3574 struct { 3575 u8 bss_idx; 3576 u8 pad[3]; 3577 } req_hdr = { 3578 .bss_idx = mvif->idx, 3579 }; 3580 int err; 3581 3582 if (vif->type != NL80211_IFTYPE_STATION || 3583 !mt7615_firmware_offload(dev)) 3584 return -ENOTSUPP; 3585 3586 err = __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_BSS_ABORT, 3587 &req_hdr, sizeof(req_hdr), false); 3588 if (err < 0 || !enable) 3589 return err; 3590 3591 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_BSS_CONNECTED, 3592 &req, sizeof(req), false); 3593} 3594 3595#ifdef CONFIG_PM 3596int mt7615_mcu_set_hif_suspend(struct mt7615_dev *dev, bool suspend) 3597{ 3598 struct { 3599 struct { 3600 u8 hif_type; /* 0x0: HIF_SDIO 3601 * 0x1: HIF_USB 3602 * 0x2: HIF_PCIE 3603 */ 3604 u8 pad[3]; 3605 } __packed hdr; 3606 struct hif_suspend_tlv { 3607 __le16 tag; 3608 __le16 len; 3609 u8 suspend; 3610 } __packed hif_suspend; 3611 } req = { 3612 .hif_suspend = { 3613 .tag = cpu_to_le16(0), /* 0: UNI_HIF_CTRL_BASIC */ 3614 .len = cpu_to_le16(sizeof(struct hif_suspend_tlv)), 3615 .suspend = suspend, 3616 }, 3617 }; 3618 3619 if (mt76_is_mmio(&dev->mt76)) 3620 req.hdr.hif_type = 2; 3621 else if (mt76_is_usb(&dev->mt76)) 3622 req.hdr.hif_type = 1; 3623 3624 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_HIF_CTRL, 3625 &req, sizeof(req), true); 3626} 3627EXPORT_SYMBOL_GPL(mt7615_mcu_set_hif_suspend); 3628 3629static int 3630mt7615_mcu_set_wow_ctrl(struct mt7615_phy *phy, struct ieee80211_vif *vif, 3631 bool suspend, struct cfg80211_wowlan *wowlan) 3632{ 3633 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3634 struct mt7615_dev *dev = phy->dev; 3635 struct { 3636 struct { 3637 u8 bss_idx; 3638 u8 pad[3]; 3639 } __packed hdr; 3640 struct mt7615_wow_ctrl_tlv wow_ctrl_tlv; 3641 } req = { 3642 .hdr = { 3643 .bss_idx = mvif->idx, 3644 }, 3645 .wow_ctrl_tlv = { 3646 .tag = cpu_to_le16(UNI_SUSPEND_WOW_CTRL), 3647 .len = cpu_to_le16(sizeof(struct mt7615_wow_ctrl_tlv)), 3648 .cmd = suspend ? 1 : 2, 3649 }, 3650 }; 3651 3652 if (wowlan->magic_pkt) 3653 req.wow_ctrl_tlv.trigger |= BIT(0); 3654 if (wowlan->disconnect) 3655 req.wow_ctrl_tlv.trigger |= BIT(2); 3656 if (wowlan->nd_config) { 3657 mt7615_mcu_sched_scan_req(phy, vif, wowlan->nd_config); 3658 req.wow_ctrl_tlv.trigger |= BIT(5); 3659 mt7615_mcu_sched_scan_enable(phy, vif, suspend); 3660 } 3661 3662 if (mt76_is_mmio(&dev->mt76)) 3663 req.wow_ctrl_tlv.wakeup_hif = 2; 3664 else if (mt76_is_usb(&dev->mt76)) 3665 req.wow_ctrl_tlv.wakeup_hif = 1; 3666 3667 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_SUSPEND, 3668 &req, sizeof(req), true); 3669} 3670 3671static int 3672mt7615_mcu_set_wow_pattern(struct mt7615_dev *dev, 3673 struct ieee80211_vif *vif, 3674 u8 index, bool enable, 3675 struct cfg80211_pkt_pattern *pattern) 3676{ 3677 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3678 struct mt7615_wow_pattern_tlv *ptlv; 3679 struct sk_buff *skb; 3680 struct req_hdr { 3681 u8 bss_idx; 3682 u8 pad[3]; 3683 } __packed hdr = { 3684 .bss_idx = mvif->idx, 3685 }; 3686 3687 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, 3688 sizeof(hdr) + sizeof(*ptlv)); 3689 if (!skb) 3690 return -ENOMEM; 3691 3692 skb_put_data(skb, &hdr, sizeof(hdr)); 3693 ptlv = (struct mt7615_wow_pattern_tlv *)skb_put(skb, sizeof(*ptlv)); 3694 ptlv->tag = cpu_to_le16(UNI_SUSPEND_WOW_PATTERN); 3695 ptlv->len = cpu_to_le16(sizeof(*ptlv)); 3696 ptlv->data_len = pattern->pattern_len; 3697 ptlv->enable = enable; 3698 ptlv->index = index; 3699 3700 memcpy(ptlv->pattern, pattern->pattern, pattern->pattern_len); 3701 memcpy(ptlv->mask, pattern->mask, pattern->pattern_len / 8); 3702 3703 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 3704 MCU_UNI_CMD_SUSPEND, true); 3705} 3706 3707static int 3708mt7615_mcu_set_suspend_mode(struct mt7615_dev *dev, 3709 struct ieee80211_vif *vif, 3710 bool enable, u8 mdtim, bool wow_suspend) 3711{ 3712 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3713 struct { 3714 struct { 3715 u8 bss_idx; 3716 u8 pad[3]; 3717 } __packed hdr; 3718 struct mt7615_suspend_tlv suspend_tlv; 3719 } req = { 3720 .hdr = { 3721 .bss_idx = mvif->idx, 3722 }, 3723 .suspend_tlv = { 3724 .tag = cpu_to_le16(UNI_SUSPEND_MODE_SETTING), 3725 .len = cpu_to_le16(sizeof(struct mt7615_suspend_tlv)), 3726 .enable = enable, 3727 .mdtim = mdtim, 3728 .wow_suspend = wow_suspend, 3729 }, 3730 }; 3731 3732 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_SUSPEND, 3733 &req, sizeof(req), true); 3734} 3735 3736static int 3737mt7615_mcu_set_gtk_rekey(struct mt7615_dev *dev, 3738 struct ieee80211_vif *vif, 3739 bool suspend) 3740{ 3741 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3742 struct { 3743 struct { 3744 u8 bss_idx; 3745 u8 pad[3]; 3746 } __packed hdr; 3747 struct mt7615_gtk_rekey_tlv gtk_tlv; 3748 } __packed req = { 3749 .hdr = { 3750 .bss_idx = mvif->idx, 3751 }, 3752 .gtk_tlv = { 3753 .tag = cpu_to_le16(UNI_OFFLOAD_OFFLOAD_GTK_REKEY), 3754 .len = cpu_to_le16(sizeof(struct mt7615_gtk_rekey_tlv)), 3755 .rekey_mode = !suspend, 3756 }, 3757 }; 3758 3759 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_OFFLOAD, 3760 &req, sizeof(req), true); 3761} 3762 3763static int 3764mt7615_mcu_set_arp_filter(struct mt7615_dev *dev, struct ieee80211_vif *vif, 3765 bool suspend) 3766{ 3767 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3768 struct { 3769 struct { 3770 u8 bss_idx; 3771 u8 pad[3]; 3772 } __packed hdr; 3773 struct mt7615_arpns_tlv arpns; 3774 } req = { 3775 .hdr = { 3776 .bss_idx = mvif->idx, 3777 }, 3778 .arpns = { 3779 .tag = cpu_to_le16(UNI_OFFLOAD_OFFLOAD_ARP), 3780 .len = cpu_to_le16(sizeof(struct mt7615_arpns_tlv)), 3781 .mode = suspend, 3782 }, 3783 }; 3784 3785 return __mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD_OFFLOAD, 3786 &req, sizeof(req), true); 3787} 3788 3789void mt7615_mcu_set_suspend_iter(void *priv, u8 *mac, 3790 struct ieee80211_vif *vif) 3791{ 3792 struct mt7615_phy *phy = priv; 3793 bool suspend = test_bit(MT76_STATE_SUSPEND, &phy->mt76->state); 3794 struct ieee80211_hw *hw = phy->mt76->hw; 3795 struct cfg80211_wowlan *wowlan = hw->wiphy->wowlan_config; 3796 int i; 3797 3798 mt7615_mcu_set_bss_pm(phy->dev, vif, suspend); 3799 3800 mt7615_mcu_set_gtk_rekey(phy->dev, vif, suspend); 3801 mt7615_mcu_set_arp_filter(phy->dev, vif, suspend); 3802 3803 mt7615_mcu_set_suspend_mode(phy->dev, vif, suspend, 1, true); 3804 3805 for (i = 0; i < wowlan->n_patterns; i++) 3806 mt7615_mcu_set_wow_pattern(phy->dev, vif, i, suspend, 3807 &wowlan->patterns[i]); 3808 mt7615_mcu_set_wow_ctrl(phy, vif, suspend, wowlan); 3809} 3810 3811static void 3812mt7615_mcu_key_iter(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 3813 struct ieee80211_sta *sta, struct ieee80211_key_conf *key, 3814 void *data) 3815{ 3816 struct mt7615_gtk_rekey_tlv *gtk_tlv = data; 3817 u32 cipher; 3818 3819 if (key->cipher != WLAN_CIPHER_SUITE_AES_CMAC && 3820 key->cipher != WLAN_CIPHER_SUITE_CCMP && 3821 key->cipher != WLAN_CIPHER_SUITE_TKIP) 3822 return; 3823 3824 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) { 3825 gtk_tlv->proto = cpu_to_le32(NL80211_WPA_VERSION_1); 3826 cipher = BIT(3); 3827 } else { 3828 gtk_tlv->proto = cpu_to_le32(NL80211_WPA_VERSION_2); 3829 cipher = BIT(4); 3830 } 3831 3832 /* we are assuming here to have a single pairwise key */ 3833 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 3834 gtk_tlv->pairwise_cipher = cpu_to_le32(cipher); 3835 gtk_tlv->group_cipher = cpu_to_le32(cipher); 3836 gtk_tlv->keyid = key->keyidx; 3837 } 3838} 3839 3840int mt7615_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 3841 struct ieee80211_vif *vif, 3842 struct cfg80211_gtk_rekey_data *key) 3843{ 3844 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3845 struct mt7615_dev *dev = mt7615_hw_dev(hw); 3846 struct mt7615_gtk_rekey_tlv *gtk_tlv; 3847 struct sk_buff *skb; 3848 struct { 3849 u8 bss_idx; 3850 u8 pad[3]; 3851 } __packed hdr = { 3852 .bss_idx = mvif->idx, 3853 }; 3854 3855 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, 3856 sizeof(hdr) + sizeof(*gtk_tlv)); 3857 if (!skb) 3858 return -ENOMEM; 3859 3860 skb_put_data(skb, &hdr, sizeof(hdr)); 3861 gtk_tlv = (struct mt7615_gtk_rekey_tlv *)skb_put(skb, 3862 sizeof(*gtk_tlv)); 3863 gtk_tlv->tag = cpu_to_le16(UNI_OFFLOAD_OFFLOAD_GTK_REKEY); 3864 gtk_tlv->len = cpu_to_le16(sizeof(*gtk_tlv)); 3865 gtk_tlv->rekey_mode = 2; 3866 gtk_tlv->option = 1; 3867 3868 rcu_read_lock(); 3869 ieee80211_iter_keys_rcu(hw, vif, mt7615_mcu_key_iter, gtk_tlv); 3870 rcu_read_unlock(); 3871 3872 memcpy(gtk_tlv->kek, key->kek, NL80211_KEK_LEN); 3873 memcpy(gtk_tlv->kck, key->kck, NL80211_KCK_LEN); 3874 memcpy(gtk_tlv->replay_ctr, key->replay_ctr, NL80211_REPLAY_CTR_LEN); 3875 3876 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 3877 MCU_UNI_CMD_OFFLOAD, true); 3878} 3879#endif /* CONFIG_PM */ 3880 3881int mt7615_mcu_set_roc(struct mt7615_phy *phy, struct ieee80211_vif *vif, 3882 struct ieee80211_channel *chan, int duration) 3883{ 3884 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3885 struct mt7615_dev *dev = phy->dev; 3886 struct mt7615_roc_tlv req = { 3887 .bss_idx = mvif->idx, 3888 .active = !chan, 3889 .max_interval = cpu_to_le32(duration), 3890 .primary_chan = chan ? chan->hw_value : 0, 3891 .band = chan ? chan->band : 0, 3892 .req_type = 2, 3893 }; 3894 3895 phy->roc_grant = false; 3896 3897 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_ROC, &req, 3898 sizeof(req), false); 3899} 3900 3901int mt7615_mcu_update_arp_filter(struct ieee80211_hw *hw, 3902 struct ieee80211_vif *vif, 3903 struct ieee80211_bss_conf *info) 3904{ 3905 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3906 struct mt7615_dev *dev = mt7615_hw_dev(hw); 3907 struct sk_buff *skb; 3908 int i, len = min_t(int, info->arp_addr_cnt, 3909 IEEE80211_BSS_ARP_ADDR_LIST_LEN); 3910 struct { 3911 struct { 3912 u8 bss_idx; 3913 u8 pad[3]; 3914 } __packed hdr; 3915 struct mt7615_arpns_tlv arp; 3916 } req_hdr = { 3917 .hdr = { 3918 .bss_idx = mvif->idx, 3919 }, 3920 .arp = { 3921 .tag = cpu_to_le16(UNI_OFFLOAD_OFFLOAD_ARP), 3922 .len = cpu_to_le16(sizeof(struct mt7615_arpns_tlv)), 3923 .ips_num = len, 3924 .mode = 2, /* update */ 3925 .option = 1, 3926 }, 3927 }; 3928 3929 if (!mt7615_firmware_offload(dev)) 3930 return 0; 3931 3932 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, 3933 sizeof(req_hdr) + len * sizeof(__be32)); 3934 if (!skb) 3935 return -ENOMEM; 3936 3937 skb_put_data(skb, &req_hdr, sizeof(req_hdr)); 3938 for (i = 0; i < len; i++) { 3939 u8 *addr = (u8 *)skb_put(skb, sizeof(__be32)); 3940 3941 memcpy(addr, &info->arp_addr_list[i], sizeof(__be32)); 3942 } 3943 3944 return __mt76_mcu_skb_send_msg(&dev->mt76, skb, 3945 MCU_UNI_CMD_OFFLOAD, true); 3946} 3947 3948int mt7615_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 3949 struct ieee80211_vif *vif) 3950{ 3951 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 3952 int ct_window = vif->bss_conf.p2p_noa_attr.oppps_ctwindow; 3953 struct mt7615_dev *dev = mt7615_hw_dev(hw); 3954 struct { 3955 __le32 ct_win; 3956 u8 bss_idx; 3957 u8 rsv[3]; 3958 } __packed req = { 3959 .ct_win = cpu_to_le32(ct_window), 3960 .bss_idx = mvif->idx, 3961 }; 3962 3963 if (!mt7615_firmware_offload(dev)) 3964 return -ENOTSUPP; 3965 3966 return __mt76_mcu_send_msg(&dev->mt76, MCU_CMD_SET_P2P_OPPPS, 3967 &req, sizeof(req), false); 3968} 3969 3970u32 mt7615_mcu_reg_rr(struct mt76_dev *dev, u32 offset) 3971{ 3972 struct { 3973 __le32 addr; 3974 __le32 val; 3975 } __packed req = { 3976 .addr = cpu_to_le32(offset), 3977 }; 3978 3979 return __mt76_mcu_send_msg(dev, MCU_CMD_REG_READ, 3980 &req, sizeof(req), true); 3981} 3982EXPORT_SYMBOL_GPL(mt7615_mcu_reg_rr); 3983 3984void mt7615_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val) 3985{ 3986 struct { 3987 __le32 addr; 3988 __le32 val; 3989 } __packed req = { 3990 .addr = cpu_to_le32(offset), 3991 .val = cpu_to_le32(val), 3992 }; 3993 3994 __mt76_mcu_send_msg(dev, MCU_CMD_REG_WRITE, 3995 &req, sizeof(req), false); 3996} 3997EXPORT_SYMBOL_GPL(mt7615_mcu_reg_wr); 3998