1// SPDX-License-Identifier: ISC 2 3#include <linux/etherdevice.h> 4#include <linux/timekeeping.h> 5#include "mt7603.h" 6#include "mac.h" 7#include "../trace.h" 8 9#define MT_PSE_PAGE_SIZE 128 10 11static u32 12mt7603_ac_queue_mask0(u32 mask) 13{ 14 u32 ret = 0; 15 16 ret |= GENMASK(3, 0) * !!(mask & BIT(0)); 17 ret |= GENMASK(8, 5) * !!(mask & BIT(1)); 18 ret |= GENMASK(13, 10) * !!(mask & BIT(2)); 19 ret |= GENMASK(19, 16) * !!(mask & BIT(3)); 20 return ret; 21} 22 23static void 24mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask) 25{ 26 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); 27} 28 29static void 30mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask) 31{ 32 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); 33} 34 35void mt7603_mac_reset_counters(struct mt7603_dev *dev) 36{ 37 int i; 38 39 for (i = 0; i < 2; i++) 40 mt76_rr(dev, MT_TX_AGG_CNT(i)); 41 42 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); 43} 44 45void mt7603_mac_set_timing(struct mt7603_dev *dev) 46{ 47 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 48 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 49 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 50 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24); 51 int offset = 3 * dev->coverage_class; 52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 53 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ; 55 int sifs; 56 u32 val; 57 58 if (is_5ghz) 59 sifs = 16; 60 else 61 sifs = 10; 62 63 mt76_set(dev, MT_ARB_SCR, 64 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 65 udelay(1); 66 67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); 68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); 69 mt76_wr(dev, MT_IFS, 70 FIELD_PREP(MT_IFS_EIFS, 360) | 71 FIELD_PREP(MT_IFS_RIFS, 2) | 72 FIELD_PREP(MT_IFS_SIFS, sifs) | 73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); 74 75 if (dev->slottime < 20 || is_5ghz) 76 val = MT7603_CFEND_RATE_DEFAULT; 77 else 78 val = MT7603_CFEND_RATE_11B; 79 80 mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val); 81 82 mt76_clear(dev, MT_ARB_SCR, 83 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 84} 85 86static void 87mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) 88{ 89 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 90 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 91 92 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 93} 94 95static u32 96mt7603_wtbl1_addr(int idx) 97{ 98 return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 99} 100 101static u32 102mt7603_wtbl2_addr(int idx) 103{ 104 /* Mapped to WTBL2 */ 105 return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE; 106} 107 108static u32 109mt7603_wtbl3_addr(int idx) 110{ 111 u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE); 112 113 return base + idx * MT_WTBL3_SIZE; 114} 115 116static u32 117mt7603_wtbl4_addr(int idx) 118{ 119 u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE); 120 121 return base + idx * MT_WTBL4_SIZE; 122} 123 124void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, 125 const u8 *mac_addr) 126{ 127 const void *_mac = mac_addr; 128 u32 addr = mt7603_wtbl1_addr(idx); 129 u32 w0 = 0, w1 = 0; 130 int i; 131 132 if (_mac) { 133 w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI, 134 get_unaligned_le16(_mac + 4)); 135 w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO, 136 get_unaligned_le32(_mac)); 137 } 138 139 if (vif < 0) 140 vif = 0; 141 else 142 w0 |= MT_WTBL1_W0_RX_CHECK_A1; 143 w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif); 144 145 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 146 147 mt76_set(dev, addr + 0 * 4, w0); 148 mt76_set(dev, addr + 1 * 4, w1); 149 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL); 150 151 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 152 addr = mt7603_wtbl2_addr(idx); 153 for (i = 0; i < MT_WTBL2_SIZE; i += 4) 154 mt76_wr(dev, addr + i, 0); 155 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 156 mt76_start_tx_ac(dev, GENMASK(3, 0)); 157 158 addr = mt7603_wtbl3_addr(idx); 159 for (i = 0; i < MT_WTBL3_SIZE; i += 4) 160 mt76_wr(dev, addr + i, 0); 161 162 addr = mt7603_wtbl4_addr(idx); 163 for (i = 0; i < MT_WTBL4_SIZE; i += 4) 164 mt76_wr(dev, addr + i, 0); 165 166 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 167} 168 169static void 170mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled) 171{ 172 u32 addr = mt7603_wtbl1_addr(idx); 173 u32 val = mt76_rr(dev, addr + 3 * 4); 174 175 val &= ~MT_WTBL1_W3_SKIP_TX; 176 val |= enabled * MT_WTBL1_W3_SKIP_TX; 177 178 mt76_wr(dev, addr + 3 * 4, val); 179} 180 181void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort) 182{ 183 int i, port, queue; 184 185 if (abort) { 186 port = 3; /* PSE */ 187 queue = 8; /* free queue */ 188 } else { 189 port = 0; /* HIF */ 190 queue = 1; /* MCU queue */ 191 } 192 193 mt7603_wtbl_set_skip_tx(dev, idx, true); 194 195 mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN | 196 FIELD_PREP(MT_TX_ABORT_WCID, idx)); 197 198 for (i = 0; i < 4; i++) { 199 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | 200 FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) | 201 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) | 202 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) | 203 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue)); 204 205 WARN_ON_ONCE(!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 206 0, 5000)); 207 } 208 209 mt76_wr(dev, MT_TX_ABORT, 0); 210 211 mt7603_wtbl_set_skip_tx(dev, idx, false); 212} 213 214void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, 215 bool enabled) 216{ 217 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx); 218 219 if (sta->smps == enabled) 220 return; 221 222 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled); 223 sta->smps = enabled; 224} 225 226void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, 227 bool enabled) 228{ 229 int idx = sta->wcid.idx; 230 u32 addr; 231 232 spin_lock_bh(&dev->ps_lock); 233 234 if (sta->ps == enabled) 235 goto out; 236 237 mt76_wr(dev, MT_PSE_RTA, 238 FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) | 239 FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) | 240 FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) | 241 FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) | 242 MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY); 243 244 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); 245 246 if (enabled) 247 mt7603_filter_tx(dev, idx, false); 248 249 addr = mt7603_wtbl1_addr(idx); 250 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 251 mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE, 252 enabled * MT_WTBL1_W3_POWER_SAVE); 253 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 254 sta->ps = enabled; 255 256out: 257 spin_unlock_bh(&dev->ps_lock); 258} 259 260void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx) 261{ 262 int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE; 263 int wtbl2_frame = idx / wtbl2_frame_size; 264 int wtbl2_entry = idx % wtbl2_frame_size; 265 266 int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE; 267 int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE; 268 int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size; 269 int wtbl3_entry = (idx % wtbl3_frame_size) * 2; 270 271 int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE; 272 int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE; 273 int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size; 274 int wtbl4_entry = idx % wtbl4_frame_size; 275 276 u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 277 int i; 278 279 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 280 281 mt76_wr(dev, addr + 0 * 4, 282 MT_WTBL1_W0_RX_CHECK_A1 | 283 MT_WTBL1_W0_RX_CHECK_A2 | 284 MT_WTBL1_W0_RX_VALID); 285 mt76_wr(dev, addr + 1 * 4, 0); 286 mt76_wr(dev, addr + 2 * 4, 0); 287 288 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 289 290 mt76_wr(dev, addr + 3 * 4, 291 FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) | 292 FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) | 293 FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) | 294 MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM); 295 mt76_wr(dev, addr + 4 * 4, 296 FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) | 297 FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) | 298 FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry)); 299 300 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 301 302 addr = mt7603_wtbl2_addr(idx); 303 304 /* Clear BA information */ 305 mt76_wr(dev, addr + (15 * 4), 0); 306 307 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 308 for (i = 2; i <= 4; i++) 309 mt76_wr(dev, addr + (i * 4), 0); 310 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 311 mt76_start_tx_ac(dev, GENMASK(3, 0)); 312 313 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR); 314 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR); 315 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 316} 317 318void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta) 319{ 320 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 321 int idx = msta->wcid.idx; 322 u8 ampdu_density; 323 u32 addr; 324 u32 val; 325 326 addr = mt7603_wtbl1_addr(idx); 327 328 ampdu_density = sta->ht_cap.ampdu_density; 329 if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4) 330 ampdu_density = IEEE80211_HT_MPDU_DENSITY_4; 331 332 val = mt76_rr(dev, addr + 2 * 4); 333 val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL; 334 val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) | 335 FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) | 336 MT_WTBL1_W2_TXS_BAF_REPORT; 337 338 if (sta->ht_cap.cap) 339 val |= MT_WTBL1_W2_HT; 340 if (sta->vht_cap.cap) 341 val |= MT_WTBL1_W2_VHT; 342 343 mt76_wr(dev, addr + 2 * 4, val); 344 345 addr = mt7603_wtbl2_addr(idx); 346 val = mt76_rr(dev, addr + 9 * 4); 347 val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 348 MT_WTBL2_W9_SHORT_GI_80); 349 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) 350 val |= MT_WTBL2_W9_SHORT_GI_20; 351 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 352 val |= MT_WTBL2_W9_SHORT_GI_40; 353 mt76_wr(dev, addr + 9 * 4, val); 354} 355 356void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid) 357{ 358 mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr)); 359 mt76_wr(dev, MT_BA_CONTROL_1, 360 (get_unaligned_le16(addr + 4) | 361 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) | 362 MT_BA_CONTROL_1_RESET)); 363} 364 365void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, 366 int ba_size) 367{ 368 u32 addr = mt7603_wtbl2_addr(wcid); 369 u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 370 (MT_WTBL2_W15_BA_WIN_SIZE << 371 (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT)); 372 u32 tid_val; 373 int i; 374 375 if (ba_size < 0) { 376 /* disable */ 377 mt76_clear(dev, addr + (15 * 4), tid_mask); 378 return; 379 } 380 381 for (i = 7; i > 0; i--) { 382 if (ba_size >= MT_AGG_SIZE_LIMIT(i)) 383 break; 384 } 385 386 tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 387 i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT); 388 389 mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val); 390} 391 392void mt7603_mac_sta_poll(struct mt7603_dev *dev) 393{ 394 static const u8 ac_to_tid[4] = { 395 [IEEE80211_AC_BE] = 0, 396 [IEEE80211_AC_BK] = 1, 397 [IEEE80211_AC_VI] = 4, 398 [IEEE80211_AC_VO] = 6 399 }; 400 struct ieee80211_sta *sta; 401 struct mt7603_sta *msta; 402 u32 total_airtime = 0; 403 u32 airtime[4]; 404 u32 addr; 405 int i; 406 407 rcu_read_lock(); 408 409 while (1) { 410 bool clear = false; 411 412 spin_lock_bh(&dev->sta_poll_lock); 413 if (list_empty(&dev->sta_poll_list)) { 414 spin_unlock_bh(&dev->sta_poll_lock); 415 break; 416 } 417 418 msta = list_first_entry(&dev->sta_poll_list, struct mt7603_sta, 419 poll_list); 420 list_del_init(&msta->poll_list); 421 spin_unlock_bh(&dev->sta_poll_lock); 422 423 addr = mt7603_wtbl4_addr(msta->wcid.idx); 424 for (i = 0; i < 4; i++) { 425 u32 airtime_last = msta->tx_airtime_ac[i]; 426 427 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); 428 airtime[i] = msta->tx_airtime_ac[i] - airtime_last; 429 airtime[i] *= 32; 430 total_airtime += airtime[i]; 431 432 if (msta->tx_airtime_ac[i] & BIT(22)) 433 clear = true; 434 } 435 436 if (clear) { 437 mt7603_wtbl_update(dev, msta->wcid.idx, 438 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 439 memset(msta->tx_airtime_ac, 0, 440 sizeof(msta->tx_airtime_ac)); 441 } 442 443 if (!msta->wcid.sta) 444 continue; 445 446 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 447 for (i = 0; i < 4; i++) { 448 struct mt76_queue *q = dev->mt76.q_tx[i]; 449 u8 qidx = q->hw_idx; 450 u8 tid = ac_to_tid[i]; 451 u32 txtime = airtime[qidx]; 452 453 if (!txtime) 454 continue; 455 456 ieee80211_sta_register_airtime(sta, tid, txtime, 0); 457 } 458 } 459 460 rcu_read_unlock(); 461 462 if (!total_airtime) 463 return; 464 465 spin_lock_bh(&dev->mt76.cc_lock); 466 dev->mphy.chan_state->cc_tx += total_airtime; 467 spin_unlock_bh(&dev->mt76.cc_lock); 468} 469 470static struct mt76_wcid * 471mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast) 472{ 473 struct mt7603_sta *sta; 474 struct mt76_wcid *wcid; 475 476 if (idx >= MT7603_WTBL_SIZE) 477 return NULL; 478 479 wcid = rcu_dereference(dev->mt76.wcid[idx]); 480 if (unicast || !wcid) 481 return wcid; 482 483 if (!wcid->sta) 484 return NULL; 485 486 sta = container_of(wcid, struct mt7603_sta, wcid); 487 if (!sta->vif) 488 return NULL; 489 490 return &sta->vif->sta.wcid; 491} 492 493int 494mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb) 495{ 496 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 497 struct ieee80211_supported_band *sband; 498 struct ieee80211_hdr *hdr; 499 __le32 *rxd = (__le32 *)skb->data; 500 u32 rxd0 = le32_to_cpu(rxd[0]); 501 u32 rxd1 = le32_to_cpu(rxd[1]); 502 u32 rxd2 = le32_to_cpu(rxd[2]); 503 bool unicast = rxd1 & MT_RXD1_NORMAL_U2M; 504 bool insert_ccmp_hdr = false; 505 bool remove_pad; 506 int idx; 507 int i; 508 509 memset(status, 0, sizeof(*status)); 510 511 i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 512 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband; 513 i >>= 1; 514 515 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 516 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); 517 518 status->band = sband->band; 519 if (i < sband->n_channels) 520 status->freq = sband->channels[i].center_freq; 521 522 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 523 status->flag |= RX_FLAG_FAILED_FCS_CRC; 524 525 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 526 status->flag |= RX_FLAG_MMIC_ERROR; 527 528 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 529 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 530 status->flag |= RX_FLAG_DECRYPTED; 531 status->flag |= RX_FLAG_IV_STRIPPED; 532 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 533 } 534 535 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 536 MT_RXD2_NORMAL_NON_AMPDU))) { 537 status->flag |= RX_FLAG_AMPDU_DETAILS; 538 539 /* all subframes of an A-MPDU have the same timestamp */ 540 if (dev->rx_ampdu_ts != rxd[12]) { 541 if (!++dev->ampdu_ref) 542 dev->ampdu_ref++; 543 } 544 dev->rx_ampdu_ts = rxd[12]; 545 546 status->ampdu_ref = dev->ampdu_ref; 547 } 548 549 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 550 551 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 552 return -EINVAL; 553 554 if (!sband->channels) 555 return -EINVAL; 556 557 rxd += 4; 558 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 559 rxd += 4; 560 if ((u8 *)rxd - skb->data >= skb->len) 561 return -EINVAL; 562 } 563 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 564 u8 *data = (u8 *)rxd; 565 566 if (status->flag & RX_FLAG_DECRYPTED) { 567 status->iv[0] = data[5]; 568 status->iv[1] = data[4]; 569 status->iv[2] = data[3]; 570 status->iv[3] = data[2]; 571 status->iv[4] = data[1]; 572 status->iv[5] = data[0]; 573 574 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 575 } 576 577 rxd += 4; 578 if ((u8 *)rxd - skb->data >= skb->len) 579 return -EINVAL; 580 } 581 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 582 rxd += 2; 583 if ((u8 *)rxd - skb->data >= skb->len) 584 return -EINVAL; 585 } 586 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 587 u32 rxdg0 = le32_to_cpu(rxd[0]); 588 u32 rxdg3 = le32_to_cpu(rxd[3]); 589 bool cck = false; 590 591 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 592 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 593 case MT_PHY_TYPE_CCK: 594 cck = true; 595 fallthrough; 596 case MT_PHY_TYPE_OFDM: 597 i = mt76_get_rate(&dev->mt76, sband, i, cck); 598 break; 599 case MT_PHY_TYPE_HT_GF: 600 case MT_PHY_TYPE_HT: 601 status->encoding = RX_ENC_HT; 602 if (i > 15) 603 return -EINVAL; 604 break; 605 default: 606 return -EINVAL; 607 } 608 609 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 610 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 611 if (rxdg0 & MT_RXV1_HT_AD_CODE) 612 status->enc_flags |= RX_ENC_FLAG_LDPC; 613 614 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * 615 FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 616 617 status->rate_idx = i; 618 619 status->chains = dev->mphy.antenna_mask; 620 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) + 621 dev->rssi_offset[0]; 622 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) + 623 dev->rssi_offset[1]; 624 625 status->signal = status->chain_signal[0]; 626 if (status->chains & BIT(1)) 627 status->signal = max(status->signal, 628 status->chain_signal[1]); 629 630 if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1) 631 status->bw = RATE_INFO_BW_40; 632 633 rxd += 6; 634 if ((u8 *)rxd - skb->data >= skb->len) 635 return -EINVAL; 636 } else { 637 return -EINVAL; 638 } 639 640 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 641 642 if (insert_ccmp_hdr) { 643 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 644 645 mt76_insert_ccmp_hdr(skb, key_id); 646 } 647 648 hdr = (struct ieee80211_hdr *)skb->data; 649 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) 650 return 0; 651 652 status->aggr = unicast && 653 !ieee80211_is_qos_nullfunc(hdr->frame_control); 654 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; 655 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 656 657 return 0; 658} 659 660static u16 661mt7603_mac_tx_rate_val(struct mt7603_dev *dev, 662 const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw) 663{ 664 u8 phy, nss, rate_idx; 665 u16 rateval; 666 667 *bw = 0; 668 if (rate->flags & IEEE80211_TX_RC_MCS) { 669 rate_idx = rate->idx; 670 nss = 1 + (rate->idx >> 3); 671 phy = MT_PHY_TYPE_HT; 672 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 673 phy = MT_PHY_TYPE_HT_GF; 674 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 675 *bw = 1; 676 } else { 677 const struct ieee80211_rate *r; 678 int band = dev->mphy.chandef.chan->band; 679 u16 val; 680 681 nss = 1; 682 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; 683 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 684 val = r->hw_value_short; 685 else 686 val = r->hw_value; 687 688 phy = val >> 8; 689 rate_idx = val & 0xff; 690 } 691 692 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 693 FIELD_PREP(MT_TX_RATE_MODE, phy)); 694 695 if (stbc && nss == 1) 696 rateval |= MT_TX_RATE_STBC; 697 698 return rateval; 699} 700 701void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta, 702 struct ieee80211_tx_rate *probe_rate, 703 struct ieee80211_tx_rate *rates) 704{ 705 struct ieee80211_tx_rate *ref; 706 int wcid = sta->wcid.idx; 707 u32 addr = mt7603_wtbl2_addr(wcid); 708 bool stbc = false; 709 int n_rates = sta->n_rates; 710 u8 bw, bw_prev, bw_idx = 0; 711 u16 val[4]; 712 u16 probe_val; 713 u32 w9 = mt76_rr(dev, addr + 9 * 4); 714 bool rateset; 715 int i, k; 716 717 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 718 return; 719 720 for (i = n_rates; i < 4; i++) 721 rates[i] = rates[n_rates - 1]; 722 723 rateset = !(sta->rate_set_tsf & BIT(0)); 724 memcpy(sta->rateset[rateset].rates, rates, 725 sizeof(sta->rateset[rateset].rates)); 726 if (probe_rate) { 727 sta->rateset[rateset].probe_rate = *probe_rate; 728 ref = &sta->rateset[rateset].probe_rate; 729 } else { 730 sta->rateset[rateset].probe_rate.idx = -1; 731 ref = &sta->rateset[rateset].rates[0]; 732 } 733 734 rates = sta->rateset[rateset].rates; 735 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 736 /* 737 * We don't support switching between short and long GI 738 * within the rate set. For accurate tx status reporting, we 739 * need to make sure that flags match. 740 * For improved performance, avoid duplicate entries by 741 * decrementing the MCS index if necessary 742 */ 743 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 744 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 745 746 for (k = 0; k < i; k++) { 747 if (rates[i].idx != rates[k].idx) 748 continue; 749 if ((rates[i].flags ^ rates[k].flags) & 750 IEEE80211_TX_RC_40_MHZ_WIDTH) 751 continue; 752 753 if (!rates[i].idx) 754 continue; 755 756 rates[i].idx--; 757 } 758 } 759 760 w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 761 MT_WTBL2_W9_SHORT_GI_80; 762 763 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); 764 bw_prev = bw; 765 766 if (probe_rate) { 767 probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw); 768 if (bw) 769 bw_idx = 1; 770 else 771 bw_prev = 0; 772 } else { 773 probe_val = val[0]; 774 } 775 776 w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw); 777 w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw); 778 779 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); 780 if (bw_prev) { 781 bw_idx = 3; 782 bw_prev = bw; 783 } 784 785 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); 786 if (bw_prev) { 787 bw_idx = 5; 788 bw_prev = bw; 789 } 790 791 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); 792 if (bw_prev) 793 bw_idx = 7; 794 795 w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE, 796 bw_idx ? bw_idx - 1 : 7); 797 798 mt76_wr(dev, MT_WTBL_RIUCR0, w9); 799 800 mt76_wr(dev, MT_WTBL_RIUCR1, 801 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) | 802 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) | 803 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1])); 804 805 mt76_wr(dev, MT_WTBL_RIUCR2, 806 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) | 807 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) | 808 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) | 809 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2])); 810 811 mt76_wr(dev, MT_WTBL_RIUCR3, 812 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) | 813 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) | 814 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3])); 815 816 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */ 817 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; 818 819 mt76_wr(dev, MT_WTBL_UPDATE, 820 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 821 MT_WTBL_UPDATE_RATE_UPDATE | 822 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 823 824 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 825 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 826 827 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates; 828 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 829} 830 831static enum mt7603_cipher_type 832mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 833{ 834 memset(key_data, 0, 32); 835 if (!key) 836 return MT_CIPHER_NONE; 837 838 if (key->keylen > 32) 839 return MT_CIPHER_NONE; 840 841 memcpy(key_data, key->key, key->keylen); 842 843 switch (key->cipher) { 844 case WLAN_CIPHER_SUITE_WEP40: 845 return MT_CIPHER_WEP40; 846 case WLAN_CIPHER_SUITE_WEP104: 847 return MT_CIPHER_WEP104; 848 case WLAN_CIPHER_SUITE_TKIP: 849 /* Rx/Tx MIC keys are swapped */ 850 memcpy(key_data + 16, key->key + 24, 8); 851 memcpy(key_data + 24, key->key + 16, 8); 852 return MT_CIPHER_TKIP; 853 case WLAN_CIPHER_SUITE_CCMP: 854 return MT_CIPHER_AES_CCMP; 855 default: 856 return MT_CIPHER_NONE; 857 } 858} 859 860int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid, 861 struct ieee80211_key_conf *key) 862{ 863 enum mt7603_cipher_type cipher; 864 u32 addr = mt7603_wtbl3_addr(wcid); 865 u8 key_data[32]; 866 int key_len = sizeof(key_data); 867 868 cipher = mt7603_mac_get_key_info(key, key_data); 869 if (cipher == MT_CIPHER_NONE && key) 870 return -EOPNOTSUPP; 871 872 if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) { 873 addr += key->keyidx * 16; 874 key_len = 16; 875 } 876 877 mt76_wr_copy(dev, addr, key_data, key_len); 878 879 addr = mt7603_wtbl1_addr(wcid); 880 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher); 881 if (key) 882 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); 883 mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key); 884 885 return 0; 886} 887 888static int 889mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi, 890 struct sk_buff *skb, enum mt76_txq_id qid, 891 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 892 int pid, struct ieee80211_key_conf *key) 893{ 894 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 895 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 896 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 897 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data; 898 struct ieee80211_vif *vif = info->control.vif; 899 struct mt76_queue *q = dev->mt76.q_tx[qid]; 900 struct mt7603_vif *mvif; 901 int wlan_idx; 902 int hdr_len = ieee80211_get_hdrlen_from_skb(skb); 903 int tx_count = 8; 904 u8 frame_type, frame_subtype; 905 u16 fc = le16_to_cpu(hdr->frame_control); 906 u16 seqno = 0; 907 u8 vif_idx = 0; 908 u32 val; 909 u8 bw; 910 911 if (vif) { 912 mvif = (struct mt7603_vif *)vif->drv_priv; 913 vif_idx = mvif->idx; 914 if (vif_idx && qid >= MT_TXQ_BEACON) 915 vif_idx += 0x10; 916 } 917 918 if (sta) { 919 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 920 921 tx_count = msta->rate_count; 922 } 923 924 if (wcid) 925 wlan_idx = wcid->idx; 926 else 927 wlan_idx = MT7603_WTBL_RESERVED; 928 929 frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2; 930 frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4; 931 932 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 933 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx); 934 txwi[0] = cpu_to_le32(val); 935 936 val = MT_TXD1_LONG_FORMAT | 937 FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) | 938 FIELD_PREP(MT_TXD1_TID, 939 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 940 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 941 FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) | 942 FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) | 943 FIELD_PREP(MT_TXD1_PROTECTED, !!key); 944 txwi[1] = cpu_to_le32(val); 945 946 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 947 txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK); 948 949 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) | 950 FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) | 951 FIELD_PREP(MT_TXD2_MULTICAST, 952 is_multicast_ether_addr(hdr->addr1)); 953 txwi[2] = cpu_to_le32(val); 954 955 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 956 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 957 958 txwi[4] = 0; 959 960 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT | 961 FIELD_PREP(MT_TXD5_PID, pid); 962 txwi[5] = cpu_to_le32(val); 963 964 txwi[6] = 0; 965 966 if (rate->idx >= 0 && rate->count && 967 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 968 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 969 u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw); 970 971 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 972 973 val = MT_TXD6_FIXED_BW | 974 FIELD_PREP(MT_TXD6_BW, bw) | 975 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 976 txwi[6] |= cpu_to_le32(val); 977 978 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 979 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 980 981 if (!(rate->flags & IEEE80211_TX_RC_MCS)) 982 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 983 984 tx_count = rate->count; 985 } 986 987 /* use maximum tx count for beacons and buffered multicast */ 988 if (qid >= MT_TXQ_BEACON) 989 tx_count = 0x1f; 990 991 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) | 992 MT_TXD3_SN_VALID; 993 994 if (ieee80211_is_data_qos(hdr->frame_control)) 995 seqno = le16_to_cpu(hdr->seq_ctrl); 996 else if (ieee80211_is_back_req(hdr->frame_control)) 997 seqno = le16_to_cpu(bar->start_seq_num); 998 else 999 val &= ~MT_TXD3_SN_VALID; 1000 1001 val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4); 1002 1003 txwi[3] = cpu_to_le32(val); 1004 1005 if (key) { 1006 u64 pn = atomic64_inc_return(&key->tx_pn); 1007 1008 txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID); 1009 txwi[4] = cpu_to_le32(pn & GENMASK(31, 0)); 1010 txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32)); 1011 } 1012 1013 txwi[7] = 0; 1014 1015 return 0; 1016} 1017 1018int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1019 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1020 struct ieee80211_sta *sta, 1021 struct mt76_tx_info *tx_info) 1022{ 1023 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1024 struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid); 1025 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1026 struct ieee80211_key_conf *key = info->control.hw_key; 1027 int pid; 1028 1029 if (!wcid) 1030 wcid = &dev->global_sta.wcid; 1031 1032 if (sta) { 1033 msta = (struct mt7603_sta *)sta->drv_priv; 1034 1035 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | 1036 IEEE80211_TX_CTL_CLEAR_PS_FILT)) || 1037 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) 1038 mt7603_wtbl_set_ps(dev, msta, false); 1039 1040 mt76_tx_check_agg_ssn(sta, tx_info->skb); 1041 } 1042 1043 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1044 1045 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) { 1046 spin_lock_bh(&dev->mt76.lock); 1047 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], 1048 msta->rates); 1049 msta->rate_probe = true; 1050 spin_unlock_bh(&dev->mt76.lock); 1051 } 1052 1053 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, 1054 sta, pid, key); 1055 1056 return 0; 1057} 1058 1059static bool 1060mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta, 1061 struct ieee80211_tx_info *info, __le32 *txs_data) 1062{ 1063 struct ieee80211_supported_band *sband; 1064 struct mt7603_rate_set *rs; 1065 int first_idx = 0, last_idx; 1066 u32 rate_set_tsf; 1067 u32 final_rate; 1068 u32 final_rate_flags; 1069 bool rs_idx; 1070 bool ack_timeout; 1071 bool fixed_rate; 1072 bool probe; 1073 bool ampdu; 1074 bool cck = false; 1075 int count; 1076 u32 txs; 1077 int idx; 1078 int i; 1079 1080 fixed_rate = info->status.rates[0].count; 1081 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1082 1083 txs = le32_to_cpu(txs_data[4]); 1084 ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU); 1085 count = FIELD_GET(MT_TXS4_TX_COUNT, txs); 1086 last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs); 1087 1088 txs = le32_to_cpu(txs_data[0]); 1089 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1090 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1091 1092 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1093 return false; 1094 1095 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1096 return false; 1097 1098 if (!ack_timeout) 1099 info->flags |= IEEE80211_TX_STAT_ACK; 1100 1101 info->status.ampdu_len = 1; 1102 info->status.ampdu_ack_len = !!(info->flags & 1103 IEEE80211_TX_STAT_ACK); 1104 1105 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1106 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1107 1108 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY); 1109 1110 if (fixed_rate && !probe) { 1111 info->status.rates[0].count = count; 1112 i = 0; 1113 goto out; 1114 } 1115 1116 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1117 rs_idx = !((u32)(FIELD_GET(MT_TXS1_F0_TIMESTAMP, le32_to_cpu(txs_data[1])) - 1118 rate_set_tsf) < 1000000); 1119 rs_idx ^= rate_set_tsf & BIT(0); 1120 rs = &sta->rateset[rs_idx]; 1121 1122 if (!first_idx && rs->probe_rate.idx >= 0) { 1123 info->status.rates[0] = rs->probe_rate; 1124 1125 spin_lock_bh(&dev->mt76.lock); 1126 if (sta->rate_probe) { 1127 mt7603_wtbl_set_rates(dev, sta, NULL, 1128 sta->rates); 1129 sta->rate_probe = false; 1130 } 1131 spin_unlock_bh(&dev->mt76.lock); 1132 } else { 1133 info->status.rates[0] = rs->rates[first_idx / 2]; 1134 } 1135 info->status.rates[0].count = 0; 1136 1137 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1138 struct ieee80211_tx_rate *cur_rate; 1139 int cur_count; 1140 1141 cur_rate = &rs->rates[idx / 2]; 1142 cur_count = min_t(int, MT7603_RATE_RETRY, count); 1143 count -= cur_count; 1144 1145 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1146 cur_rate->flags != info->status.rates[i].flags)) { 1147 i++; 1148 if (i == ARRAY_SIZE(info->status.rates)) { 1149 i--; 1150 break; 1151 } 1152 1153 info->status.rates[i] = *cur_rate; 1154 info->status.rates[i].count = 0; 1155 } 1156 1157 info->status.rates[i].count += cur_count; 1158 } 1159 1160out: 1161 final_rate_flags = info->status.rates[i].flags; 1162 1163 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1164 case MT_PHY_TYPE_CCK: 1165 cck = true; 1166 fallthrough; 1167 case MT_PHY_TYPE_OFDM: 1168 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) 1169 sband = &dev->mphy.sband_5g.sband; 1170 else 1171 sband = &dev->mphy.sband_2g.sband; 1172 final_rate &= GENMASK(5, 0); 1173 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1174 cck); 1175 final_rate_flags = 0; 1176 break; 1177 case MT_PHY_TYPE_HT_GF: 1178 case MT_PHY_TYPE_HT: 1179 final_rate_flags |= IEEE80211_TX_RC_MCS; 1180 final_rate &= GENMASK(5, 0); 1181 if (final_rate > 15) 1182 return false; 1183 break; 1184 default: 1185 return false; 1186 } 1187 1188 info->status.rates[i].idx = final_rate; 1189 info->status.rates[i].flags = final_rate_flags; 1190 1191 return true; 1192} 1193 1194static bool 1195mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid, 1196 __le32 *txs_data) 1197{ 1198 struct mt76_dev *mdev = &dev->mt76; 1199 struct sk_buff_head list; 1200 struct sk_buff *skb; 1201 1202 if (pid < MT_PACKET_ID_FIRST) 1203 return false; 1204 1205 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1206 1207 mt76_tx_status_lock(mdev, &list); 1208 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1209 if (skb) { 1210 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1211 1212 if (!mt7603_fill_txs(dev, sta, info, txs_data)) { 1213 ieee80211_tx_info_clear_status(info); 1214 info->status.rates[0].idx = -1; 1215 } 1216 1217 mt76_tx_status_skb_done(mdev, skb, &list); 1218 } 1219 mt76_tx_status_unlock(mdev, &list); 1220 1221 return !!skb; 1222} 1223 1224void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data) 1225{ 1226 struct ieee80211_tx_info info = {}; 1227 struct ieee80211_sta *sta = NULL; 1228 struct mt7603_sta *msta = NULL; 1229 struct mt76_wcid *wcid; 1230 __le32 *txs_data = data; 1231 u32 txs; 1232 u8 wcidx; 1233 u8 pid; 1234 1235 txs = le32_to_cpu(txs_data[4]); 1236 pid = FIELD_GET(MT_TXS4_PID, txs); 1237 txs = le32_to_cpu(txs_data[3]); 1238 wcidx = FIELD_GET(MT_TXS3_WCID, txs); 1239 1240 if (pid == MT_PACKET_ID_NO_ACK) 1241 return; 1242 1243 if (wcidx >= MT7603_WTBL_SIZE) 1244 return; 1245 1246 rcu_read_lock(); 1247 1248 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1249 if (!wcid) 1250 goto out; 1251 1252 msta = container_of(wcid, struct mt7603_sta, wcid); 1253 sta = wcid_to_sta(wcid); 1254 1255 if (list_empty(&msta->poll_list)) { 1256 spin_lock_bh(&dev->sta_poll_lock); 1257 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1258 spin_unlock_bh(&dev->sta_poll_lock); 1259 } 1260 1261 if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data)) 1262 goto out; 1263 1264 if (wcidx >= MT7603_WTBL_STA || !sta) 1265 goto out; 1266 1267 if (mt7603_fill_txs(dev, msta, &info, txs_data)) 1268 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info); 1269 1270out: 1271 rcu_read_unlock(); 1272} 1273 1274void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1275{ 1276 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1277 struct sk_buff *skb = e->skb; 1278 1279 if (!e->txwi) { 1280 dev_kfree_skb_any(skb); 1281 return; 1282 } 1283 1284 dev->tx_hang_check = 0; 1285 mt76_tx_complete_skb(mdev, e->wcid, skb); 1286} 1287 1288static bool 1289wait_for_wpdma(struct mt7603_dev *dev) 1290{ 1291 return mt76_poll(dev, MT_WPDMA_GLO_CFG, 1292 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 1293 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 1294 0, 1000); 1295} 1296 1297static void mt7603_pse_reset(struct mt7603_dev *dev) 1298{ 1299 /* Clear previous reset result */ 1300 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1301 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S); 1302 1303 /* Reset PSE */ 1304 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1305 1306 if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET, 1307 MT_MCU_DEBUG_RESET_PSE_S, 1308 MT_MCU_DEBUG_RESET_PSE_S, 500)) { 1309 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; 1310 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1311 } else { 1312 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1313 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES); 1314 } 1315 1316 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) 1317 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1318} 1319 1320void mt7603_mac_dma_start(struct mt7603_dev *dev) 1321{ 1322 mt7603_mac_start(dev); 1323 1324 wait_for_wpdma(dev); 1325 usleep_range(50, 100); 1326 1327 mt76_set(dev, MT_WPDMA_GLO_CFG, 1328 (MT_WPDMA_GLO_CFG_TX_DMA_EN | 1329 MT_WPDMA_GLO_CFG_RX_DMA_EN | 1330 FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | 1331 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE)); 1332 1333 mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL); 1334} 1335 1336void mt7603_mac_start(struct mt7603_dev *dev) 1337{ 1338 mt76_clear(dev, MT_ARB_SCR, 1339 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1340 mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); 1341 mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1342} 1343 1344void mt7603_mac_stop(struct mt7603_dev *dev) 1345{ 1346 mt76_set(dev, MT_ARB_SCR, 1347 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1348 mt76_wr(dev, MT_WF_ARB_TX_START_0, 0); 1349 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1350} 1351 1352void mt7603_pse_client_reset(struct mt7603_dev *dev) 1353{ 1354 u32 addr; 1355 1356 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + 1357 MT_CLIENT_RESET_TX); 1358 1359 /* Clear previous reset state */ 1360 mt76_clear(dev, addr, 1361 MT_CLIENT_RESET_TX_R_E_1 | 1362 MT_CLIENT_RESET_TX_R_E_2 | 1363 MT_CLIENT_RESET_TX_R_E_1_S | 1364 MT_CLIENT_RESET_TX_R_E_2_S); 1365 1366 /* Start PSE client TX abort */ 1367 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1); 1368 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S, 1369 MT_CLIENT_RESET_TX_R_E_1_S, 500); 1370 1371 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2); 1372 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 1373 1374 /* Wait for PSE client to clear TX FIFO */ 1375 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S, 1376 MT_CLIENT_RESET_TX_R_E_2_S, 500); 1377 1378 /* Clear PSE client TX abort state */ 1379 mt76_clear(dev, addr, 1380 MT_CLIENT_RESET_TX_R_E_1 | 1381 MT_CLIENT_RESET_TX_R_E_2); 1382} 1383 1384static void mt7603_dma_sched_reset(struct mt7603_dev *dev) 1385{ 1386 if (!is_mt7628(dev)) 1387 return; 1388 1389 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); 1390 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET); 1391} 1392 1393static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev) 1394{ 1395 int beacon_int = dev->mt76.beacon_int; 1396 u32 mask = dev->mt76.mmio.irqmask; 1397 int i; 1398 1399 ieee80211_stop_queues(dev->mt76.hw); 1400 set_bit(MT76_RESET, &dev->mphy.state); 1401 1402 /* lock/unlock all queues to ensure that no tx is pending */ 1403 mt76_txq_schedule_all(&dev->mphy); 1404 1405 mt76_worker_disable(&dev->mt76.tx_worker); 1406 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 1407 napi_disable(&dev->mt76.napi[0]); 1408 napi_disable(&dev->mt76.napi[1]); 1409 napi_disable(&dev->mt76.tx_napi); 1410 1411 mutex_lock(&dev->mt76.mutex); 1412 1413 mt7603_beacon_set_timer(dev, -1, 0); 1414 1415 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || 1416 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY || 1417 dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK || 1418 dev->cur_reset_cause == RESET_CAUSE_TX_HANG) 1419 mt7603_pse_reset(dev); 1420 1421 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1422 goto skip_dma_reset; 1423 1424 mt7603_mac_stop(dev); 1425 1426 mt76_clear(dev, MT_WPDMA_GLO_CFG, 1427 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN | 1428 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 1429 usleep_range(1000, 2000); 1430 1431 mt7603_irq_disable(dev, mask); 1432 1433 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF); 1434 1435 mt7603_pse_client_reset(dev); 1436 1437 for (i = 0; i < __MT_TXQ_MAX; i++) 1438 mt76_queue_tx_cleanup(dev, i, true); 1439 1440 mt76_for_each_q_rx(&dev->mt76, i) { 1441 mt76_queue_rx_reset(dev, i); 1442 } 1443 1444 mt7603_dma_sched_reset(dev); 1445 1446 mt7603_mac_dma_start(dev); 1447 1448 mt7603_irq_enable(dev, mask); 1449 1450skip_dma_reset: 1451 clear_bit(MT76_RESET, &dev->mphy.state); 1452 mutex_unlock(&dev->mt76.mutex); 1453 1454 mt76_worker_enable(&dev->mt76.tx_worker); 1455 napi_enable(&dev->mt76.tx_napi); 1456 napi_schedule(&dev->mt76.tx_napi); 1457 1458 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 1459 mt7603_beacon_set_timer(dev, -1, beacon_int); 1460 1461 napi_enable(&dev->mt76.napi[0]); 1462 napi_schedule(&dev->mt76.napi[0]); 1463 1464 napi_enable(&dev->mt76.napi[1]); 1465 napi_schedule(&dev->mt76.napi[1]); 1466 1467 ieee80211_wake_queues(dev->mt76.hw); 1468 mt76_txq_schedule_all(&dev->mphy); 1469} 1470 1471static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index) 1472{ 1473 u32 val; 1474 1475 mt76_wr(dev, MT_WPDMA_DEBUG, 1476 FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) | 1477 MT_WPDMA_DEBUG_SEL); 1478 1479 val = mt76_rr(dev, MT_WPDMA_DEBUG); 1480 return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val); 1481} 1482 1483static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev) 1484{ 1485 if (is_mt7628(dev)) 1486 return mt7603_dma_debug(dev, 9) & BIT(9); 1487 1488 return mt7603_dma_debug(dev, 2) & BIT(8); 1489} 1490 1491static bool mt7603_rx_dma_busy(struct mt7603_dev *dev) 1492{ 1493 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY)) 1494 return false; 1495 1496 return mt7603_rx_fifo_busy(dev); 1497} 1498 1499static bool mt7603_tx_dma_busy(struct mt7603_dev *dev) 1500{ 1501 u32 val; 1502 1503 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY)) 1504 return false; 1505 1506 val = mt7603_dma_debug(dev, 9); 1507 return (val & BIT(8)) && (val & 0xf) != 0xf; 1508} 1509 1510static bool mt7603_tx_hang(struct mt7603_dev *dev) 1511{ 1512 struct mt76_queue *q; 1513 u32 dma_idx, prev_dma_idx; 1514 int i; 1515 1516 for (i = 0; i < 4; i++) { 1517 q = dev->mt76.q_tx[i]; 1518 1519 if (!q->queued) 1520 continue; 1521 1522 prev_dma_idx = dev->tx_dma_idx[i]; 1523 dma_idx = readl(&q->regs->dma_idx); 1524 dev->tx_dma_idx[i] = dma_idx; 1525 1526 if (dma_idx == prev_dma_idx && 1527 dma_idx != readl(&q->regs->cpu_idx)) 1528 break; 1529 } 1530 1531 return i < 4; 1532} 1533 1534static bool mt7603_rx_pse_busy(struct mt7603_dev *dev) 1535{ 1536 u32 addr, val; 1537 1538 if (mt7603_rx_fifo_busy(dev)) 1539 goto out; 1540 1541 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS); 1542 mt76_wr(dev, addr, 3); 1543 val = mt76_rr(dev, addr) >> 16; 1544 1545 if (!(val & BIT(0))) 1546 return false; 1547 1548 if (is_mt7628(dev)) 1549 val &= 0xa000; 1550 else 1551 val &= 0x8000; 1552 if (!val) 1553 return false; 1554 1555out: 1556 if (mt76_rr(dev, MT_INT_SOURCE_CSR) & 1557 (MT_INT_RX_DONE(0) | MT_INT_RX_DONE(1))) 1558 return false; 1559 1560 return true; 1561} 1562 1563static bool 1564mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter, 1565 enum mt7603_reset_cause cause, 1566 bool (*check)(struct mt7603_dev *dev)) 1567{ 1568 if (dev->reset_test == cause + 1) { 1569 dev->reset_test = 0; 1570 goto trigger; 1571 } 1572 1573 if (check) { 1574 if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) { 1575 *counter = 0; 1576 return false; 1577 } 1578 1579 (*counter)++; 1580 } 1581 1582 if (*counter < MT7603_WATCHDOG_TIMEOUT) 1583 return false; 1584trigger: 1585 dev->cur_reset_cause = cause; 1586 dev->reset_cause[cause]++; 1587 return true; 1588} 1589 1590void mt7603_update_channel(struct mt76_dev *mdev) 1591{ 1592 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1593 struct mt76_channel_state *state; 1594 1595 state = mdev->phy.chan_state; 1596 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA); 1597} 1598 1599void 1600mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val) 1601{ 1602 u32 rxtd_6 = 0xd7c80000; 1603 1604 if (val == dev->ed_strict_mode) 1605 return; 1606 1607 dev->ed_strict_mode = val; 1608 1609 /* Ensure that ED/CCA does not trigger if disabled */ 1610 if (!dev->ed_monitor) 1611 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34); 1612 else 1613 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d); 1614 1615 if (dev->ed_monitor && !dev->ed_strict_mode) 1616 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f); 1617 else 1618 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10); 1619 1620 mt76_wr(dev, MT_RXTD(6), rxtd_6); 1621 1622 mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN, 1623 dev->ed_monitor && !dev->ed_strict_mode); 1624} 1625 1626static void 1627mt7603_edcca_check(struct mt7603_dev *dev) 1628{ 1629 u32 val = mt76_rr(dev, MT_AGC(41)); 1630 ktime_t cur_time; 1631 int rssi0, rssi1; 1632 u32 active; 1633 u32 ed_busy; 1634 1635 if (!dev->ed_monitor) 1636 return; 1637 1638 rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val); 1639 if (rssi0 > 128) 1640 rssi0 -= 256; 1641 1642 rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val); 1643 if (rssi1 > 128) 1644 rssi1 -= 256; 1645 1646 if (max(rssi0, rssi1) >= -40 && 1647 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) 1648 dev->ed_strong_signal++; 1649 else if (dev->ed_strong_signal > 0) 1650 dev->ed_strong_signal--; 1651 1652 cur_time = ktime_get_boottime(); 1653 ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK; 1654 1655 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 1656 dev->ed_time = cur_time; 1657 1658 if (!active) 1659 return; 1660 1661 if (100 * ed_busy / active > 90) { 1662 if (dev->ed_trigger < 0) 1663 dev->ed_trigger = 0; 1664 dev->ed_trigger++; 1665 } else { 1666 if (dev->ed_trigger > 0) 1667 dev->ed_trigger = 0; 1668 dev->ed_trigger--; 1669 } 1670 1671 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || 1672 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { 1673 mt7603_edcca_set_strict(dev, true); 1674 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { 1675 mt7603_edcca_set_strict(dev, false); 1676 } 1677 1678 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) 1679 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; 1680 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) 1681 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; 1682} 1683 1684void mt7603_cca_stats_reset(struct mt7603_dev *dev) 1685{ 1686 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1687 mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1688 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN); 1689} 1690 1691static void 1692mt7603_adjust_sensitivity(struct mt7603_dev *dev) 1693{ 1694 u32 agc0 = dev->agc0, agc3 = dev->agc3; 1695 u32 adj; 1696 1697 if (!dev->sensitivity || dev->sensitivity < -100) { 1698 dev->sensitivity = 0; 1699 } else if (dev->sensitivity <= -84) { 1700 adj = 7 + (dev->sensitivity + 92) / 2; 1701 1702 agc0 = 0x56f0076f; 1703 agc0 |= adj << 12; 1704 agc0 |= adj << 16; 1705 agc3 = 0x81d0d5e3; 1706 } else if (dev->sensitivity <= -72) { 1707 adj = 7 + (dev->sensitivity + 80) / 2; 1708 1709 agc0 = 0x6af0006f; 1710 agc0 |= adj << 8; 1711 agc0 |= adj << 12; 1712 agc0 |= adj << 16; 1713 1714 agc3 = 0x8181d5e3; 1715 } else { 1716 if (dev->sensitivity > -54) 1717 dev->sensitivity = -54; 1718 1719 adj = 7 + (dev->sensitivity + 80) / 2; 1720 1721 agc0 = 0x7ff0000f; 1722 agc0 |= adj << 4; 1723 agc0 |= adj << 8; 1724 agc0 |= adj << 12; 1725 agc0 |= adj << 16; 1726 1727 agc3 = 0x818181e3; 1728 } 1729 1730 mt76_wr(dev, MT_AGC(0), agc0); 1731 mt76_wr(dev, MT_AGC1(0), agc0); 1732 1733 mt76_wr(dev, MT_AGC(3), agc3); 1734 mt76_wr(dev, MT_AGC1(3), agc3); 1735} 1736 1737static void 1738mt7603_false_cca_check(struct mt7603_dev *dev) 1739{ 1740 int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm; 1741 int false_cca; 1742 int min_signal; 1743 u32 val; 1744 1745 if (!dev->dynamic_sensitivity) 1746 return; 1747 1748 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); 1749 pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val); 1750 pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val); 1751 1752 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); 1753 mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val); 1754 mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val); 1755 1756 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1757 dev->false_cca_cck = pd_cck - mdrdy_cck; 1758 1759 mt7603_cca_stats_reset(dev); 1760 1761 min_signal = mt76_get_min_avg_rssi(&dev->mt76, false); 1762 if (!min_signal) { 1763 dev->sensitivity = 0; 1764 dev->last_cca_adj = jiffies; 1765 goto out; 1766 } 1767 1768 min_signal -= 15; 1769 1770 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; 1771 if (false_cca > 600 && 1772 dev->sensitivity < -100 + dev->sensitivity_limit) { 1773 if (!dev->sensitivity) 1774 dev->sensitivity = -92; 1775 else 1776 dev->sensitivity += 2; 1777 dev->last_cca_adj = jiffies; 1778 } else if (false_cca < 100 || 1779 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { 1780 dev->last_cca_adj = jiffies; 1781 if (!dev->sensitivity) 1782 goto out; 1783 1784 dev->sensitivity -= 2; 1785 } 1786 1787 if (dev->sensitivity && dev->sensitivity > min_signal) { 1788 dev->sensitivity = min_signal; 1789 dev->last_cca_adj = jiffies; 1790 } 1791 1792out: 1793 mt7603_adjust_sensitivity(dev); 1794} 1795 1796void mt7603_mac_work(struct work_struct *work) 1797{ 1798 struct mt7603_dev *dev = container_of(work, struct mt7603_dev, 1799 mt76.mac_work.work); 1800 bool reset = false; 1801 int i, idx; 1802 1803 mt76_tx_status_check(&dev->mt76, NULL, false); 1804 1805 mutex_lock(&dev->mt76.mutex); 1806 1807 dev->mac_work_count++; 1808 mt76_update_survey(&dev->mt76); 1809 mt7603_edcca_check(dev); 1810 1811 for (i = 0, idx = 0; i < 2; i++) { 1812 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 1813 1814 dev->mt76.aggr_stats[idx++] += val & 0xffff; 1815 dev->mt76.aggr_stats[idx++] += val >> 16; 1816 } 1817 1818 if (dev->mac_work_count == 10) 1819 mt7603_false_cca_check(dev); 1820 1821 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, 1822 RESET_CAUSE_RX_PSE_BUSY, 1823 mt7603_rx_pse_busy) || 1824 mt7603_watchdog_check(dev, &dev->beacon_check, 1825 RESET_CAUSE_BEACON_STUCK, 1826 NULL) || 1827 mt7603_watchdog_check(dev, &dev->tx_hang_check, 1828 RESET_CAUSE_TX_HANG, 1829 mt7603_tx_hang) || 1830 mt7603_watchdog_check(dev, &dev->tx_dma_check, 1831 RESET_CAUSE_TX_BUSY, 1832 mt7603_tx_dma_busy) || 1833 mt7603_watchdog_check(dev, &dev->rx_dma_check, 1834 RESET_CAUSE_RX_BUSY, 1835 mt7603_rx_dma_busy) || 1836 mt7603_watchdog_check(dev, &dev->mcu_hang, 1837 RESET_CAUSE_MCU_HANG, 1838 NULL) || 1839 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { 1840 dev->beacon_check = 0; 1841 dev->tx_dma_check = 0; 1842 dev->tx_hang_check = 0; 1843 dev->rx_dma_check = 0; 1844 dev->rx_pse_check = 0; 1845 dev->mcu_hang = 0; 1846 dev->rx_dma_idx = ~0; 1847 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); 1848 reset = true; 1849 dev->mac_work_count = 0; 1850 } 1851 1852 if (dev->mac_work_count >= 10) 1853 dev->mac_work_count = 0; 1854 1855 mutex_unlock(&dev->mt76.mutex); 1856 1857 if (reset) 1858 mt7603_mac_watchdog_reset(dev); 1859 1860 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work, 1861 msecs_to_jiffies(MT7603_WATCHDOG_TIME)); 1862} 1863