1// SPDX-License-Identifier: ISC 2 3#include "mt7603.h" 4#include "mac.h" 5#include "../dma.h" 6 7static int 8mt7603_init_tx_queue(struct mt7603_dev *dev, int qid, int idx, int n_desc) 9{ 10 struct mt76_queue *hwq; 11 int err; 12 13 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL); 14 if (!hwq) 15 return -ENOMEM; 16 17 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); 18 if (err < 0) 19 return err; 20 21 dev->mt76.q_tx[qid] = hwq; 22 23 mt7603_irq_enable(dev, MT_INT_TX_DONE(idx)); 24 25 return 0; 26} 27 28static void 29mt7603_rx_loopback_skb(struct mt7603_dev *dev, struct sk_buff *skb) 30{ 31 static const u8 tid_to_ac[8] = { 32 IEEE80211_AC_BE, 33 IEEE80211_AC_BK, 34 IEEE80211_AC_BK, 35 IEEE80211_AC_BE, 36 IEEE80211_AC_VI, 37 IEEE80211_AC_VI, 38 IEEE80211_AC_VO, 39 IEEE80211_AC_VO 40 }; 41 __le32 *txd = (__le32 *)skb->data; 42 struct ieee80211_hdr *hdr; 43 struct ieee80211_sta *sta; 44 struct mt7603_sta *msta; 45 struct mt76_wcid *wcid; 46 void *priv; 47 int idx; 48 u32 val; 49 u8 tid = 0; 50 51 if (skb->len < MT_TXD_SIZE + sizeof(struct ieee80211_hdr)) 52 goto free; 53 54 val = le32_to_cpu(txd[1]); 55 idx = FIELD_GET(MT_TXD1_WLAN_IDX, val); 56 skb->priority = FIELD_GET(MT_TXD1_TID, val); 57 58 if (idx >= MT7603_WTBL_STA - 1) 59 goto free; 60 61 wcid = rcu_dereference(dev->mt76.wcid[idx]); 62 if (!wcid) 63 goto free; 64 65 priv = msta = container_of(wcid, struct mt7603_sta, wcid); 66 val = le32_to_cpu(txd[0]); 67 val &= ~(MT_TXD0_P_IDX | MT_TXD0_Q_IDX); 68 val |= FIELD_PREP(MT_TXD0_Q_IDX, MT_TX_HW_QUEUE_MGMT); 69 txd[0] = cpu_to_le32(val); 70 71 sta = container_of(priv, struct ieee80211_sta, drv_priv); 72 hdr = (struct ieee80211_hdr *)&skb->data[MT_TXD_SIZE]; 73 if (ieee80211_is_data_qos(hdr->frame_control)) 74 tid = *ieee80211_get_qos_ctl(hdr) & 75 IEEE80211_QOS_CTL_TAG1D_MASK; 76 skb_set_queue_mapping(skb, tid_to_ac[tid]); 77 ieee80211_sta_set_buffered(sta, tid, true); 78 79 spin_lock_bh(&dev->ps_lock); 80 __skb_queue_tail(&msta->psq, skb); 81 if (skb_queue_len(&msta->psq) >= 64) { 82 skb = __skb_dequeue(&msta->psq); 83 dev_kfree_skb(skb); 84 } 85 spin_unlock_bh(&dev->ps_lock); 86 return; 87 88free: 89 dev_kfree_skb(skb); 90} 91 92void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 93 struct sk_buff *skb) 94{ 95 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 96 __le32 *rxd = (__le32 *)skb->data; 97 __le32 *end = (__le32 *)&skb->data[skb->len]; 98 enum rx_pkt_type type; 99 100 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 101 102 if (q == MT_RXQ_MCU) { 103 if (type == PKT_TYPE_RX_EVENT) 104 mt76_mcu_rx_event(&dev->mt76, skb); 105 else 106 mt7603_rx_loopback_skb(dev, skb); 107 return; 108 } 109 110 switch (type) { 111 case PKT_TYPE_TXS: 112 for (rxd++; rxd + 5 <= end; rxd += 5) 113 mt7603_mac_add_txs(dev, rxd); 114 dev_kfree_skb(skb); 115 break; 116 case PKT_TYPE_RX_EVENT: 117 mt76_mcu_rx_event(&dev->mt76, skb); 118 return; 119 case PKT_TYPE_NORMAL: 120 if (mt7603_mac_fill_rx(dev, skb) == 0) { 121 mt76_rx(&dev->mt76, q, skb); 122 return; 123 } 124 fallthrough; 125 default: 126 dev_kfree_skb(skb); 127 break; 128 } 129} 130 131static int 132mt7603_init_rx_queue(struct mt7603_dev *dev, struct mt76_queue *q, 133 int idx, int n_desc, int bufsize) 134{ 135 int err; 136 137 err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize, 138 MT_RX_RING_BASE); 139 if (err < 0) 140 return err; 141 142 mt7603_irq_enable(dev, MT_INT_RX_DONE(idx)); 143 144 return 0; 145} 146 147static int mt7603_poll_tx(struct napi_struct *napi, int budget) 148{ 149 struct mt7603_dev *dev; 150 int i; 151 152 dev = container_of(napi, struct mt7603_dev, mt76.tx_napi); 153 dev->tx_dma_check = 0; 154 155 for (i = MT_TXQ_MCU; i >= 0; i--) 156 mt76_queue_tx_cleanup(dev, i, false); 157 158 if (napi_complete_done(napi, 0)) 159 mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL); 160 161 for (i = MT_TXQ_MCU; i >= 0; i--) 162 mt76_queue_tx_cleanup(dev, i, false); 163 164 mt7603_mac_sta_poll(dev); 165 166 mt76_worker_schedule(&dev->mt76.tx_worker); 167 168 return 0; 169} 170 171int mt7603_dma_init(struct mt7603_dev *dev) 172{ 173 static const u8 wmm_queue_map[] = { 174 [IEEE80211_AC_BK] = 0, 175 [IEEE80211_AC_BE] = 1, 176 [IEEE80211_AC_VI] = 2, 177 [IEEE80211_AC_VO] = 3, 178 }; 179 int ret; 180 int i; 181 182 mt76_dma_attach(&dev->mt76); 183 184 mt76_clear(dev, MT_WPDMA_GLO_CFG, 185 MT_WPDMA_GLO_CFG_TX_DMA_EN | 186 MT_WPDMA_GLO_CFG_RX_DMA_EN | 187 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE | 188 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 189 190 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 191 mt7603_pse_client_reset(dev); 192 193 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { 194 ret = mt7603_init_tx_queue(dev, i, wmm_queue_map[i], 195 MT7603_TX_RING_SIZE); 196 if (ret) 197 return ret; 198 } 199 200 ret = mt7603_init_tx_queue(dev, MT_TXQ_PSD, 201 MT_TX_HW_QUEUE_MGMT, MT7603_PSD_RING_SIZE); 202 if (ret) 203 return ret; 204 205 ret = mt7603_init_tx_queue(dev, MT_TXQ_MCU, 206 MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE); 207 if (ret) 208 return ret; 209 210 ret = mt7603_init_tx_queue(dev, MT_TXQ_BEACON, 211 MT_TX_HW_QUEUE_BCN, MT_MCU_RING_SIZE); 212 if (ret) 213 return ret; 214 215 ret = mt7603_init_tx_queue(dev, MT_TXQ_CAB, 216 MT_TX_HW_QUEUE_BMC, MT_MCU_RING_SIZE); 217 if (ret) 218 return ret; 219 220 ret = mt7603_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 221 MT7603_MCU_RX_RING_SIZE, MT_RX_BUF_SIZE); 222 if (ret) 223 return ret; 224 225 ret = mt7603_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 226 MT7603_RX_RING_SIZE, MT_RX_BUF_SIZE); 227 if (ret) 228 return ret; 229 230 mt76_wr(dev, MT_DELAY_INT_CFG, 0); 231 ret = mt76_init_queues(dev); 232 if (ret) 233 return ret; 234 235 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 236 mt7603_poll_tx, NAPI_POLL_WEIGHT); 237 napi_enable(&dev->mt76.tx_napi); 238 239 return 0; 240} 241 242void mt7603_dma_cleanup(struct mt7603_dev *dev) 243{ 244 mt76_clear(dev, MT_WPDMA_GLO_CFG, 245 MT_WPDMA_GLO_CFG_TX_DMA_EN | 246 MT_WPDMA_GLO_CFG_RX_DMA_EN | 247 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 248 249 mt76_dma_cleanup(&dev->mt76); 250} 251