1/*
2 * NXP Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright 2011-2020 NXP
5 *
6 * This software file (the "File") is distributed by NXP
7 * under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License").  You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#ifndef	_MWIFIEX_SDIO_H
21#define	_MWIFIEX_SDIO_H
22
23
24#include <linux/completion.h>
25#include <linux/mmc/sdio.h>
26#include <linux/mmc/sdio_ids.h>
27#include <linux/mmc/sdio_func.h>
28#include <linux/mmc/card.h>
29#include <linux/mmc/host.h>
30
31#include "main.h"
32
33#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
34#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
35#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
36#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
37#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
38#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
39#define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin"
40#define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin"
41#define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin"
42
43#define BLOCK_MODE	1
44#define BYTE_MODE	0
45
46#define REG_PORT			0
47
48#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff
49
50#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000
51
52#define MWIFIEX_MAX_FUNC2_REG_NUM	13
53#define MWIFIEX_SDIO_SCRATCH_SIZE	10
54
55#define SDIO_MPA_ADDR_BASE		0x1000
56#define CTRL_PORT			0
57#define CTRL_PORT_MASK			0x0001
58
59#define CMD_PORT_UPLD_INT_MASK		(0x1U<<6)
60#define CMD_PORT_DNLD_INT_MASK		(0x1U<<7)
61#define HOST_TERM_CMD53			(0x1U << 2)
62#define REG_PORT			0
63#define MEM_PORT			0x10000
64
65#define CMD53_NEW_MODE			(0x1U << 0)
66#define CMD_PORT_RD_LEN_EN		(0x1U << 2)
67#define CMD_PORT_AUTO_EN		(0x1U << 0)
68#define CMD_PORT_SLCT			0x8000
69#define UP_LD_CMD_PORT_HOST_INT_STATUS	(0x40U)
70#define DN_LD_CMD_PORT_HOST_INT_STATUS	(0x80U)
71
72#define MWIFIEX_MP_AGGR_BUF_SIZE_16K	(16384)
73#define MWIFIEX_MP_AGGR_BUF_SIZE_32K	(32768)
74/* we leave one block of 256 bytes for DMA alignment*/
75#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX    (65280)
76
77/* Misc. Config Register : Auto Re-enable interrupts */
78#define AUTO_RE_ENABLE_INT              BIT(4)
79
80/* Host Control Registers : Configuration */
81#define CONFIGURATION_REG		0x00
82/* Host Control Registers : Host power up */
83#define HOST_POWER_UP			(0x1U << 1)
84
85/* Host Control Registers : Upload host interrupt mask */
86#define UP_LD_HOST_INT_MASK		(0x1U)
87/* Host Control Registers : Download host interrupt mask */
88#define DN_LD_HOST_INT_MASK		(0x2U)
89
90/* Host Control Registers : Upload host interrupt status */
91#define UP_LD_HOST_INT_STATUS		(0x1U)
92/* Host Control Registers : Download host interrupt status */
93#define DN_LD_HOST_INT_STATUS		(0x2U)
94
95/* Host Control Registers : Host interrupt status */
96#define CARD_INT_STATUS_REG		0x28
97
98/* Card Control Registers : Card I/O ready */
99#define CARD_IO_READY                   (0x1U << 3)
100/* Card Control Registers : Download card ready */
101#define DN_LD_CARD_RDY                  (0x1U << 0)
102
103/* Max retry number of CMD53 write */
104#define MAX_WRITE_IOMEM_RETRY		2
105
106/* SDIO Tx aggregation in progress ? */
107#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
108
109/* SDIO Tx aggregation buffer room for next packet ? */
110#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
111						<= a->mpa_tx.buf_size)
112
113/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
114#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
115	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
116			payload, pkt_len);				\
117	a->mpa_tx.buf_len += pkt_len;					\
118	if (!a->mpa_tx.pkt_cnt)						\
119		a->mpa_tx.start_port = port;				\
120	if (a->mpa_tx.start_port <= port)				\
121		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
122	else								\
123		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
124						(a->max_ports -	\
125						a->mp_end_port)));	\
126	a->mpa_tx.pkt_cnt++;						\
127} while (0)
128
129/* SDIO Tx aggregation limit ? */
130#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
131			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
132
133/* Reset SDIO Tx aggregation buffer parameters */
134#define MP_TX_AGGR_BUF_RESET(a) do {					\
135	a->mpa_tx.pkt_cnt = 0;						\
136	a->mpa_tx.buf_len = 0;						\
137	a->mpa_tx.ports = 0;						\
138	a->mpa_tx.start_port = 0;					\
139} while (0)
140
141/* SDIO Rx aggregation limit ? */
142#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
143			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
144
145/* SDIO Rx aggregation in progress ? */
146#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
147
148/* SDIO Rx aggregation buffer room for next packet ? */
149#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
150			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
151
152/* Reset SDIO Rx aggregation buffer parameters */
153#define MP_RX_AGGR_BUF_RESET(a) do {					\
154	a->mpa_rx.pkt_cnt = 0;						\
155	a->mpa_rx.buf_len = 0;						\
156	a->mpa_rx.ports = 0;						\
157	a->mpa_rx.start_port = 0;					\
158} while (0)
159
160/* data structure for SDIO MPA TX */
161struct mwifiex_sdio_mpa_tx {
162	/* multiport tx aggregation buffer pointer */
163	u8 *buf;
164	u32 buf_len;
165	u32 pkt_cnt;
166	u32 ports;
167	u16 start_port;
168	u8 enabled;
169	u32 buf_size;
170	u32 pkt_aggr_limit;
171};
172
173struct mwifiex_sdio_mpa_rx {
174	u8 *buf;
175	u32 buf_len;
176	u32 pkt_cnt;
177	u32 ports;
178	u16 start_port;
179
180	struct sk_buff **skb_arr;
181	u32 *len_arr;
182
183	u8 enabled;
184	u32 buf_size;
185	u32 pkt_aggr_limit;
186};
187
188int mwifiex_bus_register(void);
189void mwifiex_bus_unregister(void);
190
191struct mwifiex_sdio_card_reg {
192	u8 start_rd_port;
193	u8 start_wr_port;
194	u8 base_0_reg;
195	u8 base_1_reg;
196	u8 poll_reg;
197	u8 host_int_enable;
198	u8 host_int_rsr_reg;
199	u8 host_int_status_reg;
200	u8 host_int_mask_reg;
201	u8 status_reg_0;
202	u8 status_reg_1;
203	u8 sdio_int_mask;
204	u32 data_port_mask;
205	u8 io_port_0_reg;
206	u8 io_port_1_reg;
207	u8 io_port_2_reg;
208	u8 max_mp_regs;
209	u8 rd_bitmap_l;
210	u8 rd_bitmap_u;
211	u8 rd_bitmap_1l;
212	u8 rd_bitmap_1u;
213	u8 wr_bitmap_l;
214	u8 wr_bitmap_u;
215	u8 wr_bitmap_1l;
216	u8 wr_bitmap_1u;
217	u8 rd_len_p0_l;
218	u8 rd_len_p0_u;
219	u8 card_misc_cfg_reg;
220	u8 card_cfg_2_1_reg;
221	u8 cmd_rd_len_0;
222	u8 cmd_rd_len_1;
223	u8 cmd_rd_len_2;
224	u8 cmd_rd_len_3;
225	u8 cmd_cfg_0;
226	u8 cmd_cfg_1;
227	u8 cmd_cfg_2;
228	u8 cmd_cfg_3;
229	u8 fw_dump_host_ready;
230	u8 fw_dump_ctrl;
231	u8 fw_dump_start;
232	u8 fw_dump_end;
233	u8 func1_dump_reg_start;
234	u8 func1_dump_reg_end;
235	u8 func1_scratch_reg;
236	u8 func1_spec_reg_num;
237	u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
238};
239
240struct sdio_mmc_card {
241	struct sdio_func *func;
242	struct mwifiex_adapter *adapter;
243
244	struct completion fw_done;
245	const char *firmware;
246	const struct mwifiex_sdio_card_reg *reg;
247	u8 max_ports;
248	u8 mp_agg_pkt_limit;
249	u16 tx_buf_size;
250	u32 mp_tx_agg_buf_size;
251	u32 mp_rx_agg_buf_size;
252
253	u32 mp_rd_bitmap;
254	u32 mp_wr_bitmap;
255
256	u16 mp_end_port;
257	u32 mp_data_port_mask;
258
259	u8 curr_rd_port;
260	u8 curr_wr_port;
261
262	u8 *mp_regs;
263	bool supports_sdio_new_mode;
264	bool has_control_mask;
265	bool can_dump_fw;
266	bool fw_dump_enh;
267	bool can_auto_tdls;
268	bool can_ext_scan;
269
270	struct mwifiex_sdio_mpa_tx mpa_tx;
271	struct mwifiex_sdio_mpa_rx mpa_rx;
272
273	struct work_struct work;
274	unsigned long work_flags;
275};
276
277struct mwifiex_sdio_device {
278	const char *firmware;
279	const struct mwifiex_sdio_card_reg *reg;
280	u8 max_ports;
281	u8 mp_agg_pkt_limit;
282	u16 tx_buf_size;
283	u32 mp_tx_agg_buf_size;
284	u32 mp_rx_agg_buf_size;
285	bool supports_sdio_new_mode;
286	bool has_control_mask;
287	bool can_dump_fw;
288	bool fw_dump_enh;
289	bool can_auto_tdls;
290	bool can_ext_scan;
291};
292
293/*
294 * .cmdrsp_complete handler
295 */
296static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
297					       struct sk_buff *skb)
298{
299	dev_kfree_skb_any(skb);
300	return 0;
301}
302
303/*
304 * .event_complete handler
305 */
306static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
307					      struct sk_buff *skb)
308{
309	dev_kfree_skb_any(skb);
310	return 0;
311}
312
313static inline bool
314mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
315{
316	u8 tmp;
317
318	if (card->curr_rd_port < card->mpa_rx.start_port) {
319		if (card->supports_sdio_new_mode)
320			tmp = card->mp_end_port >> 1;
321		else
322			tmp = card->mp_agg_pkt_limit;
323
324		if (((card->max_ports - card->mpa_rx.start_port) +
325		    card->curr_rd_port) >= tmp)
326			return true;
327	}
328
329	if (!card->supports_sdio_new_mode)
330		return false;
331
332	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
333	    (card->mp_end_port >> 1))
334		return true;
335
336	return false;
337}
338
339static inline bool
340mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
341{
342	u16 tmp;
343
344	if (card->curr_wr_port < card->mpa_tx.start_port) {
345		if (card->supports_sdio_new_mode)
346			tmp = card->mp_end_port >> 1;
347		else
348			tmp = card->mp_agg_pkt_limit;
349
350		if (((card->max_ports - card->mpa_tx.start_port) +
351		    card->curr_wr_port) >= tmp)
352			return true;
353	}
354
355	if (!card->supports_sdio_new_mode)
356		return false;
357
358	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
359	    (card->mp_end_port >> 1))
360		return true;
361
362	return false;
363}
364
365/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
366static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
367				    u16 rx_len, u8 port)
368{
369	card->mpa_rx.buf_len += rx_len;
370
371	if (!card->mpa_rx.pkt_cnt)
372		card->mpa_rx.start_port = port;
373
374	if (card->supports_sdio_new_mode) {
375		card->mpa_rx.ports |= (1 << port);
376	} else {
377		if (card->mpa_rx.start_port <= port)
378			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
379		else
380			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
381	}
382	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
383	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
384	card->mpa_rx.pkt_cnt++;
385}
386#endif /* _MWIFIEX_SDIO_H */
387