1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64#include <linux/firmware.h> 65#include <linux/rtnetlink.h> 66#include "iwl-trans.h" 67#include "iwl-csr.h" 68#include "mvm.h" 69#include "iwl-eeprom-parse.h" 70#include "iwl-eeprom-read.h" 71#include "iwl-nvm-parse.h" 72#include "iwl-prph.h" 73#include "fw/acpi.h" 74 75/* Default NVM size to read */ 76#define IWL_NVM_DEFAULT_CHUNK_SIZE (2 * 1024) 77 78#define NVM_WRITE_OPCODE 1 79#define NVM_READ_OPCODE 0 80 81/* load nvm chunk response */ 82enum { 83 READ_NVM_CHUNK_SUCCEED = 0, 84 READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 85}; 86 87/* 88 * prepare the NVM host command w/ the pointers to the nvm buffer 89 * and send it to fw 90 */ 91static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, 92 u16 offset, u16 length, const u8 *data) 93{ 94 struct iwl_nvm_access_cmd nvm_access_cmd = { 95 .offset = cpu_to_le16(offset), 96 .length = cpu_to_le16(length), 97 .type = cpu_to_le16(section), 98 .op_code = NVM_WRITE_OPCODE, 99 }; 100 struct iwl_host_cmd cmd = { 101 .id = NVM_ACCESS_CMD, 102 .len = { sizeof(struct iwl_nvm_access_cmd), length }, 103 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 104 .data = { &nvm_access_cmd, data }, 105 /* data may come from vmalloc, so use _DUP */ 106 .dataflags = { 0, IWL_HCMD_DFL_DUP }, 107 }; 108 struct iwl_rx_packet *pkt; 109 struct iwl_nvm_access_resp *nvm_resp; 110 int ret; 111 112 ret = iwl_mvm_send_cmd(mvm, &cmd); 113 if (ret) 114 return ret; 115 116 pkt = cmd.resp_pkt; 117 /* Extract & check NVM write response */ 118 nvm_resp = (void *)pkt->data; 119 if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) { 120 IWL_ERR(mvm, 121 "NVM access write command failed for section %u (status = 0x%x)\n", 122 section, le16_to_cpu(nvm_resp->status)); 123 ret = -EIO; 124 } 125 126 iwl_free_resp(&cmd); 127 return ret; 128} 129 130static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, 131 u16 offset, u16 length, u8 *data) 132{ 133 struct iwl_nvm_access_cmd nvm_access_cmd = { 134 .offset = cpu_to_le16(offset), 135 .length = cpu_to_le16(length), 136 .type = cpu_to_le16(section), 137 .op_code = NVM_READ_OPCODE, 138 }; 139 struct iwl_nvm_access_resp *nvm_resp; 140 struct iwl_rx_packet *pkt; 141 struct iwl_host_cmd cmd = { 142 .id = NVM_ACCESS_CMD, 143 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 144 .data = { &nvm_access_cmd, }, 145 }; 146 int ret, bytes_read, offset_read; 147 u8 *resp_data; 148 149 cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); 150 151 ret = iwl_mvm_send_cmd(mvm, &cmd); 152 if (ret) 153 return ret; 154 155 pkt = cmd.resp_pkt; 156 157 /* Extract NVM response */ 158 nvm_resp = (void *)pkt->data; 159 ret = le16_to_cpu(nvm_resp->status); 160 bytes_read = le16_to_cpu(nvm_resp->length); 161 offset_read = le16_to_cpu(nvm_resp->offset); 162 resp_data = nvm_resp->data; 163 if (ret) { 164 if ((offset != 0) && 165 (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { 166 /* 167 * meaning of NOT_VALID_ADDRESS: 168 * driver try to read chunk from address that is 169 * multiple of 2K and got an error since addr is empty. 170 * meaning of (offset != 0): driver already 171 * read valid data from another chunk so this case 172 * is not an error. 173 */ 174 IWL_DEBUG_EEPROM(mvm->trans->dev, 175 "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", 176 offset); 177 ret = 0; 178 } else { 179 IWL_DEBUG_EEPROM(mvm->trans->dev, 180 "NVM access command failed with status %d (device: %s)\n", 181 ret, mvm->trans->name); 182 ret = -ENODATA; 183 } 184 goto exit; 185 } 186 187 if (offset_read != offset) { 188 IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", 189 offset_read); 190 ret = -EINVAL; 191 goto exit; 192 } 193 194 /* Write data to NVM */ 195 memcpy(data + offset, resp_data, bytes_read); 196 ret = bytes_read; 197 198exit: 199 iwl_free_resp(&cmd); 200 return ret; 201} 202 203static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, 204 const u8 *data, u16 length) 205{ 206 int offset = 0; 207 208 /* copy data in chunks of 2k (and remainder if any) */ 209 210 while (offset < length) { 211 int chunk_size, ret; 212 213 chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, 214 length - offset); 215 216 ret = iwl_nvm_write_chunk(mvm, section, offset, 217 chunk_size, data + offset); 218 if (ret < 0) 219 return ret; 220 221 offset += chunk_size; 222 } 223 224 return 0; 225} 226 227/* 228 * Reads an NVM section completely. 229 * NICs prior to 7000 family doesn't have a real NVM, but just read 230 * section 0 which is the EEPROM. Because the EEPROM reading is unlimited 231 * by uCode, we need to manually check in this case that we don't 232 * overflow and try to read more than the EEPROM size. 233 * For 7000 family NICs, we supply the maximal size we can read, and 234 * the uCode fills the response with as much data as we can, 235 * without overflowing, so no check is needed. 236 */ 237static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, 238 u8 *data, u32 size_read) 239{ 240 u16 length, offset = 0; 241 int ret; 242 243 /* Set nvm section read length */ 244 length = IWL_NVM_DEFAULT_CHUNK_SIZE; 245 246 ret = length; 247 248 /* Read the NVM until exhausted (reading less than requested) */ 249 while (ret == length) { 250 /* Check no memory assumptions fail and cause an overflow */ 251 if ((size_read + offset + length) > 252 mvm->trans->trans_cfg->base_params->eeprom_size) { 253 IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); 254 return -ENOBUFS; 255 } 256 257 ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); 258 if (ret < 0) { 259 IWL_DEBUG_EEPROM(mvm->trans->dev, 260 "Cannot read NVM from section %d offset %d, length %d\n", 261 section, offset, length); 262 return ret; 263 } 264 offset += ret; 265 } 266 267 iwl_nvm_fixups(mvm->trans->hw_id, section, data, offset); 268 269 IWL_DEBUG_EEPROM(mvm->trans->dev, 270 "NVM section %d read completed\n", section); 271 return offset; 272} 273 274static struct iwl_nvm_data * 275iwl_parse_nvm_sections(struct iwl_mvm *mvm) 276{ 277 struct iwl_nvm_section *sections = mvm->nvm_sections; 278 const __be16 *hw; 279 const __le16 *sw, *calib, *regulatory, *mac_override, *phy_sku; 280 int regulatory_type; 281 282 /* Checking for required sections */ 283 if (mvm->trans->cfg->nvm_type == IWL_NVM) { 284 if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || 285 !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { 286 IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); 287 return NULL; 288 } 289 } else { 290 if (mvm->trans->cfg->nvm_type == IWL_NVM_SDP) 291 regulatory_type = NVM_SECTION_TYPE_REGULATORY_SDP; 292 else 293 regulatory_type = NVM_SECTION_TYPE_REGULATORY; 294 295 /* SW and REGULATORY sections are mandatory */ 296 if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || 297 !mvm->nvm_sections[regulatory_type].data) { 298 IWL_ERR(mvm, 299 "Can't parse empty family 8000 OTP/NVM sections\n"); 300 return NULL; 301 } 302 /* MAC_OVERRIDE or at least HW section must exist */ 303 if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && 304 !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { 305 IWL_ERR(mvm, 306 "Can't parse mac_address, empty sections\n"); 307 return NULL; 308 } 309 310 /* PHY_SKU section is mandatory in B0 */ 311 if (mvm->trans->cfg->nvm_type == IWL_NVM_EXT && 312 !mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { 313 IWL_ERR(mvm, 314 "Can't parse phy_sku in B0, empty sections\n"); 315 return NULL; 316 } 317 } 318 319 hw = (const __be16 *)sections[mvm->cfg->nvm_hw_section_num].data; 320 sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; 321 calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; 322 mac_override = 323 (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; 324 phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; 325 326 regulatory = mvm->trans->cfg->nvm_type == IWL_NVM_SDP ? 327 (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY_SDP].data : 328 (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; 329 330 return iwl_parse_nvm_data(mvm->trans, mvm->cfg, mvm->fw, hw, sw, calib, 331 regulatory, mac_override, phy_sku, 332 mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant); 333} 334 335/* Loads the NVM data stored in mvm->nvm_sections into the NIC */ 336int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) 337{ 338 int i, ret = 0; 339 struct iwl_nvm_section *sections = mvm->nvm_sections; 340 341 IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); 342 343 for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { 344 if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) 345 continue; 346 ret = iwl_nvm_write_section(mvm, i, sections[i].data, 347 sections[i].length); 348 if (ret < 0) { 349 IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); 350 break; 351 } 352 } 353 return ret; 354} 355 356int iwl_nvm_init(struct iwl_mvm *mvm) 357{ 358 int ret, section; 359 u32 size_read = 0; 360 u8 *nvm_buffer, *temp; 361 const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step; 362 363 if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) 364 return -EINVAL; 365 366 /* load NVM values from nic */ 367 /* Read From FW NVM */ 368 IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); 369 370 nvm_buffer = kmalloc(mvm->trans->trans_cfg->base_params->eeprom_size, 371 GFP_KERNEL); 372 if (!nvm_buffer) 373 return -ENOMEM; 374 for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { 375 /* we override the constness for initial read */ 376 ret = iwl_nvm_read_section(mvm, section, nvm_buffer, 377 size_read); 378 if (ret == -ENODATA) { 379 ret = 0; 380 continue; 381 } 382 if (ret < 0) 383 break; 384 size_read += ret; 385 temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); 386 if (!temp) { 387 ret = -ENOMEM; 388 break; 389 } 390 391 iwl_nvm_fixups(mvm->trans->hw_id, section, temp, ret); 392 393 mvm->nvm_sections[section].data = temp; 394 mvm->nvm_sections[section].length = ret; 395 396#ifdef CONFIG_IWLWIFI_DEBUGFS 397 switch (section) { 398 case NVM_SECTION_TYPE_SW: 399 mvm->nvm_sw_blob.data = temp; 400 mvm->nvm_sw_blob.size = ret; 401 break; 402 case NVM_SECTION_TYPE_CALIBRATION: 403 mvm->nvm_calib_blob.data = temp; 404 mvm->nvm_calib_blob.size = ret; 405 break; 406 case NVM_SECTION_TYPE_PRODUCTION: 407 mvm->nvm_prod_blob.data = temp; 408 mvm->nvm_prod_blob.size = ret; 409 break; 410 case NVM_SECTION_TYPE_PHY_SKU: 411 mvm->nvm_phy_sku_blob.data = temp; 412 mvm->nvm_phy_sku_blob.size = ret; 413 break; 414 case NVM_SECTION_TYPE_REGULATORY_SDP: 415 case NVM_SECTION_TYPE_REGULATORY: 416 mvm->nvm_reg_blob.data = temp; 417 mvm->nvm_reg_blob.size = ret; 418 break; 419 default: 420 if (section == mvm->cfg->nvm_hw_section_num) { 421 mvm->nvm_hw_blob.data = temp; 422 mvm->nvm_hw_blob.size = ret; 423 break; 424 } 425 } 426#endif 427 } 428 if (!size_read) 429 IWL_ERR(mvm, "OTP is blank\n"); 430 kfree(nvm_buffer); 431 432 /* Only if PNVM selected in the mod param - load external NVM */ 433 if (mvm->nvm_file_name) { 434 /* read External NVM file from the mod param */ 435 ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, 436 mvm->nvm_sections); 437 if (ret) { 438 mvm->nvm_file_name = nvm_file_C; 439 440 if ((ret == -EFAULT || ret == -ENOENT) && 441 mvm->nvm_file_name) { 442 /* in case nvm file was failed try again */ 443 ret = iwl_read_external_nvm(mvm->trans, 444 mvm->nvm_file_name, 445 mvm->nvm_sections); 446 if (ret) 447 return ret; 448 } else { 449 return ret; 450 } 451 } 452 } 453 454 /* parse the relevant nvm sections */ 455 mvm->nvm_data = iwl_parse_nvm_sections(mvm); 456 if (!mvm->nvm_data) 457 return -ENODATA; 458 IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", 459 mvm->nvm_data->nvm_version); 460 461 return ret < 0 ? ret : 0; 462} 463 464struct iwl_mcc_update_resp * 465iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, 466 enum iwl_mcc_source src_id) 467{ 468 struct iwl_mcc_update_cmd mcc_update_cmd = { 469 .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), 470 .source_id = (u8)src_id, 471 }; 472 struct iwl_mcc_update_resp *resp_cp; 473 struct iwl_rx_packet *pkt; 474 struct iwl_host_cmd cmd = { 475 .id = MCC_UPDATE_CMD, 476 .flags = CMD_WANT_SKB, 477 .data = { &mcc_update_cmd }, 478 }; 479 480 int ret; 481 u32 status; 482 int resp_len, n_channels; 483 u16 mcc; 484 485 if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) 486 return ERR_PTR(-EOPNOTSUPP); 487 488 cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); 489 490 IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n", 491 alpha2[0], alpha2[1], src_id); 492 493 ret = iwl_mvm_send_cmd(mvm, &cmd); 494 if (ret) 495 return ERR_PTR(ret); 496 497 pkt = cmd.resp_pkt; 498 499 /* Extract MCC response */ 500 if (fw_has_capa(&mvm->fw->ucode_capa, 501 IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT)) { 502 struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data; 503 504 n_channels = __le32_to_cpu(mcc_resp->n_channels); 505 if (iwl_rx_packet_payload_len(pkt) != 506 struct_size(mcc_resp, channels, n_channels)) { 507 resp_cp = ERR_PTR(-EINVAL); 508 goto exit; 509 } 510 resp_len = sizeof(struct iwl_mcc_update_resp) + 511 n_channels * sizeof(__le32); 512 resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); 513 if (!resp_cp) { 514 resp_cp = ERR_PTR(-ENOMEM); 515 goto exit; 516 } 517 } else { 518 struct iwl_mcc_update_resp_v3 *mcc_resp_v3 = (void *)pkt->data; 519 520 n_channels = __le32_to_cpu(mcc_resp_v3->n_channels); 521 if (iwl_rx_packet_payload_len(pkt) != 522 struct_size(mcc_resp_v3, channels, n_channels)) { 523 resp_cp = ERR_PTR(-EINVAL); 524 goto exit; 525 } 526 resp_len = sizeof(struct iwl_mcc_update_resp) + 527 n_channels * sizeof(__le32); 528 resp_cp = kzalloc(resp_len, GFP_KERNEL); 529 if (!resp_cp) { 530 resp_cp = ERR_PTR(-ENOMEM); 531 goto exit; 532 } 533 534 resp_cp->status = mcc_resp_v3->status; 535 resp_cp->mcc = mcc_resp_v3->mcc; 536 resp_cp->cap = cpu_to_le16(mcc_resp_v3->cap); 537 resp_cp->source_id = mcc_resp_v3->source_id; 538 resp_cp->time = mcc_resp_v3->time; 539 resp_cp->geo_info = mcc_resp_v3->geo_info; 540 resp_cp->n_channels = mcc_resp_v3->n_channels; 541 memcpy(resp_cp->channels, mcc_resp_v3->channels, 542 n_channels * sizeof(__le32)); 543 } 544 545 status = le32_to_cpu(resp_cp->status); 546 547 mcc = le16_to_cpu(resp_cp->mcc); 548 549 /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ 550 if (mcc == 0) { 551 mcc = 0x3030; /* "00" - world */ 552 resp_cp->mcc = cpu_to_le16(mcc); 553 } 554 555 IWL_DEBUG_LAR(mvm, 556 "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') n_chans: %d\n", 557 status, mcc, mcc >> 8, mcc & 0xff, n_channels); 558 559exit: 560 iwl_free_resp(&cmd); 561 return resp_cp; 562} 563 564int iwl_mvm_init_mcc(struct iwl_mvm *mvm) 565{ 566 bool tlv_lar; 567 bool nvm_lar; 568 int retval; 569 struct ieee80211_regdomain *regd; 570 char mcc[3]; 571 572 if (mvm->cfg->nvm_type == IWL_NVM_EXT) { 573 tlv_lar = fw_has_capa(&mvm->fw->ucode_capa, 574 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 575 nvm_lar = mvm->nvm_data->lar_enabled; 576 if (tlv_lar != nvm_lar) 577 IWL_INFO(mvm, 578 "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", 579 tlv_lar ? "enabled" : "disabled", 580 nvm_lar ? "enabled" : "disabled"); 581 } 582 583 if (!iwl_mvm_is_lar_supported(mvm)) 584 return 0; 585 586 /* 587 * try to replay the last set MCC to FW. If it doesn't exist, 588 * queue an update to cfg80211 to retrieve the default alpha2 from FW. 589 */ 590 retval = iwl_mvm_init_fw_regd(mvm); 591 if (retval != -ENOENT) 592 return retval; 593 594 /* 595 * Driver regulatory hint for initial update, this also informs the 596 * firmware we support wifi location updates. 597 * Disallow scans that might crash the FW while the LAR regdomain 598 * is not set. 599 */ 600 mvm->lar_regdom_set = false; 601 602 regd = iwl_mvm_get_current_regdomain(mvm, NULL); 603 if (IS_ERR_OR_NULL(regd)) 604 return -EIO; 605 606 if (iwl_mvm_is_wifi_mcc_supported(mvm) && 607 !iwl_acpi_get_mcc(mvm->dev, mcc)) { 608 kfree(regd); 609 regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, 610 MCC_SOURCE_BIOS, NULL); 611 if (IS_ERR_OR_NULL(regd)) 612 return -EIO; 613 } 614 615 retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd); 616 kfree(regd); 617 return retval; 618} 619 620void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, 621 struct iwl_rx_cmd_buffer *rxb) 622{ 623 struct iwl_rx_packet *pkt = rxb_addr(rxb); 624 struct iwl_mcc_chub_notif *notif = (void *)pkt->data; 625 enum iwl_mcc_source src; 626 char mcc[3]; 627 struct ieee80211_regdomain *regd; 628 int wgds_tbl_idx; 629 630 lockdep_assert_held(&mvm->mutex); 631 632 if (iwl_mvm_is_vif_assoc(mvm) && notif->source_id == MCC_SOURCE_WIFI) { 633 IWL_DEBUG_LAR(mvm, "Ignore mcc update while associated\n"); 634 return; 635 } 636 637 if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) 638 return; 639 640 mcc[0] = le16_to_cpu(notif->mcc) >> 8; 641 mcc[1] = le16_to_cpu(notif->mcc) & 0xff; 642 mcc[2] = '\0'; 643 src = notif->source_id; 644 645 IWL_DEBUG_LAR(mvm, 646 "RX: received chub update mcc cmd (mcc '%s' src %d)\n", 647 mcc, src); 648 regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL); 649 if (IS_ERR_OR_NULL(regd)) 650 return; 651 652 wgds_tbl_idx = iwl_mvm_get_sar_geo_profile(mvm); 653 if (wgds_tbl_idx < 0) 654 IWL_DEBUG_INFO(mvm, "SAR WGDS is disabled (%d)\n", 655 wgds_tbl_idx); 656 else 657 IWL_DEBUG_INFO(mvm, "SAR WGDS: geo profile %d is configured\n", 658 wgds_tbl_idx); 659 660 regulatory_set_wiphy_regd(mvm->hw->wiphy, regd); 661 kfree(regd); 662} 663