1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64#ifndef __iwl_trans_h__ 65#define __iwl_trans_h__ 66 67#include <linux/ieee80211.h> 68#include <linux/mm.h> /* for page_address */ 69#include <linux/lockdep.h> 70#include <linux/kernel.h> 71 72#include "iwl-debug.h" 73#include "iwl-config.h" 74#include "fw/img.h" 75#include "iwl-op-mode.h" 76#include <linux/firmware.h> 77#include "fw/api/cmdhdr.h" 78#include "fw/api/txq.h" 79#include "fw/api/dbg-tlv.h" 80#include "iwl-dbg-tlv.h" 81 82/** 83 * DOC: Transport layer - what is it ? 84 * 85 * The transport layer is the layer that deals with the HW directly. It provides 86 * an abstraction of the underlying HW to the upper layer. The transport layer 87 * doesn't provide any policy, algorithm or anything of this kind, but only 88 * mechanisms to make the HW do something. It is not completely stateless but 89 * close to it. 90 * We will have an implementation for each different supported bus. 91 */ 92 93/** 94 * DOC: Life cycle of the transport layer 95 * 96 * The transport layer has a very precise life cycle. 97 * 98 * 1) A helper function is called during the module initialization and 99 * registers the bus driver's ops with the transport's alloc function. 100 * 2) Bus's probe calls to the transport layer's allocation functions. 101 * Of course this function is bus specific. 102 * 3) This allocation functions will spawn the upper layer which will 103 * register mac80211. 104 * 105 * 4) At some point (i.e. mac80211's start call), the op_mode will call 106 * the following sequence: 107 * start_hw 108 * start_fw 109 * 110 * 5) Then when finished (or reset): 111 * stop_device 112 * 113 * 6) Eventually, the free function will be called. 114 */ 115 116#define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 117 118#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 119#define FH_RSCSR_FRAME_INVALID 0x55550000 120#define FH_RSCSR_FRAME_ALIGN 0x40 121#define FH_RSCSR_RPA_EN BIT(25) 122#define FH_RSCSR_RADA_EN BIT(26) 123#define FH_RSCSR_RXQ_POS 16 124#define FH_RSCSR_RXQ_MASK 0x3F0000 125 126struct iwl_rx_packet { 127 /* 128 * The first 4 bytes of the RX frame header contain both the RX frame 129 * size and some flags. 130 * Bit fields: 131 * 31: flag flush RB request 132 * 30: flag ignore TC (terminal counter) request 133 * 29: flag fast IRQ request 134 * 28-27: Reserved 135 * 26: RADA enabled 136 * 25: Offload enabled 137 * 24: RPF enabled 138 * 23: RSS enabled 139 * 22: Checksum enabled 140 * 21-16: RX queue 141 * 15-14: Reserved 142 * 13-00: RX frame size 143 */ 144 __le32 len_n_flags; 145 struct iwl_cmd_header hdr; 146 u8 data[]; 147} __packed; 148 149static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 150{ 151 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 152} 153 154static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 155{ 156 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 157} 158 159/** 160 * enum CMD_MODE - how to send the host commands ? 161 * 162 * @CMD_ASYNC: Return right away and don't wait for the response 163 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 164 * the response. The caller needs to call iwl_free_resp when done. 165 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 166 * called after this command completes. Valid only with CMD_ASYNC. 167 */ 168enum CMD_MODE { 169 CMD_ASYNC = BIT(0), 170 CMD_WANT_SKB = BIT(1), 171 CMD_SEND_IN_RFKILL = BIT(2), 172 CMD_WANT_ASYNC_CALLBACK = BIT(3), 173}; 174 175#define DEF_CMD_PAYLOAD_SIZE 320 176 177/** 178 * struct iwl_device_cmd 179 * 180 * For allocation of the command and tx queues, this establishes the overall 181 * size of the largest command we send to uCode, except for commands that 182 * aren't fully copied and use other TFD space. 183 */ 184struct iwl_device_cmd { 185 union { 186 struct { 187 struct iwl_cmd_header hdr; /* uCode API */ 188 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 189 }; 190 struct { 191 struct iwl_cmd_header_wide hdr_wide; 192 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 193 sizeof(struct iwl_cmd_header_wide) + 194 sizeof(struct iwl_cmd_header)]; 195 }; 196 }; 197} __packed; 198 199/** 200 * struct iwl_device_tx_cmd - buffer for TX command 201 * @hdr: the header 202 * @payload: the payload placeholder 203 * 204 * The actual structure is sized dynamically according to need. 205 */ 206struct iwl_device_tx_cmd { 207 struct iwl_cmd_header hdr; 208 u8 payload[]; 209} __packed; 210 211#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 212 213/* 214 * number of transfer buffers (fragments) per transmit frame descriptor; 215 * this is just the driver's idea, the hardware supports 20 216 */ 217#define IWL_MAX_CMD_TBS_PER_TFD 2 218 219/* We need 2 entries for the TX command and header, and another one might 220 * be needed for potential data in the SKB's head. The remaining ones can 221 * be used for frags. 222 */ 223#define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 224 225/** 226 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 227 * 228 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 229 * ring. The transport layer doesn't map the command's buffer to DMA, but 230 * rather copies it to a previously allocated DMA buffer. This flag tells 231 * the transport layer not to copy the command, but to map the existing 232 * buffer (that is passed in) instead. This saves the memcpy and allows 233 * commands that are bigger than the fixed buffer to be submitted. 234 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 235 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 236 * chunk internally and free it again after the command completes. This 237 * can (currently) be used only once per command. 238 * Note that a TFD entry after a DUP one cannot be a normal copied one. 239 */ 240enum iwl_hcmd_dataflag { 241 IWL_HCMD_DFL_NOCOPY = BIT(0), 242 IWL_HCMD_DFL_DUP = BIT(1), 243}; 244 245enum iwl_error_event_table_status { 246 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 247 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 248 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 249}; 250 251/** 252 * struct iwl_host_cmd - Host command to the uCode 253 * 254 * @data: array of chunks that composes the data of the host command 255 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 256 * @_rx_page_order: (internally used to free response packet) 257 * @_rx_page_addr: (internally used to free response packet) 258 * @flags: can be CMD_* 259 * @len: array of the lengths of the chunks in data 260 * @dataflags: IWL_HCMD_DFL_* 261 * @id: command id of the host command, for wide commands encoding the 262 * version and group as well 263 */ 264struct iwl_host_cmd { 265 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 266 struct iwl_rx_packet *resp_pkt; 267 unsigned long _rx_page_addr; 268 u32 _rx_page_order; 269 270 u32 flags; 271 u32 id; 272 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 273 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 274}; 275 276static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 277{ 278 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 279} 280 281struct iwl_rx_cmd_buffer { 282 struct page *_page; 283 int _offset; 284 bool _page_stolen; 285 u32 _rx_page_order; 286 unsigned int truesize; 287}; 288 289static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 290{ 291 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 292} 293 294static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 295{ 296 return r->_offset; 297} 298 299static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 300{ 301 r->_page_stolen = true; 302 get_page(r->_page); 303 return r->_page; 304} 305 306static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 307{ 308 __free_pages(r->_page, r->_rx_page_order); 309} 310 311#define MAX_NO_RECLAIM_CMDS 6 312 313#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 314 315/* 316 * Maximum number of HW queues the transport layer 317 * currently supports 318 */ 319#define IWL_MAX_HW_QUEUES 32 320#define IWL_MAX_TVQM_QUEUES 512 321 322#define IWL_MAX_TID_COUNT 8 323#define IWL_MGMT_TID 15 324#define IWL_FRAME_LIMIT 64 325#define IWL_MAX_RX_HW_QUEUES 16 326#define IWL_9000_MAX_RX_HW_QUEUES 6 327 328/** 329 * enum iwl_wowlan_status - WoWLAN image/device status 330 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 331 * @IWL_D3_STATUS_RESET: device was reset while suspended 332 */ 333enum iwl_d3_status { 334 IWL_D3_STATUS_ALIVE, 335 IWL_D3_STATUS_RESET, 336}; 337 338/** 339 * enum iwl_trans_status: transport status flags 340 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 341 * @STATUS_DEVICE_ENABLED: APM is enabled 342 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 343 * @STATUS_INT_ENABLED: interrupts are enabled 344 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 345 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 346 * @STATUS_FW_ERROR: the fw is in error state 347 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 348 * are sent 349 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 350 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 351 */ 352enum iwl_trans_status { 353 STATUS_SYNC_HCMD_ACTIVE, 354 STATUS_DEVICE_ENABLED, 355 STATUS_TPOWER_PMI, 356 STATUS_INT_ENABLED, 357 STATUS_RFKILL_HW, 358 STATUS_RFKILL_OPMODE, 359 STATUS_FW_ERROR, 360 STATUS_TRANS_GOING_IDLE, 361 STATUS_TRANS_IDLE, 362 STATUS_TRANS_DEAD, 363}; 364 365static inline int 366iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 367{ 368 switch (rb_size) { 369 case IWL_AMSDU_2K: 370 return get_order(2 * 1024); 371 case IWL_AMSDU_4K: 372 return get_order(4 * 1024); 373 case IWL_AMSDU_8K: 374 return get_order(8 * 1024); 375 case IWL_AMSDU_12K: 376 return get_order(12 * 1024); 377 default: 378 WARN_ON(1); 379 return -1; 380 } 381} 382 383static inline int 384iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 385{ 386 switch (rb_size) { 387 case IWL_AMSDU_2K: 388 return 2 * 1024; 389 case IWL_AMSDU_4K: 390 return 4 * 1024; 391 case IWL_AMSDU_8K: 392 return 8 * 1024; 393 case IWL_AMSDU_12K: 394 return 12 * 1024; 395 default: 396 WARN_ON(1); 397 return 0; 398 } 399} 400 401struct iwl_hcmd_names { 402 u8 cmd_id; 403 const char *const cmd_name; 404}; 405 406#define HCMD_NAME(x) \ 407 { .cmd_id = x, .cmd_name = #x } 408 409struct iwl_hcmd_arr { 410 const struct iwl_hcmd_names *arr; 411 int size; 412}; 413 414#define HCMD_ARR(x) \ 415 { .arr = x, .size = ARRAY_SIZE(x) } 416 417/** 418 * struct iwl_trans_config - transport configuration 419 * 420 * @op_mode: pointer to the upper layer. 421 * @cmd_queue: the index of the command queue. 422 * Must be set before start_fw. 423 * @cmd_fifo: the fifo for host commands 424 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 425 * @no_reclaim_cmds: Some devices erroneously don't set the 426 * SEQ_RX_FRAME bit on some notifications, this is the 427 * list of such notifications to filter. Max length is 428 * %MAX_NO_RECLAIM_CMDS. 429 * @n_no_reclaim_cmds: # of commands in list 430 * @rx_buf_size: RX buffer size needed for A-MSDUs 431 * if unset 4k will be the RX buffer size 432 * @bc_table_dword: set to true if the BC table expects the byte count to be 433 * in DWORD (as opposed to bytes) 434 * @scd_set_active: should the transport configure the SCD for HCMD queue 435 * @sw_csum_tx: transport should compute the TCP checksum 436 * @command_groups: array of command groups, each member is an array of the 437 * commands in the group; for debugging only 438 * @command_groups_size: number of command groups, to avoid illegal access 439 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 440 * space for at least two pointers 441 */ 442struct iwl_trans_config { 443 struct iwl_op_mode *op_mode; 444 445 u8 cmd_queue; 446 u8 cmd_fifo; 447 unsigned int cmd_q_wdg_timeout; 448 const u8 *no_reclaim_cmds; 449 unsigned int n_no_reclaim_cmds; 450 451 enum iwl_amsdu_size rx_buf_size; 452 bool bc_table_dword; 453 bool scd_set_active; 454 bool sw_csum_tx; 455 const struct iwl_hcmd_arr *command_groups; 456 int command_groups_size; 457 458 u8 cb_data_offs; 459}; 460 461struct iwl_trans_dump_data { 462 u32 len; 463 u8 data[]; 464}; 465 466struct iwl_trans; 467 468struct iwl_trans_txq_scd_cfg { 469 u8 fifo; 470 u8 sta_id; 471 u8 tid; 472 bool aggregate; 473 int frame_limit; 474}; 475 476/** 477 * struct iwl_trans_rxq_dma_data - RX queue DMA data 478 * @fr_bd_cb: DMA address of free BD cyclic buffer 479 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 480 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 481 * @ur_bd_cb: DMA address of used BD cyclic buffer 482 */ 483struct iwl_trans_rxq_dma_data { 484 u64 fr_bd_cb; 485 u32 fr_bd_wid; 486 u64 urbd_stts_wrptr; 487 u64 ur_bd_cb; 488}; 489 490/** 491 * struct iwl_trans_ops - transport specific operations 492 * 493 * All the handlers MUST be implemented 494 * 495 * @start_hw: starts the HW. From that point on, the HW can send interrupts. 496 * May sleep. 497 * @op_mode_leave: Turn off the HW RF kill indication if on 498 * May sleep 499 * @start_fw: allocates and inits all the resources for the transport 500 * layer. Also kick a fw image. 501 * May sleep 502 * @fw_alive: called when the fw sends alive notification. If the fw provides 503 * the SCD base address in SRAM, then provide it here, or 0 otherwise. 504 * May sleep 505 * @stop_device: stops the whole device (embedded CPU put to reset) and stops 506 * the HW. From that point on, the HW will be stopped but will still issue 507 * an interrupt if the HW RF kill switch is triggered. 508 * This callback must do the right thing and not crash even if %start_hw() 509 * was called but not &start_fw(). May sleep. 510 * @d3_suspend: put the device into the correct mode for WoWLAN during 511 * suspend. This is optional, if not implemented WoWLAN will not be 512 * supported. This callback may sleep. 513 * @d3_resume: resume the device after WoWLAN, enabling the opmode to 514 * talk to the WoWLAN image to get its status. This is optional, if not 515 * implemented WoWLAN will not be supported. This callback may sleep. 516 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 517 * If RFkill is asserted in the middle of a SYNC host command, it must 518 * return -ERFKILL straight away. 519 * May sleep only if CMD_ASYNC is not set 520 * @tx: send an skb. The transport relies on the op_mode to zero the 521 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 522 * the CSUM will be taken care of (TCP CSUM and IP header in case of 523 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 524 * header if it is IPv4. 525 * Must be atomic 526 * @reclaim: free packet until ssn. Returns a list of freed packets. 527 * Must be atomic 528 * @txq_enable: setup a queue. To setup an AC queue, use the 529 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 530 * this one. The op_mode must not configure the HCMD queue. The scheduler 531 * configuration may be %NULL, in which case the hardware will not be 532 * configured. If true is returned, the operation mode needs to increment 533 * the sequence number of the packets routed to this queue because of a 534 * hardware scheduler bug. May sleep. 535 * @txq_disable: de-configure a Tx queue to send AMPDUs 536 * Must be atomic 537 * @txq_set_shared_mode: change Tx queue shared/unshared marking 538 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 539 * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 540 * @freeze_txq_timer: prevents the timer of the queue from firing until the 541 * queue is set to awake. Must be atomic. 542 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 543 * that the transport needs to refcount the calls since this function 544 * will be called several times with block = true, and then the queues 545 * need to be unblocked only after the same number of calls with 546 * block = false. 547 * @write8: write a u8 to a register at offset ofs from the BAR 548 * @write32: write a u32 to a register at offset ofs from the BAR 549 * @read32: read a u32 register at offset ofs from the BAR 550 * @read_prph: read a DWORD from a periphery register 551 * @write_prph: write a DWORD to a periphery register 552 * @read_mem: read device's SRAM in DWORD 553 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 554 * will be zeroed. 555 * @read_config32: read a u32 value from the device's config space at 556 * the given offset. 557 * @configure: configure parameters required by the transport layer from 558 * the op_mode. May be called several times before start_fw, can't be 559 * called after that. 560 * @set_pmi: set the power pmi state 561 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 562 * Sleeping is not allowed between grab_nic_access and 563 * release_nic_access. 564 * @release_nic_access: let the NIC go to sleep. The "flags" parameter 565 * must be the same one that was sent before to the grab_nic_access. 566 * @set_bits_mask - set SRAM register according to value and mask. 567 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 568 * TX'ed commands and similar. The buffer will be vfree'd by the caller. 569 * Note that the transport must fill in the proper file headers. 570 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 571 * of the trans debugfs 572 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 573 * context info. 574 */ 575struct iwl_trans_ops { 576 577 int (*start_hw)(struct iwl_trans *iwl_trans); 578 void (*op_mode_leave)(struct iwl_trans *iwl_trans); 579 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 580 bool run_in_rfkill); 581 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 582 void (*stop_device)(struct iwl_trans *trans); 583 584 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 585 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 586 bool test, bool reset); 587 588 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 589 590 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 591 struct iwl_device_tx_cmd *dev_cmd, int queue); 592 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 593 struct sk_buff_head *skbs); 594 595 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 596 597 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 598 const struct iwl_trans_txq_scd_cfg *cfg, 599 unsigned int queue_wdg_timeout); 600 void (*txq_disable)(struct iwl_trans *trans, int queue, 601 bool configure_scd); 602 /* 22000 functions */ 603 int (*txq_alloc)(struct iwl_trans *trans, 604 __le16 flags, u8 sta_id, u8 tid, 605 int cmd_id, int size, 606 unsigned int queue_wdg_timeout); 607 void (*txq_free)(struct iwl_trans *trans, int queue); 608 int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 609 struct iwl_trans_rxq_dma_data *data); 610 611 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 612 bool shared); 613 614 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 615 int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 616 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 617 bool freeze); 618 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 619 620 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 621 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 622 u32 (*read32)(struct iwl_trans *trans, u32 ofs); 623 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 624 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 625 int (*read_mem)(struct iwl_trans *trans, u32 addr, 626 void *buf, int dwords); 627 int (*write_mem)(struct iwl_trans *trans, u32 addr, 628 const void *buf, int dwords); 629 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 630 void (*configure)(struct iwl_trans *trans, 631 const struct iwl_trans_config *trans_cfg); 632 void (*set_pmi)(struct iwl_trans *trans, bool state); 633 void (*sw_reset)(struct iwl_trans *trans); 634 bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags); 635 void (*release_nic_access)(struct iwl_trans *trans, 636 unsigned long *flags); 637 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 638 u32 value); 639 int (*suspend)(struct iwl_trans *trans); 640 void (*resume)(struct iwl_trans *trans); 641 642 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 643 u32 dump_mask); 644 void (*debugfs_cleanup)(struct iwl_trans *trans); 645 void (*sync_nmi)(struct iwl_trans *trans); 646 int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len); 647}; 648 649/** 650 * enum iwl_trans_state - state of the transport layer 651 * 652 * @IWL_TRANS_NO_FW: no fw has sent an alive response 653 * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response 654 */ 655enum iwl_trans_state { 656 IWL_TRANS_NO_FW = 0, 657 IWL_TRANS_FW_ALIVE = 1, 658}; 659 660/** 661 * DOC: Platform power management 662 * 663 * In system-wide power management the entire platform goes into a low 664 * power state (e.g. idle or suspend to RAM) at the same time and the 665 * device is configured as a wakeup source for the entire platform. 666 * This is usually triggered by userspace activity (e.g. the user 667 * presses the suspend button or a power management daemon decides to 668 * put the platform in low power mode). The device's behavior in this 669 * mode is dictated by the wake-on-WLAN configuration. 670 * 671 * The terms used for the device's behavior are as follows: 672 * 673 * - D0: the device is fully powered and the host is awake; 674 * - D3: the device is in low power mode and only reacts to 675 * specific events (e.g. magic-packet received or scan 676 * results found); 677 * 678 * These terms reflect the power modes in the firmware and are not to 679 * be confused with the physical device power state. 680 */ 681 682/** 683 * enum iwl_plat_pm_mode - platform power management mode 684 * 685 * This enumeration describes the device's platform power management 686 * behavior when in system-wide suspend (i.e WoWLAN). 687 * 688 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 689 * device. In system-wide suspend mode, it means that the all 690 * connections will be closed automatically by mac80211 before 691 * the platform is suspended. 692 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 693 */ 694enum iwl_plat_pm_mode { 695 IWL_PLAT_PM_MODE_DISABLED, 696 IWL_PLAT_PM_MODE_D3, 697}; 698 699/** 700 * enum iwl_ini_cfg_state 701 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 702 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 703 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 704 * are corrupted. The rest of the debug TLVs will still be used 705 */ 706enum iwl_ini_cfg_state { 707 IWL_INI_CFG_STATE_NOT_LOADED, 708 IWL_INI_CFG_STATE_LOADED, 709 IWL_INI_CFG_STATE_CORRUPTED, 710}; 711 712/* Max time to wait for nmi interrupt */ 713#define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 714 715/** 716 * struct iwl_dram_data 717 * @physical: page phy pointer 718 * @block: pointer to the allocated block/page 719 * @size: size of the block/page 720 */ 721struct iwl_dram_data { 722 dma_addr_t physical; 723 void *block; 724 int size; 725}; 726 727/** 728 * struct iwl_fw_mon - fw monitor per allocation id 729 * @num_frags: number of fragments 730 * @frags: an array of DRAM buffer fragments 731 */ 732struct iwl_fw_mon { 733 u32 num_frags; 734 struct iwl_dram_data *frags; 735}; 736 737/** 738 * struct iwl_self_init_dram - dram data used by self init process 739 * @fw: lmac and umac dram data 740 * @fw_cnt: total number of items in array 741 * @paging: paging dram data 742 * @paging_cnt: total number of items in array 743 */ 744struct iwl_self_init_dram { 745 struct iwl_dram_data *fw; 746 int fw_cnt; 747 struct iwl_dram_data *paging; 748 int paging_cnt; 749}; 750 751/** 752 * struct iwl_trans_debug - transport debug related data 753 * 754 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 755 * @rec_on: true iff there is a fw debug recording currently active 756 * @dest_tlv: points to the destination TLV for debug 757 * @conf_tlv: array of pointers to configuration TLVs for debug 758 * @trigger_tlv: array of pointers to triggers TLVs for debug 759 * @lmac_error_event_table: addrs of lmacs error tables 760 * @umac_error_event_table: addr of umac error table 761 * @error_event_table_tlv_status: bitmap that indicates what error table 762 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 763 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 764 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 765 * @fw_mon_cfg: debug buffer allocation configuration 766 * @fw_mon_ini: DRAM buffer fragments per allocation id 767 * @fw_mon: DRAM buffer for firmware monitor 768 * @hw_error: equals true if hw error interrupt was received from the FW 769 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 770 * @active_regions: active regions 771 * @debug_info_tlv_list: list of debug info TLVs 772 * @time_point: array of debug time points 773 * @periodic_trig_list: periodic triggers list 774 * @domains_bitmap: bitmap of active domains other than 775 * &IWL_FW_INI_DOMAIN_ALWAYS_ON 776 */ 777struct iwl_trans_debug { 778 u8 n_dest_reg; 779 bool rec_on; 780 781 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 782 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 783 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 784 785 u32 lmac_error_event_table[2]; 786 u32 umac_error_event_table; 787 unsigned int error_event_table_tlv_status; 788 789 enum iwl_ini_cfg_state internal_ini_cfg; 790 enum iwl_ini_cfg_state external_ini_cfg; 791 792 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 793 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 794 795 struct iwl_dram_data fw_mon; 796 797 bool hw_error; 798 enum iwl_fw_ini_buffer_location ini_dest; 799 800 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 801 struct list_head debug_info_tlv_list; 802 struct iwl_dbg_tlv_time_point_data 803 time_point[IWL_FW_INI_TIME_POINT_NUM]; 804 struct list_head periodic_trig_list; 805 806 u32 domains_bitmap; 807}; 808 809struct iwl_dma_ptr { 810 dma_addr_t dma; 811 void *addr; 812 size_t size; 813}; 814 815struct iwl_cmd_meta { 816 /* only for SYNC commands, iff the reply skb is wanted */ 817 struct iwl_host_cmd *source; 818 u32 flags; 819 u32 tbs; 820}; 821 822/* 823 * The FH will write back to the first TB only, so we need to copy some data 824 * into the buffer regardless of whether it should be mapped or not. 825 * This indicates how big the first TB must be to include the scratch buffer 826 * and the assigned PN. 827 * Since PN location is 8 bytes at offset 12, it's 20 now. 828 * If we make it bigger then allocations will be bigger and copy slower, so 829 * that's probably not useful. 830 */ 831#define IWL_FIRST_TB_SIZE 20 832#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 833 834struct iwl_pcie_txq_entry { 835 void *cmd; 836 struct sk_buff *skb; 837 /* buffer to free after command completes */ 838 const void *free_buf; 839 struct iwl_cmd_meta meta; 840}; 841 842struct iwl_pcie_first_tb_buf { 843 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 844}; 845 846/** 847 * struct iwl_txq - Tx Queue for DMA 848 * @q: generic Rx/Tx queue descriptor 849 * @tfds: transmit frame descriptors (DMA memory) 850 * @first_tb_bufs: start of command headers, including scratch buffers, for 851 * the writeback -- this is DMA memory and an array holding one buffer 852 * for each command on the queue 853 * @first_tb_dma: DMA address for the first_tb_bufs start 854 * @entries: transmit entries (driver state) 855 * @lock: queue lock 856 * @stuck_timer: timer that fires if queue gets stuck 857 * @trans: pointer back to transport (for timer) 858 * @need_update: indicates need to update read/write index 859 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 860 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 861 * @frozen: tx stuck queue timer is frozen 862 * @frozen_expiry_remainder: remember how long until the timer fires 863 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 864 * @write_ptr: 1-st empty entry (index) host_w 865 * @read_ptr: last used entry (index) host_r 866 * @dma_addr: physical addr for BD's 867 * @n_window: safe queue window 868 * @id: queue id 869 * @low_mark: low watermark, resume queue if free space more than this 870 * @high_mark: high watermark, stop queue if free space less than this 871 * 872 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 873 * descriptors) and required locking structures. 874 * 875 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 876 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 877 * there might be HW changes in the future). For the normal TX 878 * queues, n_window, which is the size of the software queue data 879 * is also 256; however, for the command queue, n_window is only 880 * 32 since we don't need so many commands pending. Since the HW 881 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 882 * This means that we end up with the following: 883 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 884 * SW entries: | 0 | ... | 31 | 885 * where N is a number between 0 and 7. This means that the SW 886 * data is a window overlayed over the HW queue. 887 */ 888struct iwl_txq { 889 void *tfds; 890 struct iwl_pcie_first_tb_buf *first_tb_bufs; 891 dma_addr_t first_tb_dma; 892 struct iwl_pcie_txq_entry *entries; 893 /* lock for syncing changes on the queue */ 894 spinlock_t lock; 895 unsigned long frozen_expiry_remainder; 896 struct timer_list stuck_timer; 897 struct iwl_trans *trans; 898 bool need_update; 899 bool frozen; 900 bool ampdu; 901 int block; 902 unsigned long wd_timeout; 903 struct sk_buff_head overflow_q; 904 struct iwl_dma_ptr bc_tbl; 905 906 int write_ptr; 907 int read_ptr; 908 dma_addr_t dma_addr; 909 int n_window; 910 u32 id; 911 int low_mark; 912 int high_mark; 913 914 bool overflow_tx; 915}; 916 917/** 918 * struct iwl_trans_txqs - transport tx queues data 919 * 920 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 921 * @page_offs: offset from skb->cb to mac header page pointer 922 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 923 * @queue_used - bit mask of used queues 924 * @queue_stopped - bit mask of stopped queues 925 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 926 */ 927struct iwl_trans_txqs { 928 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 929 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 930 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 931 struct dma_pool *bc_pool; 932 size_t bc_tbl_size; 933 bool bc_table_dword; 934 u8 page_offs; 935 u8 dev_cmd_offs; 936 struct __percpu iwl_tso_hdr_page * tso_hdr_page; 937 938 struct { 939 u8 fifo; 940 u8 q_id; 941 unsigned int wdg_timeout; 942 } cmd; 943 944 struct { 945 u8 max_tbs; 946 u16 size; 947 u8 addr_size; 948 } tfd; 949 950 struct iwl_dma_ptr scd_bc_tbls; 951}; 952 953/** 954 * struct iwl_trans - transport common data 955 * 956 * @ops - pointer to iwl_trans_ops 957 * @op_mode - pointer to the op_mode 958 * @trans_cfg: the trans-specific configuration part 959 * @cfg - pointer to the configuration 960 * @drv - pointer to iwl_drv 961 * @status: a bit-mask of transport status flags 962 * @dev - pointer to struct device * that represents the device 963 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 964 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 965 * @hw_rf_id a u32 with the device RF ID 966 * @hw_id: a u32 with the ID of the device / sub-device. 967 * Set during transport allocation. 968 * @hw_id_str: a string with info about HW ID. Set during transport allocation. 969 * @pm_support: set to true in start_hw if link pm is supported 970 * @ltr_enabled: set to true if the LTR is enabled 971 * @wide_cmd_header: true when ucode supports wide command header format 972 * @num_rx_queues: number of RX queues allocated by the transport; 973 * the transport must set this before calling iwl_drv_start() 974 * @iml_len: the length of the image loader 975 * @iml: a pointer to the image loader itself 976 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 977 * The user should use iwl_trans_{alloc,free}_tx_cmd. 978 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 979 * starting the firmware, used for tracing 980 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 981 * start of the 802.11 header in the @rx_mpdu_cmd 982 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 983 * @system_pm_mode: the system-wide power management mode in use. 984 * This mode is set dynamically, depending on the WoWLAN values 985 * configured from the userspace at runtime. 986 * @iwl_trans_txqs: transport tx queues data. 987 */ 988struct iwl_trans { 989 const struct iwl_trans_ops *ops; 990 struct iwl_op_mode *op_mode; 991 const struct iwl_cfg_trans_params *trans_cfg; 992 const struct iwl_cfg *cfg; 993 struct iwl_drv *drv; 994 enum iwl_trans_state state; 995 unsigned long status; 996 997 struct device *dev; 998 u32 max_skb_frags; 999 u32 hw_rev; 1000 u32 hw_rf_id; 1001 u32 hw_id; 1002 char hw_id_str[52]; 1003 u32 sku_id[3]; 1004 1005 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 1006 1007 bool pm_support; 1008 bool ltr_enabled; 1009 u8 pnvm_loaded:1; 1010 1011 const struct iwl_hcmd_arr *command_groups; 1012 int command_groups_size; 1013 bool wide_cmd_header; 1014 1015 u8 num_rx_queues; 1016 1017 size_t iml_len; 1018 u8 *iml; 1019 1020 /* The following fields are internal only */ 1021 struct kmem_cache *dev_cmd_pool; 1022 char dev_cmd_pool_name[50]; 1023 1024 struct dentry *dbgfs_dir; 1025 1026#ifdef CONFIG_LOCKDEP 1027 struct lockdep_map sync_cmd_lockdep_map; 1028#endif 1029 1030 struct iwl_trans_debug dbg; 1031 struct iwl_self_init_dram init_dram; 1032 1033 enum iwl_plat_pm_mode system_pm_mode; 1034 1035 const char *name; 1036 struct iwl_trans_txqs txqs; 1037 1038 /* pointer to trans specific struct */ 1039 /*Ensure that this pointer will always be aligned to sizeof pointer */ 1040 char trans_specific[] __aligned(sizeof(void *)); 1041}; 1042 1043const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 1044int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 1045 1046static inline void iwl_trans_configure(struct iwl_trans *trans, 1047 const struct iwl_trans_config *trans_cfg) 1048{ 1049 trans->op_mode = trans_cfg->op_mode; 1050 1051 trans->ops->configure(trans, trans_cfg); 1052 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1053} 1054 1055static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1056{ 1057 might_sleep(); 1058 1059 return trans->ops->start_hw(trans); 1060} 1061 1062static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1063{ 1064 might_sleep(); 1065 1066 if (trans->ops->op_mode_leave) 1067 trans->ops->op_mode_leave(trans); 1068 1069 trans->op_mode = NULL; 1070 1071 trans->state = IWL_TRANS_NO_FW; 1072} 1073 1074static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1075{ 1076 might_sleep(); 1077 1078 trans->state = IWL_TRANS_FW_ALIVE; 1079 1080 trans->ops->fw_alive(trans, scd_addr); 1081} 1082 1083static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1084 const struct fw_img *fw, 1085 bool run_in_rfkill) 1086{ 1087 might_sleep(); 1088 1089 WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1090 1091 clear_bit(STATUS_FW_ERROR, &trans->status); 1092 return trans->ops->start_fw(trans, fw, run_in_rfkill); 1093} 1094 1095static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1096{ 1097 might_sleep(); 1098 1099 trans->ops->stop_device(trans); 1100 1101 trans->state = IWL_TRANS_NO_FW; 1102} 1103 1104static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 1105 bool reset) 1106{ 1107 might_sleep(); 1108 if (!trans->ops->d3_suspend) 1109 return 0; 1110 1111 return trans->ops->d3_suspend(trans, test, reset); 1112} 1113 1114static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1115 enum iwl_d3_status *status, 1116 bool test, bool reset) 1117{ 1118 might_sleep(); 1119 if (!trans->ops->d3_resume) 1120 return 0; 1121 1122 return trans->ops->d3_resume(trans, status, test, reset); 1123} 1124 1125static inline int iwl_trans_suspend(struct iwl_trans *trans) 1126{ 1127 if (!trans->ops->suspend) 1128 return 0; 1129 1130 return trans->ops->suspend(trans); 1131} 1132 1133static inline void iwl_trans_resume(struct iwl_trans *trans) 1134{ 1135 if (trans->ops->resume) 1136 trans->ops->resume(trans); 1137} 1138 1139static inline struct iwl_trans_dump_data * 1140iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 1141{ 1142 if (!trans->ops->dump_data) 1143 return NULL; 1144 return trans->ops->dump_data(trans, dump_mask); 1145} 1146 1147static inline struct iwl_device_tx_cmd * 1148iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1149{ 1150 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1151} 1152 1153int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 1154 1155static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1156 struct iwl_device_tx_cmd *dev_cmd) 1157{ 1158 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1159} 1160 1161static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1162 struct iwl_device_tx_cmd *dev_cmd, int queue) 1163{ 1164 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1165 return -EIO; 1166 1167 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1168 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1169 return -EIO; 1170 } 1171 1172 return trans->ops->tx(trans, skb, dev_cmd, queue); 1173} 1174 1175static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1176 int ssn, struct sk_buff_head *skbs) 1177{ 1178 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1179 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1180 return; 1181 } 1182 1183 trans->ops->reclaim(trans, queue, ssn, skbs); 1184} 1185 1186static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1187 int ptr) 1188{ 1189 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1190 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1191 return; 1192 } 1193 1194 trans->ops->set_q_ptrs(trans, queue, ptr); 1195} 1196 1197static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1198 bool configure_scd) 1199{ 1200 trans->ops->txq_disable(trans, queue, configure_scd); 1201} 1202 1203static inline bool 1204iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1205 const struct iwl_trans_txq_scd_cfg *cfg, 1206 unsigned int queue_wdg_timeout) 1207{ 1208 might_sleep(); 1209 1210 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1211 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1212 return false; 1213 } 1214 1215 return trans->ops->txq_enable(trans, queue, ssn, 1216 cfg, queue_wdg_timeout); 1217} 1218 1219static inline int 1220iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 1221 struct iwl_trans_rxq_dma_data *data) 1222{ 1223 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 1224 return -ENOTSUPP; 1225 1226 return trans->ops->rxq_dma_data(trans, queue, data); 1227} 1228 1229static inline void 1230iwl_trans_txq_free(struct iwl_trans *trans, int queue) 1231{ 1232 if (WARN_ON_ONCE(!trans->ops->txq_free)) 1233 return; 1234 1235 trans->ops->txq_free(trans, queue); 1236} 1237 1238static inline int 1239iwl_trans_txq_alloc(struct iwl_trans *trans, 1240 __le16 flags, u8 sta_id, u8 tid, 1241 int cmd_id, int size, 1242 unsigned int wdg_timeout) 1243{ 1244 might_sleep(); 1245 1246 if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 1247 return -ENOTSUPP; 1248 1249 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1250 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1251 return -EIO; 1252 } 1253 1254 return trans->ops->txq_alloc(trans, flags, sta_id, tid, 1255 cmd_id, size, wdg_timeout); 1256} 1257 1258static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1259 int queue, bool shared_mode) 1260{ 1261 if (trans->ops->txq_set_shared_mode) 1262 trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 1263} 1264 1265static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1266 int fifo, int sta_id, int tid, 1267 int frame_limit, u16 ssn, 1268 unsigned int queue_wdg_timeout) 1269{ 1270 struct iwl_trans_txq_scd_cfg cfg = { 1271 .fifo = fifo, 1272 .sta_id = sta_id, 1273 .tid = tid, 1274 .frame_limit = frame_limit, 1275 .aggregate = sta_id >= 0, 1276 }; 1277 1278 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1279} 1280 1281static inline 1282void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1283 unsigned int queue_wdg_timeout) 1284{ 1285 struct iwl_trans_txq_scd_cfg cfg = { 1286 .fifo = fifo, 1287 .sta_id = -1, 1288 .tid = IWL_MAX_TID_COUNT, 1289 .frame_limit = IWL_FRAME_LIMIT, 1290 .aggregate = false, 1291 }; 1292 1293 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1294} 1295 1296static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1297 unsigned long txqs, 1298 bool freeze) 1299{ 1300 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1301 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1302 return; 1303 } 1304 1305 if (trans->ops->freeze_txq_timer) 1306 trans->ops->freeze_txq_timer(trans, txqs, freeze); 1307} 1308 1309static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 1310 bool block) 1311{ 1312 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1313 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1314 return; 1315 } 1316 1317 if (trans->ops->block_txq_ptrs) 1318 trans->ops->block_txq_ptrs(trans, block); 1319} 1320 1321static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1322 u32 txqs) 1323{ 1324 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1325 return -ENOTSUPP; 1326 1327 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1328 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1329 return -EIO; 1330 } 1331 1332 return trans->ops->wait_tx_queues_empty(trans, txqs); 1333} 1334 1335static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1336{ 1337 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1338 return -ENOTSUPP; 1339 1340 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1341 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1342 return -EIO; 1343 } 1344 1345 return trans->ops->wait_txq_empty(trans, queue); 1346} 1347 1348static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1349{ 1350 trans->ops->write8(trans, ofs, val); 1351} 1352 1353static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1354{ 1355 trans->ops->write32(trans, ofs, val); 1356} 1357 1358static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1359{ 1360 return trans->ops->read32(trans, ofs); 1361} 1362 1363static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1364{ 1365 return trans->ops->read_prph(trans, ofs); 1366} 1367 1368static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1369 u32 val) 1370{ 1371 return trans->ops->write_prph(trans, ofs, val); 1372} 1373 1374static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1375 void *buf, int dwords) 1376{ 1377 return trans->ops->read_mem(trans, addr, buf, dwords); 1378} 1379 1380#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1381 do { \ 1382 if (__builtin_constant_p(bufsize)) \ 1383 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1384 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1385 } while (0) 1386 1387static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1388{ 1389 u32 value; 1390 1391 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1392 return 0xa5a5a5a5; 1393 1394 return value; 1395} 1396 1397static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1398 const void *buf, int dwords) 1399{ 1400 return trans->ops->write_mem(trans, addr, buf, dwords); 1401} 1402 1403static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1404 u32 val) 1405{ 1406 return iwl_trans_write_mem(trans, addr, &val, 1); 1407} 1408 1409static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1410{ 1411 if (trans->ops->set_pmi) 1412 trans->ops->set_pmi(trans, state); 1413} 1414 1415static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1416{ 1417 if (trans->ops->sw_reset) 1418 trans->ops->sw_reset(trans); 1419} 1420 1421static inline void 1422iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1423{ 1424 trans->ops->set_bits_mask(trans, reg, mask, value); 1425} 1426 1427#define iwl_trans_grab_nic_access(trans, flags) \ 1428 __cond_lock(nic_access, \ 1429 likely((trans)->ops->grab_nic_access(trans, flags))) 1430 1431static inline void __releases(nic_access) 1432iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) 1433{ 1434 trans->ops->release_nic_access(trans, flags); 1435 __release(nic_access); 1436} 1437 1438static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1439{ 1440 if (WARN_ON_ONCE(!trans->op_mode)) 1441 return; 1442 1443 /* prevent double restarts due to the same erroneous FW */ 1444 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) 1445 iwl_op_mode_nic_error(trans->op_mode); 1446} 1447 1448static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1449{ 1450 return trans->state == IWL_TRANS_FW_ALIVE; 1451} 1452 1453static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1454{ 1455 if (trans->ops->sync_nmi) 1456 trans->ops->sync_nmi(trans); 1457} 1458 1459static inline int iwl_trans_set_pnvm(struct iwl_trans *trans, 1460 const void *data, u32 len) 1461{ 1462 if (trans->ops->set_pnvm) { 1463 int ret = trans->ops->set_pnvm(trans, data, len); 1464 1465 if (ret) 1466 return ret; 1467 } 1468 1469 trans->pnvm_loaded = true; 1470 1471 return 0; 1472} 1473 1474static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1475{ 1476 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1477 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1478} 1479 1480/***************************************************** 1481 * transport helper functions 1482 *****************************************************/ 1483struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1484 struct device *dev, 1485 const struct iwl_trans_ops *ops, 1486 const struct iwl_cfg_trans_params *cfg_trans); 1487void iwl_trans_free(struct iwl_trans *trans); 1488 1489/***************************************************** 1490* driver (transport) register/unregister functions 1491******************************************************/ 1492int __must_check iwl_pci_register_driver(void); 1493void iwl_pci_unregister_driver(void); 1494 1495#endif /* __iwl_trans_h__ */ 1496