1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright (C) 2018 - 2020 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright (C) 2018 - 2020 Intel Corporation 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 38 * * Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * * Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in 42 * the documentation and/or other materials provided with the 43 * distribution. 44 * * Neither the name Intel Corporation nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 49 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 50 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 51 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 52 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 53 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 54 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 58 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 *****************************************************************************/ 61 62#include <linux/firmware.h> 63#include "iwl-drv.h" 64#include "iwl-trans.h" 65#include "iwl-dbg-tlv.h" 66#include "fw/dbg.h" 67#include "fw/runtime.h" 68 69/** 70 * enum iwl_dbg_tlv_type - debug TLV types 71 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 72 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 73 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 74 * @IWL_DBG_TLV_TYPE_REGION: region TLV 75 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 76 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 77 */ 78enum iwl_dbg_tlv_type { 79 IWL_DBG_TLV_TYPE_DEBUG_INFO = 80 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 81 IWL_DBG_TLV_TYPE_BUF_ALLOC, 82 IWL_DBG_TLV_TYPE_HCMD, 83 IWL_DBG_TLV_TYPE_REGION, 84 IWL_DBG_TLV_TYPE_TRIGGER, 85 IWL_DBG_TLV_TYPE_NUM, 86}; 87 88/** 89 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 90 * @min_ver: min version supported 91 * @max_ver: max version supported 92 */ 93struct iwl_dbg_tlv_ver_data { 94 int min_ver; 95 int max_ver; 96}; 97 98/** 99 * struct iwl_dbg_tlv_timer_node - timer node struct 100 * @list: list of &struct iwl_dbg_tlv_timer_node 101 * @timer: timer 102 * @fwrt: &struct iwl_fw_runtime 103 * @tlv: TLV attach to the timer node 104 */ 105struct iwl_dbg_tlv_timer_node { 106 struct list_head list; 107 struct timer_list timer; 108 struct iwl_fw_runtime *fwrt; 109 struct iwl_ucode_tlv *tlv; 110}; 111 112static const struct iwl_dbg_tlv_ver_data 113dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 114 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 115 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 116 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 117 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,}, 118 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 119}; 120 121static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list) 122{ 123 u32 len = le32_to_cpu(tlv->length); 124 struct iwl_dbg_tlv_node *node; 125 126 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 127 if (!node) 128 return -ENOMEM; 129 130 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 131 list_add_tail(&node->list, list); 132 133 return 0; 134} 135 136static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv) 137{ 138 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 139 u32 type = le32_to_cpu(tlv->type); 140 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 141 u32 ver = le32_to_cpu(hdr->version); 142 143 if (ver < dbg_ver_table[tlv_idx].min_ver || 144 ver > dbg_ver_table[tlv_idx].max_ver) 145 return false; 146 147 return true; 148} 149 150static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 151 struct iwl_ucode_tlv *tlv) 152{ 153 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data; 154 155 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 156 return -EINVAL; 157 158 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 159 debug_info->debug_cfg_name); 160 161 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 162} 163 164static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 165 struct iwl_ucode_tlv *tlv) 166{ 167 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data; 168 u32 buf_location; 169 u32 alloc_id; 170 171 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 172 return -EINVAL; 173 174 buf_location = le32_to_cpu(alloc->buf_location); 175 alloc_id = le32_to_cpu(alloc->alloc_id); 176 177 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 178 buf_location >= IWL_FW_INI_LOCATION_NUM) 179 goto err; 180 181 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 182 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 183 goto err; 184 185 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 186 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 187 goto err; 188 189 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 190 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1 && 191 alloc_id != IWL_FW_INI_ALLOCATION_ID_INTERNAL) 192 goto err; 193 194 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH && 195 alloc->req_size == 0) { 196 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n"); 197 return -EINVAL; 198 } 199 200 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 201 202 return 0; 203err: 204 IWL_ERR(trans, 205 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 206 alloc_id, buf_location); 207 return -EINVAL; 208} 209 210static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 211 struct iwl_ucode_tlv *tlv) 212{ 213 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data; 214 u32 tp = le32_to_cpu(hcmd->time_point); 215 216 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 217 return -EINVAL; 218 219 /* Host commands can not be sent in early time point since the FW 220 * is not ready 221 */ 222 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 223 tp >= IWL_FW_INI_TIME_POINT_NUM || 224 tp == IWL_FW_INI_TIME_POINT_EARLY) { 225 IWL_ERR(trans, 226 "WRT: Invalid time point %u for host command TLV\n", 227 tp); 228 return -EINVAL; 229 } 230 231 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 232} 233 234static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 235 struct iwl_ucode_tlv *tlv) 236{ 237 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data; 238 struct iwl_ucode_tlv **active_reg; 239 u32 id = le32_to_cpu(reg->id); 240 u32 type = le32_to_cpu(reg->type); 241 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 242 243 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 244 return -EINVAL; 245 246 if (id >= IWL_FW_INI_MAX_REGION_ID) { 247 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 248 return -EINVAL; 249 } 250 251 if (type <= IWL_FW_INI_REGION_INVALID || 252 type >= IWL_FW_INI_REGION_NUM) { 253 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 254 return -EINVAL; 255 } 256 257 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 258 !trans->ops->read_config32) { 259 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 260 return -EOPNOTSUPP; 261 } 262 263 active_reg = &trans->dbg.active_regions[id]; 264 if (*active_reg) { 265 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 266 267 kfree(*active_reg); 268 } 269 270 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 271 if (!*active_reg) 272 return -ENOMEM; 273 274 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 275 276 return 0; 277} 278 279static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 280 struct iwl_ucode_tlv *tlv) 281{ 282 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data; 283 u32 tp = le32_to_cpu(trig->time_point); 284 struct iwl_ucode_tlv *dup = NULL; 285 int ret; 286 287 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 288 return -EINVAL; 289 290 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 291 tp >= IWL_FW_INI_TIME_POINT_NUM) { 292 IWL_ERR(trans, 293 "WRT: Invalid time point %u for trigger TLV\n", 294 tp); 295 return -EINVAL; 296 } 297 298 if (!le32_to_cpu(trig->occurrences)) { 299 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 300 GFP_KERNEL); 301 if (!dup) 302 return -ENOMEM; 303 trig = (void *)dup->data; 304 trig->occurrences = cpu_to_le32(-1); 305 tlv = dup; 306 } 307 308 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 309 kfree(dup); 310 311 return ret; 312} 313 314static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 315 struct iwl_ucode_tlv *tlv) = { 316 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 317 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 318 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 319 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 320 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 321}; 322 323void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv, 324 bool ext) 325{ 326 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 327 u32 type = le32_to_cpu(tlv->type); 328 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 329 u32 domain = le32_to_cpu(hdr->domain); 330 enum iwl_ini_cfg_state *cfg_state = ext ? 331 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 332 int ret; 333 334 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 335 !(domain & trans->dbg.domains_bitmap)) { 336 IWL_DEBUG_FW(trans, 337 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 338 domain, trans->dbg.domains_bitmap); 339 return; 340 } 341 342 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 343 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 344 goto out_err; 345 } 346 347 if (!iwl_dbg_tlv_ver_support(tlv)) { 348 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 349 le32_to_cpu(hdr->version)); 350 goto out_err; 351 } 352 353 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 354 if (ret) { 355 IWL_ERR(trans, 356 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 357 type, ret, ext); 358 goto out_err; 359 } 360 361 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 362 *cfg_state = IWL_INI_CFG_STATE_LOADED; 363 364 return; 365 366out_err: 367 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 368} 369 370void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 371{ 372 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 373 struct iwl_dbg_tlv_timer_node *node, *tmp; 374 375 list_for_each_entry_safe(node, tmp, timer_list, list) { 376 del_timer_sync(&node->timer); 377 list_del(&node->list); 378 kfree(node); 379 } 380} 381IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 382 383static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 384 enum iwl_fw_ini_allocation_id alloc_id) 385{ 386 struct iwl_fw_mon *fw_mon; 387 int i; 388 389 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 390 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 391 return; 392 393 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 394 395 for (i = 0; i < fw_mon->num_frags; i++) { 396 struct iwl_dram_data *frag = &fw_mon->frags[i]; 397 398 dma_free_coherent(trans->dev, frag->size, frag->block, 399 frag->physical); 400 401 frag->physical = 0; 402 frag->block = NULL; 403 frag->size = 0; 404 } 405 406 kfree(fw_mon->frags); 407 fw_mon->frags = NULL; 408 fw_mon->num_frags = 0; 409} 410 411void iwl_dbg_tlv_free(struct iwl_trans *trans) 412{ 413 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 414 int i; 415 416 iwl_dbg_tlv_del_timers(trans); 417 418 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 419 struct iwl_ucode_tlv **active_reg = 420 &trans->dbg.active_regions[i]; 421 422 kfree(*active_reg); 423 *active_reg = NULL; 424 } 425 426 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 427 &trans->dbg.debug_info_tlv_list, list) { 428 list_del(&tlv_node->list); 429 kfree(tlv_node); 430 } 431 432 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 433 struct iwl_dbg_tlv_time_point_data *tp = 434 &trans->dbg.time_point[i]; 435 436 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 437 list) { 438 list_del(&tlv_node->list); 439 kfree(tlv_node); 440 } 441 442 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 443 list) { 444 list_del(&tlv_node->list); 445 kfree(tlv_node); 446 } 447 448 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 449 &tp->active_trig_list, list) { 450 list_del(&tlv_node->list); 451 kfree(tlv_node); 452 } 453 } 454 455 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 456 iwl_dbg_tlv_fragments_free(trans, i); 457} 458 459static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 460 size_t len) 461{ 462 struct iwl_ucode_tlv *tlv; 463 u32 tlv_len; 464 465 while (len >= sizeof(*tlv)) { 466 len -= sizeof(*tlv); 467 tlv = (void *)data; 468 469 tlv_len = le32_to_cpu(tlv->length); 470 471 if (len < tlv_len) { 472 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 473 len, tlv_len); 474 return -EINVAL; 475 } 476 len -= ALIGN(tlv_len, 4); 477 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 478 479 iwl_dbg_tlv_alloc(trans, tlv, true); 480 } 481 482 return 0; 483} 484 485void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 486{ 487 const struct firmware *fw; 488 int res; 489 490 if (!iwlwifi_mod_params.enable_ini) 491 return; 492 493 res = firmware_request_nowarn(&fw, "iwl-debug-yoyo.bin", dev); 494 if (res) 495 return; 496 497 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 498 499 release_firmware(fw); 500} 501 502void iwl_dbg_tlv_init(struct iwl_trans *trans) 503{ 504 int i; 505 506 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 507 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 508 509 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 510 struct iwl_dbg_tlv_time_point_data *tp = 511 &trans->dbg.time_point[i]; 512 513 INIT_LIST_HEAD(&tp->trig_list); 514 INIT_LIST_HEAD(&tp->hcmd_list); 515 INIT_LIST_HEAD(&tp->active_trig_list); 516 } 517} 518 519static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 520 struct iwl_dram_data *frag, u32 pages) 521{ 522 void *block = NULL; 523 dma_addr_t physical; 524 525 if (!frag || frag->size || !pages) 526 return -EIO; 527 528 /* 529 * We try to allocate as many pages as we can, starting with 530 * the requested amount and going down until we can allocate 531 * something. Because of DIV_ROUND_UP(), pages will never go 532 * down to 0 and stop the loop, so stop when pages reaches 1, 533 * which is too small anyway. 534 */ 535 while (pages > 1) { 536 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 537 &physical, 538 GFP_KERNEL | __GFP_NOWARN); 539 if (block) 540 break; 541 542 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 543 pages * PAGE_SIZE); 544 545 pages = DIV_ROUND_UP(pages, 2); 546 } 547 548 if (!block) 549 return -ENOMEM; 550 551 frag->physical = physical; 552 frag->block = block; 553 frag->size = pages * PAGE_SIZE; 554 555 return pages; 556} 557 558static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 559 enum iwl_fw_ini_allocation_id alloc_id) 560{ 561 struct iwl_fw_mon *fw_mon; 562 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 563 u32 num_frags, remain_pages, frag_pages; 564 int i; 565 566 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 567 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 568 return -EIO; 569 570 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 571 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 572 573 if (fw_mon->num_frags || 574 fw_mon_cfg->buf_location != 575 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 576 return 0; 577 578 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 579 if (!fw_has_capa(&fwrt->fw->ucode_capa, 580 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 581 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 582 return -EIO; 583 num_frags = 1; 584 } 585 586 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 587 PAGE_SIZE); 588 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 589 num_frags = min_t(u32, num_frags, remain_pages); 590 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 591 592 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 593 if (!fw_mon->frags) 594 return -ENOMEM; 595 596 for (i = 0; i < num_frags; i++) { 597 int pages = min_t(u32, frag_pages, remain_pages); 598 599 IWL_DEBUG_FW(fwrt, 600 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 601 alloc_id, i, pages * PAGE_SIZE); 602 603 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 604 pages); 605 if (pages < 0) { 606 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 607 (remain_pages * PAGE_SIZE); 608 609 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 610 iwl_dbg_tlv_fragments_free(fwrt->trans, 611 alloc_id); 612 return pages; 613 } 614 break; 615 } 616 617 remain_pages -= pages; 618 fw_mon->num_frags++; 619 } 620 621 return 0; 622} 623 624static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 625 enum iwl_fw_ini_allocation_id alloc_id) 626{ 627 struct iwl_fw_mon *fw_mon; 628 u32 remain_frags, num_commands; 629 int i, fw_mon_idx = 0; 630 631 if (!fw_has_capa(&fwrt->fw->ucode_capa, 632 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 633 return 0; 634 635 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 636 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 637 return -EIO; 638 639 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 640 IWL_FW_INI_LOCATION_DRAM_PATH) 641 return 0; 642 643 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 644 645 /* the first fragment of DBGC1 is given to the FW via register 646 * or context info 647 */ 648 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 649 fw_mon_idx++; 650 651 remain_frags = fw_mon->num_frags - fw_mon_idx; 652 if (!remain_frags) 653 return 0; 654 655 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 656 657 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 658 alloc_id); 659 660 for (i = 0; i < num_commands; i++) { 661 u32 num_frags = min_t(u32, remain_frags, 662 BUF_ALLOC_MAX_NUM_FRAGS); 663 struct iwl_buf_alloc_cmd data = { 664 .alloc_id = cpu_to_le32(alloc_id), 665 .num_frags = cpu_to_le32(num_frags), 666 .buf_location = 667 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 668 }; 669 struct iwl_host_cmd hcmd = { 670 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 671 .data[0] = &data, 672 .len[0] = sizeof(data), 673 }; 674 int ret, j; 675 676 for (j = 0; j < num_frags; j++) { 677 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 678 struct iwl_dram_data *fw_mon_frag = 679 &fw_mon->frags[fw_mon_idx++]; 680 681 frag->addr = cpu_to_le64(fw_mon_frag->physical); 682 frag->size = cpu_to_le32(fw_mon_frag->size); 683 } 684 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 685 if (ret) 686 return ret; 687 688 remain_frags -= num_frags; 689 } 690 691 return 0; 692} 693 694static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 695{ 696 int ret, i; 697 698 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 699 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 700 if (ret) 701 IWL_WARN(fwrt, 702 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 703 i, ret); 704 } 705} 706 707static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 708 struct list_head *hcmd_list) 709{ 710 struct iwl_dbg_tlv_node *node; 711 712 list_for_each_entry(node, hcmd_list, list) { 713 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 714 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 715 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 716 struct iwl_host_cmd cmd = { 717 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 718 .len = { hcmd_len, }, 719 .data = { hcmd_data->data, }, 720 }; 721 722 iwl_trans_send_cmd(fwrt->trans, &cmd); 723 } 724} 725 726static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 727{ 728 struct iwl_dbg_tlv_timer_node *timer_node = 729 from_timer(timer_node, t, timer); 730 struct iwl_fwrt_dump_data dump_data = { 731 .trig = (void *)timer_node->tlv->data, 732 }; 733 int ret; 734 735 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data); 736 if (!ret || ret == -EBUSY) { 737 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 738 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 739 740 if (!occur) 741 return; 742 743 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 744 } 745} 746 747static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 748{ 749 struct iwl_dbg_tlv_node *node; 750 struct list_head *trig_list = 751 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 752 753 list_for_each_entry(node, trig_list, list) { 754 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 755 struct iwl_dbg_tlv_timer_node *timer_node; 756 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 757 u32 min_interval = 100; 758 759 if (!occur) 760 continue; 761 762 /* make sure there is at least one dword of data for the 763 * interval value 764 */ 765 if (le32_to_cpu(node->tlv.length) < 766 sizeof(*trig) + sizeof(__le32)) { 767 IWL_ERR(fwrt, 768 "WRT: Invalid periodic trigger data was not given\n"); 769 continue; 770 } 771 772 if (le32_to_cpu(trig->data[0]) < min_interval) { 773 IWL_WARN(fwrt, 774 "WRT: Override min interval from %u to %u msec\n", 775 le32_to_cpu(trig->data[0]), min_interval); 776 trig->data[0] = cpu_to_le32(min_interval); 777 } 778 779 collect_interval = le32_to_cpu(trig->data[0]); 780 781 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 782 if (!timer_node) { 783 IWL_ERR(fwrt, 784 "WRT: Failed to allocate periodic trigger\n"); 785 continue; 786 } 787 788 timer_node->fwrt = fwrt; 789 timer_node->tlv = &node->tlv; 790 timer_setup(&timer_node->timer, 791 iwl_dbg_tlv_periodic_trig_handler, 0); 792 793 list_add_tail(&timer_node->list, 794 &fwrt->trans->dbg.periodic_trig_list); 795 796 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 797 798 mod_timer(&timer_node->timer, 799 jiffies + msecs_to_jiffies(collect_interval)); 800 } 801} 802 803static bool is_trig_data_contained(struct iwl_ucode_tlv *new, 804 struct iwl_ucode_tlv *old) 805{ 806 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data; 807 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data; 808 __le32 *new_data = new_trig->data, *old_data = old_trig->data; 809 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 810 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 811 int i, j; 812 813 for (i = 0; i < new_dwords_num; i++) { 814 bool match = false; 815 816 for (j = 0; j < old_dwords_num; j++) { 817 if (new_data[i] == old_data[j]) { 818 match = true; 819 break; 820 } 821 } 822 if (!match) 823 return false; 824 } 825 826 return true; 827} 828 829static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 830 struct iwl_ucode_tlv *trig_tlv, 831 struct iwl_dbg_tlv_node *node) 832{ 833 struct iwl_ucode_tlv *node_tlv = &node->tlv; 834 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 835 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 836 u32 policy = le32_to_cpu(trig->apply_policy); 837 u32 size = le32_to_cpu(trig_tlv->length); 838 u32 trig_data_len = size - sizeof(*trig); 839 u32 offset = 0; 840 841 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 842 u32 data_len = le32_to_cpu(node_tlv->length) - 843 sizeof(*node_trig); 844 845 IWL_DEBUG_FW(fwrt, 846 "WRT: Appending trigger data (time point %u)\n", 847 le32_to_cpu(trig->time_point)); 848 849 offset += data_len; 850 size += data_len; 851 } else { 852 IWL_DEBUG_FW(fwrt, 853 "WRT: Overriding trigger data (time point %u)\n", 854 le32_to_cpu(trig->time_point)); 855 } 856 857 if (size != le32_to_cpu(node_tlv->length)) { 858 struct list_head *prev = node->list.prev; 859 struct iwl_dbg_tlv_node *tmp; 860 861 list_del(&node->list); 862 863 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 864 if (!tmp) { 865 IWL_WARN(fwrt, 866 "WRT: No memory to override trigger (time point %u)\n", 867 le32_to_cpu(trig->time_point)); 868 869 list_add(&node->list, prev); 870 871 return -ENOMEM; 872 } 873 874 list_add(&tmp->list, prev); 875 node_tlv = &tmp->tlv; 876 node_trig = (void *)node_tlv->data; 877 } 878 879 memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len); 880 node_tlv->length = cpu_to_le32(size); 881 882 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 883 IWL_DEBUG_FW(fwrt, 884 "WRT: Overriding trigger configuration (time point %u)\n", 885 le32_to_cpu(trig->time_point)); 886 887 /* the first 11 dwords are configuration related */ 888 memcpy(node_trig, trig, sizeof(__le32) * 11); 889 } 890 891 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 892 IWL_DEBUG_FW(fwrt, 893 "WRT: Overriding trigger regions (time point %u)\n", 894 le32_to_cpu(trig->time_point)); 895 896 node_trig->regions_mask = trig->regions_mask; 897 } else { 898 IWL_DEBUG_FW(fwrt, 899 "WRT: Appending trigger regions (time point %u)\n", 900 le32_to_cpu(trig->time_point)); 901 902 node_trig->regions_mask |= trig->regions_mask; 903 } 904 905 return 0; 906} 907 908static int 909iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 910 struct list_head *trig_list, 911 struct iwl_ucode_tlv *trig_tlv) 912{ 913 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 914 struct iwl_dbg_tlv_node *node, *match = NULL; 915 u32 policy = le32_to_cpu(trig->apply_policy); 916 917 list_for_each_entry(node, trig_list, list) { 918 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 919 break; 920 921 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 922 is_trig_data_contained(trig_tlv, &node->tlv)) { 923 match = node; 924 break; 925 } 926 } 927 928 if (!match) { 929 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 930 le32_to_cpu(trig->time_point)); 931 return iwl_dbg_tlv_add(trig_tlv, trig_list); 932 } 933 934 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 935} 936 937static void 938iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 939 struct iwl_dbg_tlv_time_point_data *tp) 940{ 941 struct iwl_dbg_tlv_node *node; 942 struct list_head *trig_list = &tp->trig_list; 943 struct list_head *active_trig_list = &tp->active_trig_list; 944 945 list_for_each_entry(node, trig_list, list) { 946 struct iwl_ucode_tlv *tlv = &node->tlv; 947 948 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 949 } 950} 951 952static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 953 struct iwl_fwrt_dump_data *dump_data, 954 union iwl_dbg_tlv_tp_data *tp_data, 955 u32 trig_data) 956{ 957 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 958 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 959 960 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 961 pkt->hdr.group_id == wanted_hdr->group_id)) { 962 struct iwl_rx_packet *fw_pkt = 963 kmemdup(pkt, 964 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 965 GFP_ATOMIC); 966 967 if (!fw_pkt) 968 return false; 969 970 dump_data->fw_pkt = fw_pkt; 971 972 return true; 973 } 974 975 return false; 976} 977 978static int 979iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, 980 struct list_head *active_trig_list, 981 union iwl_dbg_tlv_tp_data *tp_data, 982 bool (*data_check)(struct iwl_fw_runtime *fwrt, 983 struct iwl_fwrt_dump_data *dump_data, 984 union iwl_dbg_tlv_tp_data *tp_data, 985 u32 trig_data)) 986{ 987 struct iwl_dbg_tlv_node *node; 988 989 list_for_each_entry(node, active_trig_list, list) { 990 struct iwl_fwrt_dump_data dump_data = { 991 .trig = (void *)node->tlv.data, 992 }; 993 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 994 data); 995 int ret, i; 996 997 if (!num_data) { 998 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 999 if (ret) 1000 return ret; 1001 } 1002 1003 for (i = 0; i < num_data; i++) { 1004 if (!data_check || 1005 data_check(fwrt, &dump_data, tp_data, 1006 le32_to_cpu(dump_data.trig->data[i]))) { 1007 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 1008 if (ret) 1009 return ret; 1010 1011 break; 1012 } 1013 } 1014 } 1015 1016 return 0; 1017} 1018 1019static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1020{ 1021 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1022 int ret, i; 1023 1024 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 1025 return; 1026 1027 IWL_DEBUG_FW(fwrt, 1028 "WRT: Generating active triggers list, domain 0x%x\n", 1029 fwrt->trans->dbg.domains_bitmap); 1030 1031 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1032 struct iwl_dbg_tlv_time_point_data *tp = 1033 &fwrt->trans->dbg.time_point[i]; 1034 1035 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1036 } 1037 1038 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1039 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1040 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1041 &fwrt->trans->dbg.fw_mon_cfg[i]; 1042 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1043 1044 if (dest == IWL_FW_INI_LOCATION_INVALID) 1045 continue; 1046 1047 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1048 *ini_dest = dest; 1049 1050 if (dest != *ini_dest) 1051 continue; 1052 1053 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1054 if (ret) 1055 IWL_WARN(fwrt, 1056 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1057 i, ret); 1058 } 1059} 1060 1061void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1062 enum iwl_fw_ini_time_point tp_id, 1063 union iwl_dbg_tlv_tp_data *tp_data) 1064{ 1065 struct list_head *hcmd_list, *trig_list; 1066 1067 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1068 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1069 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1070 return; 1071 1072 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1073 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1074 1075 switch (tp_id) { 1076 case IWL_FW_INI_TIME_POINT_EARLY: 1077 iwl_dbg_tlv_init_cfg(fwrt); 1078 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1079 break; 1080 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1081 iwl_dbg_tlv_apply_buffers(fwrt); 1082 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1083 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1084 break; 1085 case IWL_FW_INI_TIME_POINT_PERIODIC: 1086 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1087 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1088 break; 1089 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1090 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1091 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1092 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1093 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, 1094 iwl_dbg_tlv_check_fw_pkt); 1095 break; 1096 default: 1097 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1098 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1099 break; 1100 } 1101} 1102IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point); 1103