1// SPDX-License-Identifier: GPL-2.0-only 2/****************************************************************************** 3 * 4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 5 * 6 * Portions of this file are derived from the ipw3945 project, as well 7 * as portions of the ieee80211 subsystem header files. 8 * 9 * Contact Information: 10 * Intel Linux Wireless <ilw@linux.intel.com> 11 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 12 * 13 *****************************************************************************/ 14 15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 16 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/init.h> 20#include <linux/pci.h> 21#include <linux/slab.h> 22#include <linux/dma-mapping.h> 23#include <linux/delay.h> 24#include <linux/sched.h> 25#include <linux/skbuff.h> 26#include <linux/netdevice.h> 27#include <linux/firmware.h> 28#include <linux/etherdevice.h> 29#include <linux/if_arp.h> 30#include <linux/units.h> 31 32#include <net/mac80211.h> 33 34#include <asm/div64.h> 35 36#define DRV_NAME "iwl4965" 37 38#include "common.h" 39#include "4965.h" 40 41/****************************************************************************** 42 * 43 * module boiler plate 44 * 45 ******************************************************************************/ 46 47/* 48 * module name, copyright, version, etc. 49 */ 50#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux" 51 52#ifdef CONFIG_IWLEGACY_DEBUG 53#define VD "d" 54#else 55#define VD 56#endif 57 58#define DRV_VERSION IWLWIFI_VERSION VD 59 60MODULE_DESCRIPTION(DRV_DESCRIPTION); 61MODULE_VERSION(DRV_VERSION); 62MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); 63MODULE_LICENSE("GPL"); 64MODULE_ALIAS("iwl4965"); 65 66void 67il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status) 68{ 69 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) { 70 IL_ERR("Tx flush command to flush out all frames\n"); 71 if (!test_bit(S_EXIT_PENDING, &il->status)) 72 queue_work(il->workqueue, &il->tx_flush); 73 } 74} 75 76/* 77 * EEPROM 78 */ 79struct il_mod_params il4965_mod_params = { 80 .restart_fw = 1, 81 /* the rest are 0 by default */ 82}; 83 84void 85il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq) 86{ 87 unsigned long flags; 88 int i; 89 spin_lock_irqsave(&rxq->lock, flags); 90 INIT_LIST_HEAD(&rxq->rx_free); 91 INIT_LIST_HEAD(&rxq->rx_used); 92 /* Fill the rx_used queue with _all_ of the Rx buffers */ 93 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { 94 /* In the reset function, these buffers may have been allocated 95 * to an SKB, so we need to unmap and free potential storage */ 96 if (rxq->pool[i].page != NULL) { 97 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, 98 PAGE_SIZE << il->hw_params.rx_page_order, 99 PCI_DMA_FROMDEVICE); 100 __il_free_pages(il, rxq->pool[i].page); 101 rxq->pool[i].page = NULL; 102 } 103 list_add_tail(&rxq->pool[i].list, &rxq->rx_used); 104 } 105 106 for (i = 0; i < RX_QUEUE_SIZE; i++) 107 rxq->queue[i] = NULL; 108 109 /* Set us so that we have processed and used all buffers, but have 110 * not restocked the Rx queue with fresh buffers */ 111 rxq->read = rxq->write = 0; 112 rxq->write_actual = 0; 113 rxq->free_count = 0; 114 spin_unlock_irqrestore(&rxq->lock, flags); 115} 116 117int 118il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 119{ 120 u32 rb_size; 121 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 122 u32 rb_timeout = 0; 123 124 if (il->cfg->mod_params->amsdu_size_8K) 125 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 126 else 127 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 128 129 /* Stop Rx DMA */ 130 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); 131 132 /* Reset driver's Rx queue write idx */ 133 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 134 135 /* Tell device where to find RBD circular buffer in DRAM */ 136 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8)); 137 138 /* Tell device where in DRAM to update its Rx status */ 139 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4); 140 141 /* Enable Rx DMA 142 * Direct rx interrupts to hosts 143 * Rx buffer size 4 or 8k 144 * RB timeout 0x10 145 * 256 RBDs 146 */ 147 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 148 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 149 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 150 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | 151 rb_size | 152 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 153 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 154 155 /* Set interrupt coalescing timer to default (2048 usecs) */ 156 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF); 157 158 return 0; 159} 160 161static void 162il4965_set_pwr_vmain(struct il_priv *il) 163{ 164/* 165 * (for documentation purposes) 166 * to set power to V_AUX, do: 167 168 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) 169 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 170 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 171 ~APMG_PS_CTRL_MSK_PWR_SRC); 172 */ 173 174 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 175 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 176 ~APMG_PS_CTRL_MSK_PWR_SRC); 177} 178 179int 180il4965_hw_nic_init(struct il_priv *il) 181{ 182 unsigned long flags; 183 struct il_rx_queue *rxq = &il->rxq; 184 int ret; 185 186 spin_lock_irqsave(&il->lock, flags); 187 il_apm_init(il); 188 /* Set interrupt coalescing calibration timer to default (512 usecs) */ 189 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF); 190 spin_unlock_irqrestore(&il->lock, flags); 191 192 il4965_set_pwr_vmain(il); 193 il4965_nic_config(il); 194 195 /* Allocate the RX queue, or reset if it is already allocated */ 196 if (!rxq->bd) { 197 ret = il_rx_queue_alloc(il); 198 if (ret) { 199 IL_ERR("Unable to initialize Rx queue\n"); 200 return -ENOMEM; 201 } 202 } else 203 il4965_rx_queue_reset(il, rxq); 204 205 il4965_rx_replenish(il); 206 207 il4965_rx_init(il, rxq); 208 209 spin_lock_irqsave(&il->lock, flags); 210 211 rxq->need_update = 1; 212 il_rx_queue_update_write_ptr(il, rxq); 213 214 spin_unlock_irqrestore(&il->lock, flags); 215 216 /* Allocate or reset and init all Tx and Command queues */ 217 if (!il->txq) { 218 ret = il4965_txq_ctx_alloc(il); 219 if (ret) 220 return ret; 221 } else 222 il4965_txq_ctx_reset(il); 223 224 set_bit(S_INIT, &il->status); 225 226 return 0; 227} 228 229/* 230 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 231 */ 232static inline __le32 233il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr) 234{ 235 return cpu_to_le32((u32) (dma_addr >> 8)); 236} 237 238/* 239 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool 240 * 241 * If there are slots in the RX queue that need to be restocked, 242 * and we have free pre-allocated buffers, fill the ranks as much 243 * as we can, pulling from rx_free. 244 * 245 * This moves the 'write' idx forward to catch up with 'processed', and 246 * also updates the memory address in the firmware to reference the new 247 * target buffer. 248 */ 249void 250il4965_rx_queue_restock(struct il_priv *il) 251{ 252 struct il_rx_queue *rxq = &il->rxq; 253 struct list_head *element; 254 struct il_rx_buf *rxb; 255 unsigned long flags; 256 257 spin_lock_irqsave(&rxq->lock, flags); 258 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) { 259 /* The overwritten rxb must be a used one */ 260 rxb = rxq->queue[rxq->write]; 261 BUG_ON(rxb && rxb->page); 262 263 /* Get next free Rx buffer, remove from free list */ 264 element = rxq->rx_free.next; 265 rxb = list_entry(element, struct il_rx_buf, list); 266 list_del(element); 267 268 /* Point to Rx buffer via next RBD in circular buffer */ 269 rxq->bd[rxq->write] = 270 il4965_dma_addr2rbd_ptr(il, rxb->page_dma); 271 rxq->queue[rxq->write] = rxb; 272 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 273 rxq->free_count--; 274 } 275 spin_unlock_irqrestore(&rxq->lock, flags); 276 /* If the pre-allocated buffer pool is dropping low, schedule to 277 * refill it */ 278 if (rxq->free_count <= RX_LOW_WATERMARK) 279 queue_work(il->workqueue, &il->rx_replenish); 280 281 /* If we've added more space for the firmware to place data, tell it. 282 * Increment device's write pointer in multiples of 8. */ 283 if (rxq->write_actual != (rxq->write & ~0x7)) { 284 spin_lock_irqsave(&rxq->lock, flags); 285 rxq->need_update = 1; 286 spin_unlock_irqrestore(&rxq->lock, flags); 287 il_rx_queue_update_write_ptr(il, rxq); 288 } 289} 290 291/* 292 * il4965_rx_replenish - Move all used packet from rx_used to rx_free 293 * 294 * When moving to rx_free an SKB is allocated for the slot. 295 * 296 * Also restock the Rx queue via il_rx_queue_restock. 297 * This is called as a scheduled work item (except for during initialization) 298 */ 299static void 300il4965_rx_allocate(struct il_priv *il, gfp_t priority) 301{ 302 struct il_rx_queue *rxq = &il->rxq; 303 struct list_head *element; 304 struct il_rx_buf *rxb; 305 struct page *page; 306 dma_addr_t page_dma; 307 unsigned long flags; 308 gfp_t gfp_mask = priority; 309 310 while (1) { 311 spin_lock_irqsave(&rxq->lock, flags); 312 if (list_empty(&rxq->rx_used)) { 313 spin_unlock_irqrestore(&rxq->lock, flags); 314 return; 315 } 316 spin_unlock_irqrestore(&rxq->lock, flags); 317 318 if (rxq->free_count > RX_LOW_WATERMARK) 319 gfp_mask |= __GFP_NOWARN; 320 321 if (il->hw_params.rx_page_order > 0) 322 gfp_mask |= __GFP_COMP; 323 324 /* Alloc a new receive buffer */ 325 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order); 326 if (!page) { 327 if (net_ratelimit()) 328 D_INFO("alloc_pages failed, " "order: %d\n", 329 il->hw_params.rx_page_order); 330 331 if (rxq->free_count <= RX_LOW_WATERMARK && 332 net_ratelimit()) 333 IL_ERR("Failed to alloc_pages with %s. " 334 "Only %u free buffers remaining.\n", 335 priority == 336 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", 337 rxq->free_count); 338 /* We don't reschedule replenish work here -- we will 339 * call the restock method and if it still needs 340 * more buffers it will schedule replenish */ 341 return; 342 } 343 344 /* Get physical address of the RB */ 345 page_dma = 346 pci_map_page(il->pci_dev, page, 0, 347 PAGE_SIZE << il->hw_params.rx_page_order, 348 PCI_DMA_FROMDEVICE); 349 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) { 350 __free_pages(page, il->hw_params.rx_page_order); 351 break; 352 } 353 354 spin_lock_irqsave(&rxq->lock, flags); 355 356 if (list_empty(&rxq->rx_used)) { 357 spin_unlock_irqrestore(&rxq->lock, flags); 358 pci_unmap_page(il->pci_dev, page_dma, 359 PAGE_SIZE << il->hw_params.rx_page_order, 360 PCI_DMA_FROMDEVICE); 361 __free_pages(page, il->hw_params.rx_page_order); 362 return; 363 } 364 365 element = rxq->rx_used.next; 366 rxb = list_entry(element, struct il_rx_buf, list); 367 list_del(element); 368 369 BUG_ON(rxb->page); 370 371 rxb->page = page; 372 rxb->page_dma = page_dma; 373 list_add_tail(&rxb->list, &rxq->rx_free); 374 rxq->free_count++; 375 il->alloc_rxb_page++; 376 377 spin_unlock_irqrestore(&rxq->lock, flags); 378 } 379} 380 381void 382il4965_rx_replenish(struct il_priv *il) 383{ 384 unsigned long flags; 385 386 il4965_rx_allocate(il, GFP_KERNEL); 387 388 spin_lock_irqsave(&il->lock, flags); 389 il4965_rx_queue_restock(il); 390 spin_unlock_irqrestore(&il->lock, flags); 391} 392 393void 394il4965_rx_replenish_now(struct il_priv *il) 395{ 396 il4965_rx_allocate(il, GFP_ATOMIC); 397 398 il4965_rx_queue_restock(il); 399} 400 401/* Assumes that the skb field of the buffers in 'pool' is kept accurate. 402 * If an SKB has been detached, the POOL needs to have its SKB set to NULL 403 * This free routine walks the list of POOL entries and if SKB is set to 404 * non NULL it is unmapped and freed 405 */ 406void 407il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq) 408{ 409 int i; 410 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { 411 if (rxq->pool[i].page != NULL) { 412 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, 413 PAGE_SIZE << il->hw_params.rx_page_order, 414 PCI_DMA_FROMDEVICE); 415 __il_free_pages(il, rxq->pool[i].page); 416 rxq->pool[i].page = NULL; 417 } 418 } 419 420 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, 421 rxq->bd_dma); 422 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status), 423 rxq->rb_stts, rxq->rb_stts_dma); 424 rxq->bd = NULL; 425 rxq->rb_stts = NULL; 426} 427 428int 429il4965_rxq_stop(struct il_priv *il) 430{ 431 int ret; 432 433 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); 434 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG, 435 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 436 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 437 1000); 438 if (ret < 0) 439 IL_ERR("Can't stop Rx DMA.\n"); 440 441 return 0; 442} 443 444int 445il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum nl80211_band band) 446{ 447 int idx = 0; 448 int band_offset = 0; 449 450 /* HT rate format: mac80211 wants an MCS number, which is just LSB */ 451 if (rate_n_flags & RATE_MCS_HT_MSK) { 452 idx = (rate_n_flags & 0xff); 453 return idx; 454 /* Legacy rate format, search for match in table */ 455 } else { 456 if (band == NL80211_BAND_5GHZ) 457 band_offset = IL_FIRST_OFDM_RATE; 458 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++) 459 if (il_rates[idx].plcp == (rate_n_flags & 0xFF)) 460 return idx - band_offset; 461 } 462 463 return -1; 464} 465 466static int 467il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp) 468{ 469 /* data from PHY/DSP regarding signal strength, etc., 470 * contents are always there, not configurable by host. */ 471 struct il4965_rx_non_cfg_phy *ncphy = 472 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 473 u32 agc = 474 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >> 475 IL49_AGC_DB_POS; 476 477 u32 valid_antennae = 478 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK) 479 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET; 480 u8 max_rssi = 0; 481 u32 i; 482 483 /* Find max rssi among 3 possible receivers. 484 * These values are measured by the digital signal processor (DSP). 485 * They should stay fairly constant even as the signal strength varies, 486 * if the radio's automatic gain control (AGC) is working right. 487 * AGC value (see below) will provide the "interesting" info. */ 488 for (i = 0; i < 3; i++) 489 if (valid_antennae & (1 << i)) 490 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); 491 492 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 493 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], 494 max_rssi, agc); 495 496 /* dBm = max_rssi dB - agc dB - constant. 497 * Higher AGC (higher radio gain) means lower signal. */ 498 return max_rssi - agc - IL4965_RSSI_OFFSET; 499} 500 501static u32 502il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in) 503{ 504 u32 decrypt_out = 0; 505 506 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == 507 RX_RES_STATUS_STATION_FOUND) 508 decrypt_out |= 509 (RX_RES_STATUS_STATION_FOUND | 510 RX_RES_STATUS_NO_STATION_INFO_MISMATCH); 511 512 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); 513 514 /* packet was not encrypted */ 515 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 516 RX_RES_STATUS_SEC_TYPE_NONE) 517 return decrypt_out; 518 519 /* packet was encrypted with unknown alg */ 520 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 521 RX_RES_STATUS_SEC_TYPE_ERR) 522 return decrypt_out; 523 524 /* decryption was not done in HW */ 525 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != 526 RX_MPDU_RES_STATUS_DEC_DONE_MSK) 527 return decrypt_out; 528 529 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { 530 531 case RX_RES_STATUS_SEC_TYPE_CCMP: 532 /* alg is CCM: check MIC only */ 533 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) 534 /* Bad MIC */ 535 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 536 else 537 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 538 539 break; 540 541 case RX_RES_STATUS_SEC_TYPE_TKIP: 542 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { 543 /* Bad TTAK */ 544 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; 545 break; 546 } 547 fallthrough; /* if TTAK OK */ 548 default: 549 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) 550 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 551 else 552 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 553 break; 554 } 555 556 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out); 557 558 return decrypt_out; 559} 560 561#define SMALL_PACKET_SIZE 256 562 563static void 564il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr, 565 u32 len, u32 ampdu_status, struct il_rx_buf *rxb, 566 struct ieee80211_rx_status *stats) 567{ 568 struct sk_buff *skb; 569 __le16 fc = hdr->frame_control; 570 571 /* We only process data packets if the interface is open */ 572 if (unlikely(!il->is_open)) { 573 D_DROP("Dropping packet while interface is not open.\n"); 574 return; 575 } 576 577 if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) { 578 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE); 579 D_INFO("Woke queues - frame received on passive channel\n"); 580 } 581 582 /* In case of HW accelerated crypto and bad decryption, drop */ 583 if (!il->cfg->mod_params->sw_crypto && 584 il_set_decrypted_flag(il, hdr, ampdu_status, stats)) 585 return; 586 587 skb = dev_alloc_skb(SMALL_PACKET_SIZE); 588 if (!skb) { 589 IL_ERR("dev_alloc_skb failed\n"); 590 return; 591 } 592 593 if (len <= SMALL_PACKET_SIZE) { 594 skb_put_data(skb, hdr, len); 595 } else { 596 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), 597 len, PAGE_SIZE << il->hw_params.rx_page_order); 598 il->alloc_rxb_page--; 599 rxb->page = NULL; 600 } 601 602 il_update_stats(il, false, fc, len); 603 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 604 605 ieee80211_rx(il->hw, skb); 606} 607 608/* Called for N_RX (legacy ABG frames), or 609 * N_RX_MPDU (HT high-throughput N frames). */ 610static void 611il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb) 612{ 613 struct ieee80211_hdr *header; 614 struct ieee80211_rx_status rx_status = {}; 615 struct il_rx_pkt *pkt = rxb_addr(rxb); 616 struct il_rx_phy_res *phy_res; 617 __le32 rx_pkt_status; 618 struct il_rx_mpdu_res_start *amsdu; 619 u32 len; 620 u32 ampdu_status; 621 u32 rate_n_flags; 622 623 /** 624 * N_RX and N_RX_MPDU are handled differently. 625 * N_RX: physical layer info is in this buffer 626 * N_RX_MPDU: physical layer info was sent in separate 627 * command and cached in il->last_phy_res 628 * 629 * Here we set up local variables depending on which command is 630 * received. 631 */ 632 if (pkt->hdr.cmd == N_RX) { 633 phy_res = (struct il_rx_phy_res *)pkt->u.raw; 634 header = 635 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) + 636 phy_res->cfg_phy_cnt); 637 638 len = le16_to_cpu(phy_res->byte_count); 639 rx_pkt_status = 640 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) + 641 phy_res->cfg_phy_cnt + len); 642 ampdu_status = le32_to_cpu(rx_pkt_status); 643 } else { 644 if (!il->_4965.last_phy_res_valid) { 645 IL_ERR("MPDU frame without cached PHY data\n"); 646 return; 647 } 648 phy_res = &il->_4965.last_phy_res; 649 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw; 650 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); 651 len = le16_to_cpu(amsdu->byte_count); 652 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len); 653 ampdu_status = 654 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status)); 655 } 656 657 if ((unlikely(phy_res->cfg_phy_cnt > 20))) { 658 D_DROP("dsp size out of range [0,20]: %d\n", 659 phy_res->cfg_phy_cnt); 660 return; 661 } 662 663 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || 664 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 665 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status)); 666 return; 667 } 668 669 /* This will be used in several places later */ 670 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); 671 672 /* rx_status carries information about the packet to mac80211 */ 673 rx_status.mactime = le64_to_cpu(phy_res->timestamp); 674 rx_status.band = 675 (phy_res-> 676 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? NL80211_BAND_2GHZ : 677 NL80211_BAND_5GHZ; 678 rx_status.freq = 679 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel), 680 rx_status.band); 681 rx_status.rate_idx = 682 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); 683 rx_status.flag = 0; 684 685 /* TSF isn't reliable. In order to allow smooth user experience, 686 * this W/A doesn't propagate it to the mac80211 */ 687 /*rx_status.flag |= RX_FLAG_MACTIME_START; */ 688 689 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); 690 691 /* Find max signal strength (dBm) among 3 antenna/receiver chains */ 692 rx_status.signal = il4965_calc_rssi(il, phy_res); 693 694 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal, 695 (unsigned long long)rx_status.mactime); 696 697 /* 698 * "antenna number" 699 * 700 * It seems that the antenna field in the phy flags value 701 * is actually a bit field. This is undefined by radiotap, 702 * it wants an actual antenna number but I always get "7" 703 * for most legacy frames I receive indicating that the 704 * same frame was received on all three RX chains. 705 * 706 * I think this field should be removed in favor of a 707 * new 802.11n radiotap field "RX chains" that is defined 708 * as a bitmask. 709 */ 710 rx_status.antenna = 711 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 712 RX_RES_PHY_FLAGS_ANTENNA_POS; 713 714 /* set the preamble flag if appropriate */ 715 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 716 rx_status.enc_flags |= RX_ENC_FLAG_SHORTPRE; 717 718 /* Set up the HT phy flags */ 719 if (rate_n_flags & RATE_MCS_HT_MSK) 720 rx_status.encoding = RX_ENC_HT; 721 if (rate_n_flags & RATE_MCS_HT40_MSK) 722 rx_status.bw = RATE_INFO_BW_40; 723 else 724 rx_status.bw = RATE_INFO_BW_20; 725 if (rate_n_flags & RATE_MCS_SGI_MSK) 726 rx_status.enc_flags |= RX_ENC_FLAG_SHORT_GI; 727 728 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) { 729 /* We know which subframes of an A-MPDU belong 730 * together since we get a single PHY response 731 * from the firmware for all of them. 732 */ 733 734 rx_status.flag |= RX_FLAG_AMPDU_DETAILS; 735 rx_status.ampdu_reference = il->_4965.ampdu_ref; 736 } 737 738 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb, 739 &rx_status); 740} 741 742/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY). 743 * This will be used later in il_hdl_rx() for N_RX_MPDU. */ 744static void 745il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb) 746{ 747 struct il_rx_pkt *pkt = rxb_addr(rxb); 748 il->_4965.last_phy_res_valid = true; 749 il->_4965.ampdu_ref++; 750 memcpy(&il->_4965.last_phy_res, pkt->u.raw, 751 sizeof(struct il_rx_phy_res)); 752} 753 754static int 755il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif, 756 enum nl80211_band band, u8 is_active, 757 u8 n_probes, struct il_scan_channel *scan_ch) 758{ 759 struct ieee80211_channel *chan; 760 const struct ieee80211_supported_band *sband; 761 const struct il_channel_info *ch_info; 762 u16 passive_dwell = 0; 763 u16 active_dwell = 0; 764 int added, i; 765 u16 channel; 766 767 sband = il_get_hw_mode(il, band); 768 if (!sband) 769 return 0; 770 771 active_dwell = il_get_active_dwell_time(il, band, n_probes); 772 passive_dwell = il_get_passive_dwell_time(il, band, vif); 773 774 if (passive_dwell <= active_dwell) 775 passive_dwell = active_dwell + 1; 776 777 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) { 778 chan = il->scan_request->channels[i]; 779 780 if (chan->band != band) 781 continue; 782 783 channel = chan->hw_value; 784 scan_ch->channel = cpu_to_le16(channel); 785 786 ch_info = il_get_channel_info(il, band, channel); 787 if (!il_is_channel_valid(ch_info)) { 788 D_SCAN("Channel %d is INVALID for this band.\n", 789 channel); 790 continue; 791 } 792 793 if (!is_active || il_is_channel_passive(ch_info) || 794 (chan->flags & IEEE80211_CHAN_NO_IR)) 795 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; 796 else 797 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE; 798 799 if (n_probes) 800 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes); 801 802 scan_ch->active_dwell = cpu_to_le16(active_dwell); 803 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 804 805 /* Set txpower levels to defaults */ 806 scan_ch->dsp_atten = 110; 807 808 /* NOTE: if we were doing 6Mb OFDM for scans we'd use 809 * power level: 810 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3; 811 */ 812 if (band == NL80211_BAND_5GHZ) 813 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 814 else 815 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 816 817 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel, 818 le32_to_cpu(scan_ch->type), 819 (scan_ch-> 820 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE", 821 (scan_ch-> 822 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell : 823 passive_dwell); 824 825 scan_ch++; 826 added++; 827 } 828 829 D_SCAN("total channels to scan %d\n", added); 830 return added; 831} 832 833static void 834il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid) 835{ 836 int i; 837 u8 ind = *ant; 838 839 for (i = 0; i < RATE_ANT_NUM - 1; i++) { 840 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; 841 if (valid & BIT(ind)) { 842 *ant = ind; 843 return; 844 } 845 } 846} 847 848int 849il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif) 850{ 851 struct il_host_cmd cmd = { 852 .id = C_SCAN, 853 .len = sizeof(struct il_scan_cmd), 854 .flags = CMD_SIZE_HUGE, 855 }; 856 struct il_scan_cmd *scan; 857 u32 rate_flags = 0; 858 u16 cmd_len; 859 u16 rx_chain = 0; 860 enum nl80211_band band; 861 u8 n_probes = 0; 862 u8 rx_ant = il->hw_params.valid_rx_ant; 863 u8 rate; 864 bool is_active = false; 865 int chan_mod; 866 u8 active_chains; 867 u8 scan_tx_antennas = il->hw_params.valid_tx_ant; 868 int ret; 869 870 lockdep_assert_held(&il->mutex); 871 872 if (!il->scan_cmd) { 873 il->scan_cmd = 874 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE, 875 GFP_KERNEL); 876 if (!il->scan_cmd) { 877 D_SCAN("fail to allocate memory for scan\n"); 878 return -ENOMEM; 879 } 880 } 881 scan = il->scan_cmd; 882 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE); 883 884 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH; 885 scan->quiet_time = IL_ACTIVE_QUIET_TIME; 886 887 if (il_is_any_associated(il)) { 888 u16 interval; 889 u32 extra; 890 u32 suspend_time = 100; 891 u32 scan_suspend_time = 100; 892 893 D_INFO("Scanning while associated...\n"); 894 interval = vif->bss_conf.beacon_int; 895 896 scan->suspend_time = 0; 897 scan->max_out_time = cpu_to_le32(200 * 1024); 898 if (!interval) 899 interval = suspend_time; 900 901 extra = (suspend_time / interval) << 22; 902 scan_suspend_time = 903 (extra | ((suspend_time % interval) * 1024)); 904 scan->suspend_time = cpu_to_le32(scan_suspend_time); 905 D_SCAN("suspend_time 0x%X beacon interval %d\n", 906 scan_suspend_time, interval); 907 } 908 909 if (il->scan_request->n_ssids) { 910 int i, p = 0; 911 D_SCAN("Kicking off active scan\n"); 912 for (i = 0; i < il->scan_request->n_ssids; i++) { 913 /* always does wildcard anyway */ 914 if (!il->scan_request->ssids[i].ssid_len) 915 continue; 916 scan->direct_scan[p].id = WLAN_EID_SSID; 917 scan->direct_scan[p].len = 918 il->scan_request->ssids[i].ssid_len; 919 memcpy(scan->direct_scan[p].ssid, 920 il->scan_request->ssids[i].ssid, 921 il->scan_request->ssids[i].ssid_len); 922 n_probes++; 923 p++; 924 } 925 is_active = true; 926 } else 927 D_SCAN("Start passive scan.\n"); 928 929 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; 930 scan->tx_cmd.sta_id = il->hw_params.bcast_id; 931 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 932 933 switch (il->scan_band) { 934 case NL80211_BAND_2GHZ: 935 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; 936 chan_mod = 937 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >> 938 RXON_FLG_CHANNEL_MODE_POS; 939 if (chan_mod == CHANNEL_MODE_PURE_40) { 940 rate = RATE_6M_PLCP; 941 } else { 942 rate = RATE_1M_PLCP; 943 rate_flags = RATE_MCS_CCK_MSK; 944 } 945 break; 946 case NL80211_BAND_5GHZ: 947 rate = RATE_6M_PLCP; 948 break; 949 default: 950 IL_WARN("Invalid scan band\n"); 951 return -EIO; 952 } 953 954 /* 955 * If active scanning is requested but a certain channel is 956 * marked passive, we can do active scanning if we detect 957 * transmissions. 958 * 959 * There is an issue with some firmware versions that triggers 960 * a sysassert on a "good CRC threshold" of zero (== disabled), 961 * on a radar channel even though this means that we should NOT 962 * send probes. 963 * 964 * The "good CRC threshold" is the number of frames that we 965 * need to receive during our dwell time on a channel before 966 * sending out probes -- setting this to a huge value will 967 * mean we never reach it, but at the same time work around 968 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER 969 * here instead of IL_GOOD_CRC_TH_DISABLED. 970 */ 971 scan->good_CRC_th = 972 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER; 973 974 band = il->scan_band; 975 976 if (il->cfg->scan_rx_antennas[band]) 977 rx_ant = il->cfg->scan_rx_antennas[band]; 978 979 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas); 980 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS; 981 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags); 982 983 /* In power save mode use one chain, otherwise use all chains */ 984 if (test_bit(S_POWER_PMI, &il->status)) { 985 /* rx_ant has been set to all valid chains previously */ 986 active_chains = 987 rx_ant & ((u8) (il->chain_noise_data.active_chains)); 988 if (!active_chains) 989 active_chains = rx_ant; 990 991 D_SCAN("chain_noise_data.active_chains: %u\n", 992 il->chain_noise_data.active_chains); 993 994 rx_ant = il4965_first_antenna(active_chains); 995 } 996 997 /* MIMO is not used here, but value is required */ 998 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS; 999 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; 1000 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS; 1001 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; 1002 scan->rx_chain = cpu_to_le16(rx_chain); 1003 1004 cmd_len = 1005 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data, 1006 vif->addr, il->scan_request->ie, 1007 il->scan_request->ie_len, 1008 IL_MAX_SCAN_SIZE - sizeof(*scan)); 1009 scan->tx_cmd.len = cpu_to_le16(cmd_len); 1010 1011 scan->filter_flags |= 1012 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK); 1013 1014 scan->channel_count = 1015 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes, 1016 (void *)&scan->data[cmd_len]); 1017 if (scan->channel_count == 0) { 1018 D_SCAN("channel count %d\n", scan->channel_count); 1019 return -EIO; 1020 } 1021 1022 cmd.len += 1023 le16_to_cpu(scan->tx_cmd.len) + 1024 scan->channel_count * sizeof(struct il_scan_channel); 1025 cmd.data = scan; 1026 scan->len = cpu_to_le16(cmd.len); 1027 1028 set_bit(S_SCAN_HW, &il->status); 1029 1030 ret = il_send_cmd_sync(il, &cmd); 1031 if (ret) 1032 clear_bit(S_SCAN_HW, &il->status); 1033 1034 return ret; 1035} 1036 1037int 1038il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 1039 bool add) 1040{ 1041 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 1042 1043 if (add) 1044 return il4965_add_bssid_station(il, vif->bss_conf.bssid, 1045 &vif_priv->ibss_bssid_sta_id); 1046 return il_remove_station(il, vif_priv->ibss_bssid_sta_id, 1047 vif->bss_conf.bssid); 1048} 1049 1050void 1051il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed) 1052{ 1053 lockdep_assert_held(&il->sta_lock); 1054 1055 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed) 1056 il->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1057 else { 1058 D_TX("free more than tfds_in_queue (%u:%d)\n", 1059 il->stations[sta_id].tid[tid].tfds_in_queue, freed); 1060 il->stations[sta_id].tid[tid].tfds_in_queue = 0; 1061 } 1062} 1063 1064#define IL_TX_QUEUE_MSK 0xfffff 1065 1066static bool 1067il4965_is_single_rx_stream(struct il_priv *il) 1068{ 1069 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC || 1070 il->current_ht_config.single_chain_sufficient; 1071} 1072 1073#define IL_NUM_RX_CHAINS_MULTIPLE 3 1074#define IL_NUM_RX_CHAINS_SINGLE 2 1075#define IL_NUM_IDLE_CHAINS_DUAL 2 1076#define IL_NUM_IDLE_CHAINS_SINGLE 1 1077 1078/* 1079 * Determine how many receiver/antenna chains to use. 1080 * 1081 * More provides better reception via diversity. Fewer saves power 1082 * at the expense of throughput, but only when not in powersave to 1083 * start with. 1084 * 1085 * MIMO (dual stream) requires at least 2, but works better with 3. 1086 * This does not determine *which* chains to use, just how many. 1087 */ 1088static int 1089il4965_get_active_rx_chain_count(struct il_priv *il) 1090{ 1091 /* # of Rx chains to use when expecting MIMO. */ 1092 if (il4965_is_single_rx_stream(il)) 1093 return IL_NUM_RX_CHAINS_SINGLE; 1094 else 1095 return IL_NUM_RX_CHAINS_MULTIPLE; 1096} 1097 1098/* 1099 * When we are in power saving mode, unless device support spatial 1100 * multiplexing power save, use the active count for rx chain count. 1101 */ 1102static int 1103il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt) 1104{ 1105 /* # Rx chains when idling, depending on SMPS mode */ 1106 switch (il->current_ht_config.smps) { 1107 case IEEE80211_SMPS_STATIC: 1108 case IEEE80211_SMPS_DYNAMIC: 1109 return IL_NUM_IDLE_CHAINS_SINGLE; 1110 case IEEE80211_SMPS_OFF: 1111 return active_cnt; 1112 default: 1113 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps); 1114 return active_cnt; 1115 } 1116} 1117 1118/* up to 4 chains */ 1119static u8 1120il4965_count_chain_bitmap(u32 chain_bitmap) 1121{ 1122 u8 res; 1123 res = (chain_bitmap & BIT(0)) >> 0; 1124 res += (chain_bitmap & BIT(1)) >> 1; 1125 res += (chain_bitmap & BIT(2)) >> 2; 1126 res += (chain_bitmap & BIT(3)) >> 3; 1127 return res; 1128} 1129 1130/* 1131 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image 1132 * 1133 * Selects how many and which Rx receivers/antennas/chains to use. 1134 * This should not be used for scan command ... it puts data in wrong place. 1135 */ 1136void 1137il4965_set_rxon_chain(struct il_priv *il) 1138{ 1139 bool is_single = il4965_is_single_rx_stream(il); 1140 bool is_cam = !test_bit(S_POWER_PMI, &il->status); 1141 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; 1142 u32 active_chains; 1143 u16 rx_chain; 1144 1145 /* Tell uCode which antennas are actually connected. 1146 * Before first association, we assume all antennas are connected. 1147 * Just after first association, il4965_chain_noise_calibration() 1148 * checks which antennas actually *are* connected. */ 1149 if (il->chain_noise_data.active_chains) 1150 active_chains = il->chain_noise_data.active_chains; 1151 else 1152 active_chains = il->hw_params.valid_rx_ant; 1153 1154 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; 1155 1156 /* How many receivers should we use? */ 1157 active_rx_cnt = il4965_get_active_rx_chain_count(il); 1158 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt); 1159 1160 /* correct rx chain count according hw settings 1161 * and chain noise calibration 1162 */ 1163 valid_rx_cnt = il4965_count_chain_bitmap(active_chains); 1164 if (valid_rx_cnt < active_rx_cnt) 1165 active_rx_cnt = valid_rx_cnt; 1166 1167 if (valid_rx_cnt < idle_rx_cnt) 1168 idle_rx_cnt = valid_rx_cnt; 1169 1170 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; 1171 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; 1172 1173 il->staging.rx_chain = cpu_to_le16(rx_chain); 1174 1175 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam) 1176 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; 1177 else 1178 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; 1179 1180 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain, 1181 active_rx_cnt, idle_rx_cnt); 1182 1183 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || 1184 active_rx_cnt < idle_rx_cnt); 1185} 1186 1187static const char * 1188il4965_get_fh_string(int cmd) 1189{ 1190 switch (cmd) { 1191 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG); 1192 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG); 1193 IL_CMD(FH49_RSCSR_CHNL0_WPTR); 1194 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG); 1195 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG); 1196 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG); 1197 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); 1198 IL_CMD(FH49_TSSR_TX_STATUS_REG); 1199 IL_CMD(FH49_TSSR_TX_ERROR_REG); 1200 default: 1201 return "UNKNOWN"; 1202 } 1203} 1204 1205int 1206il4965_dump_fh(struct il_priv *il, char **buf, bool display) 1207{ 1208 int i; 1209#ifdef CONFIG_IWLEGACY_DEBUG 1210 int pos = 0; 1211 size_t bufsz = 0; 1212#endif 1213 static const u32 fh_tbl[] = { 1214 FH49_RSCSR_CHNL0_STTS_WPTR_REG, 1215 FH49_RSCSR_CHNL0_RBDCB_BASE_REG, 1216 FH49_RSCSR_CHNL0_WPTR, 1217 FH49_MEM_RCSR_CHNL0_CONFIG_REG, 1218 FH49_MEM_RSSR_SHARED_CTRL_REG, 1219 FH49_MEM_RSSR_RX_STATUS_REG, 1220 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, 1221 FH49_TSSR_TX_STATUS_REG, 1222 FH49_TSSR_TX_ERROR_REG 1223 }; 1224#ifdef CONFIG_IWLEGACY_DEBUG 1225 if (display) { 1226 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; 1227 *buf = kmalloc(bufsz, GFP_KERNEL); 1228 if (!*buf) 1229 return -ENOMEM; 1230 pos += 1231 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n"); 1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1233 pos += 1234 scnprintf(*buf + pos, bufsz - pos, 1235 " %34s: 0X%08x\n", 1236 il4965_get_fh_string(fh_tbl[i]), 1237 il_rd(il, fh_tbl[i])); 1238 } 1239 return pos; 1240 } 1241#endif 1242 IL_ERR("FH register values:\n"); 1243 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1244 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]), 1245 il_rd(il, fh_tbl[i])); 1246 } 1247 return 0; 1248} 1249 1250static void 1251il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb) 1252{ 1253 struct il_rx_pkt *pkt = rxb_addr(rxb); 1254 struct il_missed_beacon_notif *missed_beacon; 1255 1256 missed_beacon = &pkt->u.missed_beacon; 1257 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) > 1258 il->missed_beacon_threshold) { 1259 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", 1260 le32_to_cpu(missed_beacon->consecutive_missed_beacons), 1261 le32_to_cpu(missed_beacon->total_missed_becons), 1262 le32_to_cpu(missed_beacon->num_recvd_beacons), 1263 le32_to_cpu(missed_beacon->num_expected_beacons)); 1264 if (!test_bit(S_SCANNING, &il->status)) 1265 il4965_init_sensitivity(il); 1266 } 1267} 1268 1269/* Calculate noise level, based on measurements during network silence just 1270 * before arriving beacon. This measurement can be done only if we know 1271 * exactly when to expect beacons, therefore only when we're associated. */ 1272static void 1273il4965_rx_calc_noise(struct il_priv *il) 1274{ 1275 struct stats_rx_non_phy *rx_info; 1276 int num_active_rx = 0; 1277 int total_silence = 0; 1278 int bcn_silence_a, bcn_silence_b, bcn_silence_c; 1279 int last_rx_noise; 1280 1281 rx_info = &(il->_4965.stats.rx.general); 1282 bcn_silence_a = 1283 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; 1284 bcn_silence_b = 1285 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; 1286 bcn_silence_c = 1287 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; 1288 1289 if (bcn_silence_a) { 1290 total_silence += bcn_silence_a; 1291 num_active_rx++; 1292 } 1293 if (bcn_silence_b) { 1294 total_silence += bcn_silence_b; 1295 num_active_rx++; 1296 } 1297 if (bcn_silence_c) { 1298 total_silence += bcn_silence_c; 1299 num_active_rx++; 1300 } 1301 1302 /* Average among active antennas */ 1303 if (num_active_rx) 1304 last_rx_noise = (total_silence / num_active_rx) - 107; 1305 else 1306 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE; 1307 1308 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a, 1309 bcn_silence_b, bcn_silence_c, last_rx_noise); 1310} 1311 1312#ifdef CONFIG_IWLEGACY_DEBUGFS 1313/* 1314 * based on the assumption of all stats counter are in DWORD 1315 * FIXME: This function is for debugging, do not deal with 1316 * the case of counters roll-over. 1317 */ 1318static void 1319il4965_accumulative_stats(struct il_priv *il, __le32 * stats) 1320{ 1321 int i, size; 1322 __le32 *prev_stats; 1323 u32 *accum_stats; 1324 u32 *delta, *max_delta; 1325 struct stats_general_common *general, *accum_general; 1326 1327 prev_stats = (__le32 *) &il->_4965.stats; 1328 accum_stats = (u32 *) &il->_4965.accum_stats; 1329 size = sizeof(struct il_notif_stats); 1330 general = &il->_4965.stats.general.common; 1331 accum_general = &il->_4965.accum_stats.general.common; 1332 delta = (u32 *) &il->_4965.delta_stats; 1333 max_delta = (u32 *) &il->_4965.max_delta; 1334 1335 for (i = sizeof(__le32); i < size; 1336 i += 1337 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++, 1338 accum_stats++) { 1339 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { 1340 *delta = 1341 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats)); 1342 *accum_stats += *delta; 1343 if (*delta > *max_delta) 1344 *max_delta = *delta; 1345 } 1346 } 1347 1348 /* reset accumulative stats for "no-counter" type stats */ 1349 accum_general->temperature = general->temperature; 1350 accum_general->ttl_timestamp = general->ttl_timestamp; 1351} 1352#endif 1353 1354static void 1355il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb) 1356{ 1357 const int recalib_seconds = 60; 1358 bool change; 1359 struct il_rx_pkt *pkt = rxb_addr(rxb); 1360 1361 D_RX("Statistics notification received (%d vs %d).\n", 1362 (int)sizeof(struct il_notif_stats), 1363 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK); 1364 1365 change = 1366 ((il->_4965.stats.general.common.temperature != 1367 pkt->u.stats.general.common.temperature) || 1368 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) != 1369 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK))); 1370#ifdef CONFIG_IWLEGACY_DEBUGFS 1371 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats); 1372#endif 1373 1374 /* TODO: reading some of stats is unneeded */ 1375 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats)); 1376 1377 set_bit(S_STATS, &il->status); 1378 1379 /* 1380 * Reschedule the stats timer to occur in recalib_seconds to ensure 1381 * we get a thermal update even if the uCode doesn't give us one 1382 */ 1383 mod_timer(&il->stats_periodic, 1384 jiffies + msecs_to_jiffies(recalib_seconds * 1000)); 1385 1386 if (unlikely(!test_bit(S_SCANNING, &il->status)) && 1387 (pkt->hdr.cmd == N_STATS)) { 1388 il4965_rx_calc_noise(il); 1389 queue_work(il->workqueue, &il->run_time_calib_work); 1390 } 1391 1392 if (change) 1393 il4965_temperature_calib(il); 1394} 1395 1396static void 1397il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb) 1398{ 1399 struct il_rx_pkt *pkt = rxb_addr(rxb); 1400 1401 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) { 1402#ifdef CONFIG_IWLEGACY_DEBUGFS 1403 memset(&il->_4965.accum_stats, 0, 1404 sizeof(struct il_notif_stats)); 1405 memset(&il->_4965.delta_stats, 0, 1406 sizeof(struct il_notif_stats)); 1407 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats)); 1408#endif 1409 D_RX("Statistics have been cleared\n"); 1410 } 1411 il4965_hdl_stats(il, rxb); 1412} 1413 1414 1415/* 1416 * mac80211 queues, ACs, hardware queues, FIFOs. 1417 * 1418 * Cf. https://wireless.wiki.kernel.org/en/developers/Documentation/mac80211/queues 1419 * 1420 * Mac80211 uses the following numbers, which we get as from it 1421 * by way of skb_get_queue_mapping(skb): 1422 * 1423 * VO 0 1424 * VI 1 1425 * BE 2 1426 * BK 3 1427 * 1428 * 1429 * Regular (not A-MPDU) frames are put into hardware queues corresponding 1430 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their 1431 * own queue per aggregation session (RA/TID combination), such queues are 1432 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In 1433 * order to map frames to the right queue, we also need an AC->hw queue 1434 * mapping. This is implemented here. 1435 * 1436 * Due to the way hw queues are set up (by the hw specific modules like 1437 * 4965.c), the AC->hw queue mapping is the identity 1438 * mapping. 1439 */ 1440 1441static const u8 tid_to_ac[] = { 1442 IEEE80211_AC_BE, 1443 IEEE80211_AC_BK, 1444 IEEE80211_AC_BK, 1445 IEEE80211_AC_BE, 1446 IEEE80211_AC_VI, 1447 IEEE80211_AC_VI, 1448 IEEE80211_AC_VO, 1449 IEEE80211_AC_VO 1450}; 1451 1452static inline int 1453il4965_get_ac_from_tid(u16 tid) 1454{ 1455 if (likely(tid < ARRAY_SIZE(tid_to_ac))) 1456 return tid_to_ac[tid]; 1457 1458 /* no support for TIDs 8-15 yet */ 1459 return -EINVAL; 1460} 1461 1462static inline int 1463il4965_get_fifo_from_tid(u16 tid) 1464{ 1465 static const u8 ac_to_fifo[] = { 1466 IL_TX_FIFO_VO, 1467 IL_TX_FIFO_VI, 1468 IL_TX_FIFO_BE, 1469 IL_TX_FIFO_BK, 1470 }; 1471 1472 if (likely(tid < ARRAY_SIZE(tid_to_ac))) 1473 return ac_to_fifo[tid_to_ac[tid]]; 1474 1475 /* no support for TIDs 8-15 yet */ 1476 return -EINVAL; 1477} 1478 1479/* 1480 * handle build C_TX command notification. 1481 */ 1482static void 1483il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb, 1484 struct il_tx_cmd *tx_cmd, 1485 struct ieee80211_tx_info *info, 1486 struct ieee80211_hdr *hdr, u8 std_id) 1487{ 1488 __le16 fc = hdr->frame_control; 1489 __le32 tx_flags = tx_cmd->tx_flags; 1490 1491 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 1492 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 1493 tx_flags |= TX_CMD_FLG_ACK_MSK; 1494 if (ieee80211_is_mgmt(fc)) 1495 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1496 if (ieee80211_is_probe_resp(fc) && 1497 !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) 1498 tx_flags |= TX_CMD_FLG_TSF_MSK; 1499 } else { 1500 tx_flags &= (~TX_CMD_FLG_ACK_MSK); 1501 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1502 } 1503 1504 if (ieee80211_is_back_req(fc)) 1505 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; 1506 1507 tx_cmd->sta_id = std_id; 1508 if (ieee80211_has_morefrags(fc)) 1509 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; 1510 1511 if (ieee80211_is_data_qos(fc)) { 1512 u8 *qc = ieee80211_get_qos_ctl(hdr); 1513 tx_cmd->tid_tspec = qc[0] & 0xf; 1514 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; 1515 } else { 1516 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1517 } 1518 1519 il_tx_cmd_protection(il, info, fc, &tx_flags); 1520 1521 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); 1522 if (ieee80211_is_mgmt(fc)) { 1523 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) 1524 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); 1525 else 1526 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); 1527 } else { 1528 tx_cmd->timeout.pm_frame_timeout = 0; 1529 } 1530 1531 tx_cmd->driver_txop = 0; 1532 tx_cmd->tx_flags = tx_flags; 1533 tx_cmd->next_frame_len = 0; 1534} 1535 1536static void 1537il4965_tx_cmd_build_rate(struct il_priv *il, 1538 struct il_tx_cmd *tx_cmd, 1539 struct ieee80211_tx_info *info, 1540 struct ieee80211_sta *sta, 1541 __le16 fc) 1542{ 1543 const u8 rts_retry_limit = 60; 1544 u32 rate_flags; 1545 int rate_idx; 1546 u8 data_retry_limit; 1547 u8 rate_plcp; 1548 1549 /* Set retry limit on DATA packets and Probe Responses */ 1550 if (ieee80211_is_probe_resp(fc)) 1551 data_retry_limit = 3; 1552 else 1553 data_retry_limit = IL4965_DEFAULT_TX_RETRY; 1554 tx_cmd->data_retry_limit = data_retry_limit; 1555 /* Set retry limit on RTS packets */ 1556 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit); 1557 1558 /* DATA packets will use the uCode station table for rate/antenna 1559 * selection */ 1560 if (ieee80211_is_data(fc)) { 1561 tx_cmd->initial_rate_idx = 0; 1562 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; 1563 return; 1564 } 1565 1566 /** 1567 * If the current TX rate stored in mac80211 has the MCS bit set, it's 1568 * not really a TX rate. Thus, we use the lowest supported rate for 1569 * this band. Also use the lowest supported rate if the stored rate 1570 * idx is invalid. 1571 */ 1572 rate_idx = info->control.rates[0].idx; 1573 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0 1574 || rate_idx > RATE_COUNT_LEGACY) 1575 rate_idx = rate_lowest_index(&il->bands[info->band], sta); 1576 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ 1577 if (info->band == NL80211_BAND_5GHZ) 1578 rate_idx += IL_FIRST_OFDM_RATE; 1579 /* Get PLCP rate for tx_cmd->rate_n_flags */ 1580 rate_plcp = il_rates[rate_idx].plcp; 1581 /* Zero out flags for this packet */ 1582 rate_flags = 0; 1583 1584 /* Set CCK flag as needed */ 1585 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE) 1586 rate_flags |= RATE_MCS_CCK_MSK; 1587 1588 /* Set up antennas */ 1589 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); 1590 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; 1591 1592 /* Set the rate in the TX cmd */ 1593 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags); 1594} 1595 1596static void 1597il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info, 1598 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag, 1599 int sta_id) 1600{ 1601 struct ieee80211_key_conf *keyconf = info->control.hw_key; 1602 1603 switch (keyconf->cipher) { 1604 case WLAN_CIPHER_SUITE_CCMP: 1605 tx_cmd->sec_ctl = TX_CMD_SEC_CCM; 1606 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); 1607 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1608 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; 1609 D_TX("tx_cmd with AES hwcrypto\n"); 1610 break; 1611 1612 case WLAN_CIPHER_SUITE_TKIP: 1613 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; 1614 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key); 1615 D_TX("tx_cmd with tkip hwcrypto\n"); 1616 break; 1617 1618 case WLAN_CIPHER_SUITE_WEP104: 1619 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; 1620 fallthrough; 1621 case WLAN_CIPHER_SUITE_WEP40: 1622 tx_cmd->sec_ctl |= 1623 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) << 1624 TX_CMD_SEC_SHIFT); 1625 1626 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); 1627 1628 D_TX("Configuring packet for WEP encryption " "with key %d\n", 1629 keyconf->keyidx); 1630 break; 1631 1632 default: 1633 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher); 1634 break; 1635 } 1636} 1637 1638/* 1639 * start C_TX command process 1640 */ 1641int 1642il4965_tx_skb(struct il_priv *il, 1643 struct ieee80211_sta *sta, 1644 struct sk_buff *skb) 1645{ 1646 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1647 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1648 struct il_station_priv *sta_priv = NULL; 1649 struct il_tx_queue *txq; 1650 struct il_queue *q; 1651 struct il_device_cmd *out_cmd; 1652 struct il_cmd_meta *out_meta; 1653 struct il_tx_cmd *tx_cmd; 1654 int txq_id; 1655 dma_addr_t phys_addr; 1656 dma_addr_t txcmd_phys; 1657 dma_addr_t scratch_phys; 1658 u16 len, firstlen, secondlen; 1659 u16 seq_number = 0; 1660 __le16 fc; 1661 u8 hdr_len; 1662 u8 sta_id; 1663 u8 wait_write_ptr = 0; 1664 u8 tid = 0; 1665 u8 *qc = NULL; 1666 unsigned long flags; 1667 bool is_agg = false; 1668 1669 spin_lock_irqsave(&il->lock, flags); 1670 if (il_is_rfkill(il)) { 1671 D_DROP("Dropping - RF KILL\n"); 1672 goto drop_unlock; 1673 } 1674 1675 fc = hdr->frame_control; 1676 1677#ifdef CONFIG_IWLEGACY_DEBUG 1678 if (ieee80211_is_auth(fc)) 1679 D_TX("Sending AUTH frame\n"); 1680 else if (ieee80211_is_assoc_req(fc)) 1681 D_TX("Sending ASSOC frame\n"); 1682 else if (ieee80211_is_reassoc_req(fc)) 1683 D_TX("Sending REASSOC frame\n"); 1684#endif 1685 1686 hdr_len = ieee80211_hdrlen(fc); 1687 1688 /* For management frames use broadcast id to do not break aggregation */ 1689 if (!ieee80211_is_data(fc)) 1690 sta_id = il->hw_params.bcast_id; 1691 else { 1692 /* Find idx into station table for destination station */ 1693 sta_id = il_sta_id_or_broadcast(il, sta); 1694 1695 if (sta_id == IL_INVALID_STATION) { 1696 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1); 1697 goto drop_unlock; 1698 } 1699 } 1700 1701 D_TX("station Id %d\n", sta_id); 1702 1703 if (sta) 1704 sta_priv = (void *)sta->drv_priv; 1705 1706 if (sta_priv && sta_priv->asleep && 1707 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) { 1708 /* 1709 * This sends an asynchronous command to the device, 1710 * but we can rely on it being processed before the 1711 * next frame is processed -- and the next frame to 1712 * this station is the one that will consume this 1713 * counter. 1714 * For now set the counter to just 1 since we do not 1715 * support uAPSD yet. 1716 */ 1717 il4965_sta_modify_sleep_tx_count(il, sta_id, 1); 1718 } 1719 1720 /* FIXME: remove me ? */ 1721 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM); 1722 1723 /* Access category (AC) is also the queue number */ 1724 txq_id = skb_get_queue_mapping(skb); 1725 1726 /* irqs already disabled/saved above when locking il->lock */ 1727 spin_lock(&il->sta_lock); 1728 1729 if (ieee80211_is_data_qos(fc)) { 1730 qc = ieee80211_get_qos_ctl(hdr); 1731 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 1732 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) { 1733 spin_unlock(&il->sta_lock); 1734 goto drop_unlock; 1735 } 1736 seq_number = il->stations[sta_id].tid[tid].seq_number; 1737 seq_number &= IEEE80211_SCTL_SEQ; 1738 hdr->seq_ctrl = 1739 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG); 1740 hdr->seq_ctrl |= cpu_to_le16(seq_number); 1741 seq_number += 0x10; 1742 /* aggregation is on for this <sta,tid> */ 1743 if (info->flags & IEEE80211_TX_CTL_AMPDU && 1744 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) { 1745 txq_id = il->stations[sta_id].tid[tid].agg.txq_id; 1746 is_agg = true; 1747 } 1748 } 1749 1750 txq = &il->txq[txq_id]; 1751 q = &txq->q; 1752 1753 if (unlikely(il_queue_space(q) < q->high_mark)) { 1754 spin_unlock(&il->sta_lock); 1755 goto drop_unlock; 1756 } 1757 1758 if (ieee80211_is_data_qos(fc)) { 1759 il->stations[sta_id].tid[tid].tfds_in_queue++; 1760 if (!ieee80211_has_morefrags(fc)) 1761 il->stations[sta_id].tid[tid].seq_number = seq_number; 1762 } 1763 1764 spin_unlock(&il->sta_lock); 1765 1766 txq->skbs[q->write_ptr] = skb; 1767 1768 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 1769 out_cmd = txq->cmd[q->write_ptr]; 1770 out_meta = &txq->meta[q->write_ptr]; 1771 tx_cmd = &out_cmd->cmd.tx; 1772 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); 1773 memset(tx_cmd, 0, sizeof(struct il_tx_cmd)); 1774 1775 /* 1776 * Set up the Tx-command (not MAC!) header. 1777 * Store the chosen Tx queue and TFD idx within the sequence field; 1778 * after Tx, uCode's Tx response will return this value so driver can 1779 * locate the frame within the tx queue and do post-tx processing. 1780 */ 1781 out_cmd->hdr.cmd = C_TX; 1782 out_cmd->hdr.sequence = 1783 cpu_to_le16((u16) 1784 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr))); 1785 1786 /* Copy MAC header from skb into command buffer */ 1787 memcpy(tx_cmd->hdr, hdr, hdr_len); 1788 1789 /* Total # bytes to be transmitted */ 1790 tx_cmd->len = cpu_to_le16((u16) skb->len); 1791 1792 if (info->control.hw_key) 1793 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id); 1794 1795 /* TODO need this for burst mode later on */ 1796 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id); 1797 1798 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc); 1799 1800 /* 1801 * Use the first empty entry in this queue's command buffer array 1802 * to contain the Tx command and MAC header concatenated together 1803 * (payload data will be in another buffer). 1804 * Size of this varies, due to varying MAC header length. 1805 * If end is not dword aligned, we'll have 2 extra bytes at the end 1806 * of the MAC header (device reads on dword boundaries). 1807 * We'll tell device about this padding later. 1808 */ 1809 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len; 1810 firstlen = (len + 3) & ~3; 1811 1812 /* Tell NIC about any 2-byte padding after MAC header */ 1813 if (firstlen != len) 1814 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 1815 1816 /* Physical address of this Tx command's header (not MAC header!), 1817 * within command buffer array. */ 1818 txcmd_phys = 1819 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen, 1820 PCI_DMA_BIDIRECTIONAL); 1821 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys))) 1822 goto drop_unlock; 1823 1824 /* Set up TFD's 2nd entry to point directly to remainder of skb, 1825 * if any (802.11 null frames have no payload). */ 1826 secondlen = skb->len - hdr_len; 1827 if (secondlen > 0) { 1828 phys_addr = 1829 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen, 1830 PCI_DMA_TODEVICE); 1831 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr))) 1832 goto drop_unlock; 1833 } 1834 1835 /* Add buffer containing Tx command and MAC(!) header to TFD's 1836 * first entry */ 1837 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0); 1838 dma_unmap_addr_set(out_meta, mapping, txcmd_phys); 1839 dma_unmap_len_set(out_meta, len, firstlen); 1840 if (secondlen) 1841 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 1842 0, 0); 1843 1844 if (!ieee80211_has_morefrags(hdr->frame_control)) { 1845 txq->need_update = 1; 1846 } else { 1847 wait_write_ptr = 1; 1848 txq->need_update = 0; 1849 } 1850 1851 scratch_phys = 1852 txcmd_phys + sizeof(struct il_cmd_header) + 1853 offsetof(struct il_tx_cmd, scratch); 1854 1855 /* take back ownership of DMA buffer to enable update */ 1856 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen, 1857 PCI_DMA_BIDIRECTIONAL); 1858 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 1859 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys); 1860 1861 il_update_stats(il, true, fc, skb->len); 1862 1863 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence)); 1864 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); 1865 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd)); 1866 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len); 1867 1868 /* Set up entry for this TFD in Tx byte-count array */ 1869 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1870 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len)); 1871 1872 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen, 1873 PCI_DMA_BIDIRECTIONAL); 1874 1875 /* Tell device the write idx *just past* this latest filled TFD */ 1876 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); 1877 il_txq_update_write_ptr(il, txq); 1878 spin_unlock_irqrestore(&il->lock, flags); 1879 1880 /* 1881 * At this point the frame is "transmitted" successfully 1882 * and we will get a TX status notification eventually, 1883 * regardless of the value of ret. "ret" only indicates 1884 * whether or not we should update the write pointer. 1885 */ 1886 1887 /* 1888 * Avoid atomic ops if it isn't an associated client. 1889 * Also, if this is a packet for aggregation, don't 1890 * increase the counter because the ucode will stop 1891 * aggregation queues when their respective station 1892 * goes to sleep. 1893 */ 1894 if (sta_priv && sta_priv->client && !is_agg) 1895 atomic_inc(&sta_priv->pending_frames); 1896 1897 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) { 1898 if (wait_write_ptr) { 1899 spin_lock_irqsave(&il->lock, flags); 1900 txq->need_update = 1; 1901 il_txq_update_write_ptr(il, txq); 1902 spin_unlock_irqrestore(&il->lock, flags); 1903 } else { 1904 il_stop_queue(il, txq); 1905 } 1906 } 1907 1908 return 0; 1909 1910drop_unlock: 1911 spin_unlock_irqrestore(&il->lock, flags); 1912 return -1; 1913} 1914 1915static inline int 1916il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size) 1917{ 1918 ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, 1919 GFP_KERNEL); 1920 if (!ptr->addr) 1921 return -ENOMEM; 1922 ptr->size = size; 1923 return 0; 1924} 1925 1926static inline void 1927il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr) 1928{ 1929 if (unlikely(!ptr->addr)) 1930 return; 1931 1932 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); 1933 memset(ptr, 0, sizeof(*ptr)); 1934} 1935 1936/* 1937 * il4965_hw_txq_ctx_free - Free TXQ Context 1938 * 1939 * Destroy all TX DMA queues and structures 1940 */ 1941void 1942il4965_hw_txq_ctx_free(struct il_priv *il) 1943{ 1944 int txq_id; 1945 1946 /* Tx queues */ 1947 if (il->txq) { 1948 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 1949 if (txq_id == il->cmd_queue) 1950 il_cmd_queue_free(il); 1951 else 1952 il_tx_queue_free(il, txq_id); 1953 } 1954 il4965_free_dma_ptr(il, &il->kw); 1955 1956 il4965_free_dma_ptr(il, &il->scd_bc_tbls); 1957 1958 /* free tx queue structure */ 1959 il_free_txq_mem(il); 1960} 1961 1962/* 1963 * il4965_txq_ctx_alloc - allocate TX queue context 1964 * Allocate all Tx DMA structures and initialize them 1965 */ 1966int 1967il4965_txq_ctx_alloc(struct il_priv *il) 1968{ 1969 int ret, txq_id; 1970 unsigned long flags; 1971 1972 /* Free all tx/cmd queues and keep-warm buffer */ 1973 il4965_hw_txq_ctx_free(il); 1974 1975 ret = 1976 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls, 1977 il->hw_params.scd_bc_tbls_size); 1978 if (ret) { 1979 IL_ERR("Scheduler BC Table allocation failed\n"); 1980 goto error_bc_tbls; 1981 } 1982 /* Alloc keep-warm buffer */ 1983 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE); 1984 if (ret) { 1985 IL_ERR("Keep Warm allocation failed\n"); 1986 goto error_kw; 1987 } 1988 1989 /* allocate tx queue structure */ 1990 ret = il_alloc_txq_mem(il); 1991 if (ret) 1992 goto error; 1993 1994 spin_lock_irqsave(&il->lock, flags); 1995 1996 /* Turn off all Tx DMA fifos */ 1997 il4965_txq_set_sched(il, 0); 1998 1999 /* Tell NIC where to find the "keep warm" buffer */ 2000 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); 2001 2002 spin_unlock_irqrestore(&il->lock, flags); 2003 2004 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 2005 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 2006 ret = il_tx_queue_init(il, txq_id); 2007 if (ret) { 2008 IL_ERR("Tx %d queue init failed\n", txq_id); 2009 goto error; 2010 } 2011 } 2012 2013 return ret; 2014 2015error: 2016 il4965_hw_txq_ctx_free(il); 2017 il4965_free_dma_ptr(il, &il->kw); 2018error_kw: 2019 il4965_free_dma_ptr(il, &il->scd_bc_tbls); 2020error_bc_tbls: 2021 return ret; 2022} 2023 2024void 2025il4965_txq_ctx_reset(struct il_priv *il) 2026{ 2027 int txq_id; 2028 unsigned long flags; 2029 2030 spin_lock_irqsave(&il->lock, flags); 2031 2032 /* Turn off all Tx DMA fifos */ 2033 il4965_txq_set_sched(il, 0); 2034 /* Tell NIC where to find the "keep warm" buffer */ 2035 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); 2036 2037 spin_unlock_irqrestore(&il->lock, flags); 2038 2039 /* Alloc and init all Tx queues, including the command queue (#4) */ 2040 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2041 il_tx_queue_reset(il, txq_id); 2042} 2043 2044static void 2045il4965_txq_ctx_unmap(struct il_priv *il) 2046{ 2047 int txq_id; 2048 2049 if (!il->txq) 2050 return; 2051 2052 /* Unmap DMA from host system and free skb's */ 2053 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2054 if (txq_id == il->cmd_queue) 2055 il_cmd_queue_unmap(il); 2056 else 2057 il_tx_queue_unmap(il, txq_id); 2058} 2059 2060/* 2061 * il4965_txq_ctx_stop - Stop all Tx DMA channels 2062 */ 2063void 2064il4965_txq_ctx_stop(struct il_priv *il) 2065{ 2066 int ch, ret; 2067 2068 _il_wr_prph(il, IL49_SCD_TXFACT, 0); 2069 2070 /* Stop each Tx DMA channel, and wait for it to be idle */ 2071 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { 2072 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 2073 ret = 2074 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG, 2075 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 2076 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 2077 1000); 2078 if (ret < 0) 2079 IL_ERR("Timeout stopping DMA channel %d [0x%08x]", 2080 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG)); 2081 } 2082} 2083 2084/* 2085 * Find first available (lowest unused) Tx Queue, mark it "active". 2086 * Called only when finding queue for aggregation. 2087 * Should never return anything < 7, because they should already 2088 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) 2089 */ 2090static int 2091il4965_txq_ctx_activate_free(struct il_priv *il) 2092{ 2093 int txq_id; 2094 2095 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2096 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk)) 2097 return txq_id; 2098 return -1; 2099} 2100 2101/* 2102 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration 2103 */ 2104static void 2105il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id) 2106{ 2107 /* Simply stop the queue, but don't change any configuration; 2108 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 2109 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), 2110 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 2111 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 2112} 2113 2114/* 2115 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue 2116 */ 2117static int 2118il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id) 2119{ 2120 u32 tbl_dw_addr; 2121 u32 tbl_dw; 2122 u16 scd_q2ratid; 2123 2124 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 2125 2126 tbl_dw_addr = 2127 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 2128 2129 tbl_dw = il_read_targ_mem(il, tbl_dw_addr); 2130 2131 if (txq_id & 0x1) 2132 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 2133 else 2134 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 2135 2136 il_write_targ_mem(il, tbl_dw_addr, tbl_dw); 2137 2138 return 0; 2139} 2140 2141/* 2142 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue 2143 * 2144 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE, 2145 * i.e. it must be one of the higher queues used for aggregation 2146 */ 2147static int 2148il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id, 2149 int tid, u16 ssn_idx) 2150{ 2151 unsigned long flags; 2152 u16 ra_tid; 2153 int ret; 2154 2155 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || 2156 (IL49_FIRST_AMPDU_QUEUE + 2157 il->cfg->num_of_ampdu_queues <= txq_id)) { 2158 IL_WARN("queue number out of range: %d, must be %d to %d\n", 2159 txq_id, IL49_FIRST_AMPDU_QUEUE, 2160 IL49_FIRST_AMPDU_QUEUE + 2161 il->cfg->num_of_ampdu_queues - 1); 2162 return -EINVAL; 2163 } 2164 2165 ra_tid = BUILD_RAxTID(sta_id, tid); 2166 2167 /* Modify device's station table to Tx this TID */ 2168 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid); 2169 if (ret) 2170 return ret; 2171 2172 spin_lock_irqsave(&il->lock, flags); 2173 2174 /* Stop this Tx queue before configuring it */ 2175 il4965_tx_queue_stop_scheduler(il, txq_id); 2176 2177 /* Map receiver-address / traffic-ID to this queue */ 2178 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id); 2179 2180 /* Set this queue as a chain-building queue */ 2181 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 2182 2183 /* Place first TFD at idx corresponding to start sequence number. 2184 * Assumes that ssn_idx is valid (!= 0xFFF) */ 2185 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 2186 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 2187 il4965_set_wr_ptrs(il, txq_id, ssn_idx); 2188 2189 /* Set up Tx win size and frame limit for this queue */ 2190 il_write_targ_mem(il, 2191 il->scd_base_addr + 2192 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id), 2193 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) 2194 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 2195 2196 il_write_targ_mem(il, 2197 il->scd_base_addr + 2198 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 2199 (SCD_FRAME_LIMIT << 2200 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 2201 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 2202 2203 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2204 2205 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 2206 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1); 2207 2208 spin_unlock_irqrestore(&il->lock, flags); 2209 2210 return 0; 2211} 2212 2213int 2214il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, 2215 struct ieee80211_sta *sta, u16 tid, u16 * ssn) 2216{ 2217 int sta_id; 2218 int tx_fifo; 2219 int txq_id; 2220 int ret; 2221 unsigned long flags; 2222 struct il_tid_data *tid_data; 2223 2224 /* FIXME: warning if tx fifo not found ? */ 2225 tx_fifo = il4965_get_fifo_from_tid(tid); 2226 if (unlikely(tx_fifo < 0)) 2227 return tx_fifo; 2228 2229 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid); 2230 2231 sta_id = il_sta_id(sta); 2232 if (sta_id == IL_INVALID_STATION) { 2233 IL_ERR("Start AGG on invalid station\n"); 2234 return -ENXIO; 2235 } 2236 if (unlikely(tid >= MAX_TID_COUNT)) 2237 return -EINVAL; 2238 2239 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) { 2240 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n"); 2241 return -ENXIO; 2242 } 2243 2244 txq_id = il4965_txq_ctx_activate_free(il); 2245 if (txq_id == -1) { 2246 IL_ERR("No free aggregation queue available\n"); 2247 return -ENXIO; 2248 } 2249 2250 spin_lock_irqsave(&il->sta_lock, flags); 2251 tid_data = &il->stations[sta_id].tid[tid]; 2252 *ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number); 2253 tid_data->agg.txq_id = txq_id; 2254 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id); 2255 spin_unlock_irqrestore(&il->sta_lock, flags); 2256 2257 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn); 2258 if (ret) 2259 return ret; 2260 2261 spin_lock_irqsave(&il->sta_lock, flags); 2262 tid_data = &il->stations[sta_id].tid[tid]; 2263 if (tid_data->tfds_in_queue == 0) { 2264 D_HT("HW queue is empty\n"); 2265 tid_data->agg.state = IL_AGG_ON; 2266 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 2267 } else { 2268 D_HT("HW queue is NOT empty: %d packets in HW queue\n", 2269 tid_data->tfds_in_queue); 2270 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA; 2271 } 2272 spin_unlock_irqrestore(&il->sta_lock, flags); 2273 return ret; 2274} 2275 2276/* 2277 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE 2278 * il->lock must be held by the caller 2279 */ 2280static int 2281il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo) 2282{ 2283 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || 2284 (IL49_FIRST_AMPDU_QUEUE + 2285 il->cfg->num_of_ampdu_queues <= txq_id)) { 2286 IL_WARN("queue number out of range: %d, must be %d to %d\n", 2287 txq_id, IL49_FIRST_AMPDU_QUEUE, 2288 IL49_FIRST_AMPDU_QUEUE + 2289 il->cfg->num_of_ampdu_queues - 1); 2290 return -EINVAL; 2291 } 2292 2293 il4965_tx_queue_stop_scheduler(il, txq_id); 2294 2295 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 2296 2297 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 2298 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 2299 /* supposes that ssn_idx is valid (!= 0xFFF) */ 2300 il4965_set_wr_ptrs(il, txq_id, ssn_idx); 2301 2302 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2303 il_txq_ctx_deactivate(il, txq_id); 2304 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0); 2305 2306 return 0; 2307} 2308 2309int 2310il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, 2311 struct ieee80211_sta *sta, u16 tid) 2312{ 2313 int tx_fifo_id, txq_id, sta_id, ssn; 2314 struct il_tid_data *tid_data; 2315 int write_ptr, read_ptr; 2316 unsigned long flags; 2317 2318 /* FIXME: warning if tx_fifo_id not found ? */ 2319 tx_fifo_id = il4965_get_fifo_from_tid(tid); 2320 if (unlikely(tx_fifo_id < 0)) 2321 return tx_fifo_id; 2322 2323 sta_id = il_sta_id(sta); 2324 2325 if (sta_id == IL_INVALID_STATION) { 2326 IL_ERR("Invalid station for AGG tid %d\n", tid); 2327 return -ENXIO; 2328 } 2329 2330 spin_lock_irqsave(&il->sta_lock, flags); 2331 2332 tid_data = &il->stations[sta_id].tid[tid]; 2333 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; 2334 txq_id = tid_data->agg.txq_id; 2335 2336 switch (il->stations[sta_id].tid[tid].agg.state) { 2337 case IL_EMPTYING_HW_QUEUE_ADDBA: 2338 /* 2339 * This can happen if the peer stops aggregation 2340 * again before we've had a chance to drain the 2341 * queue we selected previously, i.e. before the 2342 * session was really started completely. 2343 */ 2344 D_HT("AGG stop before setup done\n"); 2345 goto turn_off; 2346 case IL_AGG_ON: 2347 break; 2348 default: 2349 IL_WARN("Stopping AGG while state not ON or starting\n"); 2350 } 2351 2352 write_ptr = il->txq[txq_id].q.write_ptr; 2353 read_ptr = il->txq[txq_id].q.read_ptr; 2354 2355 /* The queue is not empty */ 2356 if (write_ptr != read_ptr) { 2357 D_HT("Stopping a non empty AGG HW QUEUE\n"); 2358 il->stations[sta_id].tid[tid].agg.state = 2359 IL_EMPTYING_HW_QUEUE_DELBA; 2360 spin_unlock_irqrestore(&il->sta_lock, flags); 2361 return 0; 2362 } 2363 2364 D_HT("HW queue is empty\n"); 2365turn_off: 2366 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF; 2367 2368 /* do not restore/save irqs */ 2369 spin_unlock(&il->sta_lock); 2370 spin_lock(&il->lock); 2371 2372 /* 2373 * the only reason this call can fail is queue number out of range, 2374 * which can happen if uCode is reloaded and all the station 2375 * information are lost. if it is outside the range, there is no need 2376 * to deactivate the uCode queue, just return "success" to allow 2377 * mac80211 to clean up it own data. 2378 */ 2379 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id); 2380 spin_unlock_irqrestore(&il->lock, flags); 2381 2382 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2383 2384 return 0; 2385} 2386 2387int 2388il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id) 2389{ 2390 struct il_queue *q = &il->txq[txq_id].q; 2391 u8 *addr = il->stations[sta_id].sta.sta.addr; 2392 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid]; 2393 2394 lockdep_assert_held(&il->sta_lock); 2395 2396 switch (il->stations[sta_id].tid[tid].agg.state) { 2397 case IL_EMPTYING_HW_QUEUE_DELBA: 2398 /* We are reclaiming the last packet of the */ 2399 /* aggregated HW queue */ 2400 if (txq_id == tid_data->agg.txq_id && 2401 q->read_ptr == q->write_ptr) { 2402 u16 ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number); 2403 int tx_fifo = il4965_get_fifo_from_tid(tid); 2404 D_HT("HW queue empty: continue DELBA flow\n"); 2405 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo); 2406 tid_data->agg.state = IL_AGG_OFF; 2407 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid); 2408 } 2409 break; 2410 case IL_EMPTYING_HW_QUEUE_ADDBA: 2411 /* We are reclaiming the last packet of the queue */ 2412 if (tid_data->tfds_in_queue == 0) { 2413 D_HT("HW queue empty: continue ADDBA flow\n"); 2414 tid_data->agg.state = IL_AGG_ON; 2415 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid); 2416 } 2417 break; 2418 } 2419 2420 return 0; 2421} 2422 2423static void 2424il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1) 2425{ 2426 struct ieee80211_sta *sta; 2427 struct il_station_priv *sta_priv; 2428 2429 rcu_read_lock(); 2430 sta = ieee80211_find_sta(il->vif, addr1); 2431 if (sta) { 2432 sta_priv = (void *)sta->drv_priv; 2433 /* avoid atomic ops if this isn't a client */ 2434 if (sta_priv->client && 2435 atomic_dec_return(&sta_priv->pending_frames) == 0) 2436 ieee80211_sta_block_awake(il->hw, sta, false); 2437 } 2438 rcu_read_unlock(); 2439} 2440 2441static void 2442il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg) 2443{ 2444 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2445 2446 if (!is_agg) 2447 il4965_non_agg_tx_status(il, hdr->addr1); 2448 2449 ieee80211_tx_status_irqsafe(il->hw, skb); 2450} 2451 2452int 2453il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx) 2454{ 2455 struct il_tx_queue *txq = &il->txq[txq_id]; 2456 struct il_queue *q = &txq->q; 2457 int nfreed = 0; 2458 struct ieee80211_hdr *hdr; 2459 struct sk_buff *skb; 2460 2461 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { 2462 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, " 2463 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, 2464 q->write_ptr, q->read_ptr); 2465 return 0; 2466 } 2467 2468 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 2469 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { 2470 2471 skb = txq->skbs[txq->q.read_ptr]; 2472 2473 if (WARN_ON_ONCE(skb == NULL)) 2474 continue; 2475 2476 hdr = (struct ieee80211_hdr *) skb->data; 2477 if (ieee80211_is_data_qos(hdr->frame_control)) 2478 nfreed++; 2479 2480 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE); 2481 2482 txq->skbs[txq->q.read_ptr] = NULL; 2483 il->ops->txq_free_tfd(il, txq); 2484 } 2485 return nfreed; 2486} 2487 2488/* 2489 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack 2490 * 2491 * Go through block-ack's bitmap of ACK'd frames, update driver's record of 2492 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. 2493 */ 2494static int 2495il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg, 2496 struct il_compressed_ba_resp *ba_resp) 2497{ 2498 int i, sh, ack; 2499 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); 2500 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); 2501 int successes = 0; 2502 struct ieee80211_tx_info *info; 2503 u64 bitmap, sent_bitmap; 2504 2505 if (unlikely(!agg->wait_for_ba)) { 2506 if (unlikely(ba_resp->bitmap)) 2507 IL_ERR("Received BA when not expected\n"); 2508 return -EINVAL; 2509 } 2510 2511 /* Mark that the expected block-ack response arrived */ 2512 agg->wait_for_ba = 0; 2513 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); 2514 2515 /* Calculate shift to align block-ack bits with our Tx win bits */ 2516 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4); 2517 if (sh < 0) /* tbw something is wrong with indices */ 2518 sh += 0x100; 2519 2520 if (agg->frame_count > (64 - sh)) { 2521 D_TX_REPLY("more frames than bitmap size"); 2522 return -1; 2523 } 2524 2525 /* don't use 64-bit values for now */ 2526 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; 2527 2528 /* check for success or failure according to the 2529 * transmitted bitmap and block-ack bitmap */ 2530 sent_bitmap = bitmap & agg->bitmap; 2531 2532 /* For each frame attempted in aggregation, 2533 * update driver's record of tx frame's status. */ 2534 i = 0; 2535 while (sent_bitmap) { 2536 ack = sent_bitmap & 1ULL; 2537 successes += ack; 2538 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK", 2539 i, (agg->start_idx + i) & 0xff, agg->start_idx + i); 2540 sent_bitmap >>= 1; 2541 ++i; 2542 } 2543 2544 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap); 2545 2546 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]); 2547 memset(&info->status, 0, sizeof(info->status)); 2548 info->flags |= IEEE80211_TX_STAT_ACK; 2549 info->flags |= IEEE80211_TX_STAT_AMPDU; 2550 info->status.ampdu_ack_len = successes; 2551 info->status.ampdu_len = agg->frame_count; 2552 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info); 2553 2554 return 0; 2555} 2556 2557static inline bool 2558il4965_is_tx_success(u32 status) 2559{ 2560 status &= TX_STATUS_MSK; 2561 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE); 2562} 2563 2564static u8 2565il4965_find_station(struct il_priv *il, const u8 *addr) 2566{ 2567 int i; 2568 int start = 0; 2569 int ret = IL_INVALID_STATION; 2570 unsigned long flags; 2571 2572 if (il->iw_mode == NL80211_IFTYPE_ADHOC) 2573 start = IL_STA_ID; 2574 2575 if (is_broadcast_ether_addr(addr)) 2576 return il->hw_params.bcast_id; 2577 2578 spin_lock_irqsave(&il->sta_lock, flags); 2579 for (i = start; i < il->hw_params.max_stations; i++) 2580 if (il->stations[i].used && 2581 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) { 2582 ret = i; 2583 goto out; 2584 } 2585 2586 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations); 2587 2588out: 2589 /* 2590 * It may be possible that more commands interacting with stations 2591 * arrive before we completed processing the adding of 2592 * station 2593 */ 2594 if (ret != IL_INVALID_STATION && 2595 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) || 2596 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) && 2597 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) { 2598 IL_ERR("Requested station info for sta %d before ready.\n", 2599 ret); 2600 ret = IL_INVALID_STATION; 2601 } 2602 spin_unlock_irqrestore(&il->sta_lock, flags); 2603 return ret; 2604} 2605 2606static int 2607il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr) 2608{ 2609 if (il->iw_mode == NL80211_IFTYPE_STATION) 2610 return IL_AP_ID; 2611 else { 2612 u8 *da = ieee80211_get_DA(hdr); 2613 2614 return il4965_find_station(il, da); 2615 } 2616} 2617 2618static inline u32 2619il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp) 2620{ 2621 return le32_to_cpup(&tx_resp->u.status + 2622 tx_resp->frame_count) & IEEE80211_MAX_SN; 2623} 2624 2625static inline u32 2626il4965_tx_status_to_mac80211(u32 status) 2627{ 2628 status &= TX_STATUS_MSK; 2629 2630 switch (status) { 2631 case TX_STATUS_SUCCESS: 2632 case TX_STATUS_DIRECT_DONE: 2633 return IEEE80211_TX_STAT_ACK; 2634 case TX_STATUS_FAIL_DEST_PS: 2635 return IEEE80211_TX_STAT_TX_FILTERED; 2636 default: 2637 return 0; 2638 } 2639} 2640 2641/* 2642 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue 2643 */ 2644static int 2645il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg, 2646 struct il4965_tx_resp *tx_resp, int txq_id, 2647 u16 start_idx) 2648{ 2649 u16 status; 2650 struct agg_tx_status *frame_status = tx_resp->u.agg_status; 2651 struct ieee80211_tx_info *info = NULL; 2652 struct ieee80211_hdr *hdr = NULL; 2653 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 2654 int i, sh, idx; 2655 u16 seq; 2656 if (agg->wait_for_ba) 2657 D_TX_REPLY("got tx response w/o block-ack\n"); 2658 2659 agg->frame_count = tx_resp->frame_count; 2660 agg->start_idx = start_idx; 2661 agg->rate_n_flags = rate_n_flags; 2662 agg->bitmap = 0; 2663 2664 /* num frames attempted by Tx command */ 2665 if (agg->frame_count == 1) { 2666 /* Only one frame was attempted; no block-ack will arrive */ 2667 status = le16_to_cpu(frame_status[0].status); 2668 idx = start_idx; 2669 2670 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 2671 agg->frame_count, agg->start_idx, idx); 2672 2673 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]); 2674 info->status.rates[0].count = tx_resp->failure_frame + 1; 2675 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 2676 info->flags |= il4965_tx_status_to_mac80211(status); 2677 il4965_hwrate_to_tx_control(il, rate_n_flags, info); 2678 2679 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff, 2680 tx_resp->failure_frame); 2681 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); 2682 2683 agg->wait_for_ba = 0; 2684 } else { 2685 /* Two or more frames were attempted; expect block-ack */ 2686 u64 bitmap = 0; 2687 int start = agg->start_idx; 2688 struct sk_buff *skb; 2689 2690 /* Construct bit-map of pending frames within Tx win */ 2691 for (i = 0; i < agg->frame_count; i++) { 2692 u16 sc; 2693 status = le16_to_cpu(frame_status[i].status); 2694 seq = le16_to_cpu(frame_status[i].sequence); 2695 idx = SEQ_TO_IDX(seq); 2696 txq_id = SEQ_TO_QUEUE(seq); 2697 2698 if (status & 2699 (AGG_TX_STATE_FEW_BYTES_MSK | 2700 AGG_TX_STATE_ABORT_MSK)) 2701 continue; 2702 2703 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 2704 agg->frame_count, txq_id, idx); 2705 2706 skb = il->txq[txq_id].skbs[idx]; 2707 if (WARN_ON_ONCE(skb == NULL)) 2708 return -1; 2709 hdr = (struct ieee80211_hdr *) skb->data; 2710 2711 sc = le16_to_cpu(hdr->seq_ctrl); 2712 if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) { 2713 IL_ERR("BUG_ON idx doesn't match seq control" 2714 " idx=%d, seq_idx=%d, seq=%d\n", idx, 2715 IEEE80211_SEQ_TO_SN(sc), hdr->seq_ctrl); 2716 return -1; 2717 } 2718 2719 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx, 2720 IEEE80211_SEQ_TO_SN(sc)); 2721 2722 sh = idx - start; 2723 if (sh > 64) { 2724 sh = (start - idx) + 0xff; 2725 bitmap = bitmap << sh; 2726 sh = 0; 2727 start = idx; 2728 } else if (sh < -64) 2729 sh = 0xff - (start - idx); 2730 else if (sh < 0) { 2731 sh = start - idx; 2732 start = idx; 2733 bitmap = bitmap << sh; 2734 sh = 0; 2735 } 2736 bitmap |= 1ULL << sh; 2737 D_TX_REPLY("start=%d bitmap=0x%llx\n", start, 2738 (unsigned long long)bitmap); 2739 } 2740 2741 agg->bitmap = bitmap; 2742 agg->start_idx = start; 2743 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 2744 agg->frame_count, agg->start_idx, 2745 (unsigned long long)agg->bitmap); 2746 2747 if (bitmap) 2748 agg->wait_for_ba = 1; 2749 } 2750 return 0; 2751} 2752 2753/* 2754 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response 2755 */ 2756static void 2757il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) 2758{ 2759 struct il_rx_pkt *pkt = rxb_addr(rxb); 2760 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 2761 int txq_id = SEQ_TO_QUEUE(sequence); 2762 int idx = SEQ_TO_IDX(sequence); 2763 struct il_tx_queue *txq = &il->txq[txq_id]; 2764 struct sk_buff *skb; 2765 struct ieee80211_hdr *hdr; 2766 struct ieee80211_tx_info *info; 2767 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 2768 u32 status = le32_to_cpu(tx_resp->u.status); 2769 int tid; 2770 int sta_id; 2771 int freed; 2772 u8 *qc = NULL; 2773 unsigned long flags; 2774 2775 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { 2776 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d " 2777 "is out of range [0-%d] %d %d\n", txq_id, idx, 2778 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr); 2779 return; 2780 } 2781 2782 txq->time_stamp = jiffies; 2783 2784 skb = txq->skbs[txq->q.read_ptr]; 2785 info = IEEE80211_SKB_CB(skb); 2786 memset(&info->status, 0, sizeof(info->status)); 2787 2788 hdr = (struct ieee80211_hdr *) skb->data; 2789 if (ieee80211_is_data_qos(hdr->frame_control)) { 2790 qc = ieee80211_get_qos_ctl(hdr); 2791 tid = qc[0] & 0xf; 2792 } 2793 2794 sta_id = il4965_get_ra_sta_id(il, hdr); 2795 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) { 2796 IL_ERR("Station not known\n"); 2797 return; 2798 } 2799 2800 /* 2801 * Firmware will not transmit frame on passive channel, if it not yet 2802 * received some valid frame on that channel. When this error happen 2803 * we have to wait until firmware will unblock itself i.e. when we 2804 * note received beacon or other frame. We unblock queues in 2805 * il4965_pass_packet_to_mac80211 or in il_mac_bss_info_changed. 2806 */ 2807 if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) && 2808 il->iw_mode == NL80211_IFTYPE_STATION) { 2809 il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE); 2810 D_INFO("Stopped queues - RX waiting on passive channel\n"); 2811 } 2812 2813 spin_lock_irqsave(&il->sta_lock, flags); 2814 if (txq->sched_retry) { 2815 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp); 2816 struct il_ht_agg *agg = NULL; 2817 WARN_ON(!qc); 2818 2819 agg = &il->stations[sta_id].tid[tid].agg; 2820 2821 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx); 2822 2823 /* check if BAR is needed */ 2824 if (tx_resp->frame_count == 1 && 2825 !il4965_is_tx_success(status)) 2826 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 2827 2828 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 2829 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 2830 D_TX_REPLY("Retry scheduler reclaim scd_ssn " 2831 "%d idx %d\n", scd_ssn, idx); 2832 freed = il4965_tx_queue_reclaim(il, txq_id, idx); 2833 if (qc) 2834 il4965_free_tfds_in_queue(il, sta_id, tid, 2835 freed); 2836 2837 if (il->mac80211_registered && 2838 il_queue_space(&txq->q) > txq->q.low_mark && 2839 agg->state != IL_EMPTYING_HW_QUEUE_DELBA) 2840 il_wake_queue(il, txq); 2841 } 2842 } else { 2843 info->status.rates[0].count = tx_resp->failure_frame + 1; 2844 info->flags |= il4965_tx_status_to_mac80211(status); 2845 il4965_hwrate_to_tx_control(il, 2846 le32_to_cpu(tx_resp->rate_n_flags), 2847 info); 2848 2849 D_TX_REPLY("TXQ %d status %s (0x%08x) " 2850 "rate_n_flags 0x%x retries %d\n", txq_id, 2851 il4965_get_tx_fail_reason(status), status, 2852 le32_to_cpu(tx_resp->rate_n_flags), 2853 tx_resp->failure_frame); 2854 2855 freed = il4965_tx_queue_reclaim(il, txq_id, idx); 2856 if (qc && likely(sta_id != IL_INVALID_STATION)) 2857 il4965_free_tfds_in_queue(il, sta_id, tid, freed); 2858 else if (sta_id == IL_INVALID_STATION) 2859 D_TX_REPLY("Station not known\n"); 2860 2861 if (il->mac80211_registered && 2862 il_queue_space(&txq->q) > txq->q.low_mark) 2863 il_wake_queue(il, txq); 2864 } 2865 if (qc && likely(sta_id != IL_INVALID_STATION)) 2866 il4965_txq_check_empty(il, sta_id, tid, txq_id); 2867 2868 il4965_check_abort_status(il, tx_resp->frame_count, status); 2869 2870 spin_unlock_irqrestore(&il->sta_lock, flags); 2871} 2872 2873/* 2874 * translate ucode response to mac80211 tx status control values 2875 */ 2876void 2877il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, 2878 struct ieee80211_tx_info *info) 2879{ 2880 struct ieee80211_tx_rate *r = &info->status.rates[0]; 2881 2882 info->status.antenna = 2883 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); 2884 if (rate_n_flags & RATE_MCS_HT_MSK) 2885 r->flags |= IEEE80211_TX_RC_MCS; 2886 if (rate_n_flags & RATE_MCS_GF_MSK) 2887 r->flags |= IEEE80211_TX_RC_GREEN_FIELD; 2888 if (rate_n_flags & RATE_MCS_HT40_MSK) 2889 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 2890 if (rate_n_flags & RATE_MCS_DUP_MSK) 2891 r->flags |= IEEE80211_TX_RC_DUP_DATA; 2892 if (rate_n_flags & RATE_MCS_SGI_MSK) 2893 r->flags |= IEEE80211_TX_RC_SHORT_GI; 2894 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band); 2895} 2896 2897/* 2898 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA 2899 * 2900 * Handles block-acknowledge notification from device, which reports success 2901 * of frames sent via aggregation. 2902 */ 2903static void 2904il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb) 2905{ 2906 struct il_rx_pkt *pkt = rxb_addr(rxb); 2907 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; 2908 struct il_tx_queue *txq = NULL; 2909 struct il_ht_agg *agg; 2910 int idx; 2911 int sta_id; 2912 int tid; 2913 unsigned long flags; 2914 2915 /* "flow" corresponds to Tx queue */ 2916 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); 2917 2918 /* "ssn" is start of block-ack Tx win, corresponds to idx 2919 * (in Tx queue's circular buffer) of first TFD/frame in win */ 2920 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); 2921 2922 if (scd_flow >= il->hw_params.max_txq_num) { 2923 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n"); 2924 return; 2925 } 2926 2927 txq = &il->txq[scd_flow]; 2928 sta_id = ba_resp->sta_id; 2929 tid = ba_resp->tid; 2930 agg = &il->stations[sta_id].tid[tid].agg; 2931 if (unlikely(agg->txq_id != scd_flow)) { 2932 /* 2933 * FIXME: this is a uCode bug which need to be addressed, 2934 * log the information and return for now! 2935 * since it is possible happen very often and in order 2936 * not to fill the syslog, don't enable the logging by default 2937 */ 2938 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n", 2939 scd_flow, agg->txq_id); 2940 return; 2941 } 2942 2943 /* Find idx just before block-ack win */ 2944 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); 2945 2946 spin_lock_irqsave(&il->sta_lock, flags); 2947 2948 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n", 2949 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32, 2950 ba_resp->sta_id); 2951 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = " 2952 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl, 2953 (unsigned long long)le64_to_cpu(ba_resp->bitmap), 2954 ba_resp->scd_flow, ba_resp->scd_ssn); 2955 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx, 2956 (unsigned long long)agg->bitmap); 2957 2958 /* Update driver's record of ACK vs. not for each frame in win */ 2959 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp); 2960 2961 /* Release all TFDs before the SSN, i.e. all TFDs in front of 2962 * block-ack win (we assume that they've been successfully 2963 * transmitted ... if not, it's too late anyway). */ 2964 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { 2965 /* calculate mac80211 ampdu sw queue to wake */ 2966 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx); 2967 il4965_free_tfds_in_queue(il, sta_id, tid, freed); 2968 2969 if (il_queue_space(&txq->q) > txq->q.low_mark && 2970 il->mac80211_registered && 2971 agg->state != IL_EMPTYING_HW_QUEUE_DELBA) 2972 il_wake_queue(il, txq); 2973 2974 il4965_txq_check_empty(il, sta_id, tid, scd_flow); 2975 } 2976 2977 spin_unlock_irqrestore(&il->sta_lock, flags); 2978} 2979 2980#ifdef CONFIG_IWLEGACY_DEBUG 2981const char * 2982il4965_get_tx_fail_reason(u32 status) 2983{ 2984#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x 2985#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x 2986 2987 switch (status & TX_STATUS_MSK) { 2988 case TX_STATUS_SUCCESS: 2989 return "SUCCESS"; 2990 TX_STATUS_POSTPONE(DELAY); 2991 TX_STATUS_POSTPONE(FEW_BYTES); 2992 TX_STATUS_POSTPONE(QUIET_PERIOD); 2993 TX_STATUS_POSTPONE(CALC_TTAK); 2994 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); 2995 TX_STATUS_FAIL(SHORT_LIMIT); 2996 TX_STATUS_FAIL(LONG_LIMIT); 2997 TX_STATUS_FAIL(FIFO_UNDERRUN); 2998 TX_STATUS_FAIL(DRAIN_FLOW); 2999 TX_STATUS_FAIL(RFKILL_FLUSH); 3000 TX_STATUS_FAIL(LIFE_EXPIRE); 3001 TX_STATUS_FAIL(DEST_PS); 3002 TX_STATUS_FAIL(HOST_ABORTED); 3003 TX_STATUS_FAIL(BT_RETRY); 3004 TX_STATUS_FAIL(STA_INVALID); 3005 TX_STATUS_FAIL(FRAG_DROPPED); 3006 TX_STATUS_FAIL(TID_DISABLE); 3007 TX_STATUS_FAIL(FIFO_FLUSHED); 3008 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); 3009 TX_STATUS_FAIL(PASSIVE_NO_RX); 3010 TX_STATUS_FAIL(NO_BEACON_ON_RADAR); 3011 } 3012 3013 return "UNKNOWN"; 3014 3015#undef TX_STATUS_FAIL 3016#undef TX_STATUS_POSTPONE 3017} 3018#endif /* CONFIG_IWLEGACY_DEBUG */ 3019 3020static struct il_link_quality_cmd * 3021il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id) 3022{ 3023 int i, r; 3024 struct il_link_quality_cmd *link_cmd; 3025 u32 rate_flags = 0; 3026 __le32 rate_n_flags; 3027 3028 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL); 3029 if (!link_cmd) { 3030 IL_ERR("Unable to allocate memory for LQ cmd.\n"); 3031 return NULL; 3032 } 3033 /* Set up the rate scaling to start at selected rate, fall back 3034 * all the way down to 1M in IEEE order, and then spin on 1M */ 3035 if (il->band == NL80211_BAND_5GHZ) 3036 r = RATE_6M_IDX; 3037 else 3038 r = RATE_1M_IDX; 3039 3040 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE) 3041 rate_flags |= RATE_MCS_CCK_MSK; 3042 3043 rate_flags |= 3044 il4965_first_antenna(il->hw_params. 3045 valid_tx_ant) << RATE_MCS_ANT_POS; 3046 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags); 3047 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) 3048 link_cmd->rs_table[i].rate_n_flags = rate_n_flags; 3049 3050 link_cmd->general_params.single_stream_ant_msk = 3051 il4965_first_antenna(il->hw_params.valid_tx_ant); 3052 3053 link_cmd->general_params.dual_stream_ant_msk = 3054 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params. 3055 valid_tx_ant); 3056 if (!link_cmd->general_params.dual_stream_ant_msk) { 3057 link_cmd->general_params.dual_stream_ant_msk = ANT_AB; 3058 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) { 3059 link_cmd->general_params.dual_stream_ant_msk = 3060 il->hw_params.valid_tx_ant; 3061 } 3062 3063 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF; 3064 link_cmd->agg_params.agg_time_limit = 3065 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF); 3066 3067 link_cmd->sta_id = sta_id; 3068 3069 return link_cmd; 3070} 3071 3072/* 3073 * il4965_add_bssid_station - Add the special IBSS BSSID station 3074 * 3075 * Function sleeps. 3076 */ 3077int 3078il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r) 3079{ 3080 int ret; 3081 u8 sta_id; 3082 struct il_link_quality_cmd *link_cmd; 3083 unsigned long flags; 3084 3085 if (sta_id_r) 3086 *sta_id_r = IL_INVALID_STATION; 3087 3088 ret = il_add_station_common(il, addr, 0, NULL, &sta_id); 3089 if (ret) { 3090 IL_ERR("Unable to add station %pM\n", addr); 3091 return ret; 3092 } 3093 3094 if (sta_id_r) 3095 *sta_id_r = sta_id; 3096 3097 spin_lock_irqsave(&il->sta_lock, flags); 3098 il->stations[sta_id].used |= IL_STA_LOCAL; 3099 spin_unlock_irqrestore(&il->sta_lock, flags); 3100 3101 /* Set up default rate scaling table in device's station table */ 3102 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3103 if (!link_cmd) { 3104 IL_ERR("Unable to initialize rate scaling for station %pM.\n", 3105 addr); 3106 return -ENOMEM; 3107 } 3108 3109 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true); 3110 if (ret) 3111 IL_ERR("Link quality command failed (%d)\n", ret); 3112 3113 spin_lock_irqsave(&il->sta_lock, flags); 3114 il->stations[sta_id].lq = link_cmd; 3115 spin_unlock_irqrestore(&il->sta_lock, flags); 3116 3117 return 0; 3118} 3119 3120static int 3121il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty) 3122{ 3123 int i; 3124 u8 buff[sizeof(struct il_wep_cmd) + 3125 sizeof(struct il_wep_key) * WEP_KEYS_MAX]; 3126 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff; 3127 size_t cmd_size = sizeof(struct il_wep_cmd); 3128 struct il_host_cmd cmd = { 3129 .id = C_WEPKEY, 3130 .data = wep_cmd, 3131 .flags = CMD_SYNC, 3132 }; 3133 bool not_empty = false; 3134 3135 might_sleep(); 3136 3137 memset(wep_cmd, 0, 3138 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX)); 3139 3140 for (i = 0; i < WEP_KEYS_MAX; i++) { 3141 u8 key_size = il->_4965.wep_keys[i].key_size; 3142 3143 wep_cmd->key[i].key_idx = i; 3144 if (key_size) { 3145 wep_cmd->key[i].key_offset = i; 3146 not_empty = true; 3147 } else 3148 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET; 3149 3150 wep_cmd->key[i].key_size = key_size; 3151 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size); 3152 } 3153 3154 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE; 3155 wep_cmd->num_keys = WEP_KEYS_MAX; 3156 3157 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX; 3158 cmd.len = cmd_size; 3159 3160 if (not_empty || send_if_empty) 3161 return il_send_cmd(il, &cmd); 3162 else 3163 return 0; 3164} 3165 3166int 3167il4965_restore_default_wep_keys(struct il_priv *il) 3168{ 3169 lockdep_assert_held(&il->mutex); 3170 3171 return il4965_static_wepkey_cmd(il, false); 3172} 3173 3174int 3175il4965_remove_default_wep_key(struct il_priv *il, 3176 struct ieee80211_key_conf *keyconf) 3177{ 3178 int ret; 3179 int idx = keyconf->keyidx; 3180 3181 lockdep_assert_held(&il->mutex); 3182 3183 D_WEP("Removing default WEP key: idx=%d\n", idx); 3184 3185 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key)); 3186 if (il_is_rfkill(il)) { 3187 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n"); 3188 /* but keys in device are clear anyway so return success */ 3189 return 0; 3190 } 3191 ret = il4965_static_wepkey_cmd(il, 1); 3192 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret); 3193 3194 return ret; 3195} 3196 3197int 3198il4965_set_default_wep_key(struct il_priv *il, 3199 struct ieee80211_key_conf *keyconf) 3200{ 3201 int ret; 3202 int len = keyconf->keylen; 3203 int idx = keyconf->keyidx; 3204 3205 lockdep_assert_held(&il->mutex); 3206 3207 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) { 3208 D_WEP("Bad WEP key length %d\n", keyconf->keylen); 3209 return -EINVAL; 3210 } 3211 3212 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 3213 keyconf->hw_key_idx = HW_KEY_DEFAULT; 3214 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher; 3215 3216 il->_4965.wep_keys[idx].key_size = len; 3217 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len); 3218 3219 ret = il4965_static_wepkey_cmd(il, false); 3220 3221 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret); 3222 return ret; 3223} 3224 3225static int 3226il4965_set_wep_dynamic_key_info(struct il_priv *il, 3227 struct ieee80211_key_conf *keyconf, u8 sta_id) 3228{ 3229 unsigned long flags; 3230 __le16 key_flags = 0; 3231 struct il_addsta_cmd sta_cmd; 3232 3233 lockdep_assert_held(&il->mutex); 3234 3235 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 3236 3237 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK); 3238 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3239 key_flags &= ~STA_KEY_FLG_INVALID; 3240 3241 if (keyconf->keylen == WEP_KEY_LEN_128) 3242 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK; 3243 3244 if (sta_id == il->hw_params.bcast_id) 3245 key_flags |= STA_KEY_MULTICAST_MSK; 3246 3247 spin_lock_irqsave(&il->sta_lock, flags); 3248 3249 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3250 il->stations[sta_id].keyinfo.keylen = keyconf->keylen; 3251 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx; 3252 3253 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); 3254 3255 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key, 3256 keyconf->keylen); 3257 3258 if ((il->stations[sta_id].sta.key. 3259 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3260 il->stations[sta_id].sta.key.key_offset = 3261 il_get_free_ucode_key_idx(il); 3262 /* else, we are overriding an existing key => no need to allocated room 3263 * in uCode. */ 3264 3265 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3266 "no space for a new key"); 3267 3268 il->stations[sta_id].sta.key.key_flags = key_flags; 3269 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3270 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3271 3272 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3273 sizeof(struct il_addsta_cmd)); 3274 spin_unlock_irqrestore(&il->sta_lock, flags); 3275 3276 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3277} 3278 3279static int 3280il4965_set_ccmp_dynamic_key_info(struct il_priv *il, 3281 struct ieee80211_key_conf *keyconf, u8 sta_id) 3282{ 3283 unsigned long flags; 3284 __le16 key_flags = 0; 3285 struct il_addsta_cmd sta_cmd; 3286 3287 lockdep_assert_held(&il->mutex); 3288 3289 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); 3290 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3291 key_flags &= ~STA_KEY_FLG_INVALID; 3292 3293 if (sta_id == il->hw_params.bcast_id) 3294 key_flags |= STA_KEY_MULTICAST_MSK; 3295 3296 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3297 3298 spin_lock_irqsave(&il->sta_lock, flags); 3299 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3300 il->stations[sta_id].keyinfo.keylen = keyconf->keylen; 3301 3302 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); 3303 3304 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen); 3305 3306 if ((il->stations[sta_id].sta.key. 3307 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3308 il->stations[sta_id].sta.key.key_offset = 3309 il_get_free_ucode_key_idx(il); 3310 /* else, we are overriding an existing key => no need to allocated room 3311 * in uCode. */ 3312 3313 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3314 "no space for a new key"); 3315 3316 il->stations[sta_id].sta.key.key_flags = key_flags; 3317 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3318 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3319 3320 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3321 sizeof(struct il_addsta_cmd)); 3322 spin_unlock_irqrestore(&il->sta_lock, flags); 3323 3324 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3325} 3326 3327static int 3328il4965_set_tkip_dynamic_key_info(struct il_priv *il, 3329 struct ieee80211_key_conf *keyconf, u8 sta_id) 3330{ 3331 unsigned long flags; 3332 __le16 key_flags = 0; 3333 3334 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); 3335 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3336 key_flags &= ~STA_KEY_FLG_INVALID; 3337 3338 if (sta_id == il->hw_params.bcast_id) 3339 key_flags |= STA_KEY_MULTICAST_MSK; 3340 3341 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3342 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 3343 3344 spin_lock_irqsave(&il->sta_lock, flags); 3345 3346 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3347 il->stations[sta_id].keyinfo.keylen = 16; 3348 3349 if ((il->stations[sta_id].sta.key. 3350 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3351 il->stations[sta_id].sta.key.key_offset = 3352 il_get_free_ucode_key_idx(il); 3353 /* else, we are overriding an existing key => no need to allocated room 3354 * in uCode. */ 3355 3356 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3357 "no space for a new key"); 3358 3359 il->stations[sta_id].sta.key.key_flags = key_flags; 3360 3361 /* This copy is acutally not needed: we get the key with each TX */ 3362 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16); 3363 3364 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16); 3365 3366 spin_unlock_irqrestore(&il->sta_lock, flags); 3367 3368 return 0; 3369} 3370 3371void 3372il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf, 3373 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key) 3374{ 3375 u8 sta_id; 3376 unsigned long flags; 3377 int i; 3378 3379 if (il_scan_cancel(il)) { 3380 /* cancel scan failed, just live w/ bad key and rely 3381 briefly on SW decryption */ 3382 return; 3383 } 3384 3385 sta_id = il_sta_id_or_broadcast(il, sta); 3386 if (sta_id == IL_INVALID_STATION) 3387 return; 3388 3389 spin_lock_irqsave(&il->sta_lock, flags); 3390 3391 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; 3392 3393 for (i = 0; i < 5; i++) 3394 il->stations[sta_id].sta.key.tkip_rx_ttak[i] = 3395 cpu_to_le16(phase1key[i]); 3396 3397 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3398 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3399 3400 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); 3401 3402 spin_unlock_irqrestore(&il->sta_lock, flags); 3403} 3404 3405int 3406il4965_remove_dynamic_key(struct il_priv *il, 3407 struct ieee80211_key_conf *keyconf, u8 sta_id) 3408{ 3409 unsigned long flags; 3410 u16 key_flags; 3411 u8 keyidx; 3412 struct il_addsta_cmd sta_cmd; 3413 3414 lockdep_assert_held(&il->mutex); 3415 3416 il->_4965.key_mapping_keys--; 3417 3418 spin_lock_irqsave(&il->sta_lock, flags); 3419 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags); 3420 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3; 3421 3422 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id); 3423 3424 if (keyconf->keyidx != keyidx) { 3425 /* We need to remove a key with idx different that the one 3426 * in the uCode. This means that the key we need to remove has 3427 * been replaced by another one with different idx. 3428 * Don't do anything and return ok 3429 */ 3430 spin_unlock_irqrestore(&il->sta_lock, flags); 3431 return 0; 3432 } 3433 3434 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) { 3435 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx, 3436 key_flags); 3437 spin_unlock_irqrestore(&il->sta_lock, flags); 3438 return 0; 3439 } 3440 3441 if (!test_and_clear_bit 3442 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table)) 3443 IL_ERR("idx %d not used in uCode key table.\n", 3444 il->stations[sta_id].sta.key.key_offset); 3445 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key)); 3446 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo)); 3447 il->stations[sta_id].sta.key.key_flags = 3448 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID; 3449 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx; 3450 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3451 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3452 3453 if (il_is_rfkill(il)) { 3454 D_WEP 3455 ("Not sending C_ADD_STA command because RFKILL enabled.\n"); 3456 spin_unlock_irqrestore(&il->sta_lock, flags); 3457 return 0; 3458 } 3459 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3460 sizeof(struct il_addsta_cmd)); 3461 spin_unlock_irqrestore(&il->sta_lock, flags); 3462 3463 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3464} 3465 3466int 3467il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf, 3468 u8 sta_id) 3469{ 3470 int ret; 3471 3472 lockdep_assert_held(&il->mutex); 3473 3474 il->_4965.key_mapping_keys++; 3475 keyconf->hw_key_idx = HW_KEY_DYNAMIC; 3476 3477 switch (keyconf->cipher) { 3478 case WLAN_CIPHER_SUITE_CCMP: 3479 ret = 3480 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id); 3481 break; 3482 case WLAN_CIPHER_SUITE_TKIP: 3483 ret = 3484 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id); 3485 break; 3486 case WLAN_CIPHER_SUITE_WEP40: 3487 case WLAN_CIPHER_SUITE_WEP104: 3488 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id); 3489 break; 3490 default: 3491 IL_ERR("Unknown alg: %s cipher = %x\n", __func__, 3492 keyconf->cipher); 3493 ret = -EINVAL; 3494 } 3495 3496 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n", 3497 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret); 3498 3499 return ret; 3500} 3501 3502/* 3503 * il4965_alloc_bcast_station - add broadcast station into driver's station table. 3504 * 3505 * This adds the broadcast station into the driver's station table 3506 * and marks it driver active, so that it will be restored to the 3507 * device at the next best time. 3508 */ 3509int 3510il4965_alloc_bcast_station(struct il_priv *il) 3511{ 3512 struct il_link_quality_cmd *link_cmd; 3513 unsigned long flags; 3514 u8 sta_id; 3515 3516 spin_lock_irqsave(&il->sta_lock, flags); 3517 sta_id = il_prep_station(il, il_bcast_addr, false, NULL); 3518 if (sta_id == IL_INVALID_STATION) { 3519 IL_ERR("Unable to prepare broadcast station\n"); 3520 spin_unlock_irqrestore(&il->sta_lock, flags); 3521 3522 return -EINVAL; 3523 } 3524 3525 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE; 3526 il->stations[sta_id].used |= IL_STA_BCAST; 3527 spin_unlock_irqrestore(&il->sta_lock, flags); 3528 3529 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3530 if (!link_cmd) { 3531 IL_ERR 3532 ("Unable to initialize rate scaling for bcast station.\n"); 3533 return -ENOMEM; 3534 } 3535 3536 spin_lock_irqsave(&il->sta_lock, flags); 3537 il->stations[sta_id].lq = link_cmd; 3538 spin_unlock_irqrestore(&il->sta_lock, flags); 3539 3540 return 0; 3541} 3542 3543/* 3544 * il4965_update_bcast_station - update broadcast station's LQ command 3545 * 3546 * Only used by iwl4965. Placed here to have all bcast station management 3547 * code together. 3548 */ 3549static int 3550il4965_update_bcast_station(struct il_priv *il) 3551{ 3552 unsigned long flags; 3553 struct il_link_quality_cmd *link_cmd; 3554 u8 sta_id = il->hw_params.bcast_id; 3555 3556 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3557 if (!link_cmd) { 3558 IL_ERR("Unable to initialize rate scaling for bcast sta.\n"); 3559 return -ENOMEM; 3560 } 3561 3562 spin_lock_irqsave(&il->sta_lock, flags); 3563 if (il->stations[sta_id].lq) 3564 kfree(il->stations[sta_id].lq); 3565 else 3566 D_INFO("Bcast sta rate scaling has not been initialized.\n"); 3567 il->stations[sta_id].lq = link_cmd; 3568 spin_unlock_irqrestore(&il->sta_lock, flags); 3569 3570 return 0; 3571} 3572 3573int 3574il4965_update_bcast_stations(struct il_priv *il) 3575{ 3576 return il4965_update_bcast_station(il); 3577} 3578 3579/* 3580 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table 3581 */ 3582int 3583il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid) 3584{ 3585 unsigned long flags; 3586 struct il_addsta_cmd sta_cmd; 3587 3588 lockdep_assert_held(&il->mutex); 3589 3590 /* Remove "disable" flag, to enable Tx for this TID */ 3591 spin_lock_irqsave(&il->sta_lock, flags); 3592 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX; 3593 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid)); 3594 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3595 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3596 sizeof(struct il_addsta_cmd)); 3597 spin_unlock_irqrestore(&il->sta_lock, flags); 3598 3599 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3600} 3601 3602int 3603il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid, 3604 u16 ssn) 3605{ 3606 unsigned long flags; 3607 int sta_id; 3608 struct il_addsta_cmd sta_cmd; 3609 3610 lockdep_assert_held(&il->mutex); 3611 3612 sta_id = il_sta_id(sta); 3613 if (sta_id == IL_INVALID_STATION) 3614 return -ENXIO; 3615 3616 spin_lock_irqsave(&il->sta_lock, flags); 3617 il->stations[sta_id].sta.station_flags_msk = 0; 3618 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; 3619 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid; 3620 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); 3621 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3622 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3623 sizeof(struct il_addsta_cmd)); 3624 spin_unlock_irqrestore(&il->sta_lock, flags); 3625 3626 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3627} 3628 3629int 3630il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid) 3631{ 3632 unsigned long flags; 3633 int sta_id; 3634 struct il_addsta_cmd sta_cmd; 3635 3636 lockdep_assert_held(&il->mutex); 3637 3638 sta_id = il_sta_id(sta); 3639 if (sta_id == IL_INVALID_STATION) { 3640 IL_ERR("Invalid station for AGG tid %d\n", tid); 3641 return -ENXIO; 3642 } 3643 3644 spin_lock_irqsave(&il->sta_lock, flags); 3645 il->stations[sta_id].sta.station_flags_msk = 0; 3646 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK; 3647 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid; 3648 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3649 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3650 sizeof(struct il_addsta_cmd)); 3651 spin_unlock_irqrestore(&il->sta_lock, flags); 3652 3653 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3654} 3655 3656void 3657il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt) 3658{ 3659 unsigned long flags; 3660 3661 spin_lock_irqsave(&il->sta_lock, flags); 3662 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK; 3663 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK; 3664 il->stations[sta_id].sta.sta.modify_mask = 3665 STA_MODIFY_SLEEP_TX_COUNT_MSK; 3666 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt); 3667 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3668 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); 3669 spin_unlock_irqrestore(&il->sta_lock, flags); 3670 3671} 3672 3673void 3674il4965_update_chain_flags(struct il_priv *il) 3675{ 3676 if (il->ops->set_rxon_chain) { 3677 il->ops->set_rxon_chain(il); 3678 if (il->active.rx_chain != il->staging.rx_chain) 3679 il_commit_rxon(il); 3680 } 3681} 3682 3683static void 3684il4965_clear_free_frames(struct il_priv *il) 3685{ 3686 struct list_head *element; 3687 3688 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count); 3689 3690 while (!list_empty(&il->free_frames)) { 3691 element = il->free_frames.next; 3692 list_del(element); 3693 kfree(list_entry(element, struct il_frame, list)); 3694 il->frames_count--; 3695 } 3696 3697 if (il->frames_count) { 3698 IL_WARN("%d frames still in use. Did we lose one?\n", 3699 il->frames_count); 3700 il->frames_count = 0; 3701 } 3702} 3703 3704static struct il_frame * 3705il4965_get_free_frame(struct il_priv *il) 3706{ 3707 struct il_frame *frame; 3708 struct list_head *element; 3709 if (list_empty(&il->free_frames)) { 3710 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 3711 if (!frame) { 3712 IL_ERR("Could not allocate frame!\n"); 3713 return NULL; 3714 } 3715 3716 il->frames_count++; 3717 return frame; 3718 } 3719 3720 element = il->free_frames.next; 3721 list_del(element); 3722 return list_entry(element, struct il_frame, list); 3723} 3724 3725static void 3726il4965_free_frame(struct il_priv *il, struct il_frame *frame) 3727{ 3728 memset(frame, 0, sizeof(*frame)); 3729 list_add(&frame->list, &il->free_frames); 3730} 3731 3732static u32 3733il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr, 3734 int left) 3735{ 3736 lockdep_assert_held(&il->mutex); 3737 3738 if (!il->beacon_skb) 3739 return 0; 3740 3741 if (il->beacon_skb->len > left) 3742 return 0; 3743 3744 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len); 3745 3746 return il->beacon_skb->len; 3747} 3748 3749/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ 3750static void 3751il4965_set_beacon_tim(struct il_priv *il, 3752 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon, 3753 u32 frame_size) 3754{ 3755 u16 tim_idx; 3756 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; 3757 3758 /* 3759 * The idx is relative to frame start but we start looking at the 3760 * variable-length part of the beacon. 3761 */ 3762 tim_idx = mgmt->u.beacon.variable - beacon; 3763 3764 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ 3765 while ((tim_idx < (frame_size - 2)) && 3766 (beacon[tim_idx] != WLAN_EID_TIM)) 3767 tim_idx += beacon[tim_idx + 1] + 2; 3768 3769 /* If TIM field was found, set variables */ 3770 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { 3771 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); 3772 tx_beacon_cmd->tim_size = beacon[tim_idx + 1]; 3773 } else 3774 IL_WARN("Unable to find TIM Element in beacon\n"); 3775} 3776 3777static unsigned int 3778il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame) 3779{ 3780 struct il_tx_beacon_cmd *tx_beacon_cmd; 3781 u32 frame_size; 3782 u32 rate_flags; 3783 u32 rate; 3784 /* 3785 * We have to set up the TX command, the TX Beacon command, and the 3786 * beacon contents. 3787 */ 3788 3789 lockdep_assert_held(&il->mutex); 3790 3791 if (!il->beacon_enabled) { 3792 IL_ERR("Trying to build beacon without beaconing enabled\n"); 3793 return 0; 3794 } 3795 3796 /* Initialize memory */ 3797 tx_beacon_cmd = &frame->u.beacon; 3798 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 3799 3800 /* Set up TX beacon contents */ 3801 frame_size = 3802 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame, 3803 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 3804 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) 3805 return 0; 3806 if (!frame_size) 3807 return 0; 3808 3809 /* Set up TX command fields */ 3810 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size); 3811 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id; 3812 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 3813 tx_beacon_cmd->tx.tx_flags = 3814 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK | 3815 TX_CMD_FLG_STA_RATE_MSK; 3816 3817 /* Set up TX beacon command fields */ 3818 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame, 3819 frame_size); 3820 3821 /* Set up packet rate and flags */ 3822 rate = il_get_lowest_plcp(il); 3823 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); 3824 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; 3825 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE)) 3826 rate_flags |= RATE_MCS_CCK_MSK; 3827 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags); 3828 3829 return sizeof(*tx_beacon_cmd) + frame_size; 3830} 3831 3832int 3833il4965_send_beacon_cmd(struct il_priv *il) 3834{ 3835 struct il_frame *frame; 3836 unsigned int frame_size; 3837 int rc; 3838 3839 frame = il4965_get_free_frame(il); 3840 if (!frame) { 3841 IL_ERR("Could not obtain free frame buffer for beacon " 3842 "command.\n"); 3843 return -ENOMEM; 3844 } 3845 3846 frame_size = il4965_hw_get_beacon_cmd(il, frame); 3847 if (!frame_size) { 3848 IL_ERR("Error configuring the beacon command\n"); 3849 il4965_free_frame(il, frame); 3850 return -EINVAL; 3851 } 3852 3853 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]); 3854 3855 il4965_free_frame(il, frame); 3856 3857 return rc; 3858} 3859 3860static inline dma_addr_t 3861il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx) 3862{ 3863 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3864 3865 dma_addr_t addr = get_unaligned_le32(&tb->lo); 3866 if (sizeof(dma_addr_t) > sizeof(u32)) 3867 addr |= 3868 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 3869 16; 3870 3871 return addr; 3872} 3873 3874static inline u16 3875il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx) 3876{ 3877 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3878 3879 return le16_to_cpu(tb->hi_n_len) >> 4; 3880} 3881 3882static inline void 3883il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len) 3884{ 3885 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3886 u16 hi_n_len = len << 4; 3887 3888 put_unaligned_le32(addr, &tb->lo); 3889 if (sizeof(dma_addr_t) > sizeof(u32)) 3890 hi_n_len |= ((addr >> 16) >> 16) & 0xF; 3891 3892 tb->hi_n_len = cpu_to_le16(hi_n_len); 3893 3894 tfd->num_tbs = idx + 1; 3895} 3896 3897static inline u8 3898il4965_tfd_get_num_tbs(struct il_tfd *tfd) 3899{ 3900 return tfd->num_tbs & 0x1f; 3901} 3902 3903/* 3904 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 3905 * 3906 * Does NOT advance any TFD circular buffer read/write idxes 3907 * Does NOT free the TFD itself (which is within circular buffer) 3908 */ 3909void 3910il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) 3911{ 3912 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds; 3913 struct il_tfd *tfd; 3914 struct pci_dev *dev = il->pci_dev; 3915 int idx = txq->q.read_ptr; 3916 int i; 3917 int num_tbs; 3918 3919 tfd = &tfd_tmp[idx]; 3920 3921 /* Sanity check on number of chunks */ 3922 num_tbs = il4965_tfd_get_num_tbs(tfd); 3923 3924 if (num_tbs >= IL_NUM_OF_TBS) { 3925 IL_ERR("Too many chunks: %i\n", num_tbs); 3926 /* @todo issue fatal error, it is quite serious situation */ 3927 return; 3928 } 3929 3930 /* Unmap tx_cmd */ 3931 if (num_tbs) 3932 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping), 3933 dma_unmap_len(&txq->meta[idx], len), 3934 PCI_DMA_BIDIRECTIONAL); 3935 3936 /* Unmap chunks, if any. */ 3937 for (i = 1; i < num_tbs; i++) 3938 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i), 3939 il4965_tfd_tb_get_len(tfd, i), 3940 PCI_DMA_TODEVICE); 3941 3942 /* free SKB */ 3943 if (txq->skbs) { 3944 struct sk_buff *skb = txq->skbs[txq->q.read_ptr]; 3945 3946 /* can be called from irqs-disabled context */ 3947 if (skb) { 3948 dev_kfree_skb_any(skb); 3949 txq->skbs[txq->q.read_ptr] = NULL; 3950 } 3951 } 3952} 3953 3954int 3955il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 3956 dma_addr_t addr, u16 len, u8 reset, u8 pad) 3957{ 3958 struct il_queue *q; 3959 struct il_tfd *tfd, *tfd_tmp; 3960 u32 num_tbs; 3961 3962 q = &txq->q; 3963 tfd_tmp = (struct il_tfd *)txq->tfds; 3964 tfd = &tfd_tmp[q->write_ptr]; 3965 3966 if (reset) 3967 memset(tfd, 0, sizeof(*tfd)); 3968 3969 num_tbs = il4965_tfd_get_num_tbs(tfd); 3970 3971 /* Each TFD can point to a maximum 20 Tx buffers */ 3972 if (num_tbs >= IL_NUM_OF_TBS) { 3973 IL_ERR("Error can not send more than %d chunks\n", 3974 IL_NUM_OF_TBS); 3975 return -EINVAL; 3976 } 3977 3978 BUG_ON(addr & ~DMA_BIT_MASK(36)); 3979 if (unlikely(addr & ~IL_TX_DMA_MASK)) 3980 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr); 3981 3982 il4965_tfd_set_tb(tfd, num_tbs, addr, len); 3983 3984 return 0; 3985} 3986 3987/* 3988 * Tell nic where to find circular buffer of Tx Frame Descriptors for 3989 * given Tx queue, and enable the DMA channel used for that queue. 3990 * 3991 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA 3992 * channels supported in hardware. 3993 */ 3994int 3995il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) 3996{ 3997 int txq_id = txq->q.id; 3998 3999 /* Circular buffer (TFD queue in DRAM) physical base address */ 4000 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8); 4001 4002 return 0; 4003} 4004 4005/****************************************************************************** 4006 * 4007 * Generic RX handler implementations 4008 * 4009 ******************************************************************************/ 4010static void 4011il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb) 4012{ 4013 struct il_rx_pkt *pkt = rxb_addr(rxb); 4014 struct il_alive_resp *palive; 4015 struct delayed_work *pwork; 4016 4017 palive = &pkt->u.alive_frame; 4018 4019 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n", 4020 palive->is_valid, palive->ver_type, palive->ver_subtype); 4021 4022 if (palive->ver_subtype == INITIALIZE_SUBTYPE) { 4023 D_INFO("Initialization Alive received.\n"); 4024 memcpy(&il->card_alive_init, &pkt->u.alive_frame, 4025 sizeof(struct il_init_alive_resp)); 4026 pwork = &il->init_alive_start; 4027 } else { 4028 D_INFO("Runtime Alive received.\n"); 4029 memcpy(&il->card_alive, &pkt->u.alive_frame, 4030 sizeof(struct il_alive_resp)); 4031 pwork = &il->alive_start; 4032 } 4033 4034 /* We delay the ALIVE response by 5ms to 4035 * give the HW RF Kill time to activate... */ 4036 if (palive->is_valid == UCODE_VALID_OK) 4037 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5)); 4038 else 4039 IL_WARN("uCode did not respond OK.\n"); 4040} 4041 4042/* 4043 * il4965_bg_stats_periodic - Timer callback to queue stats 4044 * 4045 * This callback is provided in order to send a stats request. 4046 * 4047 * This timer function is continually reset to execute within 4048 * 60 seconds since the last N_STATS was received. We need to 4049 * ensure we receive the stats in order to update the temperature 4050 * used for calibrating the TXPOWER. 4051 */ 4052static void 4053il4965_bg_stats_periodic(struct timer_list *t) 4054{ 4055 struct il_priv *il = from_timer(il, t, stats_periodic); 4056 4057 if (test_bit(S_EXIT_PENDING, &il->status)) 4058 return; 4059 4060 /* dont send host command if rf-kill is on */ 4061 if (!il_is_ready_rf(il)) 4062 return; 4063 4064 il_send_stats_request(il, CMD_ASYNC, false); 4065} 4066 4067static void 4068il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb) 4069{ 4070 struct il_rx_pkt *pkt = rxb_addr(rxb); 4071 struct il4965_beacon_notif *beacon = 4072 (struct il4965_beacon_notif *)pkt->u.raw; 4073#ifdef CONFIG_IWLEGACY_DEBUG 4074 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); 4075 4076 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n", 4077 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, 4078 beacon->beacon_notify_hdr.failure_frame, 4079 le32_to_cpu(beacon->ibss_mgr_status), 4080 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate); 4081#endif 4082 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); 4083} 4084 4085static void 4086il4965_perform_ct_kill_task(struct il_priv *il) 4087{ 4088 unsigned long flags; 4089 4090 D_POWER("Stop all queues\n"); 4091 4092 if (il->mac80211_registered) 4093 ieee80211_stop_queues(il->hw); 4094 4095 _il_wr(il, CSR_UCODE_DRV_GP1_SET, 4096 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 4097 _il_rd(il, CSR_UCODE_DRV_GP1); 4098 4099 spin_lock_irqsave(&il->reg_lock, flags); 4100 if (likely(_il_grab_nic_access(il))) 4101 _il_release_nic_access(il); 4102 spin_unlock_irqrestore(&il->reg_lock, flags); 4103} 4104 4105/* Handle notification from uCode that card's power state is changing 4106 * due to software, hardware, or critical temperature RFKILL */ 4107static void 4108il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb) 4109{ 4110 struct il_rx_pkt *pkt = rxb_addr(rxb); 4111 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); 4112 unsigned long status = il->status; 4113 4114 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n", 4115 (flags & HW_CARD_DISABLED) ? "Kill" : "On", 4116 (flags & SW_CARD_DISABLED) ? "Kill" : "On", 4117 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached"); 4118 4119 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) { 4120 4121 _il_wr(il, CSR_UCODE_DRV_GP1_SET, 4122 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 4123 4124 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 4125 4126 if (!(flags & RXON_CARD_DISABLED)) { 4127 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, 4128 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 4129 il_wr(il, HBUS_TARG_MBX_C, 4130 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 4131 } 4132 } 4133 4134 if (flags & CT_CARD_DISABLED) 4135 il4965_perform_ct_kill_task(il); 4136 4137 if (flags & HW_CARD_DISABLED) 4138 set_bit(S_RFKILL, &il->status); 4139 else 4140 clear_bit(S_RFKILL, &il->status); 4141 4142 if (!(flags & RXON_CARD_DISABLED)) 4143 il_scan_cancel(il); 4144 4145 if ((test_bit(S_RFKILL, &status) != 4146 test_bit(S_RFKILL, &il->status))) 4147 wiphy_rfkill_set_hw_state(il->hw->wiphy, 4148 test_bit(S_RFKILL, &il->status)); 4149 else 4150 wake_up(&il->wait_command_queue); 4151} 4152 4153/* 4154 * il4965_setup_handlers - Initialize Rx handler callbacks 4155 * 4156 * Setup the RX handlers for each of the reply types sent from the uCode 4157 * to the host. 4158 * 4159 * This function chains into the hardware specific files for them to setup 4160 * any hardware specific handlers as well. 4161 */ 4162static void 4163il4965_setup_handlers(struct il_priv *il) 4164{ 4165 il->handlers[N_ALIVE] = il4965_hdl_alive; 4166 il->handlers[N_ERROR] = il_hdl_error; 4167 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa; 4168 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement; 4169 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep; 4170 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats; 4171 il->handlers[N_BEACON] = il4965_hdl_beacon; 4172 4173 /* 4174 * The same handler is used for both the REPLY to a discrete 4175 * stats request from the host as well as for the periodic 4176 * stats notifications (after received beacons) from the uCode. 4177 */ 4178 il->handlers[C_STATS] = il4965_hdl_c_stats; 4179 il->handlers[N_STATS] = il4965_hdl_stats; 4180 4181 il_setup_rx_scan_handlers(il); 4182 4183 /* status change handler */ 4184 il->handlers[N_CARD_STATE] = il4965_hdl_card_state; 4185 4186 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon; 4187 /* Rx handlers */ 4188 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy; 4189 il->handlers[N_RX_MPDU] = il4965_hdl_rx; 4190 il->handlers[N_RX] = il4965_hdl_rx; 4191 /* block ack */ 4192 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba; 4193 /* Tx response */ 4194 il->handlers[C_TX] = il4965_hdl_tx; 4195} 4196 4197/* 4198 * il4965_rx_handle - Main entry function for receiving responses from uCode 4199 * 4200 * Uses the il->handlers callback function array to invoke 4201 * the appropriate handlers, including command responses, 4202 * frame-received notifications, and other notifications. 4203 */ 4204void 4205il4965_rx_handle(struct il_priv *il) 4206{ 4207 struct il_rx_buf *rxb; 4208 struct il_rx_pkt *pkt; 4209 struct il_rx_queue *rxq = &il->rxq; 4210 u32 r, i; 4211 int reclaim; 4212 unsigned long flags; 4213 u8 fill_rx = 0; 4214 u32 count = 8; 4215 int total_empty; 4216 4217 /* uCode's read idx (stored in shared DRAM) indicates the last Rx 4218 * buffer that the driver may process (last buffer filled by ucode). */ 4219 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; 4220 i = rxq->read; 4221 4222 /* Rx interrupt, but nothing sent from uCode */ 4223 if (i == r) 4224 D_RX("r = %d, i = %d\n", r, i); 4225 4226 /* calculate total frames need to be restock after handling RX */ 4227 total_empty = r - rxq->write_actual; 4228 if (total_empty < 0) 4229 total_empty += RX_QUEUE_SIZE; 4230 4231 if (total_empty > (RX_QUEUE_SIZE / 2)) 4232 fill_rx = 1; 4233 4234 while (i != r) { 4235 int len; 4236 4237 rxb = rxq->queue[i]; 4238 4239 /* If an RXB doesn't have a Rx queue slot associated with it, 4240 * then a bug has been introduced in the queue refilling 4241 * routines -- catch it here */ 4242 BUG_ON(rxb == NULL); 4243 4244 rxq->queue[i] = NULL; 4245 4246 pci_unmap_page(il->pci_dev, rxb->page_dma, 4247 PAGE_SIZE << il->hw_params.rx_page_order, 4248 PCI_DMA_FROMDEVICE); 4249 pkt = rxb_addr(rxb); 4250 4251 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK; 4252 len += sizeof(u32); /* account for status word */ 4253 4254 reclaim = il_need_reclaim(il, pkt); 4255 4256 /* Based on type of command response or notification, 4257 * handle those that need handling via function in 4258 * handlers table. See il4965_setup_handlers() */ 4259 if (il->handlers[pkt->hdr.cmd]) { 4260 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i, 4261 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); 4262 il->isr_stats.handlers[pkt->hdr.cmd]++; 4263 il->handlers[pkt->hdr.cmd] (il, rxb); 4264 } else { 4265 /* No handling needed */ 4266 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r, 4267 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); 4268 } 4269 4270 /* 4271 * XXX: After here, we should always check rxb->page 4272 * against NULL before touching it or its virtual 4273 * memory (pkt). Because some handler might have 4274 * already taken or freed the pages. 4275 */ 4276 4277 if (reclaim) { 4278 /* Invoke any callbacks, transfer the buffer to caller, 4279 * and fire off the (possibly) blocking il_send_cmd() 4280 * as we reclaim the driver command queue */ 4281 if (rxb->page) 4282 il_tx_cmd_complete(il, rxb); 4283 else 4284 IL_WARN("Claim null rxb?\n"); 4285 } 4286 4287 /* Reuse the page if possible. For notification packets and 4288 * SKBs that fail to Rx correctly, add them back into the 4289 * rx_free list for reuse later. */ 4290 spin_lock_irqsave(&rxq->lock, flags); 4291 if (rxb->page != NULL) { 4292 rxb->page_dma = 4293 pci_map_page(il->pci_dev, rxb->page, 0, 4294 PAGE_SIZE << il->hw_params. 4295 rx_page_order, PCI_DMA_FROMDEVICE); 4296 4297 if (unlikely(pci_dma_mapping_error(il->pci_dev, 4298 rxb->page_dma))) { 4299 __il_free_pages(il, rxb->page); 4300 rxb->page = NULL; 4301 list_add_tail(&rxb->list, &rxq->rx_used); 4302 } else { 4303 list_add_tail(&rxb->list, &rxq->rx_free); 4304 rxq->free_count++; 4305 } 4306 } else 4307 list_add_tail(&rxb->list, &rxq->rx_used); 4308 4309 spin_unlock_irqrestore(&rxq->lock, flags); 4310 4311 i = (i + 1) & RX_QUEUE_MASK; 4312 /* If there are a lot of unused frames, 4313 * restock the Rx queue so ucode wont assert. */ 4314 if (fill_rx) { 4315 count++; 4316 if (count >= 8) { 4317 rxq->read = i; 4318 il4965_rx_replenish_now(il); 4319 count = 0; 4320 } 4321 } 4322 } 4323 4324 /* Backtrack one entry */ 4325 rxq->read = i; 4326 if (fill_rx) 4327 il4965_rx_replenish_now(il); 4328 else 4329 il4965_rx_queue_restock(il); 4330} 4331 4332/* call this function to flush any scheduled tasklet */ 4333static inline void 4334il4965_synchronize_irq(struct il_priv *il) 4335{ 4336 /* wait to make sure we flush pending tasklet */ 4337 synchronize_irq(il->pci_dev->irq); 4338 tasklet_kill(&il->irq_tasklet); 4339} 4340 4341static void 4342il4965_irq_tasklet(struct tasklet_struct *t) 4343{ 4344 struct il_priv *il = from_tasklet(il, t, irq_tasklet); 4345 u32 inta, handled = 0; 4346 u32 inta_fh; 4347 unsigned long flags; 4348 u32 i; 4349#ifdef CONFIG_IWLEGACY_DEBUG 4350 u32 inta_mask; 4351#endif 4352 4353 spin_lock_irqsave(&il->lock, flags); 4354 4355 /* Ack/clear/reset pending uCode interrupts. 4356 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 4357 * and will clear only when CSR_FH_INT_STATUS gets cleared. */ 4358 inta = _il_rd(il, CSR_INT); 4359 _il_wr(il, CSR_INT, inta); 4360 4361 /* Ack/clear/reset pending flow-handler (DMA) interrupts. 4362 * Any new interrupts that happen after this, either while we're 4363 * in this tasklet, or later, will show up in next ISR/tasklet. */ 4364 inta_fh = _il_rd(il, CSR_FH_INT_STATUS); 4365 _il_wr(il, CSR_FH_INT_STATUS, inta_fh); 4366 4367#ifdef CONFIG_IWLEGACY_DEBUG 4368 if (il_get_debug_level(il) & IL_DL_ISR) { 4369 /* just for debug */ 4370 inta_mask = _il_rd(il, CSR_INT_MASK); 4371 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, 4372 inta_mask, inta_fh); 4373 } 4374#endif 4375 4376 spin_unlock_irqrestore(&il->lock, flags); 4377 4378 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not 4379 * atomic, make sure that inta covers all the interrupts that 4380 * we've discovered, even if FH interrupt came in just after 4381 * reading CSR_INT. */ 4382 if (inta_fh & CSR49_FH_INT_RX_MASK) 4383 inta |= CSR_INT_BIT_FH_RX; 4384 if (inta_fh & CSR49_FH_INT_TX_MASK) 4385 inta |= CSR_INT_BIT_FH_TX; 4386 4387 /* Now service all interrupt bits discovered above. */ 4388 if (inta & CSR_INT_BIT_HW_ERR) { 4389 IL_ERR("Hardware error detected. Restarting.\n"); 4390 4391 /* Tell the device to stop sending interrupts */ 4392 il_disable_interrupts(il); 4393 4394 il->isr_stats.hw++; 4395 il_irq_handle_error(il); 4396 4397 handled |= CSR_INT_BIT_HW_ERR; 4398 4399 return; 4400 } 4401#ifdef CONFIG_IWLEGACY_DEBUG 4402 if (il_get_debug_level(il) & (IL_DL_ISR)) { 4403 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 4404 if (inta & CSR_INT_BIT_SCD) { 4405 D_ISR("Scheduler finished to transmit " 4406 "the frame/frames.\n"); 4407 il->isr_stats.sch++; 4408 } 4409 4410 /* Alive notification via Rx interrupt will do the real work */ 4411 if (inta & CSR_INT_BIT_ALIVE) { 4412 D_ISR("Alive interrupt\n"); 4413 il->isr_stats.alive++; 4414 } 4415 } 4416#endif 4417 /* Safely ignore these bits for debug checks below */ 4418 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 4419 4420 /* HW RF KILL switch toggled */ 4421 if (inta & CSR_INT_BIT_RF_KILL) { 4422 int hw_rf_kill = 0; 4423 4424 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 4425 hw_rf_kill = 1; 4426 4427 IL_WARN("RF_KILL bit toggled to %s.\n", 4428 hw_rf_kill ? "disable radio" : "enable radio"); 4429 4430 il->isr_stats.rfkill++; 4431 4432 /* driver only loads ucode once setting the interface up. 4433 * the driver allows loading the ucode even if the radio 4434 * is killed. Hence update the killswitch state here. The 4435 * rfkill handler will care about restarting if needed. 4436 */ 4437 if (hw_rf_kill) { 4438 set_bit(S_RFKILL, &il->status); 4439 } else { 4440 clear_bit(S_RFKILL, &il->status); 4441 il_force_reset(il, true); 4442 } 4443 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill); 4444 4445 handled |= CSR_INT_BIT_RF_KILL; 4446 } 4447 4448 /* Chip got too hot and stopped itself */ 4449 if (inta & CSR_INT_BIT_CT_KILL) { 4450 IL_ERR("Microcode CT kill error detected.\n"); 4451 il->isr_stats.ctkill++; 4452 handled |= CSR_INT_BIT_CT_KILL; 4453 } 4454 4455 /* Error detected by uCode */ 4456 if (inta & CSR_INT_BIT_SW_ERR) { 4457 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n", 4458 inta); 4459 il->isr_stats.sw++; 4460 il_irq_handle_error(il); 4461 handled |= CSR_INT_BIT_SW_ERR; 4462 } 4463 4464 /* 4465 * uCode wakes up after power-down sleep. 4466 * Tell device about any new tx or host commands enqueued, 4467 * and about any Rx buffers made available while asleep. 4468 */ 4469 if (inta & CSR_INT_BIT_WAKEUP) { 4470 D_ISR("Wakeup interrupt\n"); 4471 il_rx_queue_update_write_ptr(il, &il->rxq); 4472 for (i = 0; i < il->hw_params.max_txq_num; i++) 4473 il_txq_update_write_ptr(il, &il->txq[i]); 4474 il->isr_stats.wakeup++; 4475 handled |= CSR_INT_BIT_WAKEUP; 4476 } 4477 4478 /* All uCode command responses, including Tx command responses, 4479 * Rx "responses" (frame-received notification), and other 4480 * notifications from uCode come through here*/ 4481 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 4482 il4965_rx_handle(il); 4483 il->isr_stats.rx++; 4484 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 4485 } 4486 4487 /* This "Tx" DMA channel is used only for loading uCode */ 4488 if (inta & CSR_INT_BIT_FH_TX) { 4489 D_ISR("uCode load interrupt\n"); 4490 il->isr_stats.tx++; 4491 handled |= CSR_INT_BIT_FH_TX; 4492 /* Wake up uCode load routine, now that load is complete */ 4493 il->ucode_write_complete = 1; 4494 wake_up(&il->wait_command_queue); 4495 } 4496 4497 if (inta & ~handled) { 4498 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); 4499 il->isr_stats.unhandled++; 4500 } 4501 4502 if (inta & ~(il->inta_mask)) { 4503 IL_WARN("Disabled INTA bits 0x%08x were pending\n", 4504 inta & ~il->inta_mask); 4505 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh); 4506 } 4507 4508 /* Re-enable all interrupts */ 4509 /* only Re-enable if disabled by irq */ 4510 if (test_bit(S_INT_ENABLED, &il->status)) 4511 il_enable_interrupts(il); 4512 /* Re-enable RF_KILL if it occurred */ 4513 else if (handled & CSR_INT_BIT_RF_KILL) 4514 il_enable_rfkill_int(il); 4515 4516#ifdef CONFIG_IWLEGACY_DEBUG 4517 if (il_get_debug_level(il) & (IL_DL_ISR)) { 4518 inta = _il_rd(il, CSR_INT); 4519 inta_mask = _il_rd(il, CSR_INT_MASK); 4520 inta_fh = _il_rd(il, CSR_FH_INT_STATUS); 4521 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " 4522 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); 4523 } 4524#endif 4525} 4526 4527/***************************************************************************** 4528 * 4529 * sysfs attributes 4530 * 4531 *****************************************************************************/ 4532 4533#ifdef CONFIG_IWLEGACY_DEBUG 4534 4535/* 4536 * The following adds a new attribute to the sysfs representation 4537 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) 4538 * used for controlling the debug level. 4539 * 4540 * See the level definitions in iwl for details. 4541 * 4542 * The debug_level being managed using sysfs below is a per device debug 4543 * level that is used instead of the global debug level if it (the per 4544 * device debug level) is set. 4545 */ 4546static ssize_t 4547il4965_show_debug_level(struct device *d, struct device_attribute *attr, 4548 char *buf) 4549{ 4550 struct il_priv *il = dev_get_drvdata(d); 4551 return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); 4552} 4553 4554static ssize_t 4555il4965_store_debug_level(struct device *d, struct device_attribute *attr, 4556 const char *buf, size_t count) 4557{ 4558 struct il_priv *il = dev_get_drvdata(d); 4559 unsigned long val; 4560 int ret; 4561 4562 ret = kstrtoul(buf, 0, &val); 4563 if (ret) 4564 IL_ERR("%s is not in hex or decimal form.\n", buf); 4565 else 4566 il->debug_level = val; 4567 4568 return strnlen(buf, count); 4569} 4570 4571static DEVICE_ATTR(debug_level, 0644, il4965_show_debug_level, 4572 il4965_store_debug_level); 4573 4574#endif /* CONFIG_IWLEGACY_DEBUG */ 4575 4576static ssize_t 4577il4965_show_temperature(struct device *d, struct device_attribute *attr, 4578 char *buf) 4579{ 4580 struct il_priv *il = dev_get_drvdata(d); 4581 4582 if (!il_is_alive(il)) 4583 return -EAGAIN; 4584 4585 return sprintf(buf, "%d\n", il->temperature); 4586} 4587 4588static DEVICE_ATTR(temperature, 0444, il4965_show_temperature, NULL); 4589 4590static ssize_t 4591il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf) 4592{ 4593 struct il_priv *il = dev_get_drvdata(d); 4594 4595 if (!il_is_ready_rf(il)) 4596 return sprintf(buf, "off\n"); 4597 else 4598 return sprintf(buf, "%d\n", il->tx_power_user_lmt); 4599} 4600 4601static ssize_t 4602il4965_store_tx_power(struct device *d, struct device_attribute *attr, 4603 const char *buf, size_t count) 4604{ 4605 struct il_priv *il = dev_get_drvdata(d); 4606 unsigned long val; 4607 int ret; 4608 4609 ret = kstrtoul(buf, 10, &val); 4610 if (ret) 4611 IL_INFO("%s is not in decimal form.\n", buf); 4612 else { 4613 ret = il_set_tx_power(il, val, false); 4614 if (ret) 4615 IL_ERR("failed setting tx power (0x%08x).\n", ret); 4616 else 4617 ret = count; 4618 } 4619 return ret; 4620} 4621 4622static DEVICE_ATTR(tx_power, 0644, il4965_show_tx_power, 4623 il4965_store_tx_power); 4624 4625static struct attribute *il_sysfs_entries[] = { 4626 &dev_attr_temperature.attr, 4627 &dev_attr_tx_power.attr, 4628#ifdef CONFIG_IWLEGACY_DEBUG 4629 &dev_attr_debug_level.attr, 4630#endif 4631 NULL 4632}; 4633 4634static const struct attribute_group il_attribute_group = { 4635 .name = NULL, /* put in device directory */ 4636 .attrs = il_sysfs_entries, 4637}; 4638 4639/****************************************************************************** 4640 * 4641 * uCode download functions 4642 * 4643 ******************************************************************************/ 4644 4645static void 4646il4965_dealloc_ucode_pci(struct il_priv *il) 4647{ 4648 il_free_fw_desc(il->pci_dev, &il->ucode_code); 4649 il_free_fw_desc(il->pci_dev, &il->ucode_data); 4650 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup); 4651 il_free_fw_desc(il->pci_dev, &il->ucode_init); 4652 il_free_fw_desc(il->pci_dev, &il->ucode_init_data); 4653 il_free_fw_desc(il->pci_dev, &il->ucode_boot); 4654} 4655 4656static void 4657il4965_nic_start(struct il_priv *il) 4658{ 4659 /* Remove all resets to allow NIC to operate */ 4660 _il_wr(il, CSR_RESET, 0); 4661} 4662 4663static void il4965_ucode_callback(const struct firmware *ucode_raw, 4664 void *context); 4665static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length); 4666 4667static int __must_check 4668il4965_request_firmware(struct il_priv *il, bool first) 4669{ 4670 const char *name_pre = il->cfg->fw_name_pre; 4671 char tag[8]; 4672 4673 if (first) { 4674 il->fw_idx = il->cfg->ucode_api_max; 4675 sprintf(tag, "%d", il->fw_idx); 4676 } else { 4677 il->fw_idx--; 4678 sprintf(tag, "%d", il->fw_idx); 4679 } 4680 4681 if (il->fw_idx < il->cfg->ucode_api_min) { 4682 IL_ERR("no suitable firmware found!\n"); 4683 return -ENOENT; 4684 } 4685 4686 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); 4687 4688 D_INFO("attempting to load firmware '%s'\n", il->firmware_name); 4689 4690 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name, 4691 &il->pci_dev->dev, GFP_KERNEL, il, 4692 il4965_ucode_callback); 4693} 4694 4695struct il4965_firmware_pieces { 4696 const void *inst, *data, *init, *init_data, *boot; 4697 size_t inst_size, data_size, init_size, init_data_size, boot_size; 4698}; 4699 4700static int 4701il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw, 4702 struct il4965_firmware_pieces *pieces) 4703{ 4704 struct il_ucode_header *ucode = (void *)ucode_raw->data; 4705 u32 api_ver, hdr_size; 4706 const u8 *src; 4707 4708 il->ucode_ver = le32_to_cpu(ucode->ver); 4709 api_ver = IL_UCODE_API(il->ucode_ver); 4710 4711 switch (api_ver) { 4712 default: 4713 case 0: 4714 case 1: 4715 case 2: 4716 hdr_size = 24; 4717 if (ucode_raw->size < hdr_size) { 4718 IL_ERR("File size too small!\n"); 4719 return -EINVAL; 4720 } 4721 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size); 4722 pieces->data_size = le32_to_cpu(ucode->v1.data_size); 4723 pieces->init_size = le32_to_cpu(ucode->v1.init_size); 4724 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size); 4725 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size); 4726 src = ucode->v1.data; 4727 break; 4728 } 4729 4730 /* Verify size of file vs. image size info in file's header */ 4731 if (ucode_raw->size != 4732 hdr_size + pieces->inst_size + pieces->data_size + 4733 pieces->init_size + pieces->init_data_size + pieces->boot_size) { 4734 4735 IL_ERR("uCode file size %d does not match expected size\n", 4736 (int)ucode_raw->size); 4737 return -EINVAL; 4738 } 4739 4740 pieces->inst = src; 4741 src += pieces->inst_size; 4742 pieces->data = src; 4743 src += pieces->data_size; 4744 pieces->init = src; 4745 src += pieces->init_size; 4746 pieces->init_data = src; 4747 src += pieces->init_data_size; 4748 pieces->boot = src; 4749 src += pieces->boot_size; 4750 4751 return 0; 4752} 4753 4754/* 4755 * il4965_ucode_callback - callback when firmware was loaded 4756 * 4757 * If loaded successfully, copies the firmware into buffers 4758 * for the card to fetch (via DMA). 4759 */ 4760static void 4761il4965_ucode_callback(const struct firmware *ucode_raw, void *context) 4762{ 4763 struct il_priv *il = context; 4764 int err; 4765 struct il4965_firmware_pieces pieces; 4766 const unsigned int api_max = il->cfg->ucode_api_max; 4767 const unsigned int api_min = il->cfg->ucode_api_min; 4768 u32 api_ver; 4769 4770 u32 max_probe_length = 200; 4771 u32 standard_phy_calibration_size = 4772 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE; 4773 4774 memset(&pieces, 0, sizeof(pieces)); 4775 4776 if (!ucode_raw) { 4777 if (il->fw_idx <= il->cfg->ucode_api_max) 4778 IL_ERR("request for firmware file '%s' failed.\n", 4779 il->firmware_name); 4780 goto try_again; 4781 } 4782 4783 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name, 4784 ucode_raw->size); 4785 4786 /* Make sure that we got at least the API version number */ 4787 if (ucode_raw->size < 4) { 4788 IL_ERR("File size way too small!\n"); 4789 goto try_again; 4790 } 4791 4792 /* Data from ucode file: header followed by uCode images */ 4793 err = il4965_load_firmware(il, ucode_raw, &pieces); 4794 4795 if (err) 4796 goto try_again; 4797 4798 api_ver = IL_UCODE_API(il->ucode_ver); 4799 4800 /* 4801 * api_ver should match the api version forming part of the 4802 * firmware filename ... but we don't check for that and only rely 4803 * on the API version read from firmware header from here on forward 4804 */ 4805 if (api_ver < api_min || api_ver > api_max) { 4806 IL_ERR("Driver unable to support your firmware API. " 4807 "Driver supports v%u, firmware is v%u.\n", api_max, 4808 api_ver); 4809 goto try_again; 4810 } 4811 4812 if (api_ver != api_max) 4813 IL_ERR("Firmware has old API version. Expected v%u, " 4814 "got v%u. New firmware can be obtained " 4815 "from http://www.intellinuxwireless.org.\n", api_max, 4816 api_ver); 4817 4818 IL_INFO("loaded firmware version %u.%u.%u.%u\n", 4819 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver), 4820 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver)); 4821 4822 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version), 4823 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver), 4824 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver), 4825 IL_UCODE_SERIAL(il->ucode_ver)); 4826 4827 /* 4828 * For any of the failures below (before allocating pci memory) 4829 * we will try to load a version with a smaller API -- maybe the 4830 * user just got a corrupted version of the latest API. 4831 */ 4832 4833 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver); 4834 D_INFO("f/w package hdr runtime inst size = %zd\n", pieces.inst_size); 4835 D_INFO("f/w package hdr runtime data size = %zd\n", pieces.data_size); 4836 D_INFO("f/w package hdr init inst size = %zd\n", pieces.init_size); 4837 D_INFO("f/w package hdr init data size = %zd\n", pieces.init_data_size); 4838 D_INFO("f/w package hdr boot inst size = %zd\n", pieces.boot_size); 4839 4840 /* Verify that uCode images will fit in card's SRAM */ 4841 if (pieces.inst_size > il->hw_params.max_inst_size) { 4842 IL_ERR("uCode instr len %zd too large to fit in\n", 4843 pieces.inst_size); 4844 goto try_again; 4845 } 4846 4847 if (pieces.data_size > il->hw_params.max_data_size) { 4848 IL_ERR("uCode data len %zd too large to fit in\n", 4849 pieces.data_size); 4850 goto try_again; 4851 } 4852 4853 if (pieces.init_size > il->hw_params.max_inst_size) { 4854 IL_ERR("uCode init instr len %zd too large to fit in\n", 4855 pieces.init_size); 4856 goto try_again; 4857 } 4858 4859 if (pieces.init_data_size > il->hw_params.max_data_size) { 4860 IL_ERR("uCode init data len %zd too large to fit in\n", 4861 pieces.init_data_size); 4862 goto try_again; 4863 } 4864 4865 if (pieces.boot_size > il->hw_params.max_bsm_size) { 4866 IL_ERR("uCode boot instr len %zd too large to fit in\n", 4867 pieces.boot_size); 4868 goto try_again; 4869 } 4870 4871 /* Allocate ucode buffers for card's bus-master loading ... */ 4872 4873 /* Runtime instructions and 2 copies of data: 4874 * 1) unmodified from disk 4875 * 2) backup cache for save/restore during power-downs */ 4876 il->ucode_code.len = pieces.inst_size; 4877 il_alloc_fw_desc(il->pci_dev, &il->ucode_code); 4878 4879 il->ucode_data.len = pieces.data_size; 4880 il_alloc_fw_desc(il->pci_dev, &il->ucode_data); 4881 4882 il->ucode_data_backup.len = pieces.data_size; 4883 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup); 4884 4885 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr || 4886 !il->ucode_data_backup.v_addr) 4887 goto err_pci_alloc; 4888 4889 /* Initialization instructions and data */ 4890 if (pieces.init_size && pieces.init_data_size) { 4891 il->ucode_init.len = pieces.init_size; 4892 il_alloc_fw_desc(il->pci_dev, &il->ucode_init); 4893 4894 il->ucode_init_data.len = pieces.init_data_size; 4895 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data); 4896 4897 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr) 4898 goto err_pci_alloc; 4899 } 4900 4901 /* Bootstrap (instructions only, no data) */ 4902 if (pieces.boot_size) { 4903 il->ucode_boot.len = pieces.boot_size; 4904 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot); 4905 4906 if (!il->ucode_boot.v_addr) 4907 goto err_pci_alloc; 4908 } 4909 4910 /* Now that we can no longer fail, copy information */ 4911 4912 il->sta_key_max_num = STA_KEY_MAX_NUM; 4913 4914 /* Copy images into buffers for card's bus-master reads ... */ 4915 4916 /* Runtime instructions (first block of data in file) */ 4917 D_INFO("Copying (but not loading) uCode instr len %zd\n", 4918 pieces.inst_size); 4919 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size); 4920 4921 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", 4922 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr); 4923 4924 /* 4925 * Runtime data 4926 * NOTE: Copy into backup buffer will be done in il_up() 4927 */ 4928 D_INFO("Copying (but not loading) uCode data len %zd\n", 4929 pieces.data_size); 4930 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size); 4931 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size); 4932 4933 /* Initialization instructions */ 4934 if (pieces.init_size) { 4935 D_INFO("Copying (but not loading) init instr len %zd\n", 4936 pieces.init_size); 4937 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size); 4938 } 4939 4940 /* Initialization data */ 4941 if (pieces.init_data_size) { 4942 D_INFO("Copying (but not loading) init data len %zd\n", 4943 pieces.init_data_size); 4944 memcpy(il->ucode_init_data.v_addr, pieces.init_data, 4945 pieces.init_data_size); 4946 } 4947 4948 /* Bootstrap instructions */ 4949 D_INFO("Copying (but not loading) boot instr len %zd\n", 4950 pieces.boot_size); 4951 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size); 4952 4953 /* 4954 * figure out the offset of chain noise reset and gain commands 4955 * base on the size of standard phy calibration commands table size 4956 */ 4957 il->_4965.phy_calib_chain_noise_reset_cmd = 4958 standard_phy_calibration_size; 4959 il->_4965.phy_calib_chain_noise_gain_cmd = 4960 standard_phy_calibration_size + 1; 4961 4962 /************************************************** 4963 * This is still part of probe() in a sense... 4964 * 4965 * 9. Setup and register with mac80211 and debugfs 4966 **************************************************/ 4967 err = il4965_mac_setup_register(il, max_probe_length); 4968 if (err) 4969 goto out_unbind; 4970 4971 il_dbgfs_register(il, DRV_NAME); 4972 4973 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group); 4974 if (err) { 4975 IL_ERR("failed to create sysfs device attributes\n"); 4976 goto out_unbind; 4977 } 4978 4979 /* We have our copies now, allow OS release its copies */ 4980 release_firmware(ucode_raw); 4981 complete(&il->_4965.firmware_loading_complete); 4982 return; 4983 4984try_again: 4985 /* try next, if any */ 4986 if (il4965_request_firmware(il, false)) 4987 goto out_unbind; 4988 release_firmware(ucode_raw); 4989 return; 4990 4991err_pci_alloc: 4992 IL_ERR("failed to allocate pci memory\n"); 4993 il4965_dealloc_ucode_pci(il); 4994out_unbind: 4995 complete(&il->_4965.firmware_loading_complete); 4996 device_release_driver(&il->pci_dev->dev); 4997 release_firmware(ucode_raw); 4998} 4999 5000static const char *const desc_lookup_text[] = { 5001 "OK", 5002 "FAIL", 5003 "BAD_PARAM", 5004 "BAD_CHECKSUM", 5005 "NMI_INTERRUPT_WDG", 5006 "SYSASSERT", 5007 "FATAL_ERROR", 5008 "BAD_COMMAND", 5009 "HW_ERROR_TUNE_LOCK", 5010 "HW_ERROR_TEMPERATURE", 5011 "ILLEGAL_CHAN_FREQ", 5012 "VCC_NOT_STBL", 5013 "FH49_ERROR", 5014 "NMI_INTERRUPT_HOST", 5015 "NMI_INTERRUPT_ACTION_PT", 5016 "NMI_INTERRUPT_UNKNOWN", 5017 "UCODE_VERSION_MISMATCH", 5018 "HW_ERROR_ABS_LOCK", 5019 "HW_ERROR_CAL_LOCK_FAIL", 5020 "NMI_INTERRUPT_INST_ACTION_PT", 5021 "NMI_INTERRUPT_DATA_ACTION_PT", 5022 "NMI_TRM_HW_ER", 5023 "NMI_INTERRUPT_TRM", 5024 "NMI_INTERRUPT_BREAK_POINT", 5025 "DEBUG_0", 5026 "DEBUG_1", 5027 "DEBUG_2", 5028 "DEBUG_3", 5029}; 5030 5031static struct { 5032 char *name; 5033 u8 num; 5034} advanced_lookup[] = { 5035 { 5036 "NMI_INTERRUPT_WDG", 0x34}, { 5037 "SYSASSERT", 0x35}, { 5038 "UCODE_VERSION_MISMATCH", 0x37}, { 5039 "BAD_COMMAND", 0x38}, { 5040 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, { 5041 "FATAL_ERROR", 0x3D}, { 5042 "NMI_TRM_HW_ERR", 0x46}, { 5043 "NMI_INTERRUPT_TRM", 0x4C}, { 5044 "NMI_INTERRUPT_BREAK_POINT", 0x54}, { 5045 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, { 5046 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, { 5047 "NMI_INTERRUPT_HOST", 0x66}, { 5048 "NMI_INTERRUPT_ACTION_PT", 0x7C}, { 5049 "NMI_INTERRUPT_UNKNOWN", 0x84}, { 5050 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, { 5051"ADVANCED_SYSASSERT", 0},}; 5052 5053static const char * 5054il4965_desc_lookup(u32 num) 5055{ 5056 int i; 5057 int max = ARRAY_SIZE(desc_lookup_text); 5058 5059 if (num < max) 5060 return desc_lookup_text[num]; 5061 5062 max = ARRAY_SIZE(advanced_lookup) - 1; 5063 for (i = 0; i < max; i++) { 5064 if (advanced_lookup[i].num == num) 5065 break; 5066 } 5067 return advanced_lookup[i].name; 5068} 5069 5070#define ERROR_START_OFFSET (1 * sizeof(u32)) 5071#define ERROR_ELEM_SIZE (7 * sizeof(u32)) 5072 5073void 5074il4965_dump_nic_error_log(struct il_priv *il) 5075{ 5076 u32 data2, line; 5077 u32 desc, time, count, base, data1; 5078 u32 blink1, blink2, ilink1, ilink2; 5079 u32 pc, hcmd; 5080 5081 if (il->ucode_type == UCODE_INIT) 5082 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr); 5083 else 5084 base = le32_to_cpu(il->card_alive.error_event_table_ptr); 5085 5086 if (!il->ops->is_valid_rtc_data_addr(base)) { 5087 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n", 5088 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); 5089 return; 5090 } 5091 5092 count = il_read_targ_mem(il, base); 5093 5094 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { 5095 IL_ERR("Start IWL Error Log Dump:\n"); 5096 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count); 5097 } 5098 5099 desc = il_read_targ_mem(il, base + 1 * sizeof(u32)); 5100 il->isr_stats.err_code = desc; 5101 pc = il_read_targ_mem(il, base + 2 * sizeof(u32)); 5102 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32)); 5103 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32)); 5104 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32)); 5105 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32)); 5106 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32)); 5107 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32)); 5108 line = il_read_targ_mem(il, base + 9 * sizeof(u32)); 5109 time = il_read_targ_mem(il, base + 11 * sizeof(u32)); 5110 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32)); 5111 5112 IL_ERR("Desc Time " 5113 "data1 data2 line\n"); 5114 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", 5115 il4965_desc_lookup(desc), desc, time, data1, data2, line); 5116 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n"); 5117 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1, 5118 blink2, ilink1, ilink2, hcmd); 5119} 5120 5121static void 5122il4965_rf_kill_ct_config(struct il_priv *il) 5123{ 5124 struct il_ct_kill_config cmd; 5125 unsigned long flags; 5126 int ret = 0; 5127 5128 spin_lock_irqsave(&il->lock, flags); 5129 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, 5130 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 5131 spin_unlock_irqrestore(&il->lock, flags); 5132 5133 cmd.critical_temperature_R = 5134 cpu_to_le32(il->hw_params.ct_kill_threshold); 5135 5136 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd); 5137 if (ret) 5138 IL_ERR("C_CT_KILL_CONFIG failed\n"); 5139 else 5140 D_INFO("C_CT_KILL_CONFIG " "succeeded, " 5141 "critical temperature is %d\n", 5142 il->hw_params.ct_kill_threshold); 5143} 5144 5145static const s8 default_queue_to_tx_fifo[] = { 5146 IL_TX_FIFO_VO, 5147 IL_TX_FIFO_VI, 5148 IL_TX_FIFO_BE, 5149 IL_TX_FIFO_BK, 5150 IL49_CMD_FIFO_NUM, 5151 IL_TX_FIFO_UNUSED, 5152 IL_TX_FIFO_UNUSED, 5153}; 5154 5155#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 5156 5157static int 5158il4965_alive_notify(struct il_priv *il) 5159{ 5160 u32 a; 5161 unsigned long flags; 5162 int i, chan; 5163 u32 reg_val; 5164 5165 spin_lock_irqsave(&il->lock, flags); 5166 5167 /* Clear 4965's internal Tx Scheduler data base */ 5168 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR); 5169 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET; 5170 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4) 5171 il_write_targ_mem(il, a, 0); 5172 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4) 5173 il_write_targ_mem(il, a, 0); 5174 for (; 5175 a < 5176 il->scd_base_addr + 5177 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); 5178 a += 4) 5179 il_write_targ_mem(il, a, 0); 5180 5181 /* Tel 4965 where to find Tx byte count tables */ 5182 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10); 5183 5184 /* Enable DMA channel */ 5185 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++) 5186 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan), 5187 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 5188 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 5189 5190 /* Update FH chicken bits */ 5191 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG); 5192 il_wr(il, FH49_TX_CHICKEN_BITS_REG, 5193 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 5194 5195 /* Disable chain mode for all queues */ 5196 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); 5197 5198 /* Initialize each Tx queue (including the command queue) */ 5199 for (i = 0; i < il->hw_params.max_txq_num; i++) { 5200 5201 /* TFD circular buffer read/write idxes */ 5202 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0); 5203 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); 5204 5205 /* Max Tx Window size for Scheduler-ACK mode */ 5206 il_write_targ_mem(il, 5207 il->scd_base_addr + 5208 IL49_SCD_CONTEXT_QUEUE_OFFSET(i), 5209 (SCD_WIN_SIZE << 5210 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 5211 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 5212 5213 /* Frame limit */ 5214 il_write_targ_mem(il, 5215 il->scd_base_addr + 5216 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) + 5217 sizeof(u32), 5218 (SCD_FRAME_LIMIT << 5219 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 5220 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 5221 5222 } 5223 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK, 5224 (1 << il->hw_params.max_txq_num) - 1); 5225 5226 /* Activate all Tx DMA/FIFO channels */ 5227 il4965_txq_set_sched(il, IL_MASK(0, 6)); 5228 5229 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0); 5230 5231 /* make sure all queue are not stopped */ 5232 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped)); 5233 for (i = 0; i < 4; i++) 5234 atomic_set(&il->queue_stop_count[i], 0); 5235 5236 /* reset to 0 to enable all the queue first */ 5237 il->txq_ctx_active_msk = 0; 5238 /* Map each Tx/cmd queue to its corresponding fifo */ 5239 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7); 5240 5241 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { 5242 int ac = default_queue_to_tx_fifo[i]; 5243 5244 il_txq_ctx_activate(il, i); 5245 5246 if (ac == IL_TX_FIFO_UNUSED) 5247 continue; 5248 5249 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0); 5250 } 5251 5252 spin_unlock_irqrestore(&il->lock, flags); 5253 5254 return 0; 5255} 5256 5257/* 5258 * il4965_alive_start - called after N_ALIVE notification received 5259 * from protocol/runtime uCode (initialization uCode's 5260 * Alive gets handled by il_init_alive_start()). 5261 */ 5262static void 5263il4965_alive_start(struct il_priv *il) 5264{ 5265 int ret = 0; 5266 5267 D_INFO("Runtime Alive received.\n"); 5268 5269 if (il->card_alive.is_valid != UCODE_VALID_OK) { 5270 /* We had an error bringing up the hardware, so take it 5271 * all the way back down so we can try again */ 5272 D_INFO("Alive failed.\n"); 5273 goto restart; 5274 } 5275 5276 /* Initialize uCode has loaded Runtime uCode ... verify inst image. 5277 * This is a paranoid check, because we would not have gotten the 5278 * "runtime" alive if code weren't properly loaded. */ 5279 if (il4965_verify_ucode(il)) { 5280 /* Runtime instruction load was bad; 5281 * take it all the way back down so we can try again */ 5282 D_INFO("Bad runtime uCode load.\n"); 5283 goto restart; 5284 } 5285 5286 ret = il4965_alive_notify(il); 5287 if (ret) { 5288 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret); 5289 goto restart; 5290 } 5291 5292 /* After the ALIVE response, we can send host commands to the uCode */ 5293 set_bit(S_ALIVE, &il->status); 5294 5295 /* Enable watchdog to monitor the driver tx queues */ 5296 il_setup_watchdog(il); 5297 5298 if (il_is_rfkill(il)) 5299 return; 5300 5301 ieee80211_wake_queues(il->hw); 5302 5303 il->active_rate = RATES_MASK; 5304 5305 il_power_update_mode(il, true); 5306 D_INFO("Updated power mode\n"); 5307 5308 if (il_is_associated(il)) { 5309 struct il_rxon_cmd *active_rxon = 5310 (struct il_rxon_cmd *)&il->active; 5311 /* apply any changes in staging */ 5312 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; 5313 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 5314 } else { 5315 /* Initialize our rx_config data */ 5316 il_connection_init_rx_config(il); 5317 5318 if (il->ops->set_rxon_chain) 5319 il->ops->set_rxon_chain(il); 5320 } 5321 5322 /* Configure bluetooth coexistence if enabled */ 5323 il_send_bt_config(il); 5324 5325 il4965_reset_run_time_calib(il); 5326 5327 set_bit(S_READY, &il->status); 5328 5329 /* Configure the adapter for unassociated operation */ 5330 il_commit_rxon(il); 5331 5332 /* At this point, the NIC is initialized and operational */ 5333 il4965_rf_kill_ct_config(il); 5334 5335 D_INFO("ALIVE processing complete.\n"); 5336 wake_up(&il->wait_command_queue); 5337 5338 return; 5339 5340restart: 5341 queue_work(il->workqueue, &il->restart); 5342} 5343 5344static void il4965_cancel_deferred_work(struct il_priv *il); 5345 5346static void 5347__il4965_down(struct il_priv *il) 5348{ 5349 unsigned long flags; 5350 int exit_pending; 5351 5352 D_INFO(DRV_NAME " is going down\n"); 5353 5354 il_scan_cancel_timeout(il, 200); 5355 5356 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status); 5357 5358 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set 5359 * to prevent rearm timer */ 5360 del_timer_sync(&il->watchdog); 5361 5362 il_clear_ucode_stations(il); 5363 5364 /* FIXME: race conditions ? */ 5365 spin_lock_irq(&il->sta_lock); 5366 /* 5367 * Remove all key information that is not stored as part 5368 * of station information since mac80211 may not have had 5369 * a chance to remove all the keys. When device is 5370 * reconfigured by mac80211 after an error all keys will 5371 * be reconfigured. 5372 */ 5373 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys)); 5374 il->_4965.key_mapping_keys = 0; 5375 spin_unlock_irq(&il->sta_lock); 5376 5377 il_dealloc_bcast_stations(il); 5378 il_clear_driver_stations(il); 5379 5380 /* Unblock any waiting calls */ 5381 wake_up_all(&il->wait_command_queue); 5382 5383 /* Wipe out the EXIT_PENDING status bit if we are not actually 5384 * exiting the module */ 5385 if (!exit_pending) 5386 clear_bit(S_EXIT_PENDING, &il->status); 5387 5388 /* stop and reset the on-board processor */ 5389 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 5390 5391 /* tell the device to stop sending interrupts */ 5392 spin_lock_irqsave(&il->lock, flags); 5393 il_disable_interrupts(il); 5394 spin_unlock_irqrestore(&il->lock, flags); 5395 il4965_synchronize_irq(il); 5396 5397 if (il->mac80211_registered) 5398 ieee80211_stop_queues(il->hw); 5399 5400 /* If we have not previously called il_init() then 5401 * clear all bits but the RF Kill bit and return */ 5402 if (!il_is_init(il)) { 5403 il->status = 5404 test_bit(S_RFKILL, &il->status) << S_RFKILL | 5405 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED | 5406 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; 5407 goto exit; 5408 } 5409 5410 /* ...otherwise clear out all the status bits but the RF Kill 5411 * bit and continue taking the NIC down. */ 5412 il->status &= 5413 test_bit(S_RFKILL, &il->status) << S_RFKILL | 5414 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED | 5415 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR | 5416 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; 5417 5418 /* 5419 * We disabled and synchronized interrupt, and priv->mutex is taken, so 5420 * here is the only thread which will program device registers, but 5421 * still have lockdep assertions, so we are taking reg_lock. 5422 */ 5423 spin_lock_irq(&il->reg_lock); 5424 /* FIXME: il_grab_nic_access if rfkill is off ? */ 5425 5426 il4965_txq_ctx_stop(il); 5427 il4965_rxq_stop(il); 5428 /* Power-down device's busmaster DMA clocks */ 5429 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); 5430 udelay(5); 5431 /* Make sure (redundant) we've released our request to stay awake */ 5432 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5433 /* Stop the device, and put it in low power state */ 5434 _il_apm_stop(il); 5435 5436 spin_unlock_irq(&il->reg_lock); 5437 5438 il4965_txq_ctx_unmap(il); 5439exit: 5440 memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); 5441 5442 dev_kfree_skb(il->beacon_skb); 5443 il->beacon_skb = NULL; 5444 5445 /* clear out any free frames */ 5446 il4965_clear_free_frames(il); 5447} 5448 5449static void 5450il4965_down(struct il_priv *il) 5451{ 5452 mutex_lock(&il->mutex); 5453 __il4965_down(il); 5454 mutex_unlock(&il->mutex); 5455 5456 il4965_cancel_deferred_work(il); 5457} 5458 5459 5460static void 5461il4965_set_hw_ready(struct il_priv *il) 5462{ 5463 int ret; 5464 5465 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 5466 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 5467 5468 /* See if we got it */ 5469 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, 5470 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 5471 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 5472 100); 5473 if (ret >= 0) 5474 il->hw_ready = true; 5475 5476 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not"); 5477} 5478 5479static void 5480il4965_prepare_card_hw(struct il_priv *il) 5481{ 5482 int ret; 5483 5484 il->hw_ready = false; 5485 5486 il4965_set_hw_ready(il); 5487 if (il->hw_ready) 5488 return; 5489 5490 /* If HW is not ready, prepare the conditions to check again */ 5491 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE); 5492 5493 ret = 5494 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, 5495 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 5496 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); 5497 5498 /* HW should be ready by now, check again. */ 5499 if (ret != -ETIMEDOUT) 5500 il4965_set_hw_ready(il); 5501} 5502 5503#define MAX_HW_RESTARTS 5 5504 5505static int 5506__il4965_up(struct il_priv *il) 5507{ 5508 int i; 5509 int ret; 5510 5511 if (test_bit(S_EXIT_PENDING, &il->status)) { 5512 IL_WARN("Exit pending; will not bring the NIC up\n"); 5513 return -EIO; 5514 } 5515 5516 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) { 5517 IL_ERR("ucode not available for device bringup\n"); 5518 return -EIO; 5519 } 5520 5521 ret = il4965_alloc_bcast_station(il); 5522 if (ret) { 5523 il_dealloc_bcast_stations(il); 5524 return ret; 5525 } 5526 5527 il4965_prepare_card_hw(il); 5528 if (!il->hw_ready) { 5529 il_dealloc_bcast_stations(il); 5530 IL_ERR("HW not ready\n"); 5531 return -EIO; 5532 } 5533 5534 /* If platform's RF_KILL switch is NOT set to KILL */ 5535 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 5536 clear_bit(S_RFKILL, &il->status); 5537 else { 5538 set_bit(S_RFKILL, &il->status); 5539 wiphy_rfkill_set_hw_state(il->hw->wiphy, true); 5540 5541 il_dealloc_bcast_stations(il); 5542 il_enable_rfkill_int(il); 5543 IL_WARN("Radio disabled by HW RF Kill switch\n"); 5544 return 0; 5545 } 5546 5547 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5548 5549 /* must be initialised before il_hw_nic_init */ 5550 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; 5551 5552 ret = il4965_hw_nic_init(il); 5553 if (ret) { 5554 IL_ERR("Unable to init nic\n"); 5555 il_dealloc_bcast_stations(il); 5556 return ret; 5557 } 5558 5559 /* make sure rfkill handshake bits are cleared */ 5560 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5561 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 5562 5563 /* clear (again), then enable host interrupts */ 5564 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5565 il_enable_interrupts(il); 5566 5567 /* really make sure rfkill handshake bits are cleared */ 5568 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5569 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5570 5571 /* Copy original ucode data image from disk into backup cache. 5572 * This will be used to initialize the on-board processor's 5573 * data SRAM for a clean start when the runtime program first loads. */ 5574 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr, 5575 il->ucode_data.len); 5576 5577 for (i = 0; i < MAX_HW_RESTARTS; i++) { 5578 5579 /* load bootstrap state machine, 5580 * load bootstrap program into processor's memory, 5581 * prepare to load the "initialize" uCode */ 5582 ret = il->ops->load_ucode(il); 5583 5584 if (ret) { 5585 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret); 5586 continue; 5587 } 5588 5589 /* start card; "initialize" will load runtime ucode */ 5590 il4965_nic_start(il); 5591 5592 D_INFO(DRV_NAME " is coming up\n"); 5593 5594 return 0; 5595 } 5596 5597 set_bit(S_EXIT_PENDING, &il->status); 5598 __il4965_down(il); 5599 clear_bit(S_EXIT_PENDING, &il->status); 5600 5601 /* tried to restart and config the device for as long as our 5602 * patience could withstand */ 5603 IL_ERR("Unable to initialize device after %d attempts.\n", i); 5604 return -EIO; 5605} 5606 5607/***************************************************************************** 5608 * 5609 * Workqueue callbacks 5610 * 5611 *****************************************************************************/ 5612 5613static void 5614il4965_bg_init_alive_start(struct work_struct *data) 5615{ 5616 struct il_priv *il = 5617 container_of(data, struct il_priv, init_alive_start.work); 5618 5619 mutex_lock(&il->mutex); 5620 if (test_bit(S_EXIT_PENDING, &il->status)) 5621 goto out; 5622 5623 il->ops->init_alive_start(il); 5624out: 5625 mutex_unlock(&il->mutex); 5626} 5627 5628static void 5629il4965_bg_alive_start(struct work_struct *data) 5630{ 5631 struct il_priv *il = 5632 container_of(data, struct il_priv, alive_start.work); 5633 5634 mutex_lock(&il->mutex); 5635 if (test_bit(S_EXIT_PENDING, &il->status)) 5636 goto out; 5637 5638 il4965_alive_start(il); 5639out: 5640 mutex_unlock(&il->mutex); 5641} 5642 5643static void 5644il4965_bg_run_time_calib_work(struct work_struct *work) 5645{ 5646 struct il_priv *il = container_of(work, struct il_priv, 5647 run_time_calib_work); 5648 5649 mutex_lock(&il->mutex); 5650 5651 if (test_bit(S_EXIT_PENDING, &il->status) || 5652 test_bit(S_SCANNING, &il->status)) { 5653 mutex_unlock(&il->mutex); 5654 return; 5655 } 5656 5657 if (il->start_calib) { 5658 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats); 5659 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats); 5660 } 5661 5662 mutex_unlock(&il->mutex); 5663} 5664 5665static void 5666il4965_bg_restart(struct work_struct *data) 5667{ 5668 struct il_priv *il = container_of(data, struct il_priv, restart); 5669 5670 if (test_bit(S_EXIT_PENDING, &il->status)) 5671 return; 5672 5673 if (test_and_clear_bit(S_FW_ERROR, &il->status)) { 5674 mutex_lock(&il->mutex); 5675 il->is_open = 0; 5676 5677 __il4965_down(il); 5678 5679 mutex_unlock(&il->mutex); 5680 il4965_cancel_deferred_work(il); 5681 ieee80211_restart_hw(il->hw); 5682 } else { 5683 il4965_down(il); 5684 5685 mutex_lock(&il->mutex); 5686 if (test_bit(S_EXIT_PENDING, &il->status)) { 5687 mutex_unlock(&il->mutex); 5688 return; 5689 } 5690 5691 __il4965_up(il); 5692 mutex_unlock(&il->mutex); 5693 } 5694} 5695 5696static void 5697il4965_bg_rx_replenish(struct work_struct *data) 5698{ 5699 struct il_priv *il = container_of(data, struct il_priv, rx_replenish); 5700 5701 if (test_bit(S_EXIT_PENDING, &il->status)) 5702 return; 5703 5704 mutex_lock(&il->mutex); 5705 il4965_rx_replenish(il); 5706 mutex_unlock(&il->mutex); 5707} 5708 5709/***************************************************************************** 5710 * 5711 * mac80211 entry point functions 5712 * 5713 *****************************************************************************/ 5714 5715#define UCODE_READY_TIMEOUT (4 * HZ) 5716 5717/* 5718 * Not a mac80211 entry point function, but it fits in with all the 5719 * other mac80211 functions grouped here. 5720 */ 5721static int 5722il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length) 5723{ 5724 int ret; 5725 struct ieee80211_hw *hw = il->hw; 5726 5727 hw->rate_control_algorithm = "iwl-4965-rs"; 5728 5729 /* Tell mac80211 our characteristics */ 5730 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5731 ieee80211_hw_set(hw, SUPPORTS_PS); 5732 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5733 ieee80211_hw_set(hw, SPECTRUM_MGMT); 5734 ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC); 5735 ieee80211_hw_set(hw, SIGNAL_DBM); 5736 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5737 if (il->cfg->sku & IL_SKU_N) 5738 hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS | 5739 NL80211_FEATURE_STATIC_SMPS; 5740 5741 hw->sta_data_size = sizeof(struct il_station_priv); 5742 hw->vif_data_size = sizeof(struct il_vif_priv); 5743 5744 hw->wiphy->interface_modes = 5745 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC); 5746 5747 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 5748 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG | 5749 REGULATORY_DISABLE_BEACON_HINTS; 5750 5751 /* 5752 * For now, disable PS by default because it affects 5753 * RX performance significantly. 5754 */ 5755 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 5756 5757 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; 5758 /* we create the 802.11 header and a zero-length SSID element */ 5759 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2; 5760 5761 /* Default value; 4 EDCA QOS priorities */ 5762 hw->queues = 4; 5763 5764 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL; 5765 5766 if (il->bands[NL80211_BAND_2GHZ].n_channels) 5767 il->hw->wiphy->bands[NL80211_BAND_2GHZ] = 5768 &il->bands[NL80211_BAND_2GHZ]; 5769 if (il->bands[NL80211_BAND_5GHZ].n_channels) 5770 il->hw->wiphy->bands[NL80211_BAND_5GHZ] = 5771 &il->bands[NL80211_BAND_5GHZ]; 5772 5773 il_leds_init(il); 5774 5775 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 5776 5777 ret = ieee80211_register_hw(il->hw); 5778 if (ret) { 5779 IL_ERR("Failed to register hw (error %d)\n", ret); 5780 return ret; 5781 } 5782 il->mac80211_registered = 1; 5783 5784 return 0; 5785} 5786 5787int 5788il4965_mac_start(struct ieee80211_hw *hw) 5789{ 5790 struct il_priv *il = hw->priv; 5791 int ret; 5792 5793 D_MAC80211("enter\n"); 5794 5795 /* we should be verifying the device is ready to be opened */ 5796 mutex_lock(&il->mutex); 5797 ret = __il4965_up(il); 5798 mutex_unlock(&il->mutex); 5799 5800 if (ret) 5801 return ret; 5802 5803 if (il_is_rfkill(il)) 5804 goto out; 5805 5806 D_INFO("Start UP work done.\n"); 5807 5808 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from 5809 * mac80211 will not be run successfully. */ 5810 ret = wait_event_timeout(il->wait_command_queue, 5811 test_bit(S_READY, &il->status), 5812 UCODE_READY_TIMEOUT); 5813 if (!ret) { 5814 if (!test_bit(S_READY, &il->status)) { 5815 IL_ERR("START_ALIVE timeout after %dms.\n", 5816 jiffies_to_msecs(UCODE_READY_TIMEOUT)); 5817 return -ETIMEDOUT; 5818 } 5819 } 5820 5821 il4965_led_enable(il); 5822 5823out: 5824 il->is_open = 1; 5825 D_MAC80211("leave\n"); 5826 return 0; 5827} 5828 5829void 5830il4965_mac_stop(struct ieee80211_hw *hw) 5831{ 5832 struct il_priv *il = hw->priv; 5833 5834 D_MAC80211("enter\n"); 5835 5836 if (!il->is_open) 5837 return; 5838 5839 il->is_open = 0; 5840 5841 il4965_down(il); 5842 5843 flush_workqueue(il->workqueue); 5844 5845 /* User space software may expect getting rfkill changes 5846 * even if interface is down */ 5847 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5848 il_enable_rfkill_int(il); 5849 5850 D_MAC80211("leave\n"); 5851} 5852 5853void 5854il4965_mac_tx(struct ieee80211_hw *hw, 5855 struct ieee80211_tx_control *control, 5856 struct sk_buff *skb) 5857{ 5858 struct il_priv *il = hw->priv; 5859 5860 D_MACDUMP("enter\n"); 5861 5862 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, 5863 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); 5864 5865 if (il4965_tx_skb(il, control->sta, skb)) 5866 dev_kfree_skb_any(skb); 5867 5868 D_MACDUMP("leave\n"); 5869} 5870 5871void 5872il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5873 struct ieee80211_key_conf *keyconf, 5874 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key) 5875{ 5876 struct il_priv *il = hw->priv; 5877 5878 D_MAC80211("enter\n"); 5879 5880 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key); 5881 5882 D_MAC80211("leave\n"); 5883} 5884 5885int 5886il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 5887 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 5888 struct ieee80211_key_conf *key) 5889{ 5890 struct il_priv *il = hw->priv; 5891 int ret; 5892 u8 sta_id; 5893 bool is_default_wep_key = false; 5894 5895 D_MAC80211("enter\n"); 5896 5897 if (il->cfg->mod_params->sw_crypto) { 5898 D_MAC80211("leave - hwcrypto disabled\n"); 5899 return -EOPNOTSUPP; 5900 } 5901 5902 /* 5903 * To support IBSS RSN, don't program group keys in IBSS, the 5904 * hardware will then not attempt to decrypt the frames. 5905 */ 5906 if (vif->type == NL80211_IFTYPE_ADHOC && 5907 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 5908 D_MAC80211("leave - ad-hoc group key\n"); 5909 return -EOPNOTSUPP; 5910 } 5911 5912 sta_id = il_sta_id_or_broadcast(il, sta); 5913 if (sta_id == IL_INVALID_STATION) 5914 return -EINVAL; 5915 5916 mutex_lock(&il->mutex); 5917 il_scan_cancel_timeout(il, 100); 5918 5919 /* 5920 * If we are getting WEP group key and we didn't receive any key mapping 5921 * so far, we are in legacy wep mode (group key only), otherwise we are 5922 * in 1X mode. 5923 * In legacy wep mode, we use another host command to the uCode. 5924 */ 5925 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || 5926 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) { 5927 if (cmd == SET_KEY) 5928 is_default_wep_key = !il->_4965.key_mapping_keys; 5929 else 5930 is_default_wep_key = 5931 (key->hw_key_idx == HW_KEY_DEFAULT); 5932 } 5933 5934 switch (cmd) { 5935 case SET_KEY: 5936 if (is_default_wep_key) 5937 ret = il4965_set_default_wep_key(il, key); 5938 else 5939 ret = il4965_set_dynamic_key(il, key, sta_id); 5940 5941 D_MAC80211("enable hwcrypto key\n"); 5942 break; 5943 case DISABLE_KEY: 5944 if (is_default_wep_key) 5945 ret = il4965_remove_default_wep_key(il, key); 5946 else 5947 ret = il4965_remove_dynamic_key(il, key, sta_id); 5948 5949 D_MAC80211("disable hwcrypto key\n"); 5950 break; 5951 default: 5952 ret = -EINVAL; 5953 } 5954 5955 mutex_unlock(&il->mutex); 5956 D_MAC80211("leave\n"); 5957 5958 return ret; 5959} 5960 5961int 5962il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5963 struct ieee80211_ampdu_params *params) 5964{ 5965 struct il_priv *il = hw->priv; 5966 int ret = -EINVAL; 5967 struct ieee80211_sta *sta = params->sta; 5968 enum ieee80211_ampdu_mlme_action action = params->action; 5969 u16 tid = params->tid; 5970 u16 *ssn = ¶ms->ssn; 5971 5972 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid); 5973 5974 if (!(il->cfg->sku & IL_SKU_N)) 5975 return -EACCES; 5976 5977 mutex_lock(&il->mutex); 5978 5979 switch (action) { 5980 case IEEE80211_AMPDU_RX_START: 5981 D_HT("start Rx\n"); 5982 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn); 5983 break; 5984 case IEEE80211_AMPDU_RX_STOP: 5985 D_HT("stop Rx\n"); 5986 ret = il4965_sta_rx_agg_stop(il, sta, tid); 5987 if (test_bit(S_EXIT_PENDING, &il->status)) 5988 ret = 0; 5989 break; 5990 case IEEE80211_AMPDU_TX_START: 5991 D_HT("start Tx\n"); 5992 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn); 5993 break; 5994 case IEEE80211_AMPDU_TX_STOP_CONT: 5995 case IEEE80211_AMPDU_TX_STOP_FLUSH: 5996 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 5997 D_HT("stop Tx\n"); 5998 ret = il4965_tx_agg_stop(il, vif, sta, tid); 5999 if (test_bit(S_EXIT_PENDING, &il->status)) 6000 ret = 0; 6001 break; 6002 case IEEE80211_AMPDU_TX_OPERATIONAL: 6003 ret = 0; 6004 break; 6005 } 6006 mutex_unlock(&il->mutex); 6007 6008 return ret; 6009} 6010 6011int 6012il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6013 struct ieee80211_sta *sta) 6014{ 6015 struct il_priv *il = hw->priv; 6016 struct il_station_priv *sta_priv = (void *)sta->drv_priv; 6017 bool is_ap = vif->type == NL80211_IFTYPE_STATION; 6018 int ret; 6019 u8 sta_id; 6020 6021 D_INFO("received request to add station %pM\n", sta->addr); 6022 mutex_lock(&il->mutex); 6023 D_INFO("proceeding to add station %pM\n", sta->addr); 6024 sta_priv->common.sta_id = IL_INVALID_STATION; 6025 6026 atomic_set(&sta_priv->pending_frames, 0); 6027 6028 ret = 6029 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id); 6030 if (ret) { 6031 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret); 6032 /* Should we return success if return code is EEXIST ? */ 6033 mutex_unlock(&il->mutex); 6034 return ret; 6035 } 6036 6037 sta_priv->common.sta_id = sta_id; 6038 6039 /* Initialize rate scaling */ 6040 D_INFO("Initializing rate scaling for station %pM\n", sta->addr); 6041 il4965_rs_rate_init(il, sta, sta_id); 6042 mutex_unlock(&il->mutex); 6043 6044 return 0; 6045} 6046 6047void 6048il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6049 struct ieee80211_channel_switch *ch_switch) 6050{ 6051 struct il_priv *il = hw->priv; 6052 const struct il_channel_info *ch_info; 6053 struct ieee80211_conf *conf = &hw->conf; 6054 struct ieee80211_channel *channel = ch_switch->chandef.chan; 6055 struct il_ht_config *ht_conf = &il->current_ht_config; 6056 u16 ch; 6057 6058 D_MAC80211("enter\n"); 6059 6060 mutex_lock(&il->mutex); 6061 6062 if (il_is_rfkill(il)) 6063 goto out; 6064 6065 if (test_bit(S_EXIT_PENDING, &il->status) || 6066 test_bit(S_SCANNING, &il->status) || 6067 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) 6068 goto out; 6069 6070 if (!il_is_associated(il)) 6071 goto out; 6072 6073 if (!il->ops->set_channel_switch) 6074 goto out; 6075 6076 ch = channel->hw_value; 6077 if (le16_to_cpu(il->active.channel) == ch) 6078 goto out; 6079 6080 ch_info = il_get_channel_info(il, channel->band, ch); 6081 if (!il_is_channel_valid(ch_info)) { 6082 D_MAC80211("invalid channel\n"); 6083 goto out; 6084 } 6085 6086 spin_lock_irq(&il->lock); 6087 6088 il->current_ht_config.smps = conf->smps_mode; 6089 6090 /* Configure HT40 channels */ 6091 switch (cfg80211_get_chandef_type(&ch_switch->chandef)) { 6092 case NL80211_CHAN_NO_HT: 6093 case NL80211_CHAN_HT20: 6094 il->ht.is_40mhz = false; 6095 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE; 6096 break; 6097 case NL80211_CHAN_HT40MINUS: 6098 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW; 6099 il->ht.is_40mhz = true; 6100 break; 6101 case NL80211_CHAN_HT40PLUS: 6102 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE; 6103 il->ht.is_40mhz = true; 6104 break; 6105 } 6106 6107 if ((le16_to_cpu(il->staging.channel) != ch)) 6108 il->staging.flags = 0; 6109 6110 il_set_rxon_channel(il, channel); 6111 il_set_rxon_ht(il, ht_conf); 6112 il_set_flags_for_band(il, channel->band, il->vif); 6113 6114 spin_unlock_irq(&il->lock); 6115 6116 il_set_rate(il); 6117 /* 6118 * at this point, staging_rxon has the 6119 * configuration for channel switch 6120 */ 6121 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status); 6122 il->switch_channel = cpu_to_le16(ch); 6123 if (il->ops->set_channel_switch(il, ch_switch)) { 6124 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status); 6125 il->switch_channel = 0; 6126 ieee80211_chswitch_done(il->vif, false); 6127 } 6128 6129out: 6130 mutex_unlock(&il->mutex); 6131 D_MAC80211("leave\n"); 6132} 6133 6134void 6135il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, 6136 unsigned int *total_flags, u64 multicast) 6137{ 6138 struct il_priv *il = hw->priv; 6139 __le32 filter_or = 0, filter_nand = 0; 6140 6141#define CHK(test, flag) do { \ 6142 if (*total_flags & (test)) \ 6143 filter_or |= (flag); \ 6144 else \ 6145 filter_nand |= (flag); \ 6146 } while (0) 6147 6148 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags, 6149 *total_flags); 6150 6151 CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK); 6152 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ 6153 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); 6154 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); 6155 6156#undef CHK 6157 6158 mutex_lock(&il->mutex); 6159 6160 il->staging.filter_flags &= ~filter_nand; 6161 il->staging.filter_flags |= filter_or; 6162 6163 /* 6164 * Not committing directly because hardware can perform a scan, 6165 * but we'll eventually commit the filter flags change anyway. 6166 */ 6167 6168 mutex_unlock(&il->mutex); 6169 6170 /* 6171 * Receiving all multicast frames is always enabled by the 6172 * default flags setup in il_connection_init_rx_config() 6173 * since we currently do not support programming multicast 6174 * filters into the device. 6175 */ 6176 *total_flags &= 6177 FIF_OTHER_BSS | FIF_ALLMULTI | 6178 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; 6179} 6180 6181/***************************************************************************** 6182 * 6183 * driver setup and teardown 6184 * 6185 *****************************************************************************/ 6186 6187static void 6188il4965_bg_txpower_work(struct work_struct *work) 6189{ 6190 struct il_priv *il = container_of(work, struct il_priv, 6191 txpower_work); 6192 6193 mutex_lock(&il->mutex); 6194 6195 /* If a scan happened to start before we got here 6196 * then just return; the stats notification will 6197 * kick off another scheduled work to compensate for 6198 * any temperature delta we missed here. */ 6199 if (test_bit(S_EXIT_PENDING, &il->status) || 6200 test_bit(S_SCANNING, &il->status)) 6201 goto out; 6202 6203 /* Regardless of if we are associated, we must reconfigure the 6204 * TX power since frames can be sent on non-radar channels while 6205 * not associated */ 6206 il->ops->send_tx_power(il); 6207 6208 /* Update last_temperature to keep is_calib_needed from running 6209 * when it isn't needed... */ 6210 il->last_temperature = il->temperature; 6211out: 6212 mutex_unlock(&il->mutex); 6213} 6214 6215static int 6216il4965_setup_deferred_work(struct il_priv *il) 6217{ 6218 il->workqueue = create_singlethread_workqueue(DRV_NAME); 6219 if (!il->workqueue) 6220 return -ENOMEM; 6221 6222 init_waitqueue_head(&il->wait_command_queue); 6223 6224 INIT_WORK(&il->restart, il4965_bg_restart); 6225 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish); 6226 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work); 6227 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start); 6228 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start); 6229 6230 il_setup_scan_deferred_work(il); 6231 6232 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work); 6233 6234 timer_setup(&il->stats_periodic, il4965_bg_stats_periodic, 0); 6235 6236 timer_setup(&il->watchdog, il_bg_watchdog, 0); 6237 6238 tasklet_setup(&il->irq_tasklet, il4965_irq_tasklet); 6239 6240 return 0; 6241} 6242 6243static void 6244il4965_cancel_deferred_work(struct il_priv *il) 6245{ 6246 cancel_work_sync(&il->txpower_work); 6247 cancel_delayed_work_sync(&il->init_alive_start); 6248 cancel_delayed_work(&il->alive_start); 6249 cancel_work_sync(&il->run_time_calib_work); 6250 6251 il_cancel_scan_deferred_work(il); 6252 6253 del_timer_sync(&il->stats_periodic); 6254} 6255 6256static void 6257il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates) 6258{ 6259 int i; 6260 6261 for (i = 0; i < RATE_COUNT_LEGACY; i++) { 6262 rates[i].bitrate = il_rates[i].ieee * 5; 6263 rates[i].hw_value = i; /* Rate scaling will work on idxes */ 6264 rates[i].hw_value_short = i; 6265 rates[i].flags = 0; 6266 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) { 6267 /* 6268 * If CCK != 1M then set short preamble rate flag. 6269 */ 6270 rates[i].flags |= 6271 (il_rates[i].plcp == 6272 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE; 6273 } 6274 } 6275} 6276 6277/* 6278 * Acquire il->lock before calling this function ! 6279 */ 6280void 6281il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx) 6282{ 6283 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8)); 6284 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx); 6285} 6286 6287void 6288il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, 6289 int tx_fifo_id, int scd_retry) 6290{ 6291 int txq_id = txq->q.id; 6292 6293 /* Find out whether to activate Tx queue */ 6294 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0; 6295 6296 /* Set up and activate */ 6297 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), 6298 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 6299 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) | 6300 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) | 6301 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) | 6302 IL49_SCD_QUEUE_STTS_REG_MSK); 6303 6304 txq->sched_retry = scd_retry; 6305 6306 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate", 6307 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 6308} 6309 6310static const struct ieee80211_ops il4965_mac_ops = { 6311 .tx = il4965_mac_tx, 6312 .start = il4965_mac_start, 6313 .stop = il4965_mac_stop, 6314 .add_interface = il_mac_add_interface, 6315 .remove_interface = il_mac_remove_interface, 6316 .change_interface = il_mac_change_interface, 6317 .config = il_mac_config, 6318 .configure_filter = il4965_configure_filter, 6319 .set_key = il4965_mac_set_key, 6320 .update_tkip_key = il4965_mac_update_tkip_key, 6321 .conf_tx = il_mac_conf_tx, 6322 .reset_tsf = il_mac_reset_tsf, 6323 .bss_info_changed = il_mac_bss_info_changed, 6324 .ampdu_action = il4965_mac_ampdu_action, 6325 .hw_scan = il_mac_hw_scan, 6326 .sta_add = il4965_mac_sta_add, 6327 .sta_remove = il_mac_sta_remove, 6328 .channel_switch = il4965_mac_channel_switch, 6329 .tx_last_beacon = il_mac_tx_last_beacon, 6330 .flush = il_mac_flush, 6331}; 6332 6333static int 6334il4965_init_drv(struct il_priv *il) 6335{ 6336 int ret; 6337 6338 spin_lock_init(&il->sta_lock); 6339 spin_lock_init(&il->hcmd_lock); 6340 6341 INIT_LIST_HEAD(&il->free_frames); 6342 6343 mutex_init(&il->mutex); 6344 6345 il->ieee_channels = NULL; 6346 il->ieee_rates = NULL; 6347 il->band = NL80211_BAND_2GHZ; 6348 6349 il->iw_mode = NL80211_IFTYPE_STATION; 6350 il->current_ht_config.smps = IEEE80211_SMPS_STATIC; 6351 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF; 6352 6353 /* initialize force reset */ 6354 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD; 6355 6356 /* Choose which receivers/antennas to use */ 6357 if (il->ops->set_rxon_chain) 6358 il->ops->set_rxon_chain(il); 6359 6360 il_init_scan_params(il); 6361 6362 ret = il_init_channel_map(il); 6363 if (ret) { 6364 IL_ERR("initializing regulatory failed: %d\n", ret); 6365 goto err; 6366 } 6367 6368 ret = il_init_geos(il); 6369 if (ret) { 6370 IL_ERR("initializing geos failed: %d\n", ret); 6371 goto err_free_channel_map; 6372 } 6373 il4965_init_hw_rates(il, il->ieee_rates); 6374 6375 return 0; 6376 6377err_free_channel_map: 6378 il_free_channel_map(il); 6379err: 6380 return ret; 6381} 6382 6383static void 6384il4965_uninit_drv(struct il_priv *il) 6385{ 6386 il_free_geos(il); 6387 il_free_channel_map(il); 6388 kfree(il->scan_cmd); 6389} 6390 6391static void 6392il4965_hw_detect(struct il_priv *il) 6393{ 6394 il->hw_rev = _il_rd(il, CSR_HW_REV); 6395 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG); 6396 il->rev_id = il->pci_dev->revision; 6397 D_INFO("HW Revision ID = 0x%X\n", il->rev_id); 6398} 6399 6400static const struct il_sensitivity_ranges il4965_sensitivity = { 6401 .min_nrg_cck = 97, 6402 .max_nrg_cck = 0, /* not used, set to 0 */ 6403 6404 .auto_corr_min_ofdm = 85, 6405 .auto_corr_min_ofdm_mrc = 170, 6406 .auto_corr_min_ofdm_x1 = 105, 6407 .auto_corr_min_ofdm_mrc_x1 = 220, 6408 6409 .auto_corr_max_ofdm = 120, 6410 .auto_corr_max_ofdm_mrc = 210, 6411 .auto_corr_max_ofdm_x1 = 140, 6412 .auto_corr_max_ofdm_mrc_x1 = 270, 6413 6414 .auto_corr_min_cck = 125, 6415 .auto_corr_max_cck = 200, 6416 .auto_corr_min_cck_mrc = 200, 6417 .auto_corr_max_cck_mrc = 400, 6418 6419 .nrg_th_cck = 100, 6420 .nrg_th_ofdm = 100, 6421 6422 .barker_corr_th_min = 190, 6423 .barker_corr_th_min_mrc = 390, 6424 .nrg_th_cca = 62, 6425}; 6426 6427static void 6428il4965_set_hw_params(struct il_priv *il) 6429{ 6430 il->hw_params.bcast_id = IL4965_BROADCAST_ID; 6431 il->hw_params.max_rxq_size = RX_QUEUE_SIZE; 6432 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 6433 if (il->cfg->mod_params->amsdu_size_8K) 6434 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K); 6435 else 6436 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K); 6437 6438 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL; 6439 6440 if (il->cfg->mod_params->disable_11n) 6441 il->cfg->sku &= ~IL_SKU_N; 6442 6443 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES && 6444 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES) 6445 il->cfg->num_of_queues = 6446 il->cfg->mod_params->num_of_queues; 6447 6448 il->hw_params.max_txq_num = il->cfg->num_of_queues; 6449 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM; 6450 il->hw_params.scd_bc_tbls_size = 6451 il->cfg->num_of_queues * 6452 sizeof(struct il4965_scd_bc_tbl); 6453 6454 il->hw_params.tfd_size = sizeof(struct il_tfd); 6455 il->hw_params.max_stations = IL4965_STATION_COUNT; 6456 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE; 6457 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE; 6458 il->hw_params.max_bsm_size = BSM_SRAM_SIZE; 6459 il->hw_params.ht40_channel = BIT(NL80211_BAND_5GHZ); 6460 6461 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR; 6462 6463 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant); 6464 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant); 6465 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant; 6466 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant; 6467 6468 il->hw_params.ct_kill_threshold = 6469 celsius_to_kelvin(CT_KILL_THRESHOLD_LEGACY); 6470 6471 il->hw_params.sens = &il4965_sensitivity; 6472 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS; 6473} 6474 6475static int 6476il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 6477{ 6478 int err = 0; 6479 struct il_priv *il; 6480 struct ieee80211_hw *hw; 6481 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data); 6482 unsigned long flags; 6483 u16 pci_cmd; 6484 6485 /************************ 6486 * 1. Allocating HW data 6487 ************************/ 6488 6489 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops); 6490 if (!hw) { 6491 err = -ENOMEM; 6492 goto out; 6493 } 6494 il = hw->priv; 6495 il->hw = hw; 6496 SET_IEEE80211_DEV(hw, &pdev->dev); 6497 6498 D_INFO("*** LOAD DRIVER ***\n"); 6499 il->cfg = cfg; 6500 il->ops = &il4965_ops; 6501#ifdef CONFIG_IWLEGACY_DEBUGFS 6502 il->debugfs_ops = &il4965_debugfs_ops; 6503#endif 6504 il->pci_dev = pdev; 6505 il->inta_mask = CSR_INI_SET_MASK; 6506 6507 /************************** 6508 * 2. Initializing PCI bus 6509 **************************/ 6510 pci_disable_link_state(pdev, 6511 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | 6512 PCIE_LINK_STATE_CLKPM); 6513 6514 if (pci_enable_device(pdev)) { 6515 err = -ENODEV; 6516 goto out_ieee80211_free_hw; 6517 } 6518 6519 pci_set_master(pdev); 6520 6521 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); 6522 if (!err) 6523 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); 6524 if (err) { 6525 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 6526 if (!err) 6527 err = 6528 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 6529 /* both attempts failed: */ 6530 if (err) { 6531 IL_WARN("No suitable DMA available.\n"); 6532 goto out_pci_disable_device; 6533 } 6534 } 6535 6536 err = pci_request_regions(pdev, DRV_NAME); 6537 if (err) 6538 goto out_pci_disable_device; 6539 6540 pci_set_drvdata(pdev, il); 6541 6542 /*********************** 6543 * 3. Read REV register 6544 ***********************/ 6545 il->hw_base = pci_ioremap_bar(pdev, 0); 6546 if (!il->hw_base) { 6547 err = -ENODEV; 6548 goto out_pci_release_regions; 6549 } 6550 6551 D_INFO("pci_resource_len = 0x%08llx\n", 6552 (unsigned long long)pci_resource_len(pdev, 0)); 6553 D_INFO("pci_resource_base = %p\n", il->hw_base); 6554 6555 /* these spin locks will be used in apm_ops.init and EEPROM access 6556 * we should init now 6557 */ 6558 spin_lock_init(&il->reg_lock); 6559 spin_lock_init(&il->lock); 6560 6561 /* 6562 * stop and reset the on-board processor just in case it is in a 6563 * strange state ... like being left stranded by a primary kernel 6564 * and this is now the kdump kernel trying to start up 6565 */ 6566 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 6567 6568 il4965_hw_detect(il); 6569 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev); 6570 6571 /* We disable the RETRY_TIMEOUT register (0x41) to keep 6572 * PCI Tx retries from interfering with C3 CPU state */ 6573 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 6574 6575 il4965_prepare_card_hw(il); 6576 if (!il->hw_ready) { 6577 IL_WARN("Failed, HW not ready\n"); 6578 err = -EIO; 6579 goto out_iounmap; 6580 } 6581 6582 /***************** 6583 * 4. Read EEPROM 6584 *****************/ 6585 /* Read the EEPROM */ 6586 err = il_eeprom_init(il); 6587 if (err) { 6588 IL_ERR("Unable to init EEPROM\n"); 6589 goto out_iounmap; 6590 } 6591 err = il4965_eeprom_check_version(il); 6592 if (err) 6593 goto out_free_eeprom; 6594 6595 /* extract MAC Address */ 6596 il4965_eeprom_get_mac(il, il->addresses[0].addr); 6597 D_INFO("MAC address: %pM\n", il->addresses[0].addr); 6598 il->hw->wiphy->addresses = il->addresses; 6599 il->hw->wiphy->n_addresses = 1; 6600 6601 /************************ 6602 * 5. Setup HW constants 6603 ************************/ 6604 il4965_set_hw_params(il); 6605 6606 /******************* 6607 * 6. Setup il 6608 *******************/ 6609 6610 err = il4965_init_drv(il); 6611 if (err) 6612 goto out_free_eeprom; 6613 /* At this point both hw and il are initialized. */ 6614 6615 /******************** 6616 * 7. Setup services 6617 ********************/ 6618 spin_lock_irqsave(&il->lock, flags); 6619 il_disable_interrupts(il); 6620 spin_unlock_irqrestore(&il->lock, flags); 6621 6622 pci_enable_msi(il->pci_dev); 6623 6624 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il); 6625 if (err) { 6626 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq); 6627 goto out_disable_msi; 6628 } 6629 6630 err = il4965_setup_deferred_work(il); 6631 if (err) 6632 goto out_free_irq; 6633 6634 il4965_setup_handlers(il); 6635 6636 /********************************************* 6637 * 8. Enable interrupts and read RFKILL state 6638 *********************************************/ 6639 6640 /* enable rfkill interrupt: hw bug w/a */ 6641 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd); 6642 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 6643 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 6644 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd); 6645 } 6646 6647 il_enable_rfkill_int(il); 6648 6649 /* If platform's RF_KILL switch is NOT set to KILL */ 6650 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 6651 clear_bit(S_RFKILL, &il->status); 6652 else 6653 set_bit(S_RFKILL, &il->status); 6654 6655 wiphy_rfkill_set_hw_state(il->hw->wiphy, 6656 test_bit(S_RFKILL, &il->status)); 6657 6658 il_power_initialize(il); 6659 6660 init_completion(&il->_4965.firmware_loading_complete); 6661 6662 err = il4965_request_firmware(il, true); 6663 if (err) 6664 goto out_destroy_workqueue; 6665 6666 return 0; 6667 6668out_destroy_workqueue: 6669 destroy_workqueue(il->workqueue); 6670 il->workqueue = NULL; 6671out_free_irq: 6672 free_irq(il->pci_dev->irq, il); 6673out_disable_msi: 6674 pci_disable_msi(il->pci_dev); 6675 il4965_uninit_drv(il); 6676out_free_eeprom: 6677 il_eeprom_free(il); 6678out_iounmap: 6679 iounmap(il->hw_base); 6680out_pci_release_regions: 6681 pci_release_regions(pdev); 6682out_pci_disable_device: 6683 pci_disable_device(pdev); 6684out_ieee80211_free_hw: 6685 ieee80211_free_hw(il->hw); 6686out: 6687 return err; 6688} 6689 6690static void 6691il4965_pci_remove(struct pci_dev *pdev) 6692{ 6693 struct il_priv *il = pci_get_drvdata(pdev); 6694 unsigned long flags; 6695 6696 if (!il) 6697 return; 6698 6699 wait_for_completion(&il->_4965.firmware_loading_complete); 6700 6701 D_INFO("*** UNLOAD DRIVER ***\n"); 6702 6703 il_dbgfs_unregister(il); 6704 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group); 6705 6706 /* ieee80211_unregister_hw call wil cause il_mac_stop to 6707 * to be called and il4965_down since we are removing the device 6708 * we need to set S_EXIT_PENDING bit. 6709 */ 6710 set_bit(S_EXIT_PENDING, &il->status); 6711 6712 il_leds_exit(il); 6713 6714 if (il->mac80211_registered) { 6715 ieee80211_unregister_hw(il->hw); 6716 il->mac80211_registered = 0; 6717 } else { 6718 il4965_down(il); 6719 } 6720 6721 /* 6722 * Make sure device is reset to low power before unloading driver. 6723 * This may be redundant with il4965_down(), but there are paths to 6724 * run il4965_down() without calling apm_ops.stop(), and there are 6725 * paths to avoid running il4965_down() at all before leaving driver. 6726 * This (inexpensive) call *makes sure* device is reset. 6727 */ 6728 il_apm_stop(il); 6729 6730 /* make sure we flush any pending irq or 6731 * tasklet for the driver 6732 */ 6733 spin_lock_irqsave(&il->lock, flags); 6734 il_disable_interrupts(il); 6735 spin_unlock_irqrestore(&il->lock, flags); 6736 6737 il4965_synchronize_irq(il); 6738 6739 il4965_dealloc_ucode_pci(il); 6740 6741 if (il->rxq.bd) 6742 il4965_rx_queue_free(il, &il->rxq); 6743 il4965_hw_txq_ctx_free(il); 6744 6745 il_eeprom_free(il); 6746 6747 /*netif_stop_queue(dev); */ 6748 flush_workqueue(il->workqueue); 6749 6750 /* ieee80211_unregister_hw calls il_mac_stop, which flushes 6751 * il->workqueue... so we can't take down the workqueue 6752 * until now... */ 6753 destroy_workqueue(il->workqueue); 6754 il->workqueue = NULL; 6755 6756 free_irq(il->pci_dev->irq, il); 6757 pci_disable_msi(il->pci_dev); 6758 iounmap(il->hw_base); 6759 pci_release_regions(pdev); 6760 pci_disable_device(pdev); 6761 6762 il4965_uninit_drv(il); 6763 6764 dev_kfree_skb(il->beacon_skb); 6765 6766 ieee80211_free_hw(il->hw); 6767} 6768 6769/* 6770 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 6771 * must be called under il->lock and mac access 6772 */ 6773void 6774il4965_txq_set_sched(struct il_priv *il, u32 mask) 6775{ 6776 il_wr_prph(il, IL49_SCD_TXFACT, mask); 6777} 6778 6779/***************************************************************************** 6780 * 6781 * driver and module entry point 6782 * 6783 *****************************************************************************/ 6784 6785/* Hardware specific file defines the PCI IDs table for that hardware module */ 6786static const struct pci_device_id il4965_hw_card_ids[] = { 6787 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)}, 6788 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)}, 6789 {0} 6790}; 6791MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids); 6792 6793static struct pci_driver il4965_driver = { 6794 .name = DRV_NAME, 6795 .id_table = il4965_hw_card_ids, 6796 .probe = il4965_pci_probe, 6797 .remove = il4965_pci_remove, 6798 .driver.pm = IL_LEGACY_PM_OPS, 6799}; 6800 6801static int __init 6802il4965_init(void) 6803{ 6804 6805 int ret; 6806 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); 6807 pr_info(DRV_COPYRIGHT "\n"); 6808 6809 ret = il4965_rate_control_register(); 6810 if (ret) { 6811 pr_err("Unable to register rate control algorithm: %d\n", ret); 6812 return ret; 6813 } 6814 6815 ret = pci_register_driver(&il4965_driver); 6816 if (ret) { 6817 pr_err("Unable to initialize PCI module\n"); 6818 goto error_register; 6819 } 6820 6821 return ret; 6822 6823error_register: 6824 il4965_rate_control_unregister(); 6825 return ret; 6826} 6827 6828static void __exit 6829il4965_exit(void) 6830{ 6831 pci_unregister_driver(&il4965_driver); 6832 il4965_rate_control_unregister(); 6833} 6834 6835module_exit(il4965_exit); 6836module_init(il4965_init); 6837 6838#ifdef CONFIG_IWLEGACY_DEBUG 6839module_param_named(debug, il_debug_level, uint, 0644); 6840MODULE_PARM_DESC(debug, "debug output mask"); 6841#endif 6842 6843module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, 0444); 6844MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); 6845module_param_named(queues_num, il4965_mod_params.num_of_queues, int, 0444); 6846MODULE_PARM_DESC(queues_num, "number of hw queues."); 6847module_param_named(11n_disable, il4965_mod_params.disable_11n, int, 0444); 6848MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); 6849module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int, 0444); 6850MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size (default 0 [disabled])"); 6851module_param_named(fw_restart, il4965_mod_params.restart_fw, int, 0444); 6852MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); 6853