1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/etherdevice.h> 7#include <linux/moduleparam.h> 8#include <linux/prefetch.h> 9#include <linux/types.h> 10#include <linux/list.h> 11#include <linux/ip.h> 12#include <linux/ipv6.h> 13#include "wil6210.h" 14#include "txrx_edma.h" 15#include "txrx.h" 16#include "trace.h" 17 18/* Max number of entries (packets to complete) to update the hwtail of tx 19 * status ring. Should be power of 2 20 */ 21#define WIL_EDMA_TX_SRING_UPDATE_HW_TAIL 128 22#define WIL_EDMA_MAX_DATA_OFFSET (2) 23/* RX buffer size must be aligned to 4 bytes */ 24#define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) 25#define MAX_INVALID_BUFF_ID_RETRY (3) 26 27static void wil_tx_desc_unmap_edma(struct device *dev, 28 union wil_tx_desc *desc, 29 struct wil_ctx *ctx) 30{ 31 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc; 32 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); 33 u16 dmalen = le16_to_cpu(d->dma.length); 34 35 switch (ctx->mapped_as) { 36 case wil_mapped_as_single: 37 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 38 break; 39 case wil_mapped_as_page: 40 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 41 break; 42 default: 43 break; 44 } 45} 46 47static int wil_find_free_sring(struct wil6210_priv *wil) 48{ 49 int i; 50 51 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) { 52 if (!wil->srings[i].va) 53 return i; 54 } 55 56 return -EINVAL; 57} 58 59static void wil_sring_free(struct wil6210_priv *wil, 60 struct wil_status_ring *sring) 61{ 62 struct device *dev = wil_to_dev(wil); 63 size_t sz; 64 65 if (!sring || !sring->va) 66 return; 67 68 sz = sring->elem_size * sring->size; 69 70 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n", 71 sz, sring->va, &sring->pa); 72 73 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa); 74 sring->pa = 0; 75 sring->va = NULL; 76} 77 78static int wil_sring_alloc(struct wil6210_priv *wil, 79 struct wil_status_ring *sring) 80{ 81 struct device *dev = wil_to_dev(wil); 82 size_t sz = sring->elem_size * sring->size; 83 84 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz); 85 86 if (sz == 0) { 87 wil_err(wil, "Cannot allocate a zero size status ring\n"); 88 return -EINVAL; 89 } 90 91 sring->swhead = 0; 92 93 /* Status messages are allocated and initialized to 0. This is necessary 94 * since DR bit should be initialized to 0. 95 */ 96 sring->va = dma_alloc_coherent(dev, sz, &sring->pa, GFP_KERNEL); 97 if (!sring->va) 98 return -ENOMEM; 99 100 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va, 101 &sring->pa); 102 103 return 0; 104} 105 106static int wil_tx_init_edma(struct wil6210_priv *wil) 107{ 108 int ring_id = wil_find_free_sring(wil); 109 struct wil_status_ring *sring; 110 int rc; 111 u16 status_ring_size; 112 113 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 114 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 115 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 116 117 status_ring_size = 1 << wil->tx_status_ring_order; 118 119 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n", 120 status_ring_size, ring_id); 121 122 if (ring_id < 0) 123 return ring_id; 124 125 /* Allocate Tx status ring. Tx descriptor rings will be 126 * allocated on WMI connect event 127 */ 128 sring = &wil->srings[ring_id]; 129 130 sring->is_rx = false; 131 sring->size = status_ring_size; 132 sring->elem_size = sizeof(struct wil_ring_tx_status); 133 rc = wil_sring_alloc(wil, sring); 134 if (rc) 135 return rc; 136 137 rc = wil_wmi_tx_sring_cfg(wil, ring_id); 138 if (rc) 139 goto out_free; 140 141 sring->desc_rdy_pol = 1; 142 wil->tx_sring_idx = ring_id; 143 144 return 0; 145out_free: 146 wil_sring_free(wil, sring); 147 return rc; 148} 149 150/* Allocate one skb for Rx descriptor RING */ 151static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, 152 struct wil_ring *ring, u32 i) 153{ 154 struct device *dev = wil_to_dev(wil); 155 unsigned int sz = wil->rx_buf_len; 156 dma_addr_t pa; 157 u16 buff_id; 158 struct list_head *active = &wil->rx_buff_mgmt.active; 159 struct list_head *free = &wil->rx_buff_mgmt.free; 160 struct wil_rx_buff *rx_buff; 161 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr; 162 struct sk_buff *skb; 163 struct wil_rx_enhanced_desc dd, *d = ⅆ 164 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *) 165 &ring->va[i].rx.enhanced; 166 167 if (unlikely(list_empty(free))) { 168 wil->rx_buff_mgmt.free_list_empty_cnt++; 169 return -EAGAIN; 170 } 171 172 skb = dev_alloc_skb(sz); 173 if (unlikely(!skb)) 174 return -ENOMEM; 175 176 skb_put(skb, sz); 177 178 /** 179 * Make sure that the network stack calculates checksum for packets 180 * which failed the HW checksum calculation 181 */ 182 skb->ip_summed = CHECKSUM_NONE; 183 184 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 185 if (unlikely(dma_mapping_error(dev, pa))) { 186 kfree_skb(skb); 187 return -ENOMEM; 188 } 189 190 /* Get the buffer ID - the index of the rx buffer in the buff_arr */ 191 rx_buff = list_first_entry(free, struct wil_rx_buff, list); 192 buff_id = rx_buff->id; 193 194 /* Move a buffer from the free list to the active list */ 195 list_move(&rx_buff->list, active); 196 197 buff_arr[buff_id].skb = skb; 198 199 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 200 d->dma.length = cpu_to_le16(sz); 201 d->mac.buff_id = cpu_to_le16(buff_id); 202 *_d = *d; 203 204 /* Save the physical address in skb->cb for later use in dma_unmap */ 205 memcpy(skb->cb, &pa, sizeof(pa)); 206 207 return 0; 208} 209 210static inline 211void wil_get_next_rx_status_msg(struct wil_status_ring *sring, u8 *dr_bit, 212 void *msg) 213{ 214 struct wil_rx_status_compressed *_msg; 215 216 _msg = (struct wil_rx_status_compressed *) 217 (sring->va + (sring->elem_size * sring->swhead)); 218 *dr_bit = WIL_GET_BITS(_msg->d0, 31, 31); 219 /* make sure dr_bit is read before the rest of status msg */ 220 rmb(); 221 memcpy(msg, (void *)_msg, sring->elem_size); 222} 223 224static inline void wil_sring_advance_swhead(struct wil_status_ring *sring) 225{ 226 sring->swhead = (sring->swhead + 1) % sring->size; 227 if (sring->swhead == 0) 228 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol; 229} 230 231static int wil_rx_refill_edma(struct wil6210_priv *wil) 232{ 233 struct wil_ring *ring = &wil->ring_rx; 234 u32 next_head; 235 int rc = 0; 236 ring->swtail = *ring->edma_rx_swtail.va; 237 238 for (; next_head = wil_ring_next_head(ring), 239 (next_head != ring->swtail); 240 ring->swhead = next_head) { 241 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead); 242 if (unlikely(rc)) { 243 if (rc == -EAGAIN) 244 wil_dbg_txrx(wil, "No free buffer ID found\n"); 245 else 246 wil_err_ratelimited(wil, 247 "Error %d in refill desc[%d]\n", 248 rc, ring->swhead); 249 break; 250 } 251 } 252 253 /* make sure all writes to descriptors (shared memory) are done before 254 * committing them to HW 255 */ 256 wmb(); 257 258 wil_w(wil, ring->hwtail, ring->swhead); 259 260 return rc; 261} 262 263static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil, 264 struct wil_ring *ring) 265{ 266 struct device *dev = wil_to_dev(wil); 267 struct list_head *active = &wil->rx_buff_mgmt.active; 268 dma_addr_t pa; 269 270 if (!wil->rx_buff_mgmt.buff_arr) 271 return; 272 273 while (!list_empty(active)) { 274 struct wil_rx_buff *rx_buff = 275 list_first_entry(active, struct wil_rx_buff, list); 276 struct sk_buff *skb = rx_buff->skb; 277 278 if (unlikely(!skb)) { 279 wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id); 280 } else { 281 rx_buff->skb = NULL; 282 memcpy(&pa, skb->cb, sizeof(pa)); 283 dma_unmap_single(dev, pa, wil->rx_buf_len, 284 DMA_FROM_DEVICE); 285 kfree_skb(skb); 286 } 287 288 /* Move the buffer from the active to the free list */ 289 list_move(&rx_buff->list, &wil->rx_buff_mgmt.free); 290 } 291} 292 293static void wil_free_rx_buff_arr(struct wil6210_priv *wil) 294{ 295 struct wil_ring *ring = &wil->ring_rx; 296 297 if (!wil->rx_buff_mgmt.buff_arr) 298 return; 299 300 /* Move all the buffers to the free list in case active list is 301 * not empty in order to release all SKBs before deleting the array 302 */ 303 wil_move_all_rx_buff_to_free_list(wil, ring); 304 305 kfree(wil->rx_buff_mgmt.buff_arr); 306 wil->rx_buff_mgmt.buff_arr = NULL; 307} 308 309static int wil_init_rx_buff_arr(struct wil6210_priv *wil, 310 size_t size) 311{ 312 struct wil_rx_buff *buff_arr; 313 struct list_head *active = &wil->rx_buff_mgmt.active; 314 struct list_head *free = &wil->rx_buff_mgmt.free; 315 int i; 316 317 wil->rx_buff_mgmt.buff_arr = kcalloc(size + 1, 318 sizeof(struct wil_rx_buff), 319 GFP_KERNEL); 320 if (!wil->rx_buff_mgmt.buff_arr) 321 return -ENOMEM; 322 323 /* Set list heads */ 324 INIT_LIST_HEAD(active); 325 INIT_LIST_HEAD(free); 326 327 /* Linkify the list. 328 * buffer id 0 should not be used (marks invalid id). 329 */ 330 buff_arr = wil->rx_buff_mgmt.buff_arr; 331 for (i = 1; i <= size; i++) { 332 list_add(&buff_arr[i].list, free); 333 buff_arr[i].id = i; 334 } 335 336 wil->rx_buff_mgmt.size = size + 1; 337 338 return 0; 339} 340 341static int wil_init_rx_sring(struct wil6210_priv *wil, 342 u16 status_ring_size, 343 size_t elem_size, 344 u16 ring_id) 345{ 346 struct wil_status_ring *sring = &wil->srings[ring_id]; 347 int rc; 348 349 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", 350 status_ring_size, ring_id); 351 352 memset(&sring->rx_data, 0, sizeof(sring->rx_data)); 353 354 sring->is_rx = true; 355 sring->size = status_ring_size; 356 sring->elem_size = elem_size; 357 rc = wil_sring_alloc(wil, sring); 358 if (rc) 359 return rc; 360 361 rc = wil_wmi_rx_sring_add(wil, ring_id); 362 if (rc) 363 goto out_free; 364 365 sring->desc_rdy_pol = 1; 366 367 return 0; 368out_free: 369 wil_sring_free(wil, sring); 370 return rc; 371} 372 373static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil, 374 struct wil_ring *ring) 375{ 376 struct device *dev = wil_to_dev(wil); 377 size_t sz = ring->size * sizeof(ring->va[0]); 378 379 wil_dbg_misc(wil, "alloc_desc_ring:\n"); 380 381 BUILD_BUG_ON(sizeof(ring->va[0]) != 32); 382 383 ring->swhead = 0; 384 ring->swtail = 0; 385 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL); 386 if (!ring->ctx) 387 goto err; 388 389 ring->va = dma_alloc_coherent(dev, sz, &ring->pa, GFP_KERNEL); 390 if (!ring->va) 391 goto err_free_ctx; 392 393 if (ring->is_rx) { 394 sz = sizeof(*ring->edma_rx_swtail.va); 395 ring->edma_rx_swtail.va = 396 dma_alloc_coherent(dev, sz, &ring->edma_rx_swtail.pa, 397 GFP_KERNEL); 398 if (!ring->edma_rx_swtail.va) 399 goto err_free_va; 400 } 401 402 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n", 403 ring->is_rx ? "RX" : "TX", 404 ring->size, ring->va, &ring->pa, ring->ctx); 405 406 return 0; 407err_free_va: 408 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]), 409 (void *)ring->va, ring->pa); 410 ring->va = NULL; 411err_free_ctx: 412 kfree(ring->ctx); 413 ring->ctx = NULL; 414err: 415 return -ENOMEM; 416} 417 418static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring) 419{ 420 struct device *dev = wil_to_dev(wil); 421 size_t sz; 422 int ring_index = 0; 423 424 if (!ring->va) 425 return; 426 427 sz = ring->size * sizeof(ring->va[0]); 428 429 lockdep_assert_held(&wil->mutex); 430 if (ring->is_rx) { 431 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n", 432 ring->size, ring->va, 433 &ring->pa, ring->ctx); 434 435 wil_move_all_rx_buff_to_free_list(wil, ring); 436 dma_free_coherent(dev, sizeof(*ring->edma_rx_swtail.va), 437 ring->edma_rx_swtail.va, 438 ring->edma_rx_swtail.pa); 439 goto out; 440 } 441 442 /* TX ring */ 443 ring_index = ring - wil->ring_tx; 444 445 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n", 446 ring_index, ring->size, ring->va, 447 &ring->pa, ring->ctx); 448 449 while (!wil_ring_is_empty(ring)) { 450 struct wil_ctx *ctx; 451 452 struct wil_tx_enhanced_desc dd, *d = ⅆ 453 struct wil_tx_enhanced_desc *_d = 454 (struct wil_tx_enhanced_desc *) 455 &ring->va[ring->swtail].tx.enhanced; 456 457 ctx = &ring->ctx[ring->swtail]; 458 if (!ctx) { 459 wil_dbg_txrx(wil, 460 "ctx(%d) was already completed\n", 461 ring->swtail); 462 ring->swtail = wil_ring_next_tail(ring); 463 continue; 464 } 465 *d = *_d; 466 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 467 if (ctx->skb) 468 dev_kfree_skb_any(ctx->skb); 469 ring->swtail = wil_ring_next_tail(ring); 470 } 471 472out: 473 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa); 474 kfree(ring->ctx); 475 ring->pa = 0; 476 ring->va = NULL; 477 ring->ctx = NULL; 478} 479 480static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size, 481 int status_ring_id) 482{ 483 struct wil_ring *ring = &wil->ring_rx; 484 int rc; 485 486 wil_dbg_misc(wil, "init RX desc ring\n"); 487 488 ring->size = desc_ring_size; 489 ring->is_rx = true; 490 rc = wil_ring_alloc_desc_ring(wil, ring); 491 if (rc) 492 return rc; 493 494 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id); 495 if (rc) 496 goto out_free; 497 498 return 0; 499out_free: 500 wil_ring_free_edma(wil, ring); 501 return rc; 502} 503 504static void wil_get_reorder_params_edma(struct wil6210_priv *wil, 505 struct sk_buff *skb, int *tid, 506 int *cid, int *mid, u16 *seq, 507 int *mcast, int *retry) 508{ 509 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 510 511 *tid = wil_rx_status_get_tid(s); 512 *cid = wil_rx_status_get_cid(s); 513 *mid = wil_rx_status_get_mid(s); 514 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s)); 515 *mcast = wil_rx_status_get_mcast(s); 516 *retry = wil_rx_status_get_retry(s); 517} 518 519static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid, 520 int *security) 521{ 522 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 523 524 *cid = wil_rx_status_get_cid(s); 525 *security = wil_rx_status_get_security(s); 526} 527 528static int wil_rx_crypto_check_edma(struct wil6210_priv *wil, 529 struct sk_buff *skb) 530{ 531 struct wil_rx_status_extended *st; 532 int cid, tid, key_id, mc; 533 struct wil_sta_info *s; 534 struct wil_tid_crypto_rx *c; 535 struct wil_tid_crypto_rx_single *cc; 536 const u8 *pn; 537 538 /* In HW reorder, HW is responsible for crypto check */ 539 if (wil->use_rx_hw_reordering) 540 return 0; 541 542 st = wil_skb_rxstatus(skb); 543 544 cid = wil_rx_status_get_cid(st); 545 tid = wil_rx_status_get_tid(st); 546 key_id = wil_rx_status_get_key_id(st); 547 mc = wil_rx_status_get_mcast(st); 548 s = &wil->sta[cid]; 549 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid]; 550 cc = &c->key_id[key_id]; 551 pn = (u8 *)&st->ext.pn; 552 553 if (!cc->key_set) { 554 wil_err_ratelimited(wil, 555 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 556 cid, tid, mc, key_id); 557 return -EINVAL; 558 } 559 560 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 561 wil_err_ratelimited(wil, 562 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 563 cid, tid, mc, key_id, pn, cc->pn); 564 return -EINVAL; 565 } 566 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 567 568 return 0; 569} 570 571static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) 572{ 573 struct wil_status_ring *sring; 574 struct wil_rx_status_extended msg1; 575 void *msg = &msg1; 576 u8 dr_bit; 577 int i; 578 579 for (i = 0; i < wil->num_rx_status_rings; i++) { 580 sring = &wil->srings[i]; 581 if (!sring->va) 582 continue; 583 584 wil_get_next_rx_status_msg(sring, &dr_bit, msg); 585 586 /* Check if there are unhandled RX status messages */ 587 if (dr_bit == sring->desc_rdy_pol) 588 return false; 589 } 590 591 return true; 592} 593 594static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) 595{ 596 /* RX buffer size must be aligned to 4 bytes */ 597 wil->rx_buf_len = rx_large_buf ? 598 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT; 599} 600 601static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order) 602{ 603 u16 status_ring_size, desc_ring_size = 1 << desc_ring_order; 604 struct wil_ring *ring = &wil->ring_rx; 605 int rc; 606 size_t elem_size = wil->use_compressed_rx_status ? 607 sizeof(struct wil_rx_status_compressed) : 608 sizeof(struct wil_rx_status_extended); 609 int i; 610 611 /* In SW reorder one must use extended status messages */ 612 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) { 613 wil_err(wil, 614 "compressed RX status cannot be used with SW reorder\n"); 615 return -EINVAL; 616 } 617 if (wil->rx_status_ring_order <= desc_ring_order) 618 /* make sure sring is larger than desc ring */ 619 wil->rx_status_ring_order = desc_ring_order + 1; 620 if (wil->rx_buff_id_count <= desc_ring_size) 621 /* make sure we will not run out of buff_ids */ 622 wil->rx_buff_id_count = desc_ring_size + 512; 623 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 624 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 625 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 626 627 status_ring_size = 1 << wil->rx_status_ring_order; 628 629 wil_dbg_misc(wil, 630 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n", 631 desc_ring_size, status_ring_size, elem_size); 632 633 wil_rx_buf_len_init_edma(wil); 634 635 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ 636 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) 637 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1; 638 639 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n", 640 wil->num_rx_status_rings); 641 642 rc = wil_wmi_cfg_def_rx_offload(wil, wil->rx_buf_len); 643 if (rc) 644 return rc; 645 646 /* Allocate status ring */ 647 for (i = 0; i < wil->num_rx_status_rings; i++) { 648 int sring_id = wil_find_free_sring(wil); 649 650 if (sring_id < 0) { 651 rc = -EFAULT; 652 goto err_free_status; 653 } 654 rc = wil_init_rx_sring(wil, status_ring_size, elem_size, 655 sring_id); 656 if (rc) 657 goto err_free_status; 658 } 659 660 /* Allocate descriptor ring */ 661 rc = wil_init_rx_desc_ring(wil, desc_ring_size, 662 WIL_DEFAULT_RX_STATUS_RING_ID); 663 if (rc) 664 goto err_free_status; 665 666 if (wil->rx_buff_id_count >= status_ring_size) { 667 wil_info(wil, 668 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n", 669 wil->rx_buff_id_count, status_ring_size, 670 status_ring_size - 1); 671 wil->rx_buff_id_count = status_ring_size - 1; 672 } 673 674 /* Allocate Rx buffer array */ 675 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count); 676 if (rc) 677 goto err_free_desc; 678 679 /* Fill descriptor ring with credits */ 680 rc = wil_rx_refill_edma(wil); 681 if (rc) 682 goto err_free_rx_buff_arr; 683 684 return 0; 685err_free_rx_buff_arr: 686 wil_free_rx_buff_arr(wil); 687err_free_desc: 688 wil_ring_free_edma(wil, ring); 689err_free_status: 690 for (i = 0; i < wil->num_rx_status_rings; i++) 691 wil_sring_free(wil, &wil->srings[i]); 692 693 return rc; 694} 695 696static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id, 697 int size, int cid, int tid) 698{ 699 struct wil6210_priv *wil = vif_to_wil(vif); 700 int rc; 701 struct wil_ring *ring = &wil->ring_tx[ring_id]; 702 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 703 704 lockdep_assert_held(&wil->mutex); 705 706 wil_dbg_misc(wil, 707 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n", 708 ring_id, cid, tid, wil->tx_sring_idx); 709 710 wil_tx_data_init(txdata); 711 ring->size = size; 712 rc = wil_ring_alloc_desc_ring(wil, ring); 713 if (rc) 714 goto out; 715 716 wil->ring2cid_tid[ring_id][0] = cid; 717 wil->ring2cid_tid[ring_id][1] = tid; 718 if (!vif->privacy) 719 txdata->dot1x_open = true; 720 721 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid); 722 if (rc) { 723 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n"); 724 goto out_free; 725 } 726 727 if (txdata->dot1x_open && agg_wsize >= 0) 728 wil_addba_tx_request(wil, ring_id, agg_wsize); 729 730 return 0; 731 out_free: 732 spin_lock_bh(&txdata->lock); 733 txdata->dot1x_open = false; 734 txdata->enabled = 0; 735 spin_unlock_bh(&txdata->lock); 736 wil_ring_free_edma(wil, ring); 737 wil->ring2cid_tid[ring_id][0] = wil->max_assoc_sta; 738 wil->ring2cid_tid[ring_id][1] = 0; 739 740 out: 741 return rc; 742} 743 744static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id, 745 int cid, int tid) 746{ 747 struct wil6210_priv *wil = vif_to_wil(vif); 748 749 wil_err(wil, "ring modify is not supported for EDMA\n"); 750 751 return -EOPNOTSUPP; 752} 753 754/* This function is used only for RX SW reorder */ 755static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, 756 struct sk_buff *skb, struct wil_net_stats *stats) 757{ 758 u8 ftype; 759 u8 fc1; 760 int mid; 761 int tid; 762 u16 seq; 763 struct wil6210_vif *vif; 764 765 ftype = wil_rx_status_get_frame_type(wil, msg); 766 if (ftype == IEEE80211_FTYPE_DATA) 767 return 0; 768 769 fc1 = wil_rx_status_get_fc1(wil, msg); 770 mid = wil_rx_status_get_mid(msg); 771 tid = wil_rx_status_get_tid(msg); 772 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); 773 vif = wil->vifs[mid]; 774 775 if (unlikely(!vif)) { 776 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid); 777 return -EAGAIN; 778 } 779 780 wil_dbg_txrx(wil, 781 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 782 fc1, mid, cid, tid, seq); 783 if (stats) 784 stats->rx_non_data_frame++; 785 if (wil_is_back_req(fc1)) { 786 wil_dbg_txrx(wil, 787 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 788 mid, cid, tid, seq); 789 wil_rx_bar(wil, vif, cid, tid, seq); 790 } else { 791 u32 sz = wil->use_compressed_rx_status ? 792 sizeof(struct wil_rx_status_compressed) : 793 sizeof(struct wil_rx_status_extended); 794 795 /* print again all info. One can enable only this 796 * without overhead for printing every Rx frame 797 */ 798 wil_dbg_txrx(wil, 799 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 800 fc1, mid, cid, tid, seq); 801 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 802 (const void *)msg, sz, false); 803 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 804 skb->data, skb_headlen(skb), false); 805 } 806 807 return -EAGAIN; 808} 809 810static int wil_rx_error_check_edma(struct wil6210_priv *wil, 811 struct sk_buff *skb, 812 struct wil_net_stats *stats) 813{ 814 int l2_rx_status; 815 void *msg = wil_skb_rxstatus(skb); 816 817 l2_rx_status = wil_rx_status_get_l2_rx_status(msg); 818 if (l2_rx_status != 0) { 819 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n", 820 l2_rx_status); 821 /* Due to HW issue, KEY error will trigger a MIC error */ 822 if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) { 823 wil_err_ratelimited(wil, 824 "L2 MIC/KEY error, dropping packet\n"); 825 stats->rx_mic_error++; 826 } 827 if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) { 828 wil_err_ratelimited(wil, 829 "L2 KEY error, dropping packet\n"); 830 stats->rx_key_error++; 831 } 832 if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) { 833 wil_err_ratelimited(wil, 834 "L2 REPLAY error, dropping packet\n"); 835 stats->rx_replay++; 836 } 837 if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) { 838 wil_err_ratelimited(wil, 839 "L2 AMSDU error, dropping packet\n"); 840 stats->rx_amsdu_error++; 841 } 842 return -EFAULT; 843 } 844 845 skb->ip_summed = wil_rx_status_get_checksum(msg, stats); 846 847 return 0; 848} 849 850static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, 851 struct wil_status_ring *sring) 852{ 853 struct device *dev = wil_to_dev(wil); 854 struct wil_rx_status_extended msg1; 855 void *msg = &msg1; 856 u16 buff_id; 857 struct sk_buff *skb; 858 dma_addr_t pa; 859 struct wil_ring_rx_data *rxdata = &sring->rx_data; 860 unsigned int sz = wil->rx_buf_len; 861 struct wil_net_stats *stats = NULL; 862 u16 dmalen; 863 int cid; 864 bool eop, headstolen; 865 int delta; 866 u8 dr_bit; 867 u8 data_offset; 868 struct wil_rx_status_extended *s; 869 u16 sring_idx = sring - wil->srings; 870 int invalid_buff_id_retry; 871 872 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb)); 873 874again: 875 wil_get_next_rx_status_msg(sring, &dr_bit, msg); 876 877 /* Completed handling all the ready status messages */ 878 if (dr_bit != sring->desc_rdy_pol) 879 return NULL; 880 881 /* Extract the buffer ID from the status message */ 882 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 883 884 invalid_buff_id_retry = 0; 885 while (!buff_id) { 886 struct wil_rx_status_extended *s; 887 888 wil_dbg_txrx(wil, 889 "buff_id is not updated yet by HW, (swhead 0x%x)\n", 890 sring->swhead); 891 if (++invalid_buff_id_retry > MAX_INVALID_BUFF_ID_RETRY) 892 break; 893 894 /* Read the status message again */ 895 s = (struct wil_rx_status_extended *) 896 (sring->va + (sring->elem_size * sring->swhead)); 897 *(struct wil_rx_status_extended *)msg = *s; 898 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 899 } 900 901 if (unlikely(!wil_val_in_range(buff_id, 1, wil->rx_buff_mgmt.size))) { 902 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", 903 buff_id, sring->swhead); 904 print_hex_dump(KERN_ERR, "RxS ", DUMP_PREFIX_OFFSET, 16, 1, 905 msg, wil->use_compressed_rx_status ? 906 sizeof(struct wil_rx_status_compressed) : 907 sizeof(struct wil_rx_status_extended), false); 908 909 wil_rx_status_reset_buff_id(sring); 910 wil_sring_advance_swhead(sring); 911 sring->invalid_buff_id_cnt++; 912 goto again; 913 } 914 915 /* Extract the SKB from the rx_buff management array */ 916 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 917 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 918 if (!skb) { 919 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 920 wil_rx_status_reset_buff_id(sring); 921 /* Move the buffer from the active list to the free list */ 922 list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 923 &wil->rx_buff_mgmt.free); 924 wil_sring_advance_swhead(sring); 925 sring->invalid_buff_id_cnt++; 926 goto again; 927 } 928 929 wil_rx_status_reset_buff_id(sring); 930 wil_sring_advance_swhead(sring); 931 932 memcpy(&pa, skb->cb, sizeof(pa)); 933 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 934 dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); 935 936 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id, 937 msg); 938 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n", 939 buff_id, sring_idx, dmalen); 940 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 941 (const void *)msg, wil->use_compressed_rx_status ? 942 sizeof(struct wil_rx_status_compressed) : 943 sizeof(struct wil_rx_status_extended), false); 944 945 /* Move the buffer from the active list to the free list */ 946 list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 947 &wil->rx_buff_mgmt.free); 948 949 eop = wil_rx_status_get_eop(msg); 950 951 cid = wil_rx_status_get_cid(msg); 952 if (unlikely(!wil_val_in_range(cid, 0, wil->max_assoc_sta))) { 953 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n", 954 cid, sring->swhead); 955 rxdata->skipping = true; 956 goto skipping; 957 } 958 stats = &wil->sta[cid].stats; 959 960 if (unlikely(dmalen < ETH_HLEN)) { 961 wil_dbg_txrx(wil, "Short frame, len = %d\n", dmalen); 962 stats->rx_short_frame++; 963 rxdata->skipping = true; 964 goto skipping; 965 } 966 967 if (unlikely(dmalen > sz)) { 968 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 969 print_hex_dump(KERN_ERR, "RxS ", DUMP_PREFIX_OFFSET, 16, 1, 970 msg, wil->use_compressed_rx_status ? 971 sizeof(struct wil_rx_status_compressed) : 972 sizeof(struct wil_rx_status_extended), false); 973 974 stats->rx_large_frame++; 975 rxdata->skipping = true; 976 } 977 978skipping: 979 /* skipping indicates if a certain SKB should be dropped. 980 * It is set in case there is an error on the current SKB or in case 981 * of RX chaining: as long as we manage to merge the SKBs it will 982 * be false. once we have a bad SKB or we don't manage to merge SKBs 983 * it will be set to the !EOP value of the current SKB. 984 * This guarantees that all the following SKBs until EOP will also 985 * get dropped. 986 */ 987 if (unlikely(rxdata->skipping)) { 988 kfree_skb(skb); 989 if (rxdata->skb) { 990 kfree_skb(rxdata->skb); 991 rxdata->skb = NULL; 992 } 993 rxdata->skipping = !eop; 994 goto again; 995 } 996 997 skb_trim(skb, dmalen); 998 999 prefetch(skb->data); 1000 1001 if (!rxdata->skb) { 1002 rxdata->skb = skb; 1003 } else { 1004 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen, 1005 &delta))) { 1006 kfree_skb_partial(skb, headstolen); 1007 } else { 1008 wil_err(wil, "failed to merge skbs!\n"); 1009 kfree_skb(skb); 1010 kfree_skb(rxdata->skb); 1011 rxdata->skb = NULL; 1012 rxdata->skipping = !eop; 1013 goto again; 1014 } 1015 } 1016 1017 if (!eop) 1018 goto again; 1019 1020 /* reaching here rxdata->skb always contains a full packet */ 1021 skb = rxdata->skb; 1022 rxdata->skb = NULL; 1023 rxdata->skipping = false; 1024 1025 if (stats) { 1026 stats->last_mcs_rx = wil_rx_status_get_mcs(msg); 1027 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 1028 stats->rx_per_mcs[stats->last_mcs_rx]++; 1029 1030 stats->last_cb_mode_rx = wil_rx_status_get_cb_mode(msg); 1031 } 1032 1033 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status && 1034 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) { 1035 kfree_skb(skb); 1036 goto again; 1037 } 1038 1039 /* Compensate for the HW data alignment according to the status 1040 * message 1041 */ 1042 data_offset = wil_rx_status_get_data_offset(msg); 1043 if (data_offset == 0xFF || 1044 data_offset > WIL_EDMA_MAX_DATA_OFFSET) { 1045 wil_err(wil, "Unexpected data offset %d\n", data_offset); 1046 kfree_skb(skb); 1047 goto again; 1048 } 1049 1050 skb_pull(skb, data_offset); 1051 1052 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 1053 skb->data, skb_headlen(skb), false); 1054 1055 /* Has to be done after dma_unmap_single as skb->cb is also 1056 * used for holding the pa 1057 */ 1058 s = wil_skb_rxstatus(skb); 1059 memcpy(s, msg, sring->elem_size); 1060 1061 return skb; 1062} 1063 1064void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota) 1065{ 1066 struct net_device *ndev; 1067 struct wil_ring *ring = &wil->ring_rx; 1068 struct wil_status_ring *sring; 1069 struct sk_buff *skb; 1070 int i; 1071 1072 if (unlikely(!ring->va)) { 1073 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 1074 return; 1075 } 1076 wil_dbg_txrx(wil, "rx_handle\n"); 1077 1078 for (i = 0; i < wil->num_rx_status_rings; i++) { 1079 sring = &wil->srings[i]; 1080 if (unlikely(!sring->va)) { 1081 wil_err(wil, 1082 "Rx IRQ while Rx status ring %d not yet initialized\n", 1083 i); 1084 continue; 1085 } 1086 1087 while ((*quota > 0) && 1088 (NULL != (skb = 1089 wil_sring_reap_rx_edma(wil, sring)))) { 1090 (*quota)--; 1091 if (wil->use_rx_hw_reordering) { 1092 void *msg = wil_skb_rxstatus(skb); 1093 int mid = wil_rx_status_get_mid(msg); 1094 struct wil6210_vif *vif = wil->vifs[mid]; 1095 1096 if (unlikely(!vif)) { 1097 wil_dbg_txrx(wil, 1098 "RX desc invalid mid %d", 1099 mid); 1100 kfree_skb(skb); 1101 continue; 1102 } 1103 ndev = vif_to_ndev(vif); 1104 wil_netif_rx_any(skb, ndev); 1105 } else { 1106 wil_rx_reorder(wil, skb); 1107 } 1108 } 1109 1110 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1111 } 1112 1113 wil_rx_refill_edma(wil); 1114} 1115 1116static int wil_tx_desc_map_edma(union wil_tx_desc *desc, 1117 dma_addr_t pa, 1118 u32 len, 1119 int ring_index) 1120{ 1121 struct wil_tx_enhanced_desc *d = 1122 (struct wil_tx_enhanced_desc *)&desc->enhanced; 1123 1124 memset(d, 0, sizeof(struct wil_tx_enhanced_desc)); 1125 1126 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 1127 1128 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 1129 d->dma.length = cpu_to_le16((u16)len); 1130 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS); 1131 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi; 1132 * 3 - eth mode 1133 */ 1134 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 1135 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 1136 1137 return 0; 1138} 1139 1140static inline void 1141wil_get_next_tx_status_msg(struct wil_status_ring *sring, u8 *dr_bit, 1142 struct wil_ring_tx_status *msg) 1143{ 1144 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *) 1145 (sring->va + (sring->elem_size * sring->swhead)); 1146 1147 *dr_bit = _msg->desc_ready >> TX_STATUS_DESC_READY_POS; 1148 /* make sure dr_bit is read before the rest of status msg */ 1149 rmb(); 1150 *msg = *_msg; 1151} 1152 1153/* Clean up transmitted skb's from the Tx descriptor RING. 1154 * Return number of descriptors cleared. 1155 */ 1156int wil_tx_sring_handler(struct wil6210_priv *wil, 1157 struct wil_status_ring *sring) 1158{ 1159 struct net_device *ndev; 1160 struct device *dev = wil_to_dev(wil); 1161 struct wil_ring *ring = NULL; 1162 struct wil_ring_tx_data *txdata; 1163 /* Total number of completed descriptors in all descriptor rings */ 1164 int desc_cnt = 0; 1165 int cid; 1166 struct wil_net_stats *stats; 1167 struct wil_tx_enhanced_desc *_d; 1168 unsigned int ring_id; 1169 unsigned int num_descs, num_statuses = 0; 1170 int i; 1171 u8 dr_bit; /* Descriptor Ready bit */ 1172 struct wil_ring_tx_status msg; 1173 struct wil6210_vif *vif; 1174 int used_before_complete; 1175 int used_new; 1176 1177 wil_get_next_tx_status_msg(sring, &dr_bit, &msg); 1178 1179 /* Process completion messages while DR bit has the expected polarity */ 1180 while (dr_bit == sring->desc_rdy_pol) { 1181 num_descs = msg.num_descriptors; 1182 if (!num_descs) { 1183 wil_err(wil, "invalid num_descs 0\n"); 1184 goto again; 1185 } 1186 1187 /* Find the corresponding descriptor ring */ 1188 ring_id = msg.ring_id; 1189 1190 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) { 1191 wil_err(wil, "invalid ring id %d\n", ring_id); 1192 goto again; 1193 } 1194 ring = &wil->ring_tx[ring_id]; 1195 if (unlikely(!ring->va)) { 1196 wil_err(wil, "Tx irq[%d]: ring not initialized\n", 1197 ring_id); 1198 goto again; 1199 } 1200 txdata = &wil->ring_tx_data[ring_id]; 1201 if (unlikely(!txdata->enabled)) { 1202 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id); 1203 goto again; 1204 } 1205 vif = wil->vifs[txdata->mid]; 1206 if (unlikely(!vif)) { 1207 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n", 1208 txdata->mid, ring_id); 1209 goto again; 1210 } 1211 1212 ndev = vif_to_ndev(vif); 1213 1214 cid = wil->ring2cid_tid[ring_id][0]; 1215 stats = (cid < wil->max_assoc_sta) ? &wil->sta[cid].stats : 1216 NULL; 1217 1218 wil_dbg_txrx(wil, 1219 "tx_status: completed desc_ring (%d), num_descs (%d)\n", 1220 ring_id, num_descs); 1221 1222 used_before_complete = wil_ring_used_tx(ring); 1223 1224 for (i = 0 ; i < num_descs; ++i) { 1225 struct wil_ctx *ctx = &ring->ctx[ring->swtail]; 1226 struct wil_tx_enhanced_desc dd, *d = ⅆ 1227 u16 dmalen; 1228 struct sk_buff *skb = ctx->skb; 1229 1230 _d = (struct wil_tx_enhanced_desc *) 1231 &ring->va[ring->swtail].tx.enhanced; 1232 *d = *_d; 1233 1234 dmalen = le16_to_cpu(d->dma.length); 1235 trace_wil6210_tx_status(&msg, ring->swtail, dmalen); 1236 wil_dbg_txrx(wil, 1237 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n", 1238 ring_id, ring->swtail, dmalen, 1239 msg.status); 1240 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4, 1241 (const void *)&msg, sizeof(msg), 1242 false); 1243 1244 wil_tx_desc_unmap_edma(dev, 1245 (union wil_tx_desc *)d, 1246 ctx); 1247 1248 if (skb) { 1249 if (likely(msg.status == 0)) { 1250 ndev->stats.tx_packets++; 1251 ndev->stats.tx_bytes += skb->len; 1252 if (stats) { 1253 stats->tx_packets++; 1254 stats->tx_bytes += skb->len; 1255 1256 wil_tx_latency_calc(wil, skb, 1257 &wil->sta[cid]); 1258 } 1259 } else { 1260 ndev->stats.tx_errors++; 1261 if (stats) 1262 stats->tx_errors++; 1263 } 1264 1265 if (skb->protocol == cpu_to_be16(ETH_P_PAE)) 1266 wil_tx_complete_handle_eapol(vif, skb); 1267 1268 wil_consume_skb(skb, msg.status == 0); 1269 } 1270 memset(ctx, 0, sizeof(*ctx)); 1271 /* Make sure the ctx is zeroed before updating the tail 1272 * to prevent a case where wil_tx_ring will see 1273 * this descriptor as used and handle it before ctx zero 1274 * is completed. 1275 */ 1276 wmb(); 1277 1278 ring->swtail = wil_ring_next_tail(ring); 1279 1280 desc_cnt++; 1281 } 1282 1283 /* performance monitoring */ 1284 used_new = wil_ring_used_tx(ring); 1285 if (wil_val_in_range(wil->ring_idle_trsh, 1286 used_new, used_before_complete)) { 1287 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 1288 ring_id, used_before_complete, used_new); 1289 txdata->last_idle = get_cycles(); 1290 } 1291 1292again: 1293 num_statuses++; 1294 if (num_statuses % WIL_EDMA_TX_SRING_UPDATE_HW_TAIL == 0) 1295 /* update HW tail to allow HW to push new statuses */ 1296 wil_w(wil, sring->hwtail, sring->swhead); 1297 1298 wil_sring_advance_swhead(sring); 1299 1300 wil_get_next_tx_status_msg(sring, &dr_bit, &msg); 1301 } 1302 1303 /* shall we wake net queues? */ 1304 if (desc_cnt) 1305 wil_update_net_queues(wil, vif, NULL, false); 1306 1307 if (num_statuses % WIL_EDMA_TX_SRING_UPDATE_HW_TAIL != 0) 1308 /* Update the HW tail ptr (RD ptr) */ 1309 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1310 1311 return desc_cnt; 1312} 1313 1314/* Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1315 * @skb is used to obtain the protocol and headers length. 1316 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1317 * 2 - middle, 3 - last descriptor. 1318 */ 1319static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d, 1320 int tso_desc_type, bool is_ipv4, 1321 int tcp_hdr_len, 1322 int skb_net_hdr_len, 1323 int mss) 1324{ 1325 /* Number of descriptors */ 1326 d->mac.d[2] |= 1; 1327 /* Maximum Segment Size */ 1328 d->mac.tso_mss |= cpu_to_le16(mss >> 2); 1329 /* L4 header len: TCP header length */ 1330 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK; 1331 /* EOP, TSO desc type, Segmentation enable, 1332 * Insert IPv4 and TCP / UDP Checksum 1333 */ 1334 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | 1335 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS | 1336 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | 1337 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | 1338 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); 1339 /* Calculate pseudo-header */ 1340 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | 1341 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); 1342 /* IP Header Length */ 1343 d->dma.ip_length |= skb_net_hdr_len; 1344 /* MAC header length and IP address family*/ 1345 d->dma.b11 |= ETH_HLEN | 1346 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1347} 1348 1349static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr, 1350 int len, uint i, int tso_desc_type, 1351 skb_frag_t *frag, struct wil_ring *ring, 1352 struct sk_buff *skb, bool is_ipv4, 1353 int tcp_hdr_len, int skb_net_hdr_len, 1354 int mss, int *descs_used) 1355{ 1356 struct device *dev = wil_to_dev(wil); 1357 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *) 1358 &ring->va[i].tx.enhanced; 1359 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem; 1360 int ring_index = ring - wil->ring_tx; 1361 dma_addr_t pa; 1362 1363 if (len == 0) 1364 return 0; 1365 1366 if (!frag) { 1367 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE); 1368 ring->ctx[i].mapped_as = wil_mapped_as_single; 1369 } else { 1370 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 1371 ring->ctx[i].mapped_as = wil_mapped_as_page; 1372 } 1373 if (unlikely(dma_mapping_error(dev, pa))) { 1374 wil_err(wil, "TSO: Skb DMA map error\n"); 1375 return -EINVAL; 1376 } 1377 1378 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, 1379 len, ring_index); 1380 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4, 1381 tcp_hdr_len, 1382 skb_net_hdr_len, mss); 1383 1384 /* hold reference to skb 1385 * to prevent skb release before accounting 1386 * in case of immediate "tx done" 1387 */ 1388 if (tso_desc_type == wil_tso_type_lst) 1389 ring->ctx[i].skb = skb_get(skb); 1390 1391 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1392 (const void *)d, sizeof(*d), false); 1393 1394 *_desc = *d; 1395 (*descs_used)++; 1396 1397 return 0; 1398} 1399 1400static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil, 1401 struct wil6210_vif *vif, 1402 struct wil_ring *ring, 1403 struct sk_buff *skb) 1404{ 1405 int ring_index = ring - wil->ring_tx; 1406 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1407 int nr_frags = skb_shinfo(skb)->nr_frags; 1408 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */ 1409 int used, avail = wil_ring_avail_tx(ring); 1410 int f, hdrlen, headlen; 1411 int gso_type; 1412 bool is_ipv4; 1413 u32 swhead = ring->swhead; 1414 int descs_used = 0; /* total number of used descriptors */ 1415 int rc = -EINVAL; 1416 int tcp_hdr_len; 1417 int skb_net_hdr_len; 1418 int mss = skb_shinfo(skb)->gso_size; 1419 1420 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len, 1421 ring_index); 1422 1423 if (unlikely(!txdata->enabled)) 1424 return -EINVAL; 1425 1426 if (unlikely(avail < min_desc_required)) { 1427 wil_err_ratelimited(wil, 1428 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1429 ring_index, min_desc_required); 1430 return -ENOMEM; 1431 } 1432 1433 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1434 switch (gso_type) { 1435 case SKB_GSO_TCPV4: 1436 is_ipv4 = true; 1437 break; 1438 case SKB_GSO_TCPV6: 1439 is_ipv4 = false; 1440 break; 1441 default: 1442 return -EINVAL; 1443 } 1444 1445 if (skb->ip_summed != CHECKSUM_PARTIAL) 1446 return -EINVAL; 1447 1448 /* tcp header length and skb network header length are fixed for all 1449 * packet's descriptors - read them once here 1450 */ 1451 tcp_hdr_len = tcp_hdrlen(skb); 1452 skb_net_hdr_len = skb_network_header_len(skb); 1453 1454 /* First descriptor must contain the header only 1455 * Header Length = MAC header len + IP header len + TCP header len 1456 */ 1457 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len; 1458 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n", 1459 hdrlen); 1460 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead, 1461 wil_tso_type_hdr, NULL, ring, skb, 1462 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1463 mss, &descs_used); 1464 if (rc) 1465 return -EINVAL; 1466 1467 /* Second descriptor contains the head */ 1468 headlen = skb_headlen(skb) - hdrlen; 1469 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen); 1470 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen, 1471 (swhead + descs_used) % ring->size, 1472 (nr_frags != 0) ? wil_tso_type_first : 1473 wil_tso_type_lst, NULL, ring, skb, 1474 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1475 mss, &descs_used); 1476 if (rc) 1477 goto mem_error; 1478 1479 /* Rest of the descriptors are from the SKB fragments */ 1480 for (f = 0; f < nr_frags; f++) { 1481 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1482 int len = skb_frag_size(frag); 1483 1484 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f, 1485 len, descs_used); 1486 1487 rc = wil_tx_tso_gen_desc(wil, NULL, len, 1488 (swhead + descs_used) % ring->size, 1489 (f != nr_frags - 1) ? 1490 wil_tso_type_mid : wil_tso_type_lst, 1491 frag, ring, skb, is_ipv4, 1492 tcp_hdr_len, skb_net_hdr_len, 1493 mss, &descs_used); 1494 if (rc) 1495 goto mem_error; 1496 } 1497 1498 /* performance monitoring */ 1499 used = wil_ring_used_tx(ring); 1500 if (wil_val_in_range(wil->ring_idle_trsh, 1501 used, used + descs_used)) { 1502 txdata->idle += get_cycles() - txdata->last_idle; 1503 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1504 ring_index, used, used + descs_used); 1505 } 1506 1507 /* advance swhead */ 1508 wil_ring_advance_head(ring, descs_used); 1509 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead); 1510 1511 /* make sure all writes to descriptors (shared memory) are done before 1512 * committing them to HW 1513 */ 1514 wmb(); 1515 1516 if (wil->tx_latency) 1517 *(ktime_t *)&skb->cb = ktime_get(); 1518 else 1519 memset(skb->cb, 0, sizeof(ktime_t)); 1520 1521 wil_w(wil, ring->hwtail, ring->swhead); 1522 1523 return 0; 1524 1525mem_error: 1526 while (descs_used > 0) { 1527 struct device *dev = wil_to_dev(wil); 1528 struct wil_ctx *ctx; 1529 int i = (swhead + descs_used - 1) % ring->size; 1530 struct wil_tx_enhanced_desc dd, *d = ⅆ 1531 struct wil_tx_enhanced_desc *_desc = 1532 (struct wil_tx_enhanced_desc *) 1533 &ring->va[i].tx.enhanced; 1534 1535 *d = *_desc; 1536 ctx = &ring->ctx[i]; 1537 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 1538 memset(ctx, 0, sizeof(*ctx)); 1539 descs_used--; 1540 } 1541 return rc; 1542} 1543 1544static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id, 1545 int size) 1546{ 1547 struct wil6210_priv *wil = vif_to_wil(vif); 1548 struct wil_ring *ring = &wil->ring_tx[ring_id]; 1549 int rc; 1550 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1551 1552 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n", 1553 ring_id, wil->tx_sring_idx); 1554 1555 lockdep_assert_held(&wil->mutex); 1556 1557 wil_tx_data_init(txdata); 1558 ring->size = size; 1559 ring->is_rx = false; 1560 rc = wil_ring_alloc_desc_ring(wil, ring); 1561 if (rc) 1562 goto out; 1563 1564 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */ 1565 wil->ring2cid_tid[ring_id][1] = 0; /* TID */ 1566 if (!vif->privacy) 1567 txdata->dot1x_open = true; 1568 1569 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id); 1570 if (rc) 1571 goto out_free; 1572 1573 return 0; 1574 1575 out_free: 1576 spin_lock_bh(&txdata->lock); 1577 txdata->enabled = 0; 1578 txdata->dot1x_open = false; 1579 spin_unlock_bh(&txdata->lock); 1580 wil_ring_free_edma(wil, ring); 1581 1582out: 1583 return rc; 1584} 1585 1586static void wil_tx_fini_edma(struct wil6210_priv *wil) 1587{ 1588 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx]; 1589 1590 wil_dbg_misc(wil, "free TX sring\n"); 1591 1592 wil_sring_free(wil, sring); 1593} 1594 1595static void wil_rx_data_free(struct wil_status_ring *sring) 1596{ 1597 if (!sring) 1598 return; 1599 1600 kfree_skb(sring->rx_data.skb); 1601 sring->rx_data.skb = NULL; 1602} 1603 1604static void wil_rx_fini_edma(struct wil6210_priv *wil) 1605{ 1606 struct wil_ring *ring = &wil->ring_rx; 1607 int i; 1608 1609 wil_dbg_misc(wil, "rx_fini_edma\n"); 1610 1611 wil_ring_free_edma(wil, ring); 1612 1613 for (i = 0; i < wil->num_rx_status_rings; i++) { 1614 wil_rx_data_free(&wil->srings[i]); 1615 wil_sring_free(wil, &wil->srings[i]); 1616 } 1617 1618 wil_free_rx_buff_arr(wil); 1619} 1620 1621void wil_init_txrx_ops_edma(struct wil6210_priv *wil) 1622{ 1623 wil->txrx_ops.configure_interrupt_moderation = 1624 wil_configure_interrupt_moderation_edma; 1625 /* TX ops */ 1626 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma; 1627 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma; 1628 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma; 1629 wil->txrx_ops.tx_init = wil_tx_init_edma; 1630 wil->txrx_ops.tx_fini = wil_tx_fini_edma; 1631 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma; 1632 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma; 1633 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma; 1634 wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma; 1635 /* RX ops */ 1636 wil->txrx_ops.rx_init = wil_rx_init_edma; 1637 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma; 1638 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma; 1639 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma; 1640 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma; 1641 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma; 1642 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma; 1643 wil->txrx_ops.rx_fini = wil_rx_fini_edma; 1644} 1645 1646