18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: ISC 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 48c2ecf20Sopenharmony_ci * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#include <linux/interrupt.h> 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include "wil6210.h" 108c2ecf20Sopenharmony_ci#include "trace.h" 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/** 138c2ecf20Sopenharmony_ci * Theory of operation: 148c2ecf20Sopenharmony_ci * 158c2ecf20Sopenharmony_ci * There is ISR pseudo-cause register, 168c2ecf20Sopenharmony_ci * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE 178c2ecf20Sopenharmony_ci * Its bits represents OR'ed bits from 3 real ISR registers: 188c2ecf20Sopenharmony_ci * TX, RX, and MISC. 198c2ecf20Sopenharmony_ci * 208c2ecf20Sopenharmony_ci * Registers may be configured to either "write 1 to clear" or 218c2ecf20Sopenharmony_ci * "clear on read" mode 228c2ecf20Sopenharmony_ci * 238c2ecf20Sopenharmony_ci * When handling interrupt, one have to mask/unmask interrupts for the 248c2ecf20Sopenharmony_ci * real ISR registers, or hardware may malfunction. 258c2ecf20Sopenharmony_ci * 268c2ecf20Sopenharmony_ci */ 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL) 298c2ecf20Sopenharmony_ci#define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL) 308c2ecf20Sopenharmony_ci#define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \ 318c2ecf20Sopenharmony_ci BIT_DMA_EP_RX_ICR_RX_HTRSH) 328c2ecf20Sopenharmony_ci#define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \ 338c2ecf20Sopenharmony_ci (~(BIT_DMA_EP_RX_ICR_RX_HTRSH))) 348c2ecf20Sopenharmony_ci#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \ 358c2ecf20Sopenharmony_ci BIT_DMA_EP_TX_ICR_TX_DONE_N(0)) 368c2ecf20Sopenharmony_ci#define WIL6210_IMC_TX_EDMA BIT_TX_STATUS_IRQ 378c2ecf20Sopenharmony_ci#define WIL6210_IMC_RX_EDMA BIT_RX_STATUS_IRQ 388c2ecf20Sopenharmony_ci#define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \ 398c2ecf20Sopenharmony_ci ISR_MISC_MBOX_EVT | \ 408c2ecf20Sopenharmony_ci ISR_MISC_FW_ERROR) 418c2ecf20Sopenharmony_ci#define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \ 428c2ecf20Sopenharmony_ci BIT_DMA_EP_MISC_ICR_HALP) 438c2ecf20Sopenharmony_ci#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \ 448c2ecf20Sopenharmony_ci BIT_DMA_PSEUDO_CAUSE_TX | \ 458c2ecf20Sopenharmony_ci BIT_DMA_PSEUDO_CAUSE_MISC)) 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci#if defined(CONFIG_WIL6210_ISR_COR) 488c2ecf20Sopenharmony_ci/* configure to Clear-On-Read mode */ 498c2ecf20Sopenharmony_ci#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL) 508c2ecf20Sopenharmony_ci#define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL) 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_cistatic inline void wil_icr_clear(u32 x, void __iomem *addr) 538c2ecf20Sopenharmony_ci{ 548c2ecf20Sopenharmony_ci} 558c2ecf20Sopenharmony_ci#else /* defined(CONFIG_WIL6210_ISR_COR) */ 568c2ecf20Sopenharmony_ci/* configure to Write-1-to-Clear mode */ 578c2ecf20Sopenharmony_ci#define WIL_ICR_ICC_VALUE (0UL) 588c2ecf20Sopenharmony_ci#define WIL_ICR_ICC_MISC_VALUE (0UL) 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_cistatic inline void wil_icr_clear(u32 x, void __iomem *addr) 618c2ecf20Sopenharmony_ci{ 628c2ecf20Sopenharmony_ci writel(x, addr); 638c2ecf20Sopenharmony_ci} 648c2ecf20Sopenharmony_ci#endif /* defined(CONFIG_WIL6210_ISR_COR) */ 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_cistatic inline u32 wil_ioread32_and_clear(void __iomem *addr) 678c2ecf20Sopenharmony_ci{ 688c2ecf20Sopenharmony_ci u32 x = readl(addr); 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci wil_icr_clear(x, addr); 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci return x; 738c2ecf20Sopenharmony_ci} 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_cistatic void wil6210_mask_irq_tx(struct wil6210_priv *wil) 768c2ecf20Sopenharmony_ci{ 778c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS), 788c2ecf20Sopenharmony_ci WIL6210_IRQ_DISABLE); 798c2ecf20Sopenharmony_ci} 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_cistatic void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil) 828c2ecf20Sopenharmony_ci{ 838c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS), 848c2ecf20Sopenharmony_ci WIL6210_IRQ_DISABLE); 858c2ecf20Sopenharmony_ci} 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_cistatic void wil6210_mask_irq_rx(struct wil6210_priv *wil) 888c2ecf20Sopenharmony_ci{ 898c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS), 908c2ecf20Sopenharmony_ci WIL6210_IRQ_DISABLE); 918c2ecf20Sopenharmony_ci} 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_cistatic void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil) 948c2ecf20Sopenharmony_ci{ 958c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS), 968c2ecf20Sopenharmony_ci WIL6210_IRQ_DISABLE); 978c2ecf20Sopenharmony_ci} 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_cistatic void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp) 1008c2ecf20Sopenharmony_ci{ 1018c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n", 1028c2ecf20Sopenharmony_ci mask_halp ? "true" : "false"); 1038c2ecf20Sopenharmony_ci 1048c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), 1058c2ecf20Sopenharmony_ci mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP); 1068c2ecf20Sopenharmony_ci} 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_civoid wil6210_mask_halp(struct wil6210_priv *wil) 1098c2ecf20Sopenharmony_ci{ 1108c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "mask_halp\n"); 1118c2ecf20Sopenharmony_ci 1128c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), 1138c2ecf20Sopenharmony_ci BIT_DMA_EP_MISC_ICR_HALP); 1148c2ecf20Sopenharmony_ci} 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_cistatic void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) 1178c2ecf20Sopenharmony_ci{ 1188c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "mask_irq_pseudo\n"); 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE); 1218c2ecf20Sopenharmony_ci 1228c2ecf20Sopenharmony_ci clear_bit(wil_status_irqen, wil->status); 1238c2ecf20Sopenharmony_ci} 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_civoid wil6210_unmask_irq_tx(struct wil6210_priv *wil) 1268c2ecf20Sopenharmony_ci{ 1278c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC), 1288c2ecf20Sopenharmony_ci WIL6210_IMC_TX); 1298c2ecf20Sopenharmony_ci} 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_civoid wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil) 1328c2ecf20Sopenharmony_ci{ 1338c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC), 1348c2ecf20Sopenharmony_ci WIL6210_IMC_TX_EDMA); 1358c2ecf20Sopenharmony_ci} 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_civoid wil6210_unmask_irq_rx(struct wil6210_priv *wil) 1388c2ecf20Sopenharmony_ci{ 1398c2ecf20Sopenharmony_ci bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; 1408c2ecf20Sopenharmony_ci 1418c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC), 1428c2ecf20Sopenharmony_ci unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH); 1438c2ecf20Sopenharmony_ci} 1448c2ecf20Sopenharmony_ci 1458c2ecf20Sopenharmony_civoid wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil) 1468c2ecf20Sopenharmony_ci{ 1478c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC), 1488c2ecf20Sopenharmony_ci WIL6210_IMC_RX_EDMA); 1498c2ecf20Sopenharmony_ci} 1508c2ecf20Sopenharmony_ci 1518c2ecf20Sopenharmony_cistatic void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp) 1528c2ecf20Sopenharmony_ci{ 1538c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n", 1548c2ecf20Sopenharmony_ci unmask_halp ? "true" : "false"); 1558c2ecf20Sopenharmony_ci 1568c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), 1578c2ecf20Sopenharmony_ci unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP); 1588c2ecf20Sopenharmony_ci} 1598c2ecf20Sopenharmony_ci 1608c2ecf20Sopenharmony_cistatic void wil6210_unmask_halp(struct wil6210_priv *wil) 1618c2ecf20Sopenharmony_ci{ 1628c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "unmask_halp\n"); 1638c2ecf20Sopenharmony_ci 1648c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), 1658c2ecf20Sopenharmony_ci BIT_DMA_EP_MISC_ICR_HALP); 1668c2ecf20Sopenharmony_ci} 1678c2ecf20Sopenharmony_ci 1688c2ecf20Sopenharmony_cistatic void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) 1698c2ecf20Sopenharmony_ci{ 1708c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "unmask_irq_pseudo\n"); 1718c2ecf20Sopenharmony_ci 1728c2ecf20Sopenharmony_ci set_bit(wil_status_irqen, wil->status); 1738c2ecf20Sopenharmony_ci 1748c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK); 1758c2ecf20Sopenharmony_ci} 1768c2ecf20Sopenharmony_ci 1778c2ecf20Sopenharmony_civoid wil_mask_irq(struct wil6210_priv *wil) 1788c2ecf20Sopenharmony_ci{ 1798c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "mask_irq\n"); 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_ci wil6210_mask_irq_tx(wil); 1828c2ecf20Sopenharmony_ci wil6210_mask_irq_tx_edma(wil); 1838c2ecf20Sopenharmony_ci wil6210_mask_irq_rx(wil); 1848c2ecf20Sopenharmony_ci wil6210_mask_irq_rx_edma(wil); 1858c2ecf20Sopenharmony_ci wil6210_mask_irq_misc(wil, true); 1868c2ecf20Sopenharmony_ci wil6210_mask_irq_pseudo(wil); 1878c2ecf20Sopenharmony_ci} 1888c2ecf20Sopenharmony_ci 1898c2ecf20Sopenharmony_civoid wil_unmask_irq(struct wil6210_priv *wil) 1908c2ecf20Sopenharmony_ci{ 1918c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "unmask_irq\n"); 1928c2ecf20Sopenharmony_ci 1938c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC), 1948c2ecf20Sopenharmony_ci WIL_ICR_ICC_VALUE); 1958c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC), 1968c2ecf20Sopenharmony_ci WIL_ICR_ICC_VALUE); 1978c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC), 1988c2ecf20Sopenharmony_ci WIL_ICR_ICC_MISC_VALUE); 1998c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC), 2008c2ecf20Sopenharmony_ci WIL_ICR_ICC_VALUE); 2018c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC), 2028c2ecf20Sopenharmony_ci WIL_ICR_ICC_VALUE); 2038c2ecf20Sopenharmony_ci 2048c2ecf20Sopenharmony_ci wil6210_unmask_irq_pseudo(wil); 2058c2ecf20Sopenharmony_ci if (wil->use_enhanced_dma_hw) { 2068c2ecf20Sopenharmony_ci wil6210_unmask_irq_tx_edma(wil); 2078c2ecf20Sopenharmony_ci wil6210_unmask_irq_rx_edma(wil); 2088c2ecf20Sopenharmony_ci } else { 2098c2ecf20Sopenharmony_ci wil6210_unmask_irq_tx(wil); 2108c2ecf20Sopenharmony_ci wil6210_unmask_irq_rx(wil); 2118c2ecf20Sopenharmony_ci } 2128c2ecf20Sopenharmony_ci wil6210_unmask_irq_misc(wil, true); 2138c2ecf20Sopenharmony_ci} 2148c2ecf20Sopenharmony_ci 2158c2ecf20Sopenharmony_civoid wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil) 2168c2ecf20Sopenharmony_ci{ 2178c2ecf20Sopenharmony_ci u32 moderation; 2188c2ecf20Sopenharmony_ci 2198c2ecf20Sopenharmony_ci wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC); 2208c2ecf20Sopenharmony_ci 2218c2ecf20Sopenharmony_ci wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES); 2228c2ecf20Sopenharmony_ci 2238c2ecf20Sopenharmony_ci /* Update RX and TX moderation */ 2248c2ecf20Sopenharmony_ci moderation = wil->rx_max_burst_duration | 2258c2ecf20Sopenharmony_ci (WIL_EDMA_AGG_WATERMARK << WIL_EDMA_AGG_WATERMARK_POS); 2268c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation); 2278c2ecf20Sopenharmony_ci wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation); 2288c2ecf20Sopenharmony_ci 2298c2ecf20Sopenharmony_ci /* Treat special events as regular 2308c2ecf20Sopenharmony_ci * (set bit 0 to 0x1 and clear bits 1-8) 2318c2ecf20Sopenharmony_ci */ 2328c2ecf20Sopenharmony_ci wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE); 2338c2ecf20Sopenharmony_ci wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1); 2348c2ecf20Sopenharmony_ci} 2358c2ecf20Sopenharmony_ci 2368c2ecf20Sopenharmony_civoid wil_configure_interrupt_moderation(struct wil6210_priv *wil) 2378c2ecf20Sopenharmony_ci{ 2388c2ecf20Sopenharmony_ci struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr; 2398c2ecf20Sopenharmony_ci 2408c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "configure_interrupt_moderation\n"); 2418c2ecf20Sopenharmony_ci 2428c2ecf20Sopenharmony_ci /* disable interrupt moderation for monitor 2438c2ecf20Sopenharmony_ci * to get better timestamp precision 2448c2ecf20Sopenharmony_ci */ 2458c2ecf20Sopenharmony_ci if (wdev->iftype == NL80211_IFTYPE_MONITOR) 2468c2ecf20Sopenharmony_ci return; 2478c2ecf20Sopenharmony_ci 2488c2ecf20Sopenharmony_ci /* Disable and clear tx counter before (re)configuration */ 2498c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR); 2508c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); 2518c2ecf20Sopenharmony_ci wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n", 2528c2ecf20Sopenharmony_ci wil->tx_max_burst_duration); 2538c2ecf20Sopenharmony_ci /* Configure TX max burst duration timer to use usec units */ 2548c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, 2558c2ecf20Sopenharmony_ci BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL); 2568c2ecf20Sopenharmony_ci 2578c2ecf20Sopenharmony_ci /* Disable and clear tx idle counter before (re)configuration */ 2588c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR); 2598c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); 2608c2ecf20Sopenharmony_ci wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n", 2618c2ecf20Sopenharmony_ci wil->tx_interframe_timeout); 2628c2ecf20Sopenharmony_ci /* Configure TX max burst duration timer to use usec units */ 2638c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN | 2648c2ecf20Sopenharmony_ci BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL); 2658c2ecf20Sopenharmony_ci 2668c2ecf20Sopenharmony_ci /* Disable and clear rx counter before (re)configuration */ 2678c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR); 2688c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); 2698c2ecf20Sopenharmony_ci wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n", 2708c2ecf20Sopenharmony_ci wil->rx_max_burst_duration); 2718c2ecf20Sopenharmony_ci /* Configure TX max burst duration timer to use usec units */ 2728c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, 2738c2ecf20Sopenharmony_ci BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL); 2748c2ecf20Sopenharmony_ci 2758c2ecf20Sopenharmony_ci /* Disable and clear rx idle counter before (re)configuration */ 2768c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR); 2778c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); 2788c2ecf20Sopenharmony_ci wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n", 2798c2ecf20Sopenharmony_ci wil->rx_interframe_timeout); 2808c2ecf20Sopenharmony_ci /* Configure TX max burst duration timer to use usec units */ 2818c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN | 2828c2ecf20Sopenharmony_ci BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL); 2838c2ecf20Sopenharmony_ci} 2848c2ecf20Sopenharmony_ci 2858c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_irq_rx(int irq, void *cookie) 2868c2ecf20Sopenharmony_ci{ 2878c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 2888c2ecf20Sopenharmony_ci u32 isr; 2898c2ecf20Sopenharmony_ci bool need_unmask = true; 2908c2ecf20Sopenharmony_ci 2918c2ecf20Sopenharmony_ci wil6210_mask_irq_rx(wil); 2928c2ecf20Sopenharmony_ci 2938c2ecf20Sopenharmony_ci isr = wil_ioread32_and_clear(wil->csr + 2948c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_RX_ICR) + 2958c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 2968c2ecf20Sopenharmony_ci 2978c2ecf20Sopenharmony_ci trace_wil6210_irq_rx(isr); 2988c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); 2998c2ecf20Sopenharmony_ci 3008c2ecf20Sopenharmony_ci if (unlikely(!isr)) { 3018c2ecf20Sopenharmony_ci wil_err_ratelimited(wil, "spurious IRQ: RX\n"); 3028c2ecf20Sopenharmony_ci wil6210_unmask_irq_rx(wil); 3038c2ecf20Sopenharmony_ci return IRQ_NONE; 3048c2ecf20Sopenharmony_ci } 3058c2ecf20Sopenharmony_ci 3068c2ecf20Sopenharmony_ci /* RX_DONE and RX_HTRSH interrupts are the same if interrupt 3078c2ecf20Sopenharmony_ci * moderation is not used. Interrupt moderation may cause RX 3088c2ecf20Sopenharmony_ci * buffer overflow while RX_DONE is delayed. The required 3098c2ecf20Sopenharmony_ci * action is always the same - should empty the accumulated 3108c2ecf20Sopenharmony_ci * packets from the RX ring. 3118c2ecf20Sopenharmony_ci */ 3128c2ecf20Sopenharmony_ci if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE | 3138c2ecf20Sopenharmony_ci BIT_DMA_EP_RX_ICR_RX_HTRSH))) { 3148c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n", 3158c2ecf20Sopenharmony_ci isr); 3168c2ecf20Sopenharmony_ci 3178c2ecf20Sopenharmony_ci isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE | 3188c2ecf20Sopenharmony_ci BIT_DMA_EP_RX_ICR_RX_HTRSH); 3198c2ecf20Sopenharmony_ci if (likely(test_bit(wil_status_fwready, wil->status))) { 3208c2ecf20Sopenharmony_ci if (likely(test_bit(wil_status_napi_en, wil->status))) { 3218c2ecf20Sopenharmony_ci wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); 3228c2ecf20Sopenharmony_ci need_unmask = false; 3238c2ecf20Sopenharmony_ci napi_schedule(&wil->napi_rx); 3248c2ecf20Sopenharmony_ci } else { 3258c2ecf20Sopenharmony_ci wil_err_ratelimited( 3268c2ecf20Sopenharmony_ci wil, 3278c2ecf20Sopenharmony_ci "Got Rx interrupt while stopping interface\n"); 3288c2ecf20Sopenharmony_ci } 3298c2ecf20Sopenharmony_ci } else { 3308c2ecf20Sopenharmony_ci wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n"); 3318c2ecf20Sopenharmony_ci } 3328c2ecf20Sopenharmony_ci } 3338c2ecf20Sopenharmony_ci 3348c2ecf20Sopenharmony_ci if (unlikely(isr)) 3358c2ecf20Sopenharmony_ci wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); 3368c2ecf20Sopenharmony_ci 3378c2ecf20Sopenharmony_ci /* Rx IRQ will be enabled when NAPI processing finished */ 3388c2ecf20Sopenharmony_ci 3398c2ecf20Sopenharmony_ci atomic_inc(&wil->isr_count_rx); 3408c2ecf20Sopenharmony_ci 3418c2ecf20Sopenharmony_ci if (unlikely(need_unmask)) 3428c2ecf20Sopenharmony_ci wil6210_unmask_irq_rx(wil); 3438c2ecf20Sopenharmony_ci 3448c2ecf20Sopenharmony_ci return IRQ_HANDLED; 3458c2ecf20Sopenharmony_ci} 3468c2ecf20Sopenharmony_ci 3478c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_irq_rx_edma(int irq, void *cookie) 3488c2ecf20Sopenharmony_ci{ 3498c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 3508c2ecf20Sopenharmony_ci u32 isr; 3518c2ecf20Sopenharmony_ci bool need_unmask = true; 3528c2ecf20Sopenharmony_ci 3538c2ecf20Sopenharmony_ci wil6210_mask_irq_rx_edma(wil); 3548c2ecf20Sopenharmony_ci 3558c2ecf20Sopenharmony_ci isr = wil_ioread32_and_clear(wil->csr + 3568c2ecf20Sopenharmony_ci HOSTADDR(RGF_INT_GEN_RX_ICR) + 3578c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 3588c2ecf20Sopenharmony_ci 3598c2ecf20Sopenharmony_ci trace_wil6210_irq_rx(isr); 3608c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); 3618c2ecf20Sopenharmony_ci 3628c2ecf20Sopenharmony_ci if (unlikely(!isr)) { 3638c2ecf20Sopenharmony_ci wil_err(wil, "spurious IRQ: RX\n"); 3648c2ecf20Sopenharmony_ci wil6210_unmask_irq_rx_edma(wil); 3658c2ecf20Sopenharmony_ci return IRQ_NONE; 3668c2ecf20Sopenharmony_ci } 3678c2ecf20Sopenharmony_ci 3688c2ecf20Sopenharmony_ci if (likely(isr & BIT_RX_STATUS_IRQ)) { 3698c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "RX status ring\n"); 3708c2ecf20Sopenharmony_ci isr &= ~BIT_RX_STATUS_IRQ; 3718c2ecf20Sopenharmony_ci if (likely(test_bit(wil_status_fwready, wil->status))) { 3728c2ecf20Sopenharmony_ci if (likely(test_bit(wil_status_napi_en, wil->status))) { 3738c2ecf20Sopenharmony_ci wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); 3748c2ecf20Sopenharmony_ci need_unmask = false; 3758c2ecf20Sopenharmony_ci napi_schedule(&wil->napi_rx); 3768c2ecf20Sopenharmony_ci } else { 3778c2ecf20Sopenharmony_ci wil_err(wil, 3788c2ecf20Sopenharmony_ci "Got Rx interrupt while stopping interface\n"); 3798c2ecf20Sopenharmony_ci } 3808c2ecf20Sopenharmony_ci } else { 3818c2ecf20Sopenharmony_ci wil_err(wil, "Got Rx interrupt while in reset\n"); 3828c2ecf20Sopenharmony_ci } 3838c2ecf20Sopenharmony_ci } 3848c2ecf20Sopenharmony_ci 3858c2ecf20Sopenharmony_ci if (unlikely(isr)) 3868c2ecf20Sopenharmony_ci wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); 3878c2ecf20Sopenharmony_ci 3888c2ecf20Sopenharmony_ci /* Rx IRQ will be enabled when NAPI processing finished */ 3898c2ecf20Sopenharmony_ci 3908c2ecf20Sopenharmony_ci atomic_inc(&wil->isr_count_rx); 3918c2ecf20Sopenharmony_ci 3928c2ecf20Sopenharmony_ci if (unlikely(need_unmask)) 3938c2ecf20Sopenharmony_ci wil6210_unmask_irq_rx_edma(wil); 3948c2ecf20Sopenharmony_ci 3958c2ecf20Sopenharmony_ci return IRQ_HANDLED; 3968c2ecf20Sopenharmony_ci} 3978c2ecf20Sopenharmony_ci 3988c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_irq_tx_edma(int irq, void *cookie) 3998c2ecf20Sopenharmony_ci{ 4008c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 4018c2ecf20Sopenharmony_ci u32 isr; 4028c2ecf20Sopenharmony_ci bool need_unmask = true; 4038c2ecf20Sopenharmony_ci 4048c2ecf20Sopenharmony_ci wil6210_mask_irq_tx_edma(wil); 4058c2ecf20Sopenharmony_ci 4068c2ecf20Sopenharmony_ci isr = wil_ioread32_and_clear(wil->csr + 4078c2ecf20Sopenharmony_ci HOSTADDR(RGF_INT_GEN_TX_ICR) + 4088c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 4098c2ecf20Sopenharmony_ci 4108c2ecf20Sopenharmony_ci trace_wil6210_irq_tx(isr); 4118c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); 4128c2ecf20Sopenharmony_ci 4138c2ecf20Sopenharmony_ci if (unlikely(!isr)) { 4148c2ecf20Sopenharmony_ci wil_err(wil, "spurious IRQ: TX\n"); 4158c2ecf20Sopenharmony_ci wil6210_unmask_irq_tx_edma(wil); 4168c2ecf20Sopenharmony_ci return IRQ_NONE; 4178c2ecf20Sopenharmony_ci } 4188c2ecf20Sopenharmony_ci 4198c2ecf20Sopenharmony_ci if (likely(isr & BIT_TX_STATUS_IRQ)) { 4208c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "TX status ring\n"); 4218c2ecf20Sopenharmony_ci isr &= ~BIT_TX_STATUS_IRQ; 4228c2ecf20Sopenharmony_ci if (likely(test_bit(wil_status_fwready, wil->status))) { 4238c2ecf20Sopenharmony_ci wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); 4248c2ecf20Sopenharmony_ci need_unmask = false; 4258c2ecf20Sopenharmony_ci napi_schedule(&wil->napi_tx); 4268c2ecf20Sopenharmony_ci } else { 4278c2ecf20Sopenharmony_ci wil_err(wil, "Got Tx status ring IRQ while in reset\n"); 4288c2ecf20Sopenharmony_ci } 4298c2ecf20Sopenharmony_ci } 4308c2ecf20Sopenharmony_ci 4318c2ecf20Sopenharmony_ci if (unlikely(isr)) 4328c2ecf20Sopenharmony_ci wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); 4338c2ecf20Sopenharmony_ci 4348c2ecf20Sopenharmony_ci /* Tx IRQ will be enabled when NAPI processing finished */ 4358c2ecf20Sopenharmony_ci 4368c2ecf20Sopenharmony_ci atomic_inc(&wil->isr_count_tx); 4378c2ecf20Sopenharmony_ci 4388c2ecf20Sopenharmony_ci if (unlikely(need_unmask)) 4398c2ecf20Sopenharmony_ci wil6210_unmask_irq_tx_edma(wil); 4408c2ecf20Sopenharmony_ci 4418c2ecf20Sopenharmony_ci return IRQ_HANDLED; 4428c2ecf20Sopenharmony_ci} 4438c2ecf20Sopenharmony_ci 4448c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_irq_tx(int irq, void *cookie) 4458c2ecf20Sopenharmony_ci{ 4468c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 4478c2ecf20Sopenharmony_ci u32 isr; 4488c2ecf20Sopenharmony_ci bool need_unmask = true; 4498c2ecf20Sopenharmony_ci 4508c2ecf20Sopenharmony_ci wil6210_mask_irq_tx(wil); 4518c2ecf20Sopenharmony_ci 4528c2ecf20Sopenharmony_ci isr = wil_ioread32_and_clear(wil->csr + 4538c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_TX_ICR) + 4548c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 4558c2ecf20Sopenharmony_ci 4568c2ecf20Sopenharmony_ci trace_wil6210_irq_tx(isr); 4578c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); 4588c2ecf20Sopenharmony_ci 4598c2ecf20Sopenharmony_ci if (unlikely(!isr)) { 4608c2ecf20Sopenharmony_ci wil_err_ratelimited(wil, "spurious IRQ: TX\n"); 4618c2ecf20Sopenharmony_ci wil6210_unmask_irq_tx(wil); 4628c2ecf20Sopenharmony_ci return IRQ_NONE; 4638c2ecf20Sopenharmony_ci } 4648c2ecf20Sopenharmony_ci 4658c2ecf20Sopenharmony_ci if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) { 4668c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "TX done\n"); 4678c2ecf20Sopenharmony_ci isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE; 4688c2ecf20Sopenharmony_ci /* clear also all VRING interrupts */ 4698c2ecf20Sopenharmony_ci isr &= ~(BIT(25) - 1UL); 4708c2ecf20Sopenharmony_ci if (likely(test_bit(wil_status_fwready, wil->status))) { 4718c2ecf20Sopenharmony_ci wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); 4728c2ecf20Sopenharmony_ci need_unmask = false; 4738c2ecf20Sopenharmony_ci napi_schedule(&wil->napi_tx); 4748c2ecf20Sopenharmony_ci } else { 4758c2ecf20Sopenharmony_ci wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n"); 4768c2ecf20Sopenharmony_ci } 4778c2ecf20Sopenharmony_ci } 4788c2ecf20Sopenharmony_ci 4798c2ecf20Sopenharmony_ci if (unlikely(isr)) 4808c2ecf20Sopenharmony_ci wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", 4818c2ecf20Sopenharmony_ci isr); 4828c2ecf20Sopenharmony_ci 4838c2ecf20Sopenharmony_ci /* Tx IRQ will be enabled when NAPI processing finished */ 4848c2ecf20Sopenharmony_ci 4858c2ecf20Sopenharmony_ci atomic_inc(&wil->isr_count_tx); 4868c2ecf20Sopenharmony_ci 4878c2ecf20Sopenharmony_ci if (unlikely(need_unmask)) 4888c2ecf20Sopenharmony_ci wil6210_unmask_irq_tx(wil); 4898c2ecf20Sopenharmony_ci 4908c2ecf20Sopenharmony_ci return IRQ_HANDLED; 4918c2ecf20Sopenharmony_ci} 4928c2ecf20Sopenharmony_ci 4938c2ecf20Sopenharmony_cistatic void wil_notify_fw_error(struct wil6210_priv *wil) 4948c2ecf20Sopenharmony_ci{ 4958c2ecf20Sopenharmony_ci struct device *dev = &wil->main_ndev->dev; 4968c2ecf20Sopenharmony_ci char *envp[3] = { 4978c2ecf20Sopenharmony_ci [0] = "SOURCE=wil6210", 4988c2ecf20Sopenharmony_ci [1] = "EVENT=FW_ERROR", 4998c2ecf20Sopenharmony_ci [2] = NULL, 5008c2ecf20Sopenharmony_ci }; 5018c2ecf20Sopenharmony_ci wil_err(wil, "Notify about firmware error\n"); 5028c2ecf20Sopenharmony_ci kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp); 5038c2ecf20Sopenharmony_ci} 5048c2ecf20Sopenharmony_ci 5058c2ecf20Sopenharmony_cistatic void wil_cache_mbox_regs(struct wil6210_priv *wil) 5068c2ecf20Sopenharmony_ci{ 5078c2ecf20Sopenharmony_ci /* make shadow copy of registers that should not change on run time */ 5088c2ecf20Sopenharmony_ci wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, 5098c2ecf20Sopenharmony_ci sizeof(struct wil6210_mbox_ctl)); 5108c2ecf20Sopenharmony_ci wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); 5118c2ecf20Sopenharmony_ci wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); 5128c2ecf20Sopenharmony_ci} 5138c2ecf20Sopenharmony_ci 5148c2ecf20Sopenharmony_cistatic bool wil_validate_mbox_regs(struct wil6210_priv *wil) 5158c2ecf20Sopenharmony_ci{ 5168c2ecf20Sopenharmony_ci size_t min_size = sizeof(struct wil6210_mbox_hdr) + 5178c2ecf20Sopenharmony_ci sizeof(struct wmi_cmd_hdr); 5188c2ecf20Sopenharmony_ci 5198c2ecf20Sopenharmony_ci if (wil->mbox_ctl.rx.entry_size < min_size) { 5208c2ecf20Sopenharmony_ci wil_err(wil, "rx mbox entry too small (%d)\n", 5218c2ecf20Sopenharmony_ci wil->mbox_ctl.rx.entry_size); 5228c2ecf20Sopenharmony_ci return false; 5238c2ecf20Sopenharmony_ci } 5248c2ecf20Sopenharmony_ci if (wil->mbox_ctl.tx.entry_size < min_size) { 5258c2ecf20Sopenharmony_ci wil_err(wil, "tx mbox entry too small (%d)\n", 5268c2ecf20Sopenharmony_ci wil->mbox_ctl.tx.entry_size); 5278c2ecf20Sopenharmony_ci return false; 5288c2ecf20Sopenharmony_ci } 5298c2ecf20Sopenharmony_ci 5308c2ecf20Sopenharmony_ci return true; 5318c2ecf20Sopenharmony_ci} 5328c2ecf20Sopenharmony_ci 5338c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_irq_misc(int irq, void *cookie) 5348c2ecf20Sopenharmony_ci{ 5358c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 5368c2ecf20Sopenharmony_ci u32 isr; 5378c2ecf20Sopenharmony_ci 5388c2ecf20Sopenharmony_ci wil6210_mask_irq_misc(wil, false); 5398c2ecf20Sopenharmony_ci 5408c2ecf20Sopenharmony_ci isr = wil_ioread32_and_clear(wil->csr + 5418c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_MISC_ICR) + 5428c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 5438c2ecf20Sopenharmony_ci 5448c2ecf20Sopenharmony_ci trace_wil6210_irq_misc(isr); 5458c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); 5468c2ecf20Sopenharmony_ci 5478c2ecf20Sopenharmony_ci if (!isr) { 5488c2ecf20Sopenharmony_ci wil_err(wil, "spurious IRQ: MISC\n"); 5498c2ecf20Sopenharmony_ci wil6210_unmask_irq_misc(wil, false); 5508c2ecf20Sopenharmony_ci return IRQ_NONE; 5518c2ecf20Sopenharmony_ci } 5528c2ecf20Sopenharmony_ci 5538c2ecf20Sopenharmony_ci if (isr & ISR_MISC_FW_ERROR) { 5548c2ecf20Sopenharmony_ci u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr); 5558c2ecf20Sopenharmony_ci u32 ucode_assert_code = 5568c2ecf20Sopenharmony_ci wil_r(wil, wil->rgf_ucode_assert_code_addr); 5578c2ecf20Sopenharmony_ci 5588c2ecf20Sopenharmony_ci wil_err(wil, 5598c2ecf20Sopenharmony_ci "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n", 5608c2ecf20Sopenharmony_ci fw_assert_code, ucode_assert_code); 5618c2ecf20Sopenharmony_ci clear_bit(wil_status_fwready, wil->status); 5628c2ecf20Sopenharmony_ci /* 5638c2ecf20Sopenharmony_ci * do not clear @isr here - we do 2-nd part in thread 5648c2ecf20Sopenharmony_ci * there, user space get notified, and it should be done 5658c2ecf20Sopenharmony_ci * in non-atomic context 5668c2ecf20Sopenharmony_ci */ 5678c2ecf20Sopenharmony_ci } 5688c2ecf20Sopenharmony_ci 5698c2ecf20Sopenharmony_ci if (isr & ISR_MISC_FW_READY) { 5708c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "IRQ: FW ready\n"); 5718c2ecf20Sopenharmony_ci wil_cache_mbox_regs(wil); 5728c2ecf20Sopenharmony_ci if (wil_validate_mbox_regs(wil)) 5738c2ecf20Sopenharmony_ci set_bit(wil_status_mbox_ready, wil->status); 5748c2ecf20Sopenharmony_ci /** 5758c2ecf20Sopenharmony_ci * Actual FW ready indicated by the 5768c2ecf20Sopenharmony_ci * WMI_FW_READY_EVENTID 5778c2ecf20Sopenharmony_ci */ 5788c2ecf20Sopenharmony_ci isr &= ~ISR_MISC_FW_READY; 5798c2ecf20Sopenharmony_ci } 5808c2ecf20Sopenharmony_ci 5818c2ecf20Sopenharmony_ci if (isr & BIT_DMA_EP_MISC_ICR_HALP) { 5828c2ecf20Sopenharmony_ci isr &= ~BIT_DMA_EP_MISC_ICR_HALP; 5838c2ecf20Sopenharmony_ci if (wil->halp.handle_icr) { 5848c2ecf20Sopenharmony_ci /* no need to handle HALP ICRs until next vote */ 5858c2ecf20Sopenharmony_ci wil->halp.handle_icr = false; 5868c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n"); 5878c2ecf20Sopenharmony_ci wil6210_mask_irq_misc(wil, true); 5888c2ecf20Sopenharmony_ci complete(&wil->halp.comp); 5898c2ecf20Sopenharmony_ci } 5908c2ecf20Sopenharmony_ci } 5918c2ecf20Sopenharmony_ci 5928c2ecf20Sopenharmony_ci wil->isr_misc = isr; 5938c2ecf20Sopenharmony_ci 5948c2ecf20Sopenharmony_ci if (isr) { 5958c2ecf20Sopenharmony_ci return IRQ_WAKE_THREAD; 5968c2ecf20Sopenharmony_ci } else { 5978c2ecf20Sopenharmony_ci wil6210_unmask_irq_misc(wil, false); 5988c2ecf20Sopenharmony_ci return IRQ_HANDLED; 5998c2ecf20Sopenharmony_ci } 6008c2ecf20Sopenharmony_ci} 6018c2ecf20Sopenharmony_ci 6028c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie) 6038c2ecf20Sopenharmony_ci{ 6048c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 6058c2ecf20Sopenharmony_ci u32 isr = wil->isr_misc; 6068c2ecf20Sopenharmony_ci 6078c2ecf20Sopenharmony_ci trace_wil6210_irq_misc_thread(isr); 6088c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); 6098c2ecf20Sopenharmony_ci 6108c2ecf20Sopenharmony_ci if (isr & ISR_MISC_FW_ERROR) { 6118c2ecf20Sopenharmony_ci wil->recovery_state = fw_recovery_pending; 6128c2ecf20Sopenharmony_ci wil_fw_core_dump(wil); 6138c2ecf20Sopenharmony_ci wil_notify_fw_error(wil); 6148c2ecf20Sopenharmony_ci isr &= ~ISR_MISC_FW_ERROR; 6158c2ecf20Sopenharmony_ci if (wil->platform_ops.notify) { 6168c2ecf20Sopenharmony_ci wil_err(wil, "notify platform driver about FW crash"); 6178c2ecf20Sopenharmony_ci wil->platform_ops.notify(wil->platform_handle, 6188c2ecf20Sopenharmony_ci WIL_PLATFORM_EVT_FW_CRASH); 6198c2ecf20Sopenharmony_ci } else { 6208c2ecf20Sopenharmony_ci wil_fw_error_recovery(wil); 6218c2ecf20Sopenharmony_ci } 6228c2ecf20Sopenharmony_ci } 6238c2ecf20Sopenharmony_ci if (isr & ISR_MISC_MBOX_EVT) { 6248c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "MBOX event\n"); 6258c2ecf20Sopenharmony_ci wmi_recv_cmd(wil); 6268c2ecf20Sopenharmony_ci isr &= ~ISR_MISC_MBOX_EVT; 6278c2ecf20Sopenharmony_ci } 6288c2ecf20Sopenharmony_ci 6298c2ecf20Sopenharmony_ci if (isr) 6308c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); 6318c2ecf20Sopenharmony_ci 6328c2ecf20Sopenharmony_ci wil->isr_misc = 0; 6338c2ecf20Sopenharmony_ci 6348c2ecf20Sopenharmony_ci wil6210_unmask_irq_misc(wil, false); 6358c2ecf20Sopenharmony_ci 6368c2ecf20Sopenharmony_ci /* in non-triple MSI case, this is done inside wil6210_thread_irq 6378c2ecf20Sopenharmony_ci * because it has to be done after unmasking the pseudo. 6388c2ecf20Sopenharmony_ci */ 6398c2ecf20Sopenharmony_ci if (wil->n_msi == 3 && wil->suspend_resp_rcvd) { 6408c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); 6418c2ecf20Sopenharmony_ci wil->suspend_resp_comp = true; 6428c2ecf20Sopenharmony_ci wake_up_interruptible(&wil->wq); 6438c2ecf20Sopenharmony_ci } 6448c2ecf20Sopenharmony_ci 6458c2ecf20Sopenharmony_ci return IRQ_HANDLED; 6468c2ecf20Sopenharmony_ci} 6478c2ecf20Sopenharmony_ci 6488c2ecf20Sopenharmony_ci/* thread IRQ handler */ 6498c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_thread_irq(int irq, void *cookie) 6508c2ecf20Sopenharmony_ci{ 6518c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 6528c2ecf20Sopenharmony_ci 6538c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "Thread IRQ\n"); 6548c2ecf20Sopenharmony_ci /* Discover real IRQ cause */ 6558c2ecf20Sopenharmony_ci if (wil->isr_misc) 6568c2ecf20Sopenharmony_ci wil6210_irq_misc_thread(irq, cookie); 6578c2ecf20Sopenharmony_ci 6588c2ecf20Sopenharmony_ci wil6210_unmask_irq_pseudo(wil); 6598c2ecf20Sopenharmony_ci 6608c2ecf20Sopenharmony_ci if (wil->suspend_resp_rcvd) { 6618c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); 6628c2ecf20Sopenharmony_ci wil->suspend_resp_comp = true; 6638c2ecf20Sopenharmony_ci wake_up_interruptible(&wil->wq); 6648c2ecf20Sopenharmony_ci } 6658c2ecf20Sopenharmony_ci 6668c2ecf20Sopenharmony_ci return IRQ_HANDLED; 6678c2ecf20Sopenharmony_ci} 6688c2ecf20Sopenharmony_ci 6698c2ecf20Sopenharmony_ci/* DEBUG 6708c2ecf20Sopenharmony_ci * There is subtle bug in hardware that causes IRQ to raise when it should be 6718c2ecf20Sopenharmony_ci * masked. It is quite rare and hard to debug. 6728c2ecf20Sopenharmony_ci * 6738c2ecf20Sopenharmony_ci * Catch irq issue if it happens and print all I can. 6748c2ecf20Sopenharmony_ci */ 6758c2ecf20Sopenharmony_cistatic int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) 6768c2ecf20Sopenharmony_ci{ 6778c2ecf20Sopenharmony_ci u32 icm_rx, icr_rx, imv_rx; 6788c2ecf20Sopenharmony_ci u32 icm_tx, icr_tx, imv_tx; 6798c2ecf20Sopenharmony_ci u32 icm_misc, icr_misc, imv_misc; 6808c2ecf20Sopenharmony_ci 6818c2ecf20Sopenharmony_ci if (!test_bit(wil_status_irqen, wil->status)) { 6828c2ecf20Sopenharmony_ci if (wil->use_enhanced_dma_hw) { 6838c2ecf20Sopenharmony_ci icm_rx = wil_ioread32_and_clear(wil->csr + 6848c2ecf20Sopenharmony_ci HOSTADDR(RGF_INT_GEN_RX_ICR) + 6858c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICM)); 6868c2ecf20Sopenharmony_ci icr_rx = wil_ioread32_and_clear(wil->csr + 6878c2ecf20Sopenharmony_ci HOSTADDR(RGF_INT_GEN_RX_ICR) + 6888c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 6898c2ecf20Sopenharmony_ci imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR + 6908c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, IMV)); 6918c2ecf20Sopenharmony_ci icm_tx = wil_ioread32_and_clear(wil->csr + 6928c2ecf20Sopenharmony_ci HOSTADDR(RGF_INT_GEN_TX_ICR) + 6938c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICM)); 6948c2ecf20Sopenharmony_ci icr_tx = wil_ioread32_and_clear(wil->csr + 6958c2ecf20Sopenharmony_ci HOSTADDR(RGF_INT_GEN_TX_ICR) + 6968c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 6978c2ecf20Sopenharmony_ci imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR + 6988c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, IMV)); 6998c2ecf20Sopenharmony_ci } else { 7008c2ecf20Sopenharmony_ci icm_rx = wil_ioread32_and_clear(wil->csr + 7018c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_RX_ICR) + 7028c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICM)); 7038c2ecf20Sopenharmony_ci icr_rx = wil_ioread32_and_clear(wil->csr + 7048c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_RX_ICR) + 7058c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 7068c2ecf20Sopenharmony_ci imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR + 7078c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, IMV)); 7088c2ecf20Sopenharmony_ci icm_tx = wil_ioread32_and_clear(wil->csr + 7098c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_TX_ICR) + 7108c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICM)); 7118c2ecf20Sopenharmony_ci icr_tx = wil_ioread32_and_clear(wil->csr + 7128c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_TX_ICR) + 7138c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 7148c2ecf20Sopenharmony_ci imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR + 7158c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, IMV)); 7168c2ecf20Sopenharmony_ci } 7178c2ecf20Sopenharmony_ci icm_misc = wil_ioread32_and_clear(wil->csr + 7188c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_MISC_ICR) + 7198c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICM)); 7208c2ecf20Sopenharmony_ci icr_misc = wil_ioread32_and_clear(wil->csr + 7218c2ecf20Sopenharmony_ci HOSTADDR(RGF_DMA_EP_MISC_ICR) + 7228c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 7238c2ecf20Sopenharmony_ci imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR + 7248c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, IMV)); 7258c2ecf20Sopenharmony_ci 7268c2ecf20Sopenharmony_ci /* HALP interrupt can be unmasked when misc interrupts are 7278c2ecf20Sopenharmony_ci * masked 7288c2ecf20Sopenharmony_ci */ 7298c2ecf20Sopenharmony_ci if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP) 7308c2ecf20Sopenharmony_ci return 0; 7318c2ecf20Sopenharmony_ci 7328c2ecf20Sopenharmony_ci wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" 7338c2ecf20Sopenharmony_ci "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" 7348c2ecf20Sopenharmony_ci "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" 7358c2ecf20Sopenharmony_ci "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n", 7368c2ecf20Sopenharmony_ci pseudo_cause, 7378c2ecf20Sopenharmony_ci icm_rx, icr_rx, imv_rx, 7388c2ecf20Sopenharmony_ci icm_tx, icr_tx, imv_tx, 7398c2ecf20Sopenharmony_ci icm_misc, icr_misc, imv_misc); 7408c2ecf20Sopenharmony_ci 7418c2ecf20Sopenharmony_ci return -EINVAL; 7428c2ecf20Sopenharmony_ci } 7438c2ecf20Sopenharmony_ci 7448c2ecf20Sopenharmony_ci return 0; 7458c2ecf20Sopenharmony_ci} 7468c2ecf20Sopenharmony_ci 7478c2ecf20Sopenharmony_cistatic irqreturn_t wil6210_hardirq(int irq, void *cookie) 7488c2ecf20Sopenharmony_ci{ 7498c2ecf20Sopenharmony_ci irqreturn_t rc = IRQ_HANDLED; 7508c2ecf20Sopenharmony_ci struct wil6210_priv *wil = cookie; 7518c2ecf20Sopenharmony_ci u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE); 7528c2ecf20Sopenharmony_ci 7538c2ecf20Sopenharmony_ci /** 7548c2ecf20Sopenharmony_ci * pseudo_cause is Clear-On-Read, no need to ACK 7558c2ecf20Sopenharmony_ci */ 7568c2ecf20Sopenharmony_ci if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))) 7578c2ecf20Sopenharmony_ci return IRQ_NONE; 7588c2ecf20Sopenharmony_ci 7598c2ecf20Sopenharmony_ci /* IRQ mask debug */ 7608c2ecf20Sopenharmony_ci if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause))) 7618c2ecf20Sopenharmony_ci return IRQ_NONE; 7628c2ecf20Sopenharmony_ci 7638c2ecf20Sopenharmony_ci trace_wil6210_irq_pseudo(pseudo_cause); 7648c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); 7658c2ecf20Sopenharmony_ci 7668c2ecf20Sopenharmony_ci wil6210_mask_irq_pseudo(wil); 7678c2ecf20Sopenharmony_ci 7688c2ecf20Sopenharmony_ci /* Discover real IRQ cause 7698c2ecf20Sopenharmony_ci * There are 2 possible phases for every IRQ: 7708c2ecf20Sopenharmony_ci * - hard IRQ handler called right here 7718c2ecf20Sopenharmony_ci * - threaded handler called later 7728c2ecf20Sopenharmony_ci * 7738c2ecf20Sopenharmony_ci * Hard IRQ handler reads and clears ISR. 7748c2ecf20Sopenharmony_ci * 7758c2ecf20Sopenharmony_ci * If threaded handler requested, hard IRQ handler 7768c2ecf20Sopenharmony_ci * returns IRQ_WAKE_THREAD and saves ISR register value 7778c2ecf20Sopenharmony_ci * for the threaded handler use. 7788c2ecf20Sopenharmony_ci * 7798c2ecf20Sopenharmony_ci * voting for wake thread - need at least 1 vote 7808c2ecf20Sopenharmony_ci */ 7818c2ecf20Sopenharmony_ci if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) && 7828c2ecf20Sopenharmony_ci (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) 7838c2ecf20Sopenharmony_ci rc = IRQ_WAKE_THREAD; 7848c2ecf20Sopenharmony_ci 7858c2ecf20Sopenharmony_ci if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) && 7868c2ecf20Sopenharmony_ci (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) 7878c2ecf20Sopenharmony_ci rc = IRQ_WAKE_THREAD; 7888c2ecf20Sopenharmony_ci 7898c2ecf20Sopenharmony_ci if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) && 7908c2ecf20Sopenharmony_ci (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD)) 7918c2ecf20Sopenharmony_ci rc = IRQ_WAKE_THREAD; 7928c2ecf20Sopenharmony_ci 7938c2ecf20Sopenharmony_ci /* if thread is requested, it will unmask IRQ */ 7948c2ecf20Sopenharmony_ci if (rc != IRQ_WAKE_THREAD) 7958c2ecf20Sopenharmony_ci wil6210_unmask_irq_pseudo(wil); 7968c2ecf20Sopenharmony_ci 7978c2ecf20Sopenharmony_ci return rc; 7988c2ecf20Sopenharmony_ci} 7998c2ecf20Sopenharmony_ci 8008c2ecf20Sopenharmony_cistatic int wil6210_request_3msi(struct wil6210_priv *wil, int irq) 8018c2ecf20Sopenharmony_ci{ 8028c2ecf20Sopenharmony_ci int rc; 8038c2ecf20Sopenharmony_ci 8048c2ecf20Sopenharmony_ci /* IRQ's are in the following order: 8058c2ecf20Sopenharmony_ci * - Tx 8068c2ecf20Sopenharmony_ci * - Rx 8078c2ecf20Sopenharmony_ci * - Misc 8088c2ecf20Sopenharmony_ci */ 8098c2ecf20Sopenharmony_ci rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED, 8108c2ecf20Sopenharmony_ci WIL_NAME "_tx", wil); 8118c2ecf20Sopenharmony_ci if (rc) 8128c2ecf20Sopenharmony_ci return rc; 8138c2ecf20Sopenharmony_ci 8148c2ecf20Sopenharmony_ci rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED, 8158c2ecf20Sopenharmony_ci WIL_NAME "_rx", wil); 8168c2ecf20Sopenharmony_ci if (rc) 8178c2ecf20Sopenharmony_ci goto free0; 8188c2ecf20Sopenharmony_ci 8198c2ecf20Sopenharmony_ci rc = request_threaded_irq(irq + 2, wil6210_irq_misc, 8208c2ecf20Sopenharmony_ci wil6210_irq_misc_thread, 8218c2ecf20Sopenharmony_ci IRQF_SHARED, WIL_NAME "_misc", wil); 8228c2ecf20Sopenharmony_ci if (rc) 8238c2ecf20Sopenharmony_ci goto free1; 8248c2ecf20Sopenharmony_ci 8258c2ecf20Sopenharmony_ci return 0; 8268c2ecf20Sopenharmony_cifree1: 8278c2ecf20Sopenharmony_ci free_irq(irq + 1, wil); 8288c2ecf20Sopenharmony_cifree0: 8298c2ecf20Sopenharmony_ci free_irq(irq, wil); 8308c2ecf20Sopenharmony_ci 8318c2ecf20Sopenharmony_ci return rc; 8328c2ecf20Sopenharmony_ci} 8338c2ecf20Sopenharmony_ci 8348c2ecf20Sopenharmony_ci/* can't use wil_ioread32_and_clear because ICC value is not set yet */ 8358c2ecf20Sopenharmony_cistatic inline void wil_clear32(void __iomem *addr) 8368c2ecf20Sopenharmony_ci{ 8378c2ecf20Sopenharmony_ci u32 x = readl(addr); 8388c2ecf20Sopenharmony_ci 8398c2ecf20Sopenharmony_ci writel(x, addr); 8408c2ecf20Sopenharmony_ci} 8418c2ecf20Sopenharmony_ci 8428c2ecf20Sopenharmony_civoid wil6210_clear_irq(struct wil6210_priv *wil) 8438c2ecf20Sopenharmony_ci{ 8448c2ecf20Sopenharmony_ci wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + 8458c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 8468c2ecf20Sopenharmony_ci wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + 8478c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 8488c2ecf20Sopenharmony_ci wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) + 8498c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 8508c2ecf20Sopenharmony_ci wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) + 8518c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 8528c2ecf20Sopenharmony_ci wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + 8538c2ecf20Sopenharmony_ci offsetof(struct RGF_ICR, ICR)); 8548c2ecf20Sopenharmony_ci wmb(); /* make sure write completed */ 8558c2ecf20Sopenharmony_ci} 8568c2ecf20Sopenharmony_ci 8578c2ecf20Sopenharmony_civoid wil6210_set_halp(struct wil6210_priv *wil) 8588c2ecf20Sopenharmony_ci{ 8598c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "set_halp\n"); 8608c2ecf20Sopenharmony_ci 8618c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS), 8628c2ecf20Sopenharmony_ci BIT_DMA_EP_MISC_ICR_HALP); 8638c2ecf20Sopenharmony_ci} 8648c2ecf20Sopenharmony_ci 8658c2ecf20Sopenharmony_civoid wil6210_clear_halp(struct wil6210_priv *wil) 8668c2ecf20Sopenharmony_ci{ 8678c2ecf20Sopenharmony_ci wil_dbg_irq(wil, "clear_halp\n"); 8688c2ecf20Sopenharmony_ci 8698c2ecf20Sopenharmony_ci wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR), 8708c2ecf20Sopenharmony_ci BIT_DMA_EP_MISC_ICR_HALP); 8718c2ecf20Sopenharmony_ci wil6210_unmask_halp(wil); 8728c2ecf20Sopenharmony_ci} 8738c2ecf20Sopenharmony_ci 8748c2ecf20Sopenharmony_ciint wil6210_init_irq(struct wil6210_priv *wil, int irq) 8758c2ecf20Sopenharmony_ci{ 8768c2ecf20Sopenharmony_ci int rc; 8778c2ecf20Sopenharmony_ci 8788c2ecf20Sopenharmony_ci wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n", 8798c2ecf20Sopenharmony_ci wil->n_msi ? "MSI" : "INTx", wil->n_msi); 8808c2ecf20Sopenharmony_ci 8818c2ecf20Sopenharmony_ci if (wil->use_enhanced_dma_hw) { 8828c2ecf20Sopenharmony_ci wil->txrx_ops.irq_tx = wil6210_irq_tx_edma; 8838c2ecf20Sopenharmony_ci wil->txrx_ops.irq_rx = wil6210_irq_rx_edma; 8848c2ecf20Sopenharmony_ci } else { 8858c2ecf20Sopenharmony_ci wil->txrx_ops.irq_tx = wil6210_irq_tx; 8868c2ecf20Sopenharmony_ci wil->txrx_ops.irq_rx = wil6210_irq_rx; 8878c2ecf20Sopenharmony_ci } 8888c2ecf20Sopenharmony_ci 8898c2ecf20Sopenharmony_ci if (wil->n_msi == 3) 8908c2ecf20Sopenharmony_ci rc = wil6210_request_3msi(wil, irq); 8918c2ecf20Sopenharmony_ci else 8928c2ecf20Sopenharmony_ci rc = request_threaded_irq(irq, wil6210_hardirq, 8938c2ecf20Sopenharmony_ci wil6210_thread_irq, 8948c2ecf20Sopenharmony_ci wil->n_msi ? 0 : IRQF_SHARED, 8958c2ecf20Sopenharmony_ci WIL_NAME, wil); 8968c2ecf20Sopenharmony_ci return rc; 8978c2ecf20Sopenharmony_ci} 8988c2ecf20Sopenharmony_ci 8998c2ecf20Sopenharmony_civoid wil6210_fini_irq(struct wil6210_priv *wil, int irq) 9008c2ecf20Sopenharmony_ci{ 9018c2ecf20Sopenharmony_ci wil_dbg_misc(wil, "fini_irq:\n"); 9028c2ecf20Sopenharmony_ci 9038c2ecf20Sopenharmony_ci wil_mask_irq(wil); 9048c2ecf20Sopenharmony_ci free_irq(irq, wil); 9058c2ecf20Sopenharmony_ci if (wil->n_msi == 3) { 9068c2ecf20Sopenharmony_ci free_irq(irq + 1, wil); 9078c2ecf20Sopenharmony_ci free_irq(irq + 2, wil); 9088c2ecf20Sopenharmony_ci } 9098c2ecf20Sopenharmony_ci} 910