1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef DEBUG_H 18#define DEBUG_H 19 20#include "hw.h" 21#include "dfs_debug.h" 22 23struct ath_txq; 24struct ath_buf; 25struct fft_sample_tlv; 26 27#ifdef CONFIG_ATH9K_DEBUGFS 28#define TX_STAT_INC(sc, q, c) do { (sc)->debug.stats.txstats[q].c++; } while (0) 29#define RX_STAT_INC(sc, c) do { (sc)->debug.stats.rxstats.c++; } while (0) 30#define RESET_STAT_INC(sc, type) do { (sc)->debug.stats.reset[type]++; } while (0) 31#define ANT_STAT_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].c++; } while (0) 32#define ANT_LNA_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].lna_recv_cnt[c]++; } while (0) 33#else 34#define TX_STAT_INC(sc, q, c) do { (void)(sc); } while (0) 35#define RX_STAT_INC(sc, c) do { (void)(sc); } while (0) 36#define RESET_STAT_INC(sc, type) do { (void)(sc); } while (0) 37#define ANT_STAT_INC(sc, i, c) do { (void)(sc); } while (0) 38#define ANT_LNA_INC(sc, i, c) do { (void)(sc); } while (0) 39#endif 40 41enum ath_reset_type { 42 RESET_TYPE_BB_HANG, 43 RESET_TYPE_BB_WATCHDOG, 44 RESET_TYPE_FATAL_INT, 45 RESET_TYPE_TX_ERROR, 46 RESET_TYPE_TX_GTT, 47 RESET_TYPE_TX_HANG, 48 RESET_TYPE_PLL_HANG, 49 RESET_TYPE_MAC_HANG, 50 RESET_TYPE_BEACON_STUCK, 51 RESET_TYPE_MCI, 52 RESET_TYPE_CALIBRATION, 53 RESET_TX_DMA_ERROR, 54 RESET_RX_DMA_ERROR, 55 __RESET_TYPE_MAX 56}; 57 58#ifdef CONFIG_ATH9K_DEBUGFS 59 60/** 61 * struct ath_interrupt_stats - Contains statistics about interrupts 62 * @total: Total no. of interrupts generated so far 63 * @rxok: RX with no errors 64 * @rxlp: RX with low priority RX 65 * @rxhp: RX with high priority, uapsd only 66 * @rxeol: RX with no more RXDESC available 67 * @rxorn: RX FIFO overrun 68 * @txok: TX completed at the requested rate 69 * @txurn: TX FIFO underrun 70 * @mib: MIB regs reaching its threshold 71 * @rxphyerr: RX with phy errors 72 * @rx_keycache_miss: RX with key cache misses 73 * @swba: Software Beacon Alert 74 * @bmiss: Beacon Miss 75 * @bnr: Beacon Not Ready 76 * @cst: Carrier Sense TImeout 77 * @gtt: Global TX Timeout 78 * @tim: RX beacon TIM occurrence 79 * @cabend: RX End of CAB traffic 80 * @dtimsync: DTIM sync lossage 81 * @dtim: RX Beacon with DTIM 82 * @bb_watchdog: Baseband watchdog 83 * @tsfoor: TSF out of range, indicates that the corrected TSF received 84 * from a beacon differs from the PCU's internal TSF by more than a 85 * (programmable) threshold 86 * @local_timeout: Internal bus timeout. 87 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets 88 * @gen_timer: Generic hardware timer interrupt 89 */ 90struct ath_interrupt_stats { 91 u32 total; 92 u32 rxok; 93 u32 rxlp; 94 u32 rxhp; 95 u32 rxeol; 96 u32 rxorn; 97 u32 txok; 98 u32 txeol; 99 u32 txurn; 100 u32 mib; 101 u32 rxphyerr; 102 u32 rx_keycache_miss; 103 u32 swba; 104 u32 bmiss; 105 u32 bnr; 106 u32 cst; 107 u32 gtt; 108 u32 tim; 109 u32 cabend; 110 u32 dtimsync; 111 u32 dtim; 112 u32 bb_watchdog; 113 u32 tsfoor; 114 u32 mci; 115 u32 gen_timer; 116 117 /* Sync-cause stats */ 118 u32 sync_cause_all; 119 u32 sync_rtc_irq; 120 u32 sync_mac_irq; 121 u32 eeprom_illegal_access; 122 u32 apb_timeout; 123 u32 pci_mode_conflict; 124 u32 host1_fatal; 125 u32 host1_perr; 126 u32 trcv_fifo_perr; 127 u32 radm_cpl_ep; 128 u32 radm_cpl_dllp_abort; 129 u32 radm_cpl_tlp_abort; 130 u32 radm_cpl_ecrc_err; 131 u32 radm_cpl_timeout; 132 u32 local_timeout; 133 u32 pm_access; 134 u32 mac_awake; 135 u32 mac_asleep; 136 u32 mac_sleep_access; 137}; 138 139 140/** 141 * struct ath_tx_stats - Statistics about TX 142 * @tx_pkts_all: No. of total frames transmitted, including ones that 143 may have had errors. 144 * @tx_bytes_all: No. of total bytes transmitted, including ones that 145 may have had errors. 146 * @queued: Total MPDUs (non-aggr) queued 147 * @completed: Total MPDUs (non-aggr) completed 148 * @a_aggr: Total no. of aggregates queued 149 * @a_queued_hw: Total AMPDUs queued to hardware 150 * @a_completed: Total AMPDUs completed 151 * @a_retries: No. of AMPDUs retried (SW) 152 * @a_xretries: No. of AMPDUs dropped due to xretries 153 * @txerr_filtered: No. of frames with TXERR_FILT flag set. 154 * @fifo_underrun: FIFO underrun occurrences 155 Valid only for: 156 - non-aggregate condition. 157 - first packet of aggregate. 158 * @xtxop: No. of frames filtered because of TXOP limit 159 * @timer_exp: Transmit timer expiry 160 * @desc_cfg_err: Descriptor configuration errors 161 * @data_urn: TX data underrun errors 162 * @delim_urn: TX delimiter underrun errors 163 * @puttxbuf: Number of times hardware was given txbuf to write. 164 * @txstart: Number of times hardware was told to start tx. 165 * @txprocdesc: Number of times tx descriptor was processed 166 * @txfailed: Out-of-memory or other errors in xmit path. 167 */ 168struct ath_tx_stats { 169 u32 tx_pkts_all; 170 u32 tx_bytes_all; 171 u32 queued; 172 u32 completed; 173 u32 xretries; 174 u32 a_aggr; 175 u32 a_queued_hw; 176 u32 a_completed; 177 u32 a_retries; 178 u32 a_xretries; 179 u32 txerr_filtered; 180 u32 fifo_underrun; 181 u32 xtxop; 182 u32 timer_exp; 183 u32 desc_cfg_err; 184 u32 data_underrun; 185 u32 delim_underrun; 186 u32 puttxbuf; 187 u32 txstart; 188 u32 txprocdesc; 189 u32 txfailed; 190}; 191 192/* 193 * Various utility macros to print TX/Queue counters. 194 */ 195#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum 196#define TXSTATS sc->debug.stats.txstats 197#define PR(str, elem) \ 198 do { \ 199 seq_printf(file, "%s%13u%11u%10u%10u\n", str, \ 200 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\ 201 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\ 202 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\ 203 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \ 204 } while(0) 205 206struct ath_rx_rate_stats { 207 struct { 208 u32 ht20_cnt; 209 u32 ht40_cnt; 210 u32 sgi_cnt; 211 u32 lgi_cnt; 212 } ht_stats[24]; 213 214 struct { 215 u32 ofdm_cnt; 216 } ofdm_stats[8]; 217 218 struct { 219 u32 cck_lp_cnt; 220 u32 cck_sp_cnt; 221 } cck_stats[4]; 222}; 223 224struct ath_airtime_stats { 225 u32 rx_airtime; 226 u32 tx_airtime; 227}; 228 229#define ANT_MAIN 0 230#define ANT_ALT 1 231 232struct ath_antenna_stats { 233 u32 recv_cnt; 234 u32 rssi_avg; 235 u32 lna_recv_cnt[4]; 236 u32 lna_attempt_cnt[4]; 237}; 238 239struct ath_stats { 240 struct ath_interrupt_stats istats; 241 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 242 struct ath_rx_stats rxstats; 243 struct ath_dfs_stats dfs_stats; 244 struct ath_antenna_stats ant_stats[2]; 245 u32 reset[__RESET_TYPE_MAX]; 246}; 247 248struct ath9k_debug { 249 struct dentry *debugfs_phy; 250 u32 regidx; 251 struct ath_stats stats; 252}; 253 254int ath9k_init_debug(struct ath_hw *ah); 255void ath9k_deinit_debug(struct ath_softc *sc); 256 257void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 258void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, 259 struct ath_tx_status *ts, struct ath_txq *txq, 260 unsigned int flags); 261void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 262int ath9k_get_et_sset_count(struct ieee80211_hw *hw, 263 struct ieee80211_vif *vif, int sset); 264void ath9k_get_et_stats(struct ieee80211_hw *hw, 265 struct ieee80211_vif *vif, 266 struct ethtool_stats *stats, u64 *data); 267void ath9k_get_et_strings(struct ieee80211_hw *hw, 268 struct ieee80211_vif *vif, 269 u32 sset, u8 *data); 270void ath9k_sta_add_debugfs(struct ieee80211_hw *hw, 271 struct ieee80211_vif *vif, 272 struct ieee80211_sta *sta, 273 struct dentry *dir); 274void ath9k_debug_stat_ant(struct ath_softc *sc, 275 struct ath_hw_antcomb_conf *div_ant_conf, 276 int main_rssi_avg, int alt_rssi_avg); 277void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause); 278 279#else 280 281static inline int ath9k_init_debug(struct ath_hw *ah) 282{ 283 return 0; 284} 285 286static inline void ath9k_deinit_debug(struct ath_softc *sc) 287{ 288} 289static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 290 enum ath9k_int status) 291{ 292} 293static inline void ath_debug_stat_tx(struct ath_softc *sc, 294 struct ath_buf *bf, 295 struct ath_tx_status *ts, 296 struct ath_txq *txq, 297 unsigned int flags) 298{ 299} 300static inline void ath_debug_stat_rx(struct ath_softc *sc, 301 struct ath_rx_status *rs) 302{ 303} 304static inline void ath9k_debug_stat_ant(struct ath_softc *sc, 305 struct ath_hw_antcomb_conf *div_ant_conf, 306 int main_rssi_avg, int alt_rssi_avg) 307{ 308 309} 310 311static inline void 312ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause) 313{ 314} 315 316#endif /* CONFIG_ATH9K_DEBUGFS */ 317 318#ifdef CONFIG_ATH9K_STATION_STATISTICS 319void ath_debug_rate_stats(struct ath_softc *sc, 320 struct ath_rx_status *rs, 321 struct sk_buff *skb); 322#else 323static inline void ath_debug_rate_stats(struct ath_softc *sc, 324 struct ath_rx_status *rs, 325 struct sk_buff *skb) 326{ 327} 328#endif /* CONFIG_ATH9K_STATION_STATISTICS */ 329 330#endif /* DEBUG_H */ 331