1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "hw.h" 18#include "hw-ops.h" 19#include "../regd.h" 20#include "ar9002_phy.h" 21 22/* All code below is for AR5008, AR9001, AR9002 */ 23 24#define AR5008_OFDM_RATES 8 25#define AR5008_HT_SS_RATES 8 26#define AR5008_HT_DS_RATES 8 27 28#define AR5008_HT20_SHIFT 16 29#define AR5008_HT40_SHIFT 24 30 31#define AR5008_11NA_OFDM_SHIFT 0 32#define AR5008_11NA_HT_SS_SHIFT 8 33#define AR5008_11NA_HT_DS_SHIFT 16 34 35#define AR5008_11NG_OFDM_SHIFT 4 36#define AR5008_11NG_HT_SS_SHIFT 12 37#define AR5008_11NG_HT_DS_SHIFT 20 38 39/* 40 * register values to turn OFDM weak signal detection OFF 41 */ 42static const int m1ThreshLow_off = 127; 43static const int m2ThreshLow_off = 127; 44static const int m1Thresh_off = 127; 45static const int m2Thresh_off = 127; 46static const int m2CountThr_off = 31; 47static const int m2CountThrLow_off = 63; 48static const int m1ThreshLowExt_off = 127; 49static const int m2ThreshLowExt_off = 127; 50static const int m1ThreshExt_off = 127; 51static const int m2ThreshExt_off = 127; 52 53static const u32 ar5416Bank0[][2] = { 54 /* Addr allmodes */ 55 {0x000098b0, 0x1e5795e5}, 56 {0x000098e0, 0x02008020}, 57}; 58 59static const u32 ar5416Bank1[][2] = { 60 /* Addr allmodes */ 61 {0x000098b0, 0x02108421}, 62 {0x000098ec, 0x00000008}, 63}; 64 65static const u32 ar5416Bank2[][2] = { 66 /* Addr allmodes */ 67 {0x000098b0, 0x0e73ff17}, 68 {0x000098e0, 0x00000420}, 69}; 70 71static const u32 ar5416Bank3[][3] = { 72 /* Addr 5G 2G */ 73 {0x000098f0, 0x01400018, 0x01c00018}, 74}; 75 76static const u32 ar5416Bank7[][2] = { 77 /* Addr allmodes */ 78 {0x0000989c, 0x00000500}, 79 {0x0000989c, 0x00000800}, 80 {0x000098cc, 0x0000000e}, 81}; 82 83static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); 84static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); 85static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); 86static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); 87static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); 88 89static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) 90{ 91 struct ar5416IniArray *array = &ah->iniBank6; 92 u32 *data = ah->analogBank6Data; 93 int r; 94 95 ENABLE_REGWRITE_BUFFER(ah); 96 97 for (r = 0; r < array->ia_rows; r++) { 98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 99 DO_DELAY(*writecnt); 100 } 101 102 REGWRITE_BUFFER_FLUSH(ah); 103} 104 105/** 106 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 107 * @rfbuf: 108 * @reg32: 109 * @numBits: 110 * @firstBit: 111 * @column: 112 * 113 * Performs analog "swizzling" of parameters into their location. 114 * Used on external AR2133/AR5133 radios. 115 */ 116static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 117 u32 numBits, u32 firstBit, 118 u32 column) 119{ 120 u32 tmp32, mask, arrayEntry, lastBit; 121 int32_t bitPosition, bitsLeft; 122 123 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 124 arrayEntry = (firstBit - 1) / 8; 125 bitPosition = (firstBit - 1) % 8; 126 bitsLeft = numBits; 127 while (bitsLeft > 0) { 128 lastBit = (bitPosition + bitsLeft > 8) ? 129 8 : bitPosition + bitsLeft; 130 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 131 (column * 8); 132 rfBuf[arrayEntry] &= ~mask; 133 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 134 (column * 8)) & mask; 135 bitsLeft -= 8 - bitPosition; 136 tmp32 = tmp32 >> (8 - bitPosition); 137 bitPosition = 0; 138 arrayEntry++; 139 } 140} 141 142/* 143 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 144 * rf_pwd_icsyndiv. 145 * 146 * Theoretical Rules: 147 * if 2 GHz band 148 * if forceBiasAuto 149 * if synth_freq < 2412 150 * bias = 0 151 * else if 2412 <= synth_freq <= 2422 152 * bias = 1 153 * else // synth_freq > 2422 154 * bias = 2 155 * else if forceBias > 0 156 * bias = forceBias & 7 157 * else 158 * no change, use value from ini file 159 * else 160 * no change, invalid band 161 * 162 * 1st Mod: 163 * 2422 also uses value of 2 164 * <approved> 165 * 166 * 2nd Mod: 167 * Less than 2412 uses value of 0, 2412 and above uses value of 2 168 */ 169static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 170{ 171 struct ath_common *common = ath9k_hw_common(ah); 172 u32 tmp_reg; 173 int reg_writes = 0; 174 u32 new_bias = 0; 175 176 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 177 return; 178 179 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 180 181 if (synth_freq < 2412) 182 new_bias = 0; 183 else if (synth_freq < 2422) 184 new_bias = 1; 185 else 186 new_bias = 2; 187 188 /* pre-reverse this field */ 189 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 190 191 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 192 new_bias, synth_freq); 193 194 /* swizzle rf_pwd_icsyndiv */ 195 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 196 197 /* write Bank 6 with new params */ 198 ar5008_write_bank6(ah, ®_writes); 199} 200 201/** 202 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 203 * @ah: atheros hardware structure 204 * @chan: 205 * 206 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 207 * the channel value. Assumes writes enabled to analog bus and bank6 register 208 * cache in ah->analogBank6Data. 209 */ 210static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 211{ 212 struct ath_common *common = ath9k_hw_common(ah); 213 u32 channelSel = 0; 214 u32 bModeSynth = 0; 215 u32 aModeRefSel = 0; 216 u32 reg32 = 0; 217 u16 freq; 218 struct chan_centers centers; 219 220 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 221 freq = centers.synth_center; 222 223 if (freq < 4800) { 224 u32 txctl; 225 226 if (((freq - 2192) % 5) == 0) { 227 channelSel = ((freq - 672) * 2 - 3040) / 10; 228 bModeSynth = 0; 229 } else if (((freq - 2224) % 5) == 0) { 230 channelSel = ((freq - 704) * 2 - 3040) / 10; 231 bModeSynth = 1; 232 } else { 233 ath_err(common, "Invalid channel %u MHz\n", freq); 234 return -EINVAL; 235 } 236 237 channelSel = (channelSel << 2) & 0xff; 238 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 239 240 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 241 if (freq == 2484) { 242 243 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 244 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 245 } else { 246 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 247 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 248 } 249 250 } else if ((freq % 20) == 0 && freq >= 5120) { 251 channelSel = 252 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 253 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 254 } else if ((freq % 10) == 0) { 255 channelSel = 256 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 257 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 258 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 259 else 260 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 261 } else if ((freq % 5) == 0) { 262 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 263 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 264 } else { 265 ath_err(common, "Invalid channel %u MHz\n", freq); 266 return -EINVAL; 267 } 268 269 ar5008_hw_force_bias(ah, freq); 270 271 reg32 = 272 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 273 (1 << 5) | 0x1; 274 275 REG_WRITE(ah, AR_PHY(0x37), reg32); 276 277 ah->curchan = chan; 278 279 return 0; 280} 281 282void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, 283 struct ath9k_channel *chan, int bin) 284{ 285 int cur_bin; 286 int upper, lower, cur_vit_mask; 287 int i; 288 int8_t mask_m[123] = {0}; 289 int8_t mask_p[123] = {0}; 290 int8_t mask_amt; 291 int tmp_mask; 292 static const int pilot_mask_reg[4] = { 293 AR_PHY_TIMING7, AR_PHY_TIMING8, 294 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 295 }; 296 static const int chan_mask_reg[4] = { 297 AR_PHY_TIMING9, AR_PHY_TIMING10, 298 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 299 }; 300 static const int inc[4] = { 0, 100, 0, 0 }; 301 302 cur_bin = -6000; 303 upper = bin + 100; 304 lower = bin - 100; 305 306 for (i = 0; i < 4; i++) { 307 int pilot_mask = 0; 308 int chan_mask = 0; 309 int bp = 0; 310 311 for (bp = 0; bp < 30; bp++) { 312 if ((cur_bin > lower) && (cur_bin < upper)) { 313 pilot_mask = pilot_mask | 0x1 << bp; 314 chan_mask = chan_mask | 0x1 << bp; 315 } 316 cur_bin += 100; 317 } 318 cur_bin += inc[i]; 319 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 320 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 321 } 322 323 cur_vit_mask = 6100; 324 upper = bin + 120; 325 lower = bin - 120; 326 327 for (i = 0; i < ARRAY_SIZE(mask_m); i++) { 328 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 329 /* workaround for gcc bug #37014 */ 330 volatile int tmp_v = abs(cur_vit_mask - bin); 331 332 if (tmp_v < 75) 333 mask_amt = 1; 334 else 335 mask_amt = 0; 336 if (cur_vit_mask < 0) 337 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 338 else 339 mask_p[cur_vit_mask / 100] = mask_amt; 340 } 341 cur_vit_mask -= 100; 342 } 343 344 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 345 | (mask_m[48] << 26) | (mask_m[49] << 24) 346 | (mask_m[50] << 22) | (mask_m[51] << 20) 347 | (mask_m[52] << 18) | (mask_m[53] << 16) 348 | (mask_m[54] << 14) | (mask_m[55] << 12) 349 | (mask_m[56] << 10) | (mask_m[57] << 8) 350 | (mask_m[58] << 6) | (mask_m[59] << 4) 351 | (mask_m[60] << 2) | (mask_m[61] << 0); 352 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 353 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 354 355 tmp_mask = (mask_m[31] << 28) 356 | (mask_m[32] << 26) | (mask_m[33] << 24) 357 | (mask_m[34] << 22) | (mask_m[35] << 20) 358 | (mask_m[36] << 18) | (mask_m[37] << 16) 359 | (mask_m[48] << 14) | (mask_m[39] << 12) 360 | (mask_m[40] << 10) | (mask_m[41] << 8) 361 | (mask_m[42] << 6) | (mask_m[43] << 4) 362 | (mask_m[44] << 2) | (mask_m[45] << 0); 363 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 364 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 365 366 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 367 | (mask_m[18] << 26) | (mask_m[18] << 24) 368 | (mask_m[20] << 22) | (mask_m[20] << 20) 369 | (mask_m[22] << 18) | (mask_m[22] << 16) 370 | (mask_m[24] << 14) | (mask_m[24] << 12) 371 | (mask_m[25] << 10) | (mask_m[26] << 8) 372 | (mask_m[27] << 6) | (mask_m[28] << 4) 373 | (mask_m[29] << 2) | (mask_m[30] << 0); 374 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 375 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 376 377 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 378 | (mask_m[2] << 26) | (mask_m[3] << 24) 379 | (mask_m[4] << 22) | (mask_m[5] << 20) 380 | (mask_m[6] << 18) | (mask_m[7] << 16) 381 | (mask_m[8] << 14) | (mask_m[9] << 12) 382 | (mask_m[10] << 10) | (mask_m[11] << 8) 383 | (mask_m[12] << 6) | (mask_m[13] << 4) 384 | (mask_m[14] << 2) | (mask_m[15] << 0); 385 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 386 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 387 388 tmp_mask = (mask_p[15] << 28) 389 | (mask_p[14] << 26) | (mask_p[13] << 24) 390 | (mask_p[12] << 22) | (mask_p[11] << 20) 391 | (mask_p[10] << 18) | (mask_p[9] << 16) 392 | (mask_p[8] << 14) | (mask_p[7] << 12) 393 | (mask_p[6] << 10) | (mask_p[5] << 8) 394 | (mask_p[4] << 6) | (mask_p[3] << 4) 395 | (mask_p[2] << 2) | (mask_p[1] << 0); 396 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 397 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 398 399 tmp_mask = (mask_p[30] << 28) 400 | (mask_p[29] << 26) | (mask_p[28] << 24) 401 | (mask_p[27] << 22) | (mask_p[26] << 20) 402 | (mask_p[25] << 18) | (mask_p[24] << 16) 403 | (mask_p[23] << 14) | (mask_p[22] << 12) 404 | (mask_p[21] << 10) | (mask_p[20] << 8) 405 | (mask_p[19] << 6) | (mask_p[18] << 4) 406 | (mask_p[17] << 2) | (mask_p[16] << 0); 407 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 408 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 409 410 tmp_mask = (mask_p[45] << 28) 411 | (mask_p[44] << 26) | (mask_p[43] << 24) 412 | (mask_p[42] << 22) | (mask_p[41] << 20) 413 | (mask_p[40] << 18) | (mask_p[39] << 16) 414 | (mask_p[38] << 14) | (mask_p[37] << 12) 415 | (mask_p[36] << 10) | (mask_p[35] << 8) 416 | (mask_p[34] << 6) | (mask_p[33] << 4) 417 | (mask_p[32] << 2) | (mask_p[31] << 0); 418 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 419 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 420 421 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 422 | (mask_p[59] << 26) | (mask_p[58] << 24) 423 | (mask_p[57] << 22) | (mask_p[56] << 20) 424 | (mask_p[55] << 18) | (mask_p[54] << 16) 425 | (mask_p[53] << 14) | (mask_p[52] << 12) 426 | (mask_p[51] << 10) | (mask_p[50] << 8) 427 | (mask_p[49] << 6) | (mask_p[48] << 4) 428 | (mask_p[47] << 2) | (mask_p[46] << 0); 429 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 430 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 431} 432 433/** 434 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 435 * @ah: atheros hardware structure 436 * @chan: 437 * 438 * For non single-chip solutions. Converts to baseband spur frequency given the 439 * input channel frequency and compute register settings below. 440 */ 441static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 442 struct ath9k_channel *chan) 443{ 444 int bb_spur = AR_NO_SPUR; 445 int bin; 446 int spur_freq_sd; 447 int spur_delta_phase; 448 int denominator; 449 int tmp, new; 450 int i; 451 452 int cur_bb_spur; 453 bool is2GHz = IS_CHAN_2GHZ(chan); 454 455 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 456 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 457 if (AR_NO_SPUR == cur_bb_spur) 458 break; 459 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 460 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 461 bb_spur = cur_bb_spur; 462 break; 463 } 464 } 465 466 if (AR_NO_SPUR == bb_spur) 467 return; 468 469 bin = bb_spur * 32; 470 471 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 472 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 473 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 474 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 475 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 476 477 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 478 479 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 480 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 481 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 482 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 483 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 484 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 485 486 spur_delta_phase = ((bb_spur * 524288) / 100) & 487 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 488 489 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 490 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 491 492 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 493 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 494 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 495 REG_WRITE(ah, AR_PHY_TIMING11, new); 496 497 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); 498} 499 500/** 501 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 502 * @ah: atheros hardware structure 503 * 504 * Only required for older devices with external AR2133/AR5133 radios. 505 */ 506static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 507{ 508 int size = ah->iniBank6.ia_rows * sizeof(u32); 509 510 if (AR_SREV_9280_20_OR_LATER(ah)) 511 return 0; 512 513 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); 514 if (!ah->analogBank6Data) 515 return -ENOMEM; 516 517 return 0; 518} 519 520 521/* * 522 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 523 * @ah: atheros hardware structure 524 * @chan: 525 * @modesIndex: 526 * 527 * Used for the external AR2133/AR5133 radios. 528 * 529 * Reads the EEPROM header info from the device structure and programs 530 * all rf registers. This routine requires access to the analog 531 * rf device. This is not required for single-chip devices. 532 */ 533static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 534 struct ath9k_channel *chan, 535 u16 modesIndex) 536{ 537 u32 eepMinorRev; 538 u32 ob5GHz = 0, db5GHz = 0; 539 u32 ob2GHz = 0, db2GHz = 0; 540 int regWrites = 0; 541 int i; 542 543 /* 544 * Software does not need to program bank data 545 * for single chip devices, that is AR9280 or anything 546 * after that. 547 */ 548 if (AR_SREV_9280_20_OR_LATER(ah)) 549 return true; 550 551 /* Setup rf parameters */ 552 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah); 553 554 for (i = 0; i < ah->iniBank6.ia_rows; i++) 555 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); 556 557 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 558 if (eepMinorRev >= 2) { 559 if (IS_CHAN_2GHZ(chan)) { 560 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 561 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 562 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 563 ob2GHz, 3, 197, 0); 564 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 565 db2GHz, 3, 194, 0); 566 } else { 567 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 568 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 569 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 570 ob5GHz, 3, 203, 0); 571 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 572 db5GHz, 3, 200, 0); 573 } 574 } 575 576 /* Write Analog registers */ 577 REG_WRITE_ARRAY(&bank0, 1, regWrites); 578 REG_WRITE_ARRAY(&bank1, 1, regWrites); 579 REG_WRITE_ARRAY(&bank2, 1, regWrites); 580 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); 581 ar5008_write_bank6(ah, ®Writes); 582 REG_WRITE_ARRAY(&bank7, 1, regWrites); 583 584 return true; 585} 586 587static void ar5008_hw_init_bb(struct ath_hw *ah, 588 struct ath9k_channel *chan) 589{ 590 u32 synthDelay; 591 592 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 593 594 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 595 596 ath9k_hw_synth_delay(ah, chan, synthDelay); 597} 598 599static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 600{ 601 int rx_chainmask, tx_chainmask; 602 603 rx_chainmask = ah->rxchainmask; 604 tx_chainmask = ah->txchainmask; 605 606 607 switch (rx_chainmask) { 608 case 0x5: 609 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 610 AR_PHY_SWAP_ALT_CHAIN); 611 fallthrough; 612 case 0x3: 613 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 614 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 615 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 616 break; 617 } 618 fallthrough; 619 case 0x1: 620 case 0x2: 621 case 0x7: 622 ENABLE_REGWRITE_BUFFER(ah); 623 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 624 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 625 break; 626 default: 627 ENABLE_REGWRITE_BUFFER(ah); 628 break; 629 } 630 631 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 632 633 REGWRITE_BUFFER_FLUSH(ah); 634 635 if (tx_chainmask == 0x5) { 636 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 637 AR_PHY_SWAP_ALT_CHAIN); 638 } 639 if (AR_SREV_9100(ah)) 640 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 641 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 642} 643 644static void ar5008_hw_override_ini(struct ath_hw *ah, 645 struct ath9k_channel *chan) 646{ 647 u32 val; 648 649 /* 650 * Set the RX_ABORT and RX_DIS and clear if off only after 651 * RXE is set for MAC. This prevents frames with corrupted 652 * descriptor status. 653 */ 654 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 655 656 if (AR_SREV_9280_20_OR_LATER(ah)) { 657 /* 658 * For AR9280 and above, there is a new feature that allows 659 * Multicast search based on both MAC Address and Key ID. 660 * By default, this feature is enabled. But since the driver 661 * is not using this feature, we switch it off; otherwise 662 * multicast search based on MAC addr only will fail. 663 */ 664 val = REG_READ(ah, AR_PCU_MISC_MODE2) & 665 (~AR_ADHOC_MCAST_KEYID_ENABLE); 666 667 if (!AR_SREV_9271(ah)) 668 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 669 670 if (AR_SREV_9287_11_OR_LATER(ah)) 671 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 672 673 val |= AR_PCU_MISC_MODE2_CFP_IGNORE; 674 675 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 676 } 677 678 if (AR_SREV_9280_20_OR_LATER(ah)) 679 return; 680 /* 681 * Disable BB clock gating 682 * Necessary to avoid issues on AR5416 2.0 683 */ 684 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 685 686 /* 687 * Disable RIFS search on some chips to avoid baseband 688 * hang issues. 689 */ 690 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 691 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 692 val &= ~AR_PHY_RIFS_INIT_DELAY; 693 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 694 } 695} 696 697static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 698 struct ath9k_channel *chan) 699{ 700 u32 phymode; 701 u32 enableDacFifo = 0; 702 703 if (AR_SREV_9285_12_OR_LATER(ah)) 704 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 705 AR_PHY_FC_ENABLE_DAC_FIFO); 706 707 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 708 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 709 710 if (IS_CHAN_HT40(chan)) { 711 phymode |= AR_PHY_FC_DYN2040_EN; 712 713 if (IS_CHAN_HT40PLUS(chan)) 714 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 715 716 } 717 ENABLE_REGWRITE_BUFFER(ah); 718 REG_WRITE(ah, AR_PHY_TURBO, phymode); 719 720 /* This function do only REG_WRITE, so 721 * we can include it to REGWRITE_BUFFER. */ 722 ath9k_hw_set11nmac2040(ah, chan); 723 724 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 725 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 726 727 REGWRITE_BUFFER_FLUSH(ah); 728} 729 730 731static int ar5008_hw_process_ini(struct ath_hw *ah, 732 struct ath9k_channel *chan) 733{ 734 struct ath_common *common = ath9k_hw_common(ah); 735 int i, regWrites = 0; 736 u32 modesIndex, freqIndex; 737 738 if (IS_CHAN_5GHZ(chan)) { 739 freqIndex = 1; 740 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 741 } else { 742 freqIndex = 2; 743 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 744 } 745 746 /* 747 * Set correct baseband to analog shift setting to 748 * access analog chips. 749 */ 750 REG_WRITE(ah, AR_PHY(0), 0x00000007); 751 752 /* Write ADDAC shifts */ 753 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 754 if (ah->eep_ops->set_addac) 755 ah->eep_ops->set_addac(ah, chan); 756 757 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 758 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 759 760 ENABLE_REGWRITE_BUFFER(ah); 761 762 for (i = 0; i < ah->iniModes.ia_rows; i++) { 763 u32 reg = INI_RA(&ah->iniModes, i, 0); 764 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 765 766 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 767 val &= ~AR_AN_TOP2_PWDCLKIND; 768 769 REG_WRITE(ah, reg, val); 770 771 if (reg >= 0x7800 && reg < 0x78a0 772 && ah->config.analog_shiftreg 773 && (common->bus_ops->ath_bus_type != ATH_USB)) { 774 udelay(100); 775 } 776 777 DO_DELAY(regWrites); 778 } 779 780 REGWRITE_BUFFER_FLUSH(ah); 781 782 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 783 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 784 785 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 786 AR_SREV_9287_11_OR_LATER(ah)) 787 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 788 789 if (AR_SREV_9271_10(ah)) { 790 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 791 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 792 } 793 794 ENABLE_REGWRITE_BUFFER(ah); 795 796 /* Write common array parameters */ 797 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 798 u32 reg = INI_RA(&ah->iniCommon, i, 0); 799 u32 val = INI_RA(&ah->iniCommon, i, 1); 800 801 REG_WRITE(ah, reg, val); 802 803 if (reg >= 0x7800 && reg < 0x78a0 804 && ah->config.analog_shiftreg 805 && (common->bus_ops->ath_bus_type != ATH_USB)) { 806 udelay(100); 807 } 808 809 DO_DELAY(regWrites); 810 } 811 812 REGWRITE_BUFFER_FLUSH(ah); 813 814 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 815 816 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 817 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 818 regWrites); 819 820 ar5008_hw_override_ini(ah, chan); 821 ar5008_hw_set_channel_regs(ah, chan); 822 ar5008_hw_init_chain_masks(ah); 823 ath9k_olc_init(ah); 824 ath9k_hw_apply_txpower(ah, chan, false); 825 826 /* Write analog registers */ 827 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 828 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 829 return -EIO; 830 } 831 832 return 0; 833} 834 835static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 836{ 837 u32 rfMode = 0; 838 839 if (chan == NULL) 840 return; 841 842 if (IS_CHAN_2GHZ(chan)) 843 rfMode |= AR_PHY_MODE_DYNAMIC; 844 else 845 rfMode |= AR_PHY_MODE_OFDM; 846 847 if (!AR_SREV_9280_20_OR_LATER(ah)) 848 rfMode |= (IS_CHAN_5GHZ(chan)) ? 849 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 850 851 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 852 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 853 854 REG_WRITE(ah, AR_PHY_MODE, rfMode); 855} 856 857static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 858{ 859 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 860} 861 862static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 863 struct ath9k_channel *chan) 864{ 865 u32 coef_scaled, ds_coef_exp, ds_coef_man; 866 u32 clockMhzScaled = 0x64000000; 867 struct chan_centers centers; 868 869 if (IS_CHAN_HALF_RATE(chan)) 870 clockMhzScaled = clockMhzScaled >> 1; 871 else if (IS_CHAN_QUARTER_RATE(chan)) 872 clockMhzScaled = clockMhzScaled >> 2; 873 874 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 875 coef_scaled = clockMhzScaled / centers.synth_center; 876 877 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 878 &ds_coef_exp); 879 880 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 881 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 882 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 883 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 884 885 coef_scaled = (9 * coef_scaled) / 10; 886 887 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 888 &ds_coef_exp); 889 890 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 891 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 892 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 893 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 894} 895 896static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 897{ 898 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 899 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 900 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 901} 902 903static void ar5008_hw_rfbus_done(struct ath_hw *ah) 904{ 905 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 906 907 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 908 909 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 910} 911 912static void ar5008_restore_chainmask(struct ath_hw *ah) 913{ 914 int rx_chainmask = ah->rxchainmask; 915 916 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 917 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 918 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 919 } 920} 921 922static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 923 struct ath9k_channel *chan) 924{ 925 u32 pll; 926 927 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 928 929 if (chan && IS_CHAN_HALF_RATE(chan)) 930 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 931 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 932 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 933 934 if (chan && IS_CHAN_5GHZ(chan)) 935 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 936 else 937 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 938 939 return pll; 940} 941 942static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 943 struct ath9k_channel *chan) 944{ 945 u32 pll; 946 947 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 948 949 if (chan && IS_CHAN_HALF_RATE(chan)) 950 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 951 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 952 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 953 954 if (chan && IS_CHAN_5GHZ(chan)) 955 pll |= SM(0xa, AR_RTC_PLL_DIV); 956 else 957 pll |= SM(0xb, AR_RTC_PLL_DIV); 958 959 return pll; 960} 961 962static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 963 enum ath9k_ani_cmd cmd, 964 int param) 965{ 966 struct ath_common *common = ath9k_hw_common(ah); 967 struct ath9k_channel *chan = ah->curchan; 968 struct ar5416AniState *aniState = &ah->ani; 969 s32 value; 970 971 switch (cmd & ah->ani_function) { 972 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 973 /* 974 * on == 1 means ofdm weak signal detection is ON 975 * on == 1 is the default, for less noise immunity 976 * 977 * on == 0 means ofdm weak signal detection is OFF 978 * on == 0 means more noise imm 979 */ 980 u32 on = param ? 1 : 0; 981 /* 982 * make register setting for default 983 * (weak sig detect ON) come from INI file 984 */ 985 int m1ThreshLow = on ? 986 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 987 int m2ThreshLow = on ? 988 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 989 int m1Thresh = on ? 990 aniState->iniDef.m1Thresh : m1Thresh_off; 991 int m2Thresh = on ? 992 aniState->iniDef.m2Thresh : m2Thresh_off; 993 int m2CountThr = on ? 994 aniState->iniDef.m2CountThr : m2CountThr_off; 995 int m2CountThrLow = on ? 996 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 997 int m1ThreshLowExt = on ? 998 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 999 int m2ThreshLowExt = on ? 1000 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 1001 int m1ThreshExt = on ? 1002 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 1003 int m2ThreshExt = on ? 1004 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 1005 1006 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1007 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1008 m1ThreshLow); 1009 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1010 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1011 m2ThreshLow); 1012 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1013 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 1014 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1015 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 1016 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1017 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 1018 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1019 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1020 m2CountThrLow); 1021 1022 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1023 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 1024 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1025 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 1026 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1027 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 1028 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1029 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 1030 1031 if (on) 1032 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1033 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1034 else 1035 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1036 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1037 1038 if (on != aniState->ofdmWeakSigDetect) { 1039 ath_dbg(common, ANI, 1040 "** ch %d: ofdm weak signal: %s=>%s\n", 1041 chan->channel, 1042 aniState->ofdmWeakSigDetect ? 1043 "on" : "off", 1044 on ? "on" : "off"); 1045 if (on) 1046 ah->stats.ast_ani_ofdmon++; 1047 else 1048 ah->stats.ast_ani_ofdmoff++; 1049 aniState->ofdmWeakSigDetect = on; 1050 } 1051 break; 1052 } 1053 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1054 u32 level = param; 1055 1056 value = level * 2; 1057 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1058 AR_PHY_FIND_SIG_FIRSTEP, value); 1059 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1060 AR_PHY_FIND_SIG_FIRSTEP_LOW, value); 1061 1062 if (level != aniState->firstepLevel) { 1063 ath_dbg(common, ANI, 1064 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1065 chan->channel, 1066 aniState->firstepLevel, 1067 level, 1068 ATH9K_ANI_FIRSTEP_LVL, 1069 value, 1070 aniState->iniDef.firstep); 1071 ath_dbg(common, ANI, 1072 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1073 chan->channel, 1074 aniState->firstepLevel, 1075 level, 1076 ATH9K_ANI_FIRSTEP_LVL, 1077 value, 1078 aniState->iniDef.firstepLow); 1079 if (level > aniState->firstepLevel) 1080 ah->stats.ast_ani_stepup++; 1081 else if (level < aniState->firstepLevel) 1082 ah->stats.ast_ani_stepdown++; 1083 aniState->firstepLevel = level; 1084 } 1085 break; 1086 } 1087 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1088 u32 level = param; 1089 1090 value = (level + 1) * 2; 1091 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1092 AR_PHY_TIMING5_CYCPWR_THR1, value); 1093 1094 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1095 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); 1096 1097 if (level != aniState->spurImmunityLevel) { 1098 ath_dbg(common, ANI, 1099 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1100 chan->channel, 1101 aniState->spurImmunityLevel, 1102 level, 1103 ATH9K_ANI_SPUR_IMMUNE_LVL, 1104 value, 1105 aniState->iniDef.cycpwrThr1); 1106 ath_dbg(common, ANI, 1107 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1108 chan->channel, 1109 aniState->spurImmunityLevel, 1110 level, 1111 ATH9K_ANI_SPUR_IMMUNE_LVL, 1112 value, 1113 aniState->iniDef.cycpwrThr1Ext); 1114 if (level > aniState->spurImmunityLevel) 1115 ah->stats.ast_ani_spurup++; 1116 else if (level < aniState->spurImmunityLevel) 1117 ah->stats.ast_ani_spurdown++; 1118 aniState->spurImmunityLevel = level; 1119 } 1120 break; 1121 } 1122 case ATH9K_ANI_MRC_CCK: 1123 /* 1124 * You should not see this as AR5008, AR9001, AR9002 1125 * does not have hardware support for MRC CCK. 1126 */ 1127 WARN_ON(1); 1128 break; 1129 default: 1130 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1131 return false; 1132 } 1133 1134 ath_dbg(common, ANI, 1135 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1136 aniState->spurImmunityLevel, 1137 aniState->ofdmWeakSigDetect ? "on" : "off", 1138 aniState->firstepLevel, 1139 aniState->mrcCCK ? "on" : "off", 1140 aniState->listenTime, 1141 aniState->ofdmPhyErrCount, 1142 aniState->cckPhyErrCount); 1143 return true; 1144} 1145 1146static void ar5008_hw_do_getnf(struct ath_hw *ah, 1147 int16_t nfarray[NUM_NF_READINGS]) 1148{ 1149 int16_t nf; 1150 1151 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1152 nfarray[0] = sign_extend32(nf, 8); 1153 1154 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1155 nfarray[1] = sign_extend32(nf, 8); 1156 1157 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1158 nfarray[2] = sign_extend32(nf, 8); 1159 1160 if (!IS_CHAN_HT40(ah->curchan)) 1161 return; 1162 1163 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1164 nfarray[3] = sign_extend32(nf, 8); 1165 1166 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1167 nfarray[4] = sign_extend32(nf, 8); 1168 1169 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1170 nfarray[5] = sign_extend32(nf, 8); 1171} 1172 1173/* 1174 * Initialize the ANI register values with default (ini) values. 1175 * This routine is called during a (full) hardware reset after 1176 * all the registers are initialised from the INI. 1177 */ 1178static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1179{ 1180 struct ath_common *common = ath9k_hw_common(ah); 1181 struct ath9k_channel *chan = ah->curchan; 1182 struct ar5416AniState *aniState = &ah->ani; 1183 struct ath9k_ani_default *iniDef; 1184 u32 val; 1185 1186 iniDef = &aniState->iniDef; 1187 1188 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1189 ah->hw_version.macVersion, 1190 ah->hw_version.macRev, 1191 ah->opmode, 1192 chan->channel); 1193 1194 val = REG_READ(ah, AR_PHY_SFCORR); 1195 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1196 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1197 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1198 1199 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1200 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1201 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1202 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1203 1204 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1205 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1206 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1207 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1208 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1209 iniDef->firstep = REG_READ_FIELD(ah, 1210 AR_PHY_FIND_SIG, 1211 AR_PHY_FIND_SIG_FIRSTEP); 1212 iniDef->firstepLow = REG_READ_FIELD(ah, 1213 AR_PHY_FIND_SIG_LOW, 1214 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1215 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1216 AR_PHY_TIMING5, 1217 AR_PHY_TIMING5_CYCPWR_THR1); 1218 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1219 AR_PHY_EXT_CCA, 1220 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1221 1222 /* these levels just got reset to defaults by the INI */ 1223 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1224 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1225 aniState->ofdmWeakSigDetect = true; 1226 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1227} 1228 1229static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1230{ 1231 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1232 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1233 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1234 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1235 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1236 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1237} 1238 1239static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1240 struct ath_hw_radar_conf *conf) 1241{ 1242 u32 radar_0 = 0, radar_1; 1243 1244 if (!conf) { 1245 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1246 return; 1247 } 1248 1249 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1250 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1251 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1252 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1253 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1254 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1255 1256 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); 1257 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | 1258 AR_PHY_RADAR_1_RELPWR_THRESH); 1259 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1260 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1261 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1262 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1263 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1264 1265 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1266 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1267 if (conf->ext_channel) 1268 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1269 else 1270 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1271} 1272 1273static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1274{ 1275 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1276 1277 conf->fir_power = -33; 1278 conf->radar_rssi = 20; 1279 conf->pulse_height = 10; 1280 conf->pulse_rssi = 15; 1281 conf->pulse_inband = 15; 1282 conf->pulse_maxlen = 255; 1283 conf->pulse_inband_step = 12; 1284 conf->radar_inband = 8; 1285} 1286 1287static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) 1288{ 1289#define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x)) 1290 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]); 1291 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l], 1292 rate_array[rate2s])); 1293 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l], 1294 rate_array[rate5_5s])); 1295 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l], 1296 rate_array[rate11s])); 1297#undef CCK_DELTA 1298} 1299 1300static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, 1301 int offset) 1302{ 1303 int i, idx = 0; 1304 1305 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) { 1306 ah->tx_power[i] = rate_array[idx]; 1307 idx++; 1308 } 1309} 1310 1311static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, 1312 int ss_offset, int ds_offset, 1313 bool is_40, int ht40_delta) 1314{ 1315 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT; 1316 1317 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) { 1318 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; 1319 mcs_idx++; 1320 } 1321 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], 1322 AR5008_HT_SS_RATES); 1323} 1324 1325void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, 1326 struct ath9k_channel *chan, int ht40_delta) 1327{ 1328 if (IS_CHAN_5GHZ(chan)) { 1329 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1330 AR5008_11NA_OFDM_SHIFT); 1331 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1332 ar5008_hw_init_txpower_ht(ah, rate_array, 1333 AR5008_11NA_HT_SS_SHIFT, 1334 AR5008_11NA_HT_DS_SHIFT, 1335 IS_CHAN_HT40(chan), 1336 ht40_delta); 1337 } 1338 } else { 1339 ar5008_hw_init_txpower_cck(ah, rate_array); 1340 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1341 AR5008_11NG_OFDM_SHIFT); 1342 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1343 ar5008_hw_init_txpower_ht(ah, rate_array, 1344 AR5008_11NG_HT_SS_SHIFT, 1345 AR5008_11NG_HT_DS_SHIFT, 1346 IS_CHAN_HT40(chan), 1347 ht40_delta); 1348 } 1349 } 1350} 1351 1352int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1353{ 1354 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1355 static const u32 ar5416_cca_regs[6] = { 1356 AR_PHY_CCA, 1357 AR_PHY_CH1_CCA, 1358 AR_PHY_CH2_CCA, 1359 AR_PHY_EXT_CCA, 1360 AR_PHY_CH1_EXT_CCA, 1361 AR_PHY_CH2_EXT_CCA 1362 }; 1363 int ret; 1364 1365 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1366 if (ret) 1367 return ret; 1368 1369 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1370 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1371 1372 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1373 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1374 priv_ops->init_bb = ar5008_hw_init_bb; 1375 priv_ops->process_ini = ar5008_hw_process_ini; 1376 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1377 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1378 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1379 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1380 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1381 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1382 priv_ops->do_getnf = ar5008_hw_do_getnf; 1383 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1384 1385 priv_ops->ani_control = ar5008_hw_ani_control_new; 1386 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1387 1388 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1389 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1390 else 1391 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1392 1393 ar5008_hw_set_nf_limits(ah); 1394 ar5008_hw_set_radar_conf(ah); 1395 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1396 return 0; 1397} 1398