18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: BSD-3-Clause-Clear */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
48c2ecf20Sopenharmony_ci */
58c2ecf20Sopenharmony_ci#ifndef _ATH11K_PCI_H
68c2ecf20Sopenharmony_ci#define _ATH11K_PCI_H
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci#include <linux/mhi.h>
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci#include "core.h"
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci#define PCIE_SOC_GLOBAL_RESET			0x3008
138c2ecf20Sopenharmony_ci#define PCIE_SOC_GLOBAL_RESET_V			1
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci#define WLAON_WARM_SW_ENTRY			0x1f80504
168c2ecf20Sopenharmony_ci#define WLAON_SOC_RESET_CAUSE_REG		0x01f8060c
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ci#define PCIE_Q6_COOKIE_ADDR			0x01f80500
198c2ecf20Sopenharmony_ci#define PCIE_Q6_COOKIE_DATA			0xc0000000
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci/* register to wake the UMAC from power collapse */
228c2ecf20Sopenharmony_ci#define PCIE_SCRATCH_0_SOC_PCIE_REG		0x4040
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci/* register used for handshake mechanism to validate UMAC is awake */
258c2ecf20Sopenharmony_ci#define PCIE_SOC_WAKE_PCIE_LOCAL_REG		0x3004
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_cistruct ath11k_msi_user {
288c2ecf20Sopenharmony_ci	char *name;
298c2ecf20Sopenharmony_ci	int num_vectors;
308c2ecf20Sopenharmony_ci	u32 base_vector;
318c2ecf20Sopenharmony_ci};
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_cistruct ath11k_msi_config {
348c2ecf20Sopenharmony_ci	int total_vectors;
358c2ecf20Sopenharmony_ci	int total_users;
368c2ecf20Sopenharmony_ci	struct ath11k_msi_user *users;
378c2ecf20Sopenharmony_ci};
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_cienum ath11k_pci_flags {
408c2ecf20Sopenharmony_ci	ATH11K_PCI_FLAG_INIT_DONE,
418c2ecf20Sopenharmony_ci};
428c2ecf20Sopenharmony_ci
438c2ecf20Sopenharmony_cistruct ath11k_pci {
448c2ecf20Sopenharmony_ci	struct pci_dev *pdev;
458c2ecf20Sopenharmony_ci	struct ath11k_base *ab;
468c2ecf20Sopenharmony_ci	u16 dev_id;
478c2ecf20Sopenharmony_ci	char amss_path[100];
488c2ecf20Sopenharmony_ci	u32 msi_ep_base_data;
498c2ecf20Sopenharmony_ci	struct mhi_controller *mhi_ctrl;
508c2ecf20Sopenharmony_ci	unsigned long mhi_state;
518c2ecf20Sopenharmony_ci	u32 register_window;
528c2ecf20Sopenharmony_ci
538c2ecf20Sopenharmony_ci	/* protects register_window above */
548c2ecf20Sopenharmony_ci	spinlock_t window_lock;
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	/* enum ath11k_pci_flags */
578c2ecf20Sopenharmony_ci	unsigned long flags;
588c2ecf20Sopenharmony_ci};
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_cistatic inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
618c2ecf20Sopenharmony_ci{
628c2ecf20Sopenharmony_ci	return (struct ath11k_pci *)ab->drv_priv;
638c2ecf20Sopenharmony_ci}
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ciint ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name,
668c2ecf20Sopenharmony_ci				       int *num_vectors, u32 *user_base_data,
678c2ecf20Sopenharmony_ci				       u32 *base_vector);
688c2ecf20Sopenharmony_ciint ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
698c2ecf20Sopenharmony_civoid ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
708c2ecf20Sopenharmony_ciu32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ci#endif
73