1// SPDX-License-Identifier: BSD-3-Clause-Clear 2/* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4#include <linux/msi.h> 5#include <linux/pci.h> 6 7#include "core.h" 8#include "debug.h" 9#include "mhi.h" 10 11#define MHI_TIMEOUT_DEFAULT_MS 90000 12 13static struct mhi_channel_config ath11k_mhi_channels[] = { 14 { 15 .num = 0, 16 .name = "LOOPBACK", 17 .num_elements = 32, 18 .event_ring = 0, 19 .dir = DMA_TO_DEVICE, 20 .ee_mask = 0x4, 21 .pollcfg = 0, 22 .doorbell = MHI_DB_BRST_DISABLE, 23 .lpm_notify = false, 24 .offload_channel = false, 25 .doorbell_mode_switch = false, 26 .auto_queue = false, 27 .auto_start = false, 28 }, 29 { 30 .num = 1, 31 .name = "LOOPBACK", 32 .num_elements = 32, 33 .event_ring = 0, 34 .dir = DMA_FROM_DEVICE, 35 .ee_mask = 0x4, 36 .pollcfg = 0, 37 .doorbell = MHI_DB_BRST_DISABLE, 38 .lpm_notify = false, 39 .offload_channel = false, 40 .doorbell_mode_switch = false, 41 .auto_queue = false, 42 .auto_start = false, 43 }, 44 { 45 .num = 20, 46 .name = "IPCR", 47 .num_elements = 64, 48 .event_ring = 1, 49 .dir = DMA_TO_DEVICE, 50 .ee_mask = 0x4, 51 .pollcfg = 0, 52 .doorbell = MHI_DB_BRST_DISABLE, 53 .lpm_notify = false, 54 .offload_channel = false, 55 .doorbell_mode_switch = false, 56 .auto_queue = false, 57 .auto_start = true, 58 }, 59 { 60 .num = 21, 61 .name = "IPCR", 62 .num_elements = 64, 63 .event_ring = 1, 64 .dir = DMA_FROM_DEVICE, 65 .ee_mask = 0x4, 66 .pollcfg = 0, 67 .doorbell = MHI_DB_BRST_DISABLE, 68 .lpm_notify = false, 69 .offload_channel = false, 70 .doorbell_mode_switch = false, 71 .auto_queue = true, 72 .auto_start = true, 73 }, 74}; 75 76static struct mhi_event_config ath11k_mhi_events[] = { 77 { 78 .num_elements = 32, 79 .irq_moderation_ms = 0, 80 .irq = 1, 81 .mode = MHI_DB_BRST_DISABLE, 82 .data_type = MHI_ER_CTRL, 83 .hardware_event = false, 84 .client_managed = false, 85 .offload_channel = false, 86 }, 87 { 88 .num_elements = 256, 89 .irq_moderation_ms = 1, 90 .irq = 2, 91 .mode = MHI_DB_BRST_DISABLE, 92 .priority = 1, 93 .hardware_event = false, 94 .client_managed = false, 95 .offload_channel = false, 96 }, 97}; 98 99static struct mhi_controller_config ath11k_mhi_config = { 100 .max_channels = 128, 101 .timeout_ms = 2000, 102 .use_bounce_buf = false, 103 .buf_len = 0, 104 .num_channels = ARRAY_SIZE(ath11k_mhi_channels), 105 .ch_cfg = ath11k_mhi_channels, 106 .num_events = ARRAY_SIZE(ath11k_mhi_events), 107 .event_cfg = ath11k_mhi_events, 108}; 109 110void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 111{ 112 u32 val; 113 114 val = ath11k_pci_read32(ab, MHISTATUS); 115 116 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 117 118 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 119 * has SYSERR bit set and thus need to set MHICTRL_RESET 120 * to clear SYSERR. 121 */ 122 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 123 124 mdelay(10); 125} 126 127static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 128{ 129 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 130} 131 132static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 133{ 134 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 135} 136 137static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 138{ 139 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 140} 141 142static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 143{ 144 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 145} 146 147void ath11k_mhi_clear_vector(struct ath11k_base *ab) 148{ 149 ath11k_mhi_reset_txvecdb(ab); 150 ath11k_mhi_reset_txvecstatus(ab); 151 ath11k_mhi_reset_rxvecdb(ab); 152 ath11k_mhi_reset_rxvecstatus(ab); 153} 154 155static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 156{ 157 struct ath11k_base *ab = ab_pci->ab; 158 u32 user_base_data, base_vector; 159 int ret, num_vectors, i; 160 int *irq; 161 162 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 163 "MHI", &num_vectors, 164 &user_base_data, &base_vector); 165 if (ret) 166 return ret; 167 168 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 169 num_vectors, base_vector); 170 171 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 172 if (!irq) 173 return -ENOMEM; 174 175 for (i = 0; i < num_vectors; i++) 176 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 177 base_vector + i); 178 179 ab_pci->mhi_ctrl->irq = irq; 180 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 181 182 return 0; 183} 184 185static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 186{ 187 return 0; 188} 189 190static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 191{ 192} 193 194static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 195 enum mhi_callback cb) 196{ 197} 198 199static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 200 void __iomem *addr, 201 u32 *out) 202{ 203 *out = readl(addr); 204 205 return 0; 206} 207 208static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 209 void __iomem *addr, 210 u32 val) 211{ 212 writel(val, addr); 213} 214 215int ath11k_mhi_register(struct ath11k_pci *ab_pci) 216{ 217 struct ath11k_base *ab = ab_pci->ab; 218 struct mhi_controller *mhi_ctrl; 219 int ret; 220 221 mhi_ctrl = kzalloc(sizeof(*mhi_ctrl), GFP_KERNEL); 222 if (!mhi_ctrl) 223 return -ENOMEM; 224 225 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 226 ab_pci->amss_path, 227 sizeof(ab_pci->amss_path)); 228 229 ab_pci->mhi_ctrl = mhi_ctrl; 230 mhi_ctrl->cntrl_dev = ab->dev; 231 mhi_ctrl->fw_image = ab_pci->amss_path; 232 mhi_ctrl->regs = ab->mem; 233 234 ret = ath11k_mhi_get_msi(ab_pci); 235 if (ret) { 236 ath11k_err(ab, "failed to get msi for mhi\n"); 237 kfree(mhi_ctrl); 238 return ret; 239 } 240 241 mhi_ctrl->iova_start = 0; 242 mhi_ctrl->iova_stop = 0xffffffff; 243 mhi_ctrl->sbl_size = SZ_512K; 244 mhi_ctrl->seg_len = SZ_512K; 245 mhi_ctrl->fbc_download = true; 246 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 247 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 248 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 249 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 250 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 251 252 ret = mhi_register_controller(mhi_ctrl, &ath11k_mhi_config); 253 if (ret) { 254 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 255 kfree(mhi_ctrl); 256 return ret; 257 } 258 259 return 0; 260} 261 262void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 263{ 264 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 265 266 mhi_unregister_controller(mhi_ctrl); 267 kfree(mhi_ctrl->irq); 268} 269 270static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 271{ 272 switch (mhi_state) { 273 case ATH11K_MHI_INIT: 274 return "INIT"; 275 case ATH11K_MHI_DEINIT: 276 return "DEINIT"; 277 case ATH11K_MHI_POWER_ON: 278 return "POWER_ON"; 279 case ATH11K_MHI_POWER_OFF: 280 return "POWER_OFF"; 281 case ATH11K_MHI_FORCE_POWER_OFF: 282 return "FORCE_POWER_OFF"; 283 case ATH11K_MHI_SUSPEND: 284 return "SUSPEND"; 285 case ATH11K_MHI_RESUME: 286 return "RESUME"; 287 case ATH11K_MHI_TRIGGER_RDDM: 288 return "TRIGGER_RDDM"; 289 case ATH11K_MHI_RDDM_DONE: 290 return "RDDM_DONE"; 291 default: 292 return "UNKNOWN"; 293 } 294}; 295 296static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 297 enum ath11k_mhi_state mhi_state) 298{ 299 struct ath11k_base *ab = ab_pci->ab; 300 301 switch (mhi_state) { 302 case ATH11K_MHI_INIT: 303 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 304 break; 305 case ATH11K_MHI_DEINIT: 306 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 307 break; 308 case ATH11K_MHI_POWER_ON: 309 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 310 break; 311 case ATH11K_MHI_POWER_OFF: 312 case ATH11K_MHI_FORCE_POWER_OFF: 313 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 314 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 315 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 316 break; 317 case ATH11K_MHI_SUSPEND: 318 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 319 break; 320 case ATH11K_MHI_RESUME: 321 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 322 break; 323 case ATH11K_MHI_TRIGGER_RDDM: 324 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 325 break; 326 case ATH11K_MHI_RDDM_DONE: 327 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 328 break; 329 default: 330 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 331 } 332} 333 334static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 335 enum ath11k_mhi_state mhi_state) 336{ 337 struct ath11k_base *ab = ab_pci->ab; 338 339 switch (mhi_state) { 340 case ATH11K_MHI_INIT: 341 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 342 return 0; 343 break; 344 case ATH11K_MHI_DEINIT: 345 case ATH11K_MHI_POWER_ON: 346 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 347 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 348 return 0; 349 break; 350 case ATH11K_MHI_FORCE_POWER_OFF: 351 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 352 return 0; 353 break; 354 case ATH11K_MHI_POWER_OFF: 355 case ATH11K_MHI_SUSPEND: 356 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 357 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 358 return 0; 359 break; 360 case ATH11K_MHI_RESUME: 361 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 362 return 0; 363 break; 364 case ATH11K_MHI_TRIGGER_RDDM: 365 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 366 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 367 return 0; 368 break; 369 case ATH11K_MHI_RDDM_DONE: 370 return 0; 371 default: 372 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 373 ath11k_mhi_state_to_str(mhi_state), mhi_state); 374 } 375 376 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 377 ath11k_mhi_state_to_str(mhi_state), mhi_state, 378 ab_pci->mhi_state); 379 380 return -EINVAL; 381} 382 383static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 384 enum ath11k_mhi_state mhi_state) 385{ 386 struct ath11k_base *ab = ab_pci->ab; 387 int ret; 388 389 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 390 if (ret) 391 goto out; 392 393 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 394 ath11k_mhi_state_to_str(mhi_state), mhi_state); 395 396 switch (mhi_state) { 397 case ATH11K_MHI_INIT: 398 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 399 break; 400 case ATH11K_MHI_DEINIT: 401 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 402 ret = 0; 403 break; 404 case ATH11K_MHI_POWER_ON: 405 ret = mhi_sync_power_up(ab_pci->mhi_ctrl); 406 break; 407 case ATH11K_MHI_POWER_OFF: 408 mhi_power_down(ab_pci->mhi_ctrl, true); 409 ret = 0; 410 break; 411 case ATH11K_MHI_FORCE_POWER_OFF: 412 mhi_power_down(ab_pci->mhi_ctrl, false); 413 ret = 0; 414 break; 415 case ATH11K_MHI_SUSPEND: 416 break; 417 case ATH11K_MHI_RESUME: 418 break; 419 case ATH11K_MHI_TRIGGER_RDDM: 420 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 421 break; 422 case ATH11K_MHI_RDDM_DONE: 423 break; 424 default: 425 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 426 ret = -EINVAL; 427 } 428 429 if (ret) 430 goto out; 431 432 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 433 434 return 0; 435 436out: 437 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 438 ath11k_mhi_state_to_str(mhi_state), mhi_state); 439 return ret; 440} 441 442int ath11k_mhi_start(struct ath11k_pci *ab_pci) 443{ 444 int ret; 445 446 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 447 448 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 449 if (ret) 450 goto out; 451 452 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 453 if (ret) 454 goto out; 455 456 return 0; 457 458out: 459 return ret; 460} 461 462void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 463{ 464 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 465 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 466} 467 468