1/* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2/* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5#include "core.h" 6 7#ifndef ATH11K_HAL_DESC_H 8#define ATH11K_HAL_DESC_H 9 10#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 11 12#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 13#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 14#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 15 16struct ath11k_buffer_addr { 17 u32 info0; 18 u32 info1; 19} __packed; 20 21/* ath11k_buffer_addr 22 * 23 * info0 24 * Address (lower 32 bits) of the msdu buffer or msdu extension 25 * descriptor or Link descriptor 26 * 27 * addr 28 * Address (upper 8 bits) of the msdu buffer or msdu extension 29 * descriptor or Link descriptor 30 * 31 * return_buffer_manager (RBM) 32 * Consumer: WBM 33 * Producer: SW/FW 34 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 35 * descriptor or link descriptor that is being pointed to shall be 36 * returned after the frame has been processed. It is used by WBM 37 * for routing purposes. 38 * 39 * Values are defined in enum %HAL_RX_BUF_RBM_ 40 * 41 * sw_buffer_cookie 42 * Cookie field exclusively used by SW. HW ignores the contents, 43 * accept that it passes the programmed value on to other 44 * descriptors together with the physical address. 45 * 46 * Field can be used by SW to for example associate the buffers 47 * physical address with the virtual address. 48 */ 49 50enum hal_tlv_tag { 51 HAL_MACTX_CBF_START = 0 /* 0x0 */, 52 HAL_PHYRX_DATA = 1 /* 0x1 */, 53 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 54 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 55 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 56 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 57 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 58 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 59 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 60 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 61 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 62 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 63 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 64 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 65 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 66 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 67 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 68 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 69 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 70 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 71 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 72 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 73 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 74 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 75 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 76 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 77 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 78 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 79 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 80 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 81 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 82 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 83 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 84 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 85 HAL_MACTX_PKT_END = 34 /* 0x22 */, 86 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 87 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 88 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 89 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 90 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 91 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 92 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 93 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 94 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 95 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 96 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 97 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 98 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 99 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 100 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 101 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 102 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 103 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 104 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 105 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 106 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 107 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 108 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 109 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 110 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 111 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 112 HAL_MACTX_SERVICE = 61 /* 0x3d */, 113 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 114 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 115 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 116 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 117 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 118 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 119 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 120 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 121 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 122 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 123 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 124 HAL_MACTX_DEBUG = 73 /* 0x49 */, 125 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 126 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 127 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 128 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 129 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 130 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 131 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 132 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 133 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 134 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 135 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 136 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 137 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 138 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 139 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 140 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 141 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 142 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 143 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 144 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 145 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 146 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 147 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 148 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 149 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 150 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 151 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 152 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 153 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 154 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 155 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 156 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 157 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 158 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 159 HAL_COEX_TX_REQ = 108 /* 0x6c */, 160 HAL_DUMMY = 109 /* 0x6d */, 161 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 162 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 163 HAL_MPDU_LIMIT = 112 /* 0x70 */, 164 HAL_NA_LENGTH_END = 113 /* 0x71 */, 165 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 166 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 167 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 168 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 169 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 170 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 171 HAL_PDG_RESPONSE = 120 /* 0x78 */, 172 HAL_PDG_TX_REQ = 121 /* 0x79 */, 173 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 174 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 175 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 176 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 177 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 178 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 179 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 180 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 181 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 182 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 183 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 184 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 185 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 186 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 187 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 188 HAL_TX_DATA = 137 /* 0x89 */, 189 HAL_TX_FES_SETUP = 138 /* 0x8a */, 190 HAL_RX_PACKET = 139 /* 0x8b */, 191 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 192 HAL_TX_MPDU_END = 141 /* 0x8d */, 193 HAL_TX_MPDU_START = 142 /* 0x8e */, 194 HAL_TX_MSDU_END = 143 /* 0x8f */, 195 HAL_TX_MSDU_START = 144 /* 0x90 */, 196 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 197 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 198 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 199 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 200 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 201 HAL_MPDU_INFO = 150 /* 0x96 */, 202 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 203 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 204 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 205 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 206 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 207 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 208 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 209 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 210 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 211 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 212 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 213 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 214 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 215 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 216 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 217 HAL_TX_FLUSH = 166 /* 0xa6 */, 218 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 219 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 220 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 221 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 222 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 223 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 224 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 225 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 226 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 227 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 228 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 229 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 230 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 231 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 232 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 233 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 234 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 235 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 236 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 237 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 238 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 239 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 240 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 241 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 242 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 243 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 244 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 245 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 246 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 247 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 248 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 249 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 250 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 251 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 252 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 253 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 254 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 255 HAL_RX_START_PARAM = 204 /* 0xcc */, 256 HAL_RX_PPDU_START = 205 /* 0xcd */, 257 HAL_RX_PPDU_END = 206 /* 0xce */, 258 HAL_RX_MPDU_START = 207 /* 0xcf */, 259 HAL_RX_MPDU_END = 208 /* 0xd0 */, 260 HAL_RX_MSDU_START = 209 /* 0xd1 */, 261 HAL_RX_MSDU_END = 210 /* 0xd2 */, 262 HAL_RX_ATTENTION = 211 /* 0xd3 */, 263 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 264 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 265 HAL_RX_HEADER = 214 /* 0xd6 */, 266 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 267 HAL_RX_FLUSH = 216 /* 0xd8 */, 268 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 269 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 270 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 271 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 272 HAL_TX_CBF_INFO = 221 /* 0xdd */, 273 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 274 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 275 HAL_RX_PM_INFO = 224 /* 0xe0 */, 276 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 277 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 278 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 279 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 280 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 281 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 282 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 283 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 284 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 285 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 286 HAL_COEX_TX_RESP = 235 /* 0xeb */, 287 HAL_COEX_TX_STATUS = 236 /* 0xec */, 288 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 289 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 290 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 291 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 292 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 293 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 294 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 295 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 296 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 297 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 298 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 299 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 300 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 301 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 302 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 303 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 304 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 305 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 306 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 307 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 308 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 309 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 310 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 311 HAL_WHO_COMMIT = 260 /* 0x104 */, 312 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 313 HAL_WHO_FLUSH = 262 /* 0x106 */, 314 HAL_WHO_L2_LLC = 263 /* 0x107 */, 315 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 316 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 317 HAL_WHO_L3_INFO = 266 /* 0x10a */, 318 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 319 HAL_WHO_L4_INFO = 268 /* 0x10c */, 320 HAL_WHO_MSDU = 269 /* 0x10d */, 321 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 322 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 323 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 324 HAL_WHO_PPDU_END = 273 /* 0x111 */, 325 HAL_WHO_PPDU_START = 274 /* 0x112 */, 326 HAL_WHO_TSO = 275 /* 0x113 */, 327 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 328 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 329 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 330 HAL_MPDU_INFO_END = 279 /* 0x117 */, 331 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 332 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 333 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 334 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 335 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 336 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 337 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 338 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 339 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 340 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 341 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 342 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 343 HAL_WHO_TERMINATE = 292 /* 0x124 */, 344 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 345 HAL_TX_CV_DATA = 294 /* 0x126 */, 346 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 347 HAL_PPDU_TX_END = 296 /* 0x128 */, 348 HAL_PROT_TX_END = 297 /* 0x129 */, 349 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 350 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 351 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 352 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 353 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 354 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 355 HAL_ACK_REPORT = 304 /* 0x130 */, 356 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 357 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 358 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 359 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 360 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 361 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 362 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 363 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 364 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 365 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 366 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 367 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 368 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 369 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 370 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 371 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 372 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 373 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 374 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 375 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 376 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 377 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 378 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 379 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 380 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 381 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 382 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 383 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 384 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 385 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 386 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 387 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 388 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 389 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 390 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 391 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 392 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 393 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 394 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 395 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 396 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 397 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 398 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 399 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 400 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 401 HAL_RX_RING_MASK = 350 /* 0x15e */, 402 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 403 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 404 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 405 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 406 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 407 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 408 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 409 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 410 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 411 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 412 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 413 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 414 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 415 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 416 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 417 HAL_HT_SIG_INFO = 366 /* 0x16e */, 418 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 419 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 420 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 421 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 422 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 423 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 424 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 425 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 426 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 427 HAL_SERVICE_INFO = 376 /* 0x178 */, 428 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 429 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 430 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 431 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 432 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 433 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 434 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 435 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 436 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 437 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 438 HAL_SCHEDULER_END = 387 /* 0x183 */, 439 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 440 HAL_SW_PEER_INFO = 389 /* 0x185 */, 441 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 442 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 443 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 444 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 445 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 446 HAL_CCE_RULE = 395 /* 0x18b */, 447 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 448 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 449 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 450 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 451 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 452 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 453 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 454 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 455 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 456 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 457 HAL_CE_SRC_DESC = 406 /* 0x196 */, 458 HAL_CE_STAT_DESC = 407 /* 0x197 */, 459 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 460 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 461 HAL_CMD_PART_0_END = 410 /* 0x19a */, 462 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 463 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 464 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 465 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 466 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 467 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 468 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 469 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 470 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 471 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 472 HAL_TLV_BASE = 511 /* 0x1ff */, 473}; 474 475#define HAL_TLV_HDR_TAG GENMASK(9, 1) 476#define HAL_TLV_HDR_LEN GENMASK(25, 10) 477 478#define HAL_TLV_ALIGN 4 479 480struct hal_tlv_hdr { 481 u32 tl; 482 u8 value[]; 483} __packed; 484 485#define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) 486#define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8) 487#define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20) 488#define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21) 489#define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22) 490#define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23) 491#define RX_MPDU_DESC_INFO0_VALID_PN BIT(24) 492#define RX_MPDU_DESC_INFO0_VALID_SA BIT(25) 493#define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(26) 494#define RX_MPDU_DESC_INFO0_VALID_DA BIT(27) 495#define RX_MPDU_DESC_INFO0_DA_MCBC BIT(28) 496#define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(29) 497#define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(30) 498 499struct rx_mpdu_desc { 500 u32 info0; /* %RX_MPDU_DESC_INFO */ 501 u32 meta_data; 502} __packed; 503 504/* rx_mpdu_desc 505 * Producer: RXDMA 506 * Consumer: REO/SW/FW 507 * 508 * msdu_count 509 * The number of MSDUs within the MPDU 510 * 511 * mpdu_sequence_number 512 * The field can have two different meanings based on the setting 513 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 514 * start sequence number from the BAR frame otherwise it means 515 * the MPDU sequence number of the received frame. 516 * 517 * fragment_flag 518 * When set, this MPDU is a fragment and REO should forward this 519 * fragment MPDU to the REO destination ring without any reorder 520 * checks, pn checks or bitmap update. This implies that REO is 521 * forwarding the pointer to the MSDU link descriptor. 522 * 523 * mpdu_retry_bit 524 * The retry bit setting from the MPDU header of the received frame 525 * 526 * ampdu_flag 527 * Indicates the MPDU was received as part of an A-MPDU. 528 * 529 * bar_frame 530 * Indicates the received frame is a BAR frame. After processing, 531 * this frame shall be pushed to SW or deleted. 532 * 533 * valid_pn 534 * When not set, REO will not perform a PN sequence number check. 535 * 536 * valid_sa 537 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 538 * 539 * sa_idx_timeout 540 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 541 * MAC source address search due to the expiration of search timer. 542 * 543 * valid_da 544 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 545 * 546 * da_mcbc 547 * Field Only valid if valid_da is set. Indicates at least one of 548 * the DA addresses is a Multicast or Broadcast address. 549 * 550 * da_idx_timeout 551 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 552 * MAC destination address search due to the expiration of search 553 * timer. 554 * 555 * raw_mpdu 556 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 557 * the contents in the MSDU buffer contains a 'RAW' MPDU. 558 */ 559 560enum hal_rx_msdu_desc_reo_dest_ind { 561 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 562 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 563 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 564 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 565 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 566 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 567 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 568}; 569 570#define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) 571#define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) 572#define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) 573#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 574#define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 575#define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(22) 576#define RX_MSDU_DESC_INFO0_VALID_SA BIT(23) 577#define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(24) 578#define RX_MSDU_DESC_INFO0_VALID_DA BIT(25) 579#define RX_MSDU_DESC_INFO0_DA_MCBC BIT(26) 580#define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(27) 581 582#define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 583 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 584 585struct rx_msdu_desc { 586 u32 info0; 587 u32 rsvd0; 588} __packed; 589 590/* rx_msdu_desc 591 * 592 * first_msdu_in_mpdu 593 * Indicates first msdu in mpdu. 594 * 595 * last_msdu_in_mpdu 596 * Indicates last msdu in mpdu. This flag can be true only when 597 * 'Msdu_continuation' set to 0. This implies that when an msdu 598 * is spread out over multiple buffers and thus msdu_continuation 599 * is set, only for the very last buffer of the msdu, can the 600 * 'last_msdu_in_mpdu' be set. 601 * 602 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 603 * the MPDU that this MSDU belongs to only contains a single MSDU. 604 * 605 * msdu_continuation 606 * When set, this MSDU buffer was not able to hold the entire MSDU. 607 * The next buffer will therefor contain additional information 608 * related to this MSDU. 609 * 610 * msdu_length 611 * Field is only valid in combination with the 'first_msdu_in_mpdu' 612 * being set. Full MSDU length in bytes after decapsulation. This 613 * field is still valid for MPDU frames without A-MSDU. It still 614 * represents MSDU length after decapsulation Or in case of RAW 615 * MPDUs, it indicates the length of the entire MPDU (without FCS 616 * field). 617 * 618 * reo_destination_indication 619 * The id of the reo exit ring where the msdu frame shall push 620 * after (MPDU level) reordering has finished. Values are defined 621 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 622 * 623 * msdu_drop 624 * Indicates that REO shall drop this MSDU and not forward it to 625 * any other ring. 626 * 627 * valid_sa 628 * Indicates OLE found a valid SA entry for this MSDU. 629 * 630 * sa_idx_timeout 631 * Indicates, an unsuccessful MAC source address search due to 632 * the expiration of search timer for this MSDU. 633 * 634 * valid_da 635 * When set, OLE found a valid DA entry for this MSDU. 636 * 637 * da_mcbc 638 * Field Only valid if valid_da is set. Indicates the DA address 639 * is a Multicast or Broadcast address for this MSDU. 640 * 641 * da_idx_timeout 642 * Indicates, an unsuccessful MAC destination address search due 643 * to the expiration of search timer fot this MSDU. 644 */ 645 646enum hal_reo_dest_ring_buffer_type { 647 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 648 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 649}; 650 651enum hal_reo_dest_ring_push_reason { 652 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 653 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 654}; 655 656enum hal_reo_dest_ring_error_code { 657 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 658 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 659 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 660 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 661 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 662 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 663 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 664 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 665 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 666 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 667 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 668 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 669 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 670 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 671 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 672 HAL_REO_DEST_RING_ERROR_CODE_MAX, 673}; 674 675#define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 676#define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(8) 677#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 678#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 679#define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 680 681#define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID BIT(0) 682#define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 683#define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 684 685#define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 686#define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 687 688struct hal_reo_dest_ring { 689 struct ath11k_buffer_addr buf_addr_info; 690 struct rx_mpdu_desc rx_mpdu_info; 691 struct rx_msdu_desc rx_msdu_info; 692 u32 queue_addr_lo; 693 u32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ 694 u32 info1; /* %HAL_REO_DEST_RING_INFO1_ */ 695 u32 rsvd0; 696 u32 rsvd1; 697 u32 rsvd2; 698 u32 rsvd3; 699 u32 rsvd4; 700 u32 rsvd5; 701 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 702} __packed; 703 704/* hal_reo_dest_ring 705 * 706 * Producer: RXDMA 707 * Consumer: REO/SW/FW 708 * 709 * buf_addr_info 710 * Details of the physical address of a buffer or MSDU 711 * link descriptor. 712 * 713 * rx_mpdu_info 714 * General information related to the MPDU that is passed 715 * on from REO entrance ring to the REO destination ring. 716 * 717 * rx_msdu_info 718 * General information related to the MSDU that is passed 719 * on from RXDMA all the way to to the REO destination ring. 720 * 721 * queue_addr_lo 722 * Address (lower 32 bits) of the REO queue descriptor. 723 * 724 * queue_addr_hi 725 * Address (upper 8 bits) of the REO queue descriptor. 726 * 727 * buffer_type 728 * Indicates the type of address provided in the buf_addr_info. 729 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 730 * 731 * push_reason 732 * Reason for pushing this frame to this exit ring. Values are 733 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 734 * 735 * error_code 736 * Valid only when 'push_reason' is set. All error codes are 737 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 738 * 739 * rx_queue_num 740 * Indicates the REO MPDU reorder queue id from which this frame 741 * originated. 742 * 743 * reorder_info_valid 744 * When set, REO has been instructed to not perform the actual 745 * re-ordering of frames for this queue, but just to insert 746 * the reorder opcodes. 747 * 748 * reorder_opcode 749 * Field is valid when 'reorder_info_valid' is set. This field is 750 * always valid for debug purpose as well. 751 * 752 * reorder_slot_idx 753 * Valid only when 'reorder_info_valid' is set. 754 * 755 * ring_id 756 * The buffer pointer ring id. 757 * 0 - Idle ring 758 * 1 - N refers to other rings. 759 * 760 * looping_count 761 * Indicates the number of times the producer of entries into 762 * this ring has looped around the ring. 763 */ 764 765enum hal_reo_entr_rxdma_ecode { 766 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 767 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 768 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 769 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 770 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 771 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 772 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 773 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 774 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 775 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 776 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 777 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 778 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 779 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 780 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 781}; 782 783#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 784#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 785#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 786#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 787 788#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 789#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 790 791struct hal_reo_entrance_ring { 792 struct ath11k_buffer_addr buf_addr_info; 793 struct rx_mpdu_desc rx_mpdu_info; 794 u32 queue_addr_lo; 795 u32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 796 u32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 797 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 798 799} __packed; 800 801/* hal_reo_entrance_ring 802 * 803 * Producer: RXDMA 804 * Consumer: REO 805 * 806 * buf_addr_info 807 * Details of the physical address of a buffer or MSDU 808 * link descriptor. 809 * 810 * rx_mpdu_info 811 * General information related to the MPDU that is passed 812 * on from REO entrance ring to the REO destination ring. 813 * 814 * queue_addr_lo 815 * Address (lower 32 bits) of the REO queue descriptor. 816 * 817 * queue_addr_hi 818 * Address (upper 8 bits) of the REO queue descriptor. 819 * 820 * mpdu_byte_count 821 * An approximation of the number of bytes received in this MPDU. 822 * Used to keeps stats on the amount of data flowing 823 * through a queue. 824 * 825 * reo_destination_indication 826 * The id of the reo exit ring where the msdu frame shall push 827 * after (MPDU level) reordering has finished. Values are defined 828 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 829 * 830 * frameless_bar 831 * Indicates that this REO entrance ring struct contains BAR info 832 * from a multi TID BAR frame. The original multi TID BAR frame 833 * itself contained all the REO info for the first TID, but all 834 * the subsequent TID info and their linkage to the REO descriptors 835 * is passed down as 'frameless' BAR info. 836 * 837 * The only fields valid in this descriptor when this bit is set 838 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 839 * bar_frame and peer_meta_data. 840 * 841 * rxdma_push_reason 842 * Reason for pushing this frame to this exit ring. Values are 843 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 844 * 845 * rxdma_error_code 846 * Valid only when 'push_reason' is set. All error codes are 847 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 848 * 849 * ring_id 850 * The buffer pointer ring id. 851 * 0 - Idle ring 852 * 1 - N refers to other rings. 853 * 854 * looping_count 855 * Indicates the number of times the producer of entries into 856 * this ring has looped around the ring. 857 */ 858 859#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 860#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 861 862struct hal_reo_cmd_hdr { 863 u32 info0; 864} __packed; 865 866#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 867#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 868 869struct hal_reo_get_queue_stats { 870 struct hal_reo_cmd_hdr cmd; 871 u32 queue_addr_lo; 872 u32 info0; 873 u32 rsvd0[6]; 874} __packed; 875 876/* hal_reo_get_queue_stats 877 * Producer: SW 878 * Consumer: REO 879 * 880 * cmd 881 * Details for command execution tracking purposes. 882 * 883 * queue_addr_lo 884 * Address (lower 32 bits) of the REO queue descriptor. 885 * 886 * queue_addr_hi 887 * Address (upper 8 bits) of the REO queue descriptor. 888 * 889 * clear_stats 890 * Clear stats settings. When set, Clear the stats after 891 * generating the status. 892 * 893 * Following stats will be cleared. 894 * Timeout_count 895 * Forward_due_to_bar_count 896 * Duplicate_count 897 * Frames_in_order_count 898 * BAR_received_count 899 * MPDU_Frames_processed_count 900 * MSDU_Frames_processed_count 901 * Total_processed_byte_count 902 * Late_receive_MPDU_count 903 * window_jump_2k 904 * Hole_count 905 */ 906 907#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 908#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 909#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 910 911struct hal_reo_flush_queue { 912 struct hal_reo_cmd_hdr cmd; 913 u32 desc_addr_lo; 914 u32 info0; 915 u32 rsvd0[6]; 916} __packed; 917 918#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 919#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 920#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 921#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 922#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 923#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 924#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 925 926struct hal_reo_flush_cache { 927 struct hal_reo_cmd_hdr cmd; 928 u32 cache_addr_lo; 929 u32 info0; 930 u32 rsvd0[6]; 931} __packed; 932 933#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 934#define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 935#define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 936#define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 937#define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 938#define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 939#define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 940#define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 941#define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 942 943#define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 944#define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 945#define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 946#define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 947#define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 948#define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 949#define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 950#define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 951 952#define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 953#define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 954#define HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 955#define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 956#define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 957#define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 958 959#define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 960#define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 961#define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 962 963#define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 964#define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 965 966enum hal_encrypt_type { 967 HAL_ENCRYPT_TYPE_WEP_40, 968 HAL_ENCRYPT_TYPE_WEP_104, 969 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 970 HAL_ENCRYPT_TYPE_WEP_128, 971 HAL_ENCRYPT_TYPE_TKIP_MIC, 972 HAL_ENCRYPT_TYPE_WAPI, 973 HAL_ENCRYPT_TYPE_CCMP_128, 974 HAL_ENCRYPT_TYPE_OPEN, 975 HAL_ENCRYPT_TYPE_CCMP_256, 976 HAL_ENCRYPT_TYPE_GCMP_128, 977 HAL_ENCRYPT_TYPE_AES_GCMP_256, 978 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 979}; 980 981enum hal_tcl_encap_type { 982 HAL_TCL_ENCAP_TYPE_RAW, 983 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 984 HAL_TCL_ENCAP_TYPE_ETHERNET, 985 HAL_TCL_ENCAP_TYPE_802_3 = 3, 986}; 987 988enum hal_tcl_desc_type { 989 HAL_TCL_DESC_TYPE_BUFFER, 990 HAL_TCL_DESC_TYPE_EXT_DESC, 991}; 992 993enum hal_wbm_htt_tx_comp_status { 994 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 995 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 996 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 997 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 998 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 999 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 1000}; 1001 1002struct hal_tcl_data_cmd { 1003 struct ath11k_buffer_addr buf_addr_info; 1004 u32 info0; 1005 u32 info1; 1006 u32 info2; 1007 u32 info3; 1008 u32 info4; 1009} __packed; 1010 1011/* hal_tcl_data_cmd 1012 * 1013 * buf_addr_info 1014 * Details of the physical address of a buffer or MSDU 1015 * link descriptor. 1016 * 1017 * desc_type 1018 * Indicates the type of address provided in the buf_addr_info. 1019 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 1020 * 1021 * epd 1022 * When this bit is set then input packet is an EPD type. 1023 * 1024 * encap_type 1025 * Indicates the encapsulation that HW will perform. Values are 1026 * defined in enum %HAL_TCL_ENCAP_TYPE_. 1027 * 1028 * encrypt_type 1029 * Field only valid for encap_type: RAW 1030 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 1031 * 1032 * src_buffer_swap 1033 * Treats source memory (packet buffer) organization as big-endian. 1034 * 1'b0: Source memory is little endian 1035 * 1'b1: Source memory is big endian 1036 * 1037 * link_meta_swap 1038 * Treats link descriptor and Metadata as big-endian. 1039 * 1'b0: memory is little endian 1040 * 1'b1: memory is big endian 1041 * 1042 * search_type 1043 * Search type select 1044 * 0 - Normal search, 1 - Index based address search, 1045 * 2 - Index based flow search 1046 * 1047 * addrx_en 1048 * addry_en 1049 * Address X/Y search enable in ASE correspondingly. 1050 * 1'b0: Search disable 1051 * 1'b1: Search Enable 1052 * 1053 * cmd_num 1054 * This number can be used to match against status. 1055 * 1056 * data_length 1057 * MSDU length in case of direct descriptor. Length of link 1058 * extension descriptor in case of Link extension descriptor. 1059 * 1060 * *_checksum_en 1061 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 1062 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 1063 * 1064 * to_fw 1065 * Forward packet to FW along with classification result. The 1066 * packet will not be forward to TQM when this bit is set. 1067 * 1'b0: Use classification result to forward the packet. 1068 * 1'b1: Override classification result & forward packet only to fw 1069 * 1070 * packet_offset 1071 * Packet offset from Metadata in case of direct buffer descriptor. 1072 * 1073 * buffer_timestamp 1074 * buffer_timestamp_valid 1075 * Frame system entrance timestamp. It shall be filled by first 1076 * module (SW, TCL or TQM) that sees the frames first. 1077 * 1078 * mesh_enable 1079 * For raw WiFi frames, this indicates transmission to a mesh STA, 1080 * enabling the interpretation of the 'Mesh Control Present' bit 1081 * (bit 8) of QoS Control. 1082 * For native WiFi frames, this indicates that a 'Mesh Control' 1083 * field is present between the header and the LLC. 1084 * 1085 * hlos_tid_overwrite 1086 * 1087 * When set, TCL shall ignore the IP DSCP and VLAN PCP 1088 * fields and use HLOS_TID as the final TID. Otherwise TCL 1089 * shall consider the DSCP and PCP fields as well as HLOS_TID 1090 * and choose a final TID based on the configured priority 1091 * 1092 * hlos_tid 1093 * HLOS MSDU priority 1094 * Field is used when HLOS_TID_overwrite is set. 1095 * 1096 * lmac_id 1097 * TCL uses this LMAC_ID in address search, i.e, while 1098 * finding matching entry for the packet in AST corresponding 1099 * to given LMAC_ID 1100 * 1101 * If LMAC ID is all 1s (=> value 3), it indicates wildcard 1102 * match for any MAC 1103 * 1104 * dscp_tid_table_num 1105 * DSCP to TID mapping table number that need to be used 1106 * for the MSDU. 1107 * 1108 * search_index 1109 * The index that will be used for index based address or 1110 * flow search. The field is valid when 'search_type' is 1 or 2. 1111 * 1112 * cache_set_num 1113 * 1114 * Cache set number that should be used to cache the index 1115 * based search results, for address and flow search. This 1116 * value should be equal to LSB four bits of the hash value of 1117 * match data, in case of search index points to an entry which 1118 * may be used in content based search also. The value can be 1119 * anything when the entry pointed by search index will not be 1120 * used for content based search. 1121 * 1122 * ring_id 1123 * The buffer pointer ring ID. 1124 * 0 refers to the IDLE ring 1125 * 1 - N refers to other rings 1126 * 1127 * looping_count 1128 * 1129 * A count value that indicates the number of times the 1130 * producer of entries into the Ring has looped around the 1131 * ring. 1132 * 1133 * At initialization time, this value is set to 0. On the 1134 * first loop, this value is set to 1. After the max value is 1135 * reached allowed by the number of bits for this field, the 1136 * count value continues with 0 again. 1137 * 1138 * In case SW is the consumer of the ring entries, it can 1139 * use this field to figure out up to where the producer of 1140 * entries has created new entries. This eliminates the need to 1141 * check where the head pointer' of the ring is located once 1142 * the SW starts processing an interrupt indicating that new 1143 * entries have been put into this ring... 1144 * 1145 * Also note that SW if it wants only needs to look at the 1146 * LSB bit of this count value. 1147 */ 1148 1149#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 1150 1151enum hal_tcl_gse_ctrl { 1152 HAL_TCL_GSE_CTRL_RD_STAT, 1153 HAL_TCL_GSE_CTRL_SRCH_DIS, 1154 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 1155 HAL_TCL_GSE_CTRL_WR_BK_ALL, 1156 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 1157 HAL_TCL_GSE_CTRL_INVAL_ALL, 1158 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 1159 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 1160 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 1161}; 1162 1163/* hal_tcl_gse_ctrl 1164 * 1165 * rd_stat 1166 * Report or Read statistics 1167 * srch_dis 1168 * Search disable. Report only Hash. 1169 * wr_bk_single 1170 * Write Back single entry 1171 * wr_bk_all 1172 * Write Back entire cache entry 1173 * inval_single 1174 * Invalidate single cache entry 1175 * inval_all 1176 * Invalidate entire cache 1177 * wr_bk_inval_single 1178 * Write back and invalidate single entry in cache 1179 * wr_bk_inval_all 1180 * Write back and invalidate entire cache 1181 * clr_stat_single 1182 * Clear statistics for single entry 1183 */ 1184 1185#define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 1186#define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 1187#define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 1188#define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 1189#define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 1190 1191#define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 1192#define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 1193 1194struct hal_tcl_gse_cmd { 1195 u32 ctrl_buf_addr_lo; 1196 u32 info0; 1197 u32 meta_data[2]; 1198 u32 rsvd0[2]; 1199 u32 info1; 1200} __packed; 1201 1202/* hal_tcl_gse_cmd 1203 * 1204 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 1205 * Address of a control buffer containing additional info needed 1206 * for this command execution. 1207 * 1208 * gse_ctrl 1209 * GSE control operations. This includes cache operations and table 1210 * entry statistics read/clear operation. Values are defined in 1211 * enum %HAL_TCL_GSE_CTRL. 1212 * 1213 * gse_sel 1214 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1215 * 0: FSE select 1: ASE select 1216 * 1217 * status_destination_ring_id 1218 * TCL status ring to which the GSE status needs to be send. 1219 * 1220 * swap 1221 * Bit to enable byte swapping of contents of buffer. 1222 * 1223 * meta_data 1224 * Meta data to be returned in the status descriptor 1225 */ 1226 1227enum hal_tcl_cache_op_res { 1228 HAL_TCL_CACHE_OP_RES_DONE, 1229 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 1230 HAL_TCL_CACHE_OP_RES_TIMEOUT, 1231}; 1232 1233#define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 1234#define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 1235#define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 1236#define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 1237 1238#define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 1239 1240#define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 1241#define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 1242 1243struct hal_tcl_status_ring { 1244 u32 info0; 1245 u32 msdu_byte_count; 1246 u32 msdu_timestamp; 1247 u32 meta_data[2]; 1248 u32 info1; 1249 u32 rsvd0; 1250 u32 info2; 1251} __packed; 1252 1253/* hal_tcl_status_ring 1254 * 1255 * gse_ctrl 1256 * GSE control operations. This includes cache operations and table 1257 * entry statistics read/clear operation. Values are defined in 1258 * enum %HAL_TCL_GSE_CTRL. 1259 * 1260 * gse_sel 1261 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1262 * 0: FSE select 1: ASE select 1263 * 1264 * cache_op_res 1265 * Cache operation result. Values are defined in enum 1266 * %HAL_TCL_CACHE_OP_RES_. 1267 * 1268 * msdu_cnt 1269 * msdu_byte_count 1270 * MSDU count of Entry and MSDU byte count for entry 1. 1271 * 1272 * hash_indx 1273 * Hash value of the entry in case of search failed or disabled. 1274 */ 1275 1276#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1277#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 1278#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 1279#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 1280#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 1281#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 1282 1283#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 1284 1285#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 1286#define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1287 1288struct hal_ce_srng_src_desc { 1289 u32 buffer_addr_low; 1290 u32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 1291 u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 1292 u32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 1293} __packed; 1294 1295/* 1296 * hal_ce_srng_src_desc 1297 * 1298 * buffer_addr_lo 1299 * LSB 32 bits of the 40 Bit Pointer to the source buffer 1300 * 1301 * buffer_addr_hi 1302 * MSB 8 bits of the 40 Bit Pointer to the source buffer 1303 * 1304 * toeplitz_en 1305 * Enable generation of 32-bit Toeplitz-LFSR hash for 1306 * data transfer. In case of gather field in first source 1307 * ring entry of the gather copy cycle in taken into account. 1308 * 1309 * src_swap 1310 * Treats source memory organization as big-endian. For 1311 * each dword read (4 bytes), the byte 0 is swapped with byte 3 1312 * and byte 1 is swapped with byte 2. 1313 * In case of gather field in first source ring entry of 1314 * the gather copy cycle in taken into account. 1315 * 1316 * dest_swap 1317 * Treats destination memory organization as big-endian. 1318 * For each dword write (4 bytes), the byte 0 is swapped with 1319 * byte 3 and byte 1 is swapped with byte 2. 1320 * In case of gather field in first source ring entry of 1321 * the gather copy cycle in taken into account. 1322 * 1323 * gather 1324 * Enables gather of multiple copy engine source 1325 * descriptors to one destination. 1326 * 1327 * ce_res_0 1328 * Reserved 1329 * 1330 * 1331 * length 1332 * Length of the buffer in units of octets of the current 1333 * descriptor 1334 * 1335 * fw_metadata 1336 * Meta data used by FW. 1337 * In case of gather field in first source ring entry of 1338 * the gather copy cycle in taken into account. 1339 * 1340 * ce_res_1 1341 * Reserved 1342 * 1343 * ce_res_2 1344 * Reserved 1345 * 1346 * ring_id 1347 * The buffer pointer ring ID. 1348 * 0 refers to the IDLE ring 1349 * 1 - N refers to other rings 1350 * Helps with debugging when dumping ring contents. 1351 * 1352 * looping_count 1353 * A count value that indicates the number of times the 1354 * producer of entries into the Ring has looped around the 1355 * ring. 1356 * 1357 * At initialization time, this value is set to 0. On the 1358 * first loop, this value is set to 1. After the max value is 1359 * reached allowed by the number of bits for this field, the 1360 * count value continues with 0 again. 1361 * 1362 * In case SW is the consumer of the ring entries, it can 1363 * use this field to figure out up to where the producer of 1364 * entries has created new entries. This eliminates the need to 1365 * check where the head pointer' of the ring is located once 1366 * the SW starts processing an interrupt indicating that new 1367 * entries have been put into this ring... 1368 * 1369 * Also note that SW if it wants only needs to look at the 1370 * LSB bit of this count value. 1371 */ 1372 1373#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1374#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 1375#define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1376 1377struct hal_ce_srng_dest_desc { 1378 u32 buffer_addr_low; 1379 u32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 1380} __packed; 1381 1382/* hal_ce_srng_dest_desc 1383 * 1384 * dst_buffer_low 1385 * LSB 32 bits of the 40 Bit Pointer to the Destination 1386 * buffer 1387 * 1388 * dst_buffer_high 1389 * MSB 8 bits of the 40 Bit Pointer to the Destination 1390 * buffer 1391 * 1392 * ce_res_4 1393 * Reserved 1394 * 1395 * ring_id 1396 * The buffer pointer ring ID. 1397 * 0 refers to the IDLE ring 1398 * 1 - N refers to other rings 1399 * Helps with debugging when dumping ring contents. 1400 * 1401 * looping_count 1402 * A count value that indicates the number of times the 1403 * producer of entries into the Ring has looped around the 1404 * ring. 1405 * 1406 * At initialization time, this value is set to 0. On the 1407 * first loop, this value is set to 1. After the max value is 1408 * reached allowed by the number of bits for this field, the 1409 * count value continues with 0 again. 1410 * 1411 * In case SW is the consumer of the ring entries, it can 1412 * use this field to figure out up to where the producer of 1413 * entries has created new entries. This eliminates the need to 1414 * check where the head pointer' of the ring is located once 1415 * the SW starts processing an interrupt indicating that new 1416 * entries have been put into this ring... 1417 * 1418 * Also note that SW if it wants only needs to look at the 1419 * LSB bit of this count value. 1420 */ 1421 1422#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 1423#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 1424#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 1425#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 1426#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 1427 1428#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(7, 0) 1429#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 1430#define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1431 1432struct hal_ce_srng_dst_status_desc { 1433 u32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 1434 u32 toeplitz_hash0; 1435 u32 toeplitz_hash1; 1436 u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 1437} __packed; 1438 1439/* hal_ce_srng_dst_status_desc 1440 * 1441 * ce_res_5 1442 * Reserved 1443 * 1444 * toeplitz_en 1445 * 1446 * src_swap 1447 * Source memory buffer swapped 1448 * 1449 * dest_swap 1450 * Destination memory buffer swapped 1451 * 1452 * gather 1453 * Gather of multiple copy engine source descriptors to one 1454 * destination enabled 1455 * 1456 * ce_res_6 1457 * Reserved 1458 * 1459 * length 1460 * Sum of all the Lengths of the source descriptor in the 1461 * gather chain 1462 * 1463 * toeplitz_hash_0 1464 * 32 LS bits of 64 bit Toeplitz LFSR hash result 1465 * 1466 * toeplitz_hash_1 1467 * 32 MS bits of 64 bit Toeplitz LFSR hash result 1468 * 1469 * fw_metadata 1470 * Meta data used by FW 1471 * In case of gather field in first source ring entry of 1472 * the gather copy cycle in taken into account. 1473 * 1474 * ce_res_7 1475 * Reserved 1476 * 1477 * ring_id 1478 * The buffer pointer ring ID. 1479 * 0 refers to the IDLE ring 1480 * 1 - N refers to other rings 1481 * Helps with debugging when dumping ring contents. 1482 * 1483 * looping_count 1484 * A count value that indicates the number of times the 1485 * producer of entries into the Ring has looped around the 1486 * ring. 1487 * 1488 * At initialization time, this value is set to 0. On the 1489 * first loop, this value is set to 1. After the max value is 1490 * reached allowed by the number of bits for this field, the 1491 * count value continues with 0 again. 1492 * 1493 * In case SW is the consumer of the ring entries, it can 1494 * use this field to figure out up to where the producer of 1495 * entries has created new entries. This eliminates the need to 1496 * check where the head pointer' of the ring is located once 1497 * the SW starts processing an interrupt indicating that new 1498 * entries have been put into this ring... 1499 * 1500 * Also note that SW if it wants only needs to look at the 1501 * LSB bit of this count value. 1502 */ 1503 1504#define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 1505#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 1506#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 1507#define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 1508#define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 1509#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 1510#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 1511#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 1512#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 1513 1514enum hal_tx_rate_stats_bw { 1515 HAL_TX_RATE_STATS_BW_20, 1516 HAL_TX_RATE_STATS_BW_40, 1517 HAL_TX_RATE_STATS_BW_80, 1518 HAL_TX_RATE_STATS_BW_160, 1519}; 1520 1521enum hal_tx_rate_stats_pkt_type { 1522 HAL_TX_RATE_STATS_PKT_TYPE_11A, 1523 HAL_TX_RATE_STATS_PKT_TYPE_11B, 1524 HAL_TX_RATE_STATS_PKT_TYPE_11N, 1525 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 1526 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 1527}; 1528 1529enum hal_tx_rate_stats_sgi { 1530 HAL_TX_RATE_STATS_SGI_08US, 1531 HAL_TX_RATE_STATS_SGI_04US, 1532 HAL_TX_RATE_STATS_SGI_16US, 1533 HAL_TX_RATE_STATS_SGI_32US, 1534}; 1535 1536struct hal_tx_rate_stats { 1537 u32 info0; 1538 u32 tsf; 1539} __packed; 1540 1541struct hal_wbm_link_desc { 1542 struct ath11k_buffer_addr buf_addr_info; 1543} __packed; 1544 1545/* hal_wbm_link_desc 1546 * 1547 * Producer: WBM 1548 * Consumer: WBM 1549 * 1550 * buf_addr_info 1551 * Details of the physical address of a buffer or MSDU 1552 * link descriptor. 1553 */ 1554 1555enum hal_wbm_rel_src_module { 1556 HAL_WBM_REL_SRC_MODULE_TQM, 1557 HAL_WBM_REL_SRC_MODULE_RXDMA, 1558 HAL_WBM_REL_SRC_MODULE_REO, 1559 HAL_WBM_REL_SRC_MODULE_FW, 1560 HAL_WBM_REL_SRC_MODULE_SW, 1561}; 1562 1563enum hal_wbm_rel_desc_type { 1564 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1565 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1566 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1567 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1568 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1569}; 1570 1571/* hal_wbm_rel_desc_type 1572 * 1573 * msdu_buffer 1574 * The address points to an MSDU buffer 1575 * 1576 * msdu_link_descriptor 1577 * The address points to an Tx MSDU link descriptor 1578 * 1579 * mpdu_link_descriptor 1580 * The address points to an MPDU link descriptor 1581 * 1582 * msdu_ext_descriptor 1583 * The address points to an MSDU extension descriptor 1584 * 1585 * queue_ext_descriptor 1586 * The address points to an TQM queue extension descriptor. WBM should 1587 * treat this is the same way as a link descriptor. 1588 */ 1589 1590enum hal_wbm_rel_bm_act { 1591 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1592 HAL_WBM_REL_BM_ACT_REL_MSDU, 1593}; 1594 1595/* hal_wbm_rel_bm_act 1596 * 1597 * put_in_idle_list 1598 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1599 * MDPU link descriptor, BM does not need to check to release any 1600 * individual MSDU buffers. 1601 * 1602 * release_msdu_list 1603 * This BM action can only be used in combination with desc_type being 1604 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1605 * pointer in the MSDU link descriptor is the first of an MPDU that is 1606 * released. BM shall release all the MSDU buffers linked to this first 1607 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1608 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1609 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1610 * descriptor itself shall also be released. 1611 */ 1612 1613#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1614#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 1615#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 1616#define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1617#define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 1618#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1619#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1620#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1621#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1622#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 1623 1624#define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1625#define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1626 1627#define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1628#define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 1629#define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 1630#define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 1631#define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 1632#define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 1633#define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1634 1635#define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 1636#define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 1637#define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 1638#define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 1639 1640#define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 1641#define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 1642#define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 1643 1644struct hal_wbm_release_ring { 1645 struct ath11k_buffer_addr buf_addr_info; 1646 u32 info0; 1647 u32 info1; 1648 u32 info2; 1649 struct hal_tx_rate_stats rate_stats; 1650 u32 info3; 1651} __packed; 1652 1653/* hal_wbm_release_ring 1654 * 1655 * Producer: SW/TQM/RXDMA/REO/SWITCH 1656 * Consumer: WBM/SW/FW 1657 * 1658 * HTT tx status is overlayed on wbm_release ring on 4-byte words 2, 3, 4 and 5 1659 * for software based completions. 1660 * 1661 * buf_addr_info 1662 * Details of the physical address of the buffer or link descriptor. 1663 * 1664 * release_source_module 1665 * Indicates which module initiated the release of this buffer/descriptor. 1666 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 1667 * 1668 * bm_action 1669 * Field only valid when the field return_buffer_manager in 1670 * Released_buff_or_desc_addr_info indicates: 1671 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 1672 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 1673 * 1674 * buffer_or_desc_type 1675 * Field only valid when WBM is marked as the return_buffer_manager in 1676 * the Released_Buffer_address_info. Indicates that type of buffer or 1677 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 1678 * 1679 * first_msdu_index 1680 * Field only valid for the bm_action release_msdu_list. The index of the 1681 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 1682 * 1683 * tqm_release_reason 1684 * Field only valid when Release_source_module is set to release_source_TQM 1685 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 1686 * 1687 * rxdma_push_reason 1688 * reo_push_reason 1689 * Indicates why rxdma/reo pushed the frame to this ring and values are 1690 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 1691 * 1692 * rxdma_error_code 1693 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 1694 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 1695 * 1696 * reo_error_code 1697 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 1698 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 1699 * 1700 * wbm_internal_error 1701 * Is set when WBM got a buffer pointer but the action was to push it to 1702 * the idle link descriptor ring or do link related activity OR 1703 * Is set when WBM got a link buffer pointer but the action was to push it 1704 * to the buffer descriptor ring. 1705 * 1706 * tqm_status_number 1707 * The value in this field is equal to tqm_cmd_number in TQM command. It is 1708 * used to correlate the statu with TQM commands. Only valid when 1709 * release_source_module is TQM. 1710 * 1711 * transmit_count 1712 * The number of times the frame has been transmitted, valid only when 1713 * release source in TQM. 1714 * 1715 * ack_frame_rssi 1716 * This field is only valid when the source is TQM. If this frame is 1717 * removed as the result of the reception of an ACK or BA, this field 1718 * indicates the RSSI of the received ACK or BA frame. 1719 * 1720 * sw_release_details_valid 1721 * This is set when WMB got a 'release_msdu_list' command from TQM and 1722 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 1723 * and pass them one at a time on to the 'buffer owner'. 1724 * 1725 * first_msdu 1726 * Field only valid when SW_release_details_valid is set. 1727 * When set, this MSDU is the first MSDU pointed to in the 1728 * 'release_msdu_list' command. 1729 * 1730 * last_msdu 1731 * Field only valid when SW_release_details_valid is set. 1732 * When set, this MSDU is the last MSDU pointed to in the 1733 * 'release_msdu_list' command. 1734 * 1735 * msdu_part_of_amsdu 1736 * Field only valid when SW_release_details_valid is set. 1737 * When set, this MSDU was part of an A-MSDU in MPDU 1738 * 1739 * fw_tx_notify_frame 1740 * Field only valid when SW_release_details_valid is set. 1741 * 1742 * buffer_timestamp 1743 * Field only valid when SW_release_details_valid is set. 1744 * This is the Buffer_timestamp field from the 1745 * Timestamp in units of 1024 us 1746 * 1747 * struct hal_tx_rate_stats rate_stats 1748 * Details for command execution tracking purposes. 1749 * 1750 * sw_peer_id 1751 * tid 1752 * Field only valid when Release_source_module is set to 1753 * release_source_TQM 1754 * 1755 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 1756 * not fetched and hence sw_peer_id and tid = 0 1757 * 1758 * buffer_or_desc_type = e_num 0 1759 * MSDU_rel_buffertqm_release_reason = e_num 1 1760 * tqm_rr_rem_cmd_rem 1761 * 1762 * 2) Release of msdu buffer due to Flow is not fetched and 1763 * hence sw_peer_id and tid = 0 1764 * 1765 * buffer_or_desc_type = e_num 0 1766 * MSDU_rel_buffertqm_release_reason = e_num 1 1767 * tqm_rr_rem_cmd_rem 1768 * 1769 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 1770 * command. 1771 * 1772 * buffer_or_desc_type = e_num1 1773 * msdu_link_descriptortqm_release_reason can be:e_num 1 1774 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 1775 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 1776 * 1777 * This field represents the TID from the TX_MSDU_FLOW 1778 * descriptor or TX_MPDU_QUEUE descriptor 1779 * 1780 * rind_id 1781 * For debugging. 1782 * This field is filled in by the SRNG module. 1783 * It help to identify the ring that is being looked 1784 * 1785 * looping_count 1786 * A count value that indicates the number of times the 1787 * producer of entries into the Buffer Manager Ring has looped 1788 * around the ring. 1789 * 1790 * At initialization time, this value is set to 0. On the 1791 * first loop, this value is set to 1. After the max value is 1792 * reached allowed by the number of bits for this field, the 1793 * count value continues with 0 again. 1794 * 1795 * In case SW is the consumer of the ring entries, it can 1796 * use this field to figure out up to where the producer of 1797 * entries has created new entries. This eliminates the need to 1798 * check where the head pointer' of the ring is located once 1799 * the SW starts processing an interrupt indicating that new 1800 * entries have been put into this ring... 1801 * 1802 * Also note that SW if it wants only needs to look at the 1803 * LSB bit of this count value. 1804 */ 1805 1806/** 1807 * enum hal_wbm_tqm_rel_reason - TQM release reason code 1808 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 1809 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 1810 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 1811 * initiated by sw. 1812 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 1813 * initiated by sw. 1814 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 1815 * mpdus. 1816 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 1817 * fw with fw_reason1. 1818 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 1819 * fw with fw_reason2. 1820 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 1821 * fw with fw_reason3. 1822 */ 1823enum hal_wbm_tqm_rel_reason { 1824 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 1825 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 1826 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 1827 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 1828 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 1829 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 1830 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 1831 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 1832}; 1833 1834struct hal_wbm_buffer_ring { 1835 struct ath11k_buffer_addr buf_addr_info; 1836}; 1837 1838enum hal_desc_owner { 1839 HAL_DESC_OWNER_WBM, 1840 HAL_DESC_OWNER_SW, 1841 HAL_DESC_OWNER_TQM, 1842 HAL_DESC_OWNER_RXDMA, 1843 HAL_DESC_OWNER_REO, 1844 HAL_DESC_OWNER_SWITCH, 1845}; 1846 1847enum hal_desc_buf_type { 1848 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 1849 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 1850 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 1851 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 1852 HAL_DESC_BUF_TYPE_TX_FLOW, 1853 HAL_DESC_BUF_TYPE_TX_BUFFER, 1854 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 1855 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 1856 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 1857 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 1858 HAL_DESC_BUF_TYPE_RX_BUFFER, 1859 HAL_DESC_BUF_TYPE_IDLE_LINK, 1860}; 1861 1862#define HAL_DESC_REO_OWNED 4 1863#define HAL_DESC_REO_QUEUE_DESC 8 1864#define HAL_DESC_REO_QUEUE_EXT_DESC 9 1865#define HAL_DESC_REO_NON_QOS_TID 16 1866 1867#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 1868#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 1869#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 1870 1871struct hal_desc_header { 1872 u32 info0; 1873} __packed; 1874 1875struct hal_rx_mpdu_link_ptr { 1876 struct ath11k_buffer_addr addr_info; 1877} __packed; 1878 1879struct hal_rx_msdu_details { 1880 struct ath11k_buffer_addr buf_addr_info; 1881 struct rx_msdu_desc rx_msdu_info; 1882} __packed; 1883 1884#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 1885#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 1886 1887struct hal_rx_msdu_link { 1888 struct hal_desc_header desc_hdr; 1889 struct ath11k_buffer_addr buf_addr_info; 1890 u32 info0; 1891 u32 pn[4]; 1892 struct hal_rx_msdu_details msdu_link[6]; 1893} __packed; 1894 1895struct hal_rx_reo_queue_ext { 1896 struct hal_desc_header desc_hdr; 1897 u32 rsvd; 1898 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 1899} __packed; 1900 1901/* hal_rx_reo_queue_ext 1902 * Consumer: REO 1903 * Producer: REO 1904 * 1905 * descriptor_header 1906 * Details about which module owns this struct. 1907 * 1908 * mpdu_link 1909 * Pointer to the next MPDU_link descriptor in the MPDU queue. 1910 */ 1911 1912enum hal_rx_reo_queue_pn_size { 1913 HAL_RX_REO_QUEUE_PN_SIZE_24, 1914 HAL_RX_REO_QUEUE_PN_SIZE_48, 1915 HAL_RX_REO_QUEUE_PN_SIZE_128, 1916}; 1917 1918#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 1919 1920#define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 1921#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 1922#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 1923#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 1924#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 1925#define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 1926#define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 1927#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 1928#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 1929#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 1930#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 1931#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 1932#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 1933#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 1934#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 1935#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 1936 1937#define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 1938#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 1939#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 1940#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 1941#define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 1942#define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 1943 1944#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 1945#define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 1946 1947#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 1948#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 1949#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 10) 1950 1951#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 1952#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 1953 1954#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 1955#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 1956#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 1957 1958struct hal_rx_reo_queue { 1959 struct hal_desc_header desc_hdr; 1960 u32 rx_queue_num; 1961 u32 info0; 1962 u32 info1; 1963 u32 pn[4]; 1964 u32 last_rx_enqueue_timestamp; 1965 u32 last_rx_dequeue_timestamp; 1966 u32 next_aging_queue[2]; 1967 u32 prev_aging_queue[2]; 1968 u32 rx_bitmap[8]; 1969 u32 info2; 1970 u32 info3; 1971 u32 info4; 1972 u32 processed_mpdus; 1973 u32 processed_msdus; 1974 u32 processed_total_bytes; 1975 u32 info5; 1976 u32 rsvd[3]; 1977 struct hal_rx_reo_queue_ext ext_desc[]; 1978} __packed; 1979 1980/* hal_rx_reo_queue 1981 * 1982 * descriptor_header 1983 * Details about which module owns this struct. Note that sub field 1984 * Buffer_type shall be set to receive_reo_queue_descriptor. 1985 * 1986 * receive_queue_number 1987 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 1988 * 1989 * vld 1990 * Valid bit indicating a session is established and the queue descriptor 1991 * is valid. 1992 * associated_link_descriptor_counter 1993 * Indicates which of the 3 link descriptor counters shall be incremented 1994 * or decremented when link descriptors are added or removed from this 1995 * flow queue. 1996 * disable_duplicate_detection 1997 * When set, do not perform any duplicate detection. 1998 * soft_reorder_enable 1999 * When set, REO has been instructed to not perform the actual re-ordering 2000 * of frames for this queue, but just to insert the reorder opcodes. 2001 * ac 2002 * Indicates the access category of the queue descriptor. 2003 * bar 2004 * Indicates if BAR has been received. 2005 * retry 2006 * Retry bit is checked if this bit is set. 2007 * chk_2k_mode 2008 * Indicates what type of operation is expected from Reo when the received 2009 * frame SN falls within the 2K window. 2010 * oor_mode 2011 * Indicates what type of operation is expected when the received frame 2012 * falls within the OOR window. 2013 * ba_window_size 2014 * Indicates the negotiated (window size + 1). Max of 256 bits. 2015 * 2016 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 2017 * session, with window size of 0). The 3 values here are the main values 2018 * validated, but other values should work as well. 2019 * 2020 * A BA window size of 0 (=> one frame entry bitmat), means that there is 2021 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 2022 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 2023 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 2024 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 2025 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 2026 * pn_size 2027 * REO shall perform the PN increment check, even number check, uneven 2028 * number check, PN error check and size of the PN field check. 2029 * ignore_ampdu_flag 2030 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 2031 * 2032 * svld 2033 * Sequence number in next field is valid one. 2034 * ssn 2035 * Starting Sequence number of the session. 2036 * current_index 2037 * Points to last forwarded packet 2038 * seq_2k_error_detected_flag 2039 * REO has detected a 2k error jump in the sequence number and from that 2040 * moment forward, all new frames are forwarded directly to FW, without 2041 * duplicate detect, reordering, etc. 2042 * pn_error_detected_flag 2043 * REO has detected a PN error. 2044 */ 2045 2046#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 2047#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 2048#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 2049#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 2050#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 2051#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 2052#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 2053#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 2054#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 2055#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 2056#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 2057#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 2058#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 2059#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 2060#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 2061#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 2062#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 2063#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 2064#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 2065#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 2066#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 2067#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 2068#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 2069#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 2070 2071#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 2072#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 2073#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 2074#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 2075#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 2076#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 2077#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 2078#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 2079#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 2080#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 2081#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 2082#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 2083#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 2084#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 2085#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 2086 2087#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 2088#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 2089#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 2090#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 2091#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 2092#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 2093#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 2094 2095struct hal_reo_update_rx_queue { 2096 struct hal_reo_cmd_hdr cmd; 2097 u32 queue_addr_lo; 2098 u32 info0; 2099 u32 info1; 2100 u32 info2; 2101 u32 pn[4]; 2102} __packed; 2103 2104#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 2105#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 2106 2107struct hal_reo_unblock_cache { 2108 struct hal_reo_cmd_hdr cmd; 2109 u32 info0; 2110 u32 rsvd[7]; 2111} __packed; 2112 2113enum hal_reo_exec_status { 2114 HAL_REO_EXEC_STATUS_SUCCESS, 2115 HAL_REO_EXEC_STATUS_BLOCKED, 2116 HAL_REO_EXEC_STATUS_FAILED, 2117 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 2118}; 2119 2120#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 2121#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 2122#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 2123 2124struct hal_reo_status_hdr { 2125 u32 info0; 2126 u32 timestamp; 2127} __packed; 2128 2129/* hal_reo_status_hdr 2130 * Producer: REO 2131 * Consumer: SW 2132 * 2133 * status_num 2134 * The value in this field is equal to value of the reo command 2135 * number. This field helps to correlate the statuses with the REO 2136 * commands. 2137 * 2138 * execution_time (in us) 2139 * The amount of time REO took to excecute the command. Note that 2140 * this time does not include the duration of the command waiting 2141 * in the command ring, before the execution started. 2142 * 2143 * execution_status 2144 * Execution status of the command. Values are defined in 2145 * enum %HAL_REO_EXEC_STATUS_. 2146 */ 2147#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 2148#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 2149 2150#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 2151#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 2152 2153#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 2154#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 2155#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 2156 2157#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 2158#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 2159 2160#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 2161#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 2162#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 2163 2164#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 2165 2166struct hal_reo_get_queue_stats_status { 2167 struct hal_reo_status_hdr hdr; 2168 u32 info0; 2169 u32 pn[4]; 2170 u32 last_rx_enqueue_timestamp; 2171 u32 last_rx_dequeue_timestamp; 2172 u32 rx_bitmap[8]; 2173 u32 info1; 2174 u32 info2; 2175 u32 info3; 2176 u32 num_mpdu_frames; 2177 u32 num_msdu_frames; 2178 u32 total_bytes; 2179 u32 info4; 2180 u32 info5; 2181} __packed; 2182 2183/* hal_reo_get_queue_stats_status 2184 * Producer: REO 2185 * Consumer: SW 2186 * 2187 * status_hdr 2188 * Details that can link this status with the original command. It 2189 * also contains info on how long REO took to execute this command. 2190 * 2191 * ssn 2192 * Starting Sequence number of the session, this changes whenever 2193 * window moves (can be filled by SW then maintained by REO). 2194 * 2195 * current_index 2196 * Points to last forwarded packet. 2197 * 2198 * pn 2199 * Bits of the PN number. 2200 * 2201 * last_rx_enqueue_timestamp 2202 * last_rx_dequeue_timestamp 2203 * Timestamp of arrival of the last MPDU for this queue and 2204 * Timestamp of forwarding an MPDU accordingly. 2205 * 2206 * rx_bitmap 2207 * When a bit is set, the corresponding frame is currently held 2208 * in the re-order queue. The bitmap is Fully managed by HW. 2209 * 2210 * current_mpdu_count 2211 * current_msdu_count 2212 * The number of MPDUs and MSDUs in the queue. 2213 * 2214 * timeout_count 2215 * The number of times REO started forwarding frames even though 2216 * there is a hole in the bitmap. Forwarding reason is timeout. 2217 * 2218 * forward_due_to_bar_count 2219 * The number of times REO started forwarding frames even though 2220 * there is a hole in the bitmap. Fwd reason is reception of BAR. 2221 * 2222 * duplicate_count 2223 * The number of duplicate frames that have been detected. 2224 * 2225 * frames_in_order_count 2226 * The number of frames that have been received in order (without 2227 * a hole that prevented them from being forwarded immediately). 2228 * 2229 * bar_received_count 2230 * The number of times a BAR frame is received. 2231 * 2232 * mpdu_frames_processed_count 2233 * msdu_frames_processed_count 2234 * The total number of MPDU/MSDU frames that have been processed. 2235 * 2236 * total_bytes 2237 * An approximation of the number of bytes received for this queue. 2238 * 2239 * late_receive_mpdu_count 2240 * The number of MPDUs received after the window had already moved 2241 * on. The 'late' sequence window is defined as 2242 * (Window SSN - 256) - (Window SSN - 1). 2243 * 2244 * window_jump_2k 2245 * The number of times the window moved more than 2K 2246 * 2247 * hole_count 2248 * The number of times a hole was created in the receive bitmap. 2249 * 2250 * looping_count 2251 * A count value that indicates the number of times the producer of 2252 * entries into this Ring has looped around the ring. 2253 */ 2254 2255#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 2256 2257#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 2258#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 2259#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 2260 2261struct hal_reo_flush_queue_status { 2262 struct hal_reo_status_hdr hdr; 2263 u32 info0; 2264 u32 rsvd0[21]; 2265 u32 info1; 2266} __packed; 2267 2268/* hal_reo_flush_queue_status 2269 * Producer: REO 2270 * Consumer: SW 2271 * 2272 * status_hdr 2273 * Details that can link this status with the original command. It 2274 * also contains info on how long REO took to execute this command. 2275 * 2276 * error_detected 2277 * Status of blocking resource 2278 * 2279 * 0 - No error has been detected while executing this command 2280 * 1 - Error detected. The resource to be used for blocking was 2281 * already in use. 2282 * 2283 * looping_count 2284 * A count value that indicates the number of times the producer of 2285 * entries into this Ring has looped around the ring. 2286 */ 2287 2288#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2289#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 2290#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 2291#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 2292#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 2293#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 2294#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 2295 2296struct hal_reo_flush_cache_status { 2297 struct hal_reo_status_hdr hdr; 2298 u32 info0; 2299 u32 rsvd0[21]; 2300 u32 info1; 2301} __packed; 2302 2303/* hal_reo_flush_cache_status 2304 * Producer: REO 2305 * Consumer: SW 2306 * 2307 * status_hdr 2308 * Details that can link this status with the original command. It 2309 * also contains info on how long REO took to execute this command. 2310 * 2311 * error_detected 2312 * Status for blocking resource handling 2313 * 2314 * 0 - No error has been detected while executing this command 2315 * 1 - An error in the blocking resource management was detected 2316 * 2317 * block_error_details 2318 * only valid when error_detected is set 2319 * 2320 * 0 - No blocking related errors found 2321 * 1 - Blocking resource is already in use 2322 * 2 - Resource requested to be unblocked, was not blocked 2323 * 2324 * cache_controller_flush_status_hit 2325 * The status that the cache controller returned on executing the 2326 * flush command. 2327 * 2328 * 0 - miss; 1 - hit 2329 * 2330 * cache_controller_flush_status_desc_type 2331 * Flush descriptor type 2332 * 2333 * cache_controller_flush_status_client_id 2334 * Module who made the flush request 2335 * 2336 * In REO, this is always 0 2337 * 2338 * cache_controller_flush_status_error 2339 * Error condition 2340 * 2341 * 0 - No error found 2342 * 1 - HW interface is still busy 2343 * 2 - Line currently locked. Used for one line flush command 2344 * 3 - At least one line is still locked. 2345 * Used for cache flush command. 2346 * 2347 * cache_controller_flush_count 2348 * The number of lines that were actually flushed out 2349 * 2350 * looping_count 2351 * A count value that indicates the number of times the producer of 2352 * entries into this Ring has looped around the ring. 2353 */ 2354 2355#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2356#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 2357 2358struct hal_reo_unblock_cache_status { 2359 struct hal_reo_status_hdr hdr; 2360 u32 info0; 2361 u32 rsvd0[21]; 2362 u32 info1; 2363} __packed; 2364 2365/* hal_reo_unblock_cache_status 2366 * Producer: REO 2367 * Consumer: SW 2368 * 2369 * status_hdr 2370 * Details that can link this status with the original command. It 2371 * also contains info on how long REO took to execute this command. 2372 * 2373 * error_detected 2374 * 0 - No error has been detected while executing this command 2375 * 1 - The blocking resource was not in use, and therefore it could 2376 * not be unblocked. 2377 * 2378 * unblock_type 2379 * Reference to the type of unblock command 2380 * 0 - Unblock a blocking resource 2381 * 1 - The entire cache usage is unblock 2382 * 2383 * looping_count 2384 * A count value that indicates the number of times the producer of 2385 * entries into this Ring has looped around the ring. 2386 */ 2387 2388#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 2389#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 2390 2391#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 2392#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 2393 2394struct hal_reo_flush_timeout_list_status { 2395 struct hal_reo_status_hdr hdr; 2396 u32 info0; 2397 u32 info1; 2398 u32 rsvd0[20]; 2399 u32 info2; 2400} __packed; 2401 2402/* hal_reo_flush_timeout_list_status 2403 * Producer: REO 2404 * Consumer: SW 2405 * 2406 * status_hdr 2407 * Details that can link this status with the original command. It 2408 * also contains info on how long REO took to execute this command. 2409 * 2410 * error_detected 2411 * 0 - No error has been detected while executing this command 2412 * 1 - Command not properly executed and returned with error 2413 * 2414 * timeout_list_empty 2415 * When set, REO has depleted the timeout list and all entries are 2416 * gone. 2417 * 2418 * release_desc_count 2419 * Producer: SW; Consumer: REO 2420 * The number of link descriptor released 2421 * 2422 * forward_buf_count 2423 * Producer: SW; Consumer: REO 2424 * The number of buffers forwarded to the REO destination rings 2425 * 2426 * looping_count 2427 * A count value that indicates the number of times the producer of 2428 * entries into this Ring has looped around the ring. 2429 */ 2430 2431#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 2432#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 2433#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 2434#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 2435#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(23, 0) 2436 2437struct hal_reo_desc_thresh_reached_status { 2438 struct hal_reo_status_hdr hdr; 2439 u32 info0; 2440 u32 info1; 2441 u32 info2; 2442 u32 info3; 2443 u32 info4; 2444 u32 rsvd0[17]; 2445 u32 info5; 2446} __packed; 2447 2448/* hal_reo_desc_thresh_reached_status 2449 * Producer: REO 2450 * Consumer: SW 2451 * 2452 * status_hdr 2453 * Details that can link this status with the original command. It 2454 * also contains info on how long REO took to execute this command. 2455 * 2456 * threshold_index 2457 * The index of the threshold register whose value got reached 2458 * 2459 * link_descriptor_counter0 2460 * link_descriptor_counter1 2461 * link_descriptor_counter2 2462 * link_descriptor_counter_sum 2463 * Value of the respective counters at generation of this message 2464 * 2465 * looping_count 2466 * A count value that indicates the number of times the producer of 2467 * entries into this Ring has looped around the ring. 2468 */ 2469 2470#endif /* ATH11K_HAL_DESC_H */ 2471