1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 */ 6 7#include <linux/etherdevice.h> 8#include "htt.h" 9#include "mac.h" 10#include "hif.h" 11#include "txrx.h" 12#include "debug.h" 13 14static u8 ath10k_htt_tx_txq_calc_size(size_t count) 15{ 16 int exp; 17 int factor; 18 19 exp = 0; 20 factor = count >> 7; 21 22 while (factor >= 64 && exp < 4) { 23 factor >>= 3; 24 exp++; 25 } 26 27 if (exp == 4) 28 return 0xff; 29 30 if (count > 0) 31 factor = max(1, factor); 32 33 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 34 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 35} 36 37static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 38 struct ieee80211_txq *txq) 39{ 40 struct ath10k *ar = hw->priv; 41 struct ath10k_sta *arsta; 42 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 43 unsigned long frame_cnt; 44 unsigned long byte_cnt; 45 int idx; 46 u32 bit; 47 u16 peer_id; 48 u8 tid; 49 u8 count; 50 51 lockdep_assert_held(&ar->htt.tx_lock); 52 53 if (!ar->htt.tx_q_state.enabled) 54 return; 55 56 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 57 return; 58 59 if (txq->sta) { 60 arsta = (void *)txq->sta->drv_priv; 61 peer_id = arsta->peer_id; 62 } else { 63 peer_id = arvif->peer_id; 64 } 65 66 tid = txq->tid; 67 bit = BIT(peer_id % 32); 68 idx = peer_id / 32; 69 70 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 71 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 72 73 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 74 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 75 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n", 76 peer_id, tid); 77 return; 78 } 79 80 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 81 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 82 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 83 84 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n", 85 peer_id, tid, count); 86} 87 88static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 89{ 90 u32 seq; 91 size_t size; 92 93 lockdep_assert_held(&ar->htt.tx_lock); 94 95 if (!ar->htt.tx_q_state.enabled) 96 return; 97 98 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 99 return; 100 101 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 102 seq++; 103 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 104 105 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 106 seq); 107 108 size = sizeof(*ar->htt.tx_q_state.vaddr); 109 dma_sync_single_for_device(ar->dev, 110 ar->htt.tx_q_state.paddr, 111 size, 112 DMA_TO_DEVICE); 113} 114 115void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 116 struct ieee80211_txq *txq) 117{ 118 struct ath10k *ar = hw->priv; 119 120 spin_lock_bh(&ar->htt.tx_lock); 121 __ath10k_htt_tx_txq_recalc(hw, txq); 122 spin_unlock_bh(&ar->htt.tx_lock); 123} 124 125void ath10k_htt_tx_txq_sync(struct ath10k *ar) 126{ 127 spin_lock_bh(&ar->htt.tx_lock); 128 __ath10k_htt_tx_txq_sync(ar); 129 spin_unlock_bh(&ar->htt.tx_lock); 130} 131 132void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 133 struct ieee80211_txq *txq) 134{ 135 struct ath10k *ar = hw->priv; 136 137 spin_lock_bh(&ar->htt.tx_lock); 138 __ath10k_htt_tx_txq_recalc(hw, txq); 139 __ath10k_htt_tx_txq_sync(ar); 140 spin_unlock_bh(&ar->htt.tx_lock); 141} 142 143void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 144{ 145 lockdep_assert_held(&htt->tx_lock); 146 147 htt->num_pending_tx--; 148 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 149 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 150 151 if (htt->num_pending_tx == 0) 152 wake_up(&htt->empty_tx_wq); 153} 154 155int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 156{ 157 lockdep_assert_held(&htt->tx_lock); 158 159 if (htt->num_pending_tx >= htt->max_num_pending_tx) 160 return -EBUSY; 161 162 htt->num_pending_tx++; 163 if (htt->num_pending_tx == htt->max_num_pending_tx) 164 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 165 166 return 0; 167} 168 169int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 170 bool is_presp) 171{ 172 struct ath10k *ar = htt->ar; 173 174 lockdep_assert_held(&htt->tx_lock); 175 176 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 177 return 0; 178 179 if (is_presp && 180 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 181 return -EBUSY; 182 183 htt->num_pending_mgmt_tx++; 184 185 return 0; 186} 187 188void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 189{ 190 lockdep_assert_held(&htt->tx_lock); 191 192 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 193 return; 194 195 htt->num_pending_mgmt_tx--; 196} 197 198int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 199{ 200 struct ath10k *ar = htt->ar; 201 int ret; 202 203 spin_lock_bh(&htt->tx_lock); 204 ret = idr_alloc(&htt->pending_tx, skb, 0, 205 htt->max_num_pending_tx, GFP_ATOMIC); 206 spin_unlock_bh(&htt->tx_lock); 207 208 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 209 210 return ret; 211} 212 213void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 214{ 215 struct ath10k *ar = htt->ar; 216 217 lockdep_assert_held(&htt->tx_lock); 218 219 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id); 220 221 idr_remove(&htt->pending_tx, msdu_id); 222} 223 224static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 225{ 226 struct ath10k *ar = htt->ar; 227 size_t size; 228 229 if (!htt->txbuf.vaddr_txbuff_32) 230 return; 231 232 size = htt->txbuf.size; 233 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 234 htt->txbuf.paddr); 235 htt->txbuf.vaddr_txbuff_32 = NULL; 236} 237 238static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 239{ 240 struct ath10k *ar = htt->ar; 241 size_t size; 242 243 size = htt->max_num_pending_tx * 244 sizeof(struct ath10k_htt_txbuf_32); 245 246 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 247 &htt->txbuf.paddr, 248 GFP_KERNEL); 249 if (!htt->txbuf.vaddr_txbuff_32) 250 return -ENOMEM; 251 252 htt->txbuf.size = size; 253 254 return 0; 255} 256 257static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 258{ 259 struct ath10k *ar = htt->ar; 260 size_t size; 261 262 if (!htt->txbuf.vaddr_txbuff_64) 263 return; 264 265 size = htt->txbuf.size; 266 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 267 htt->txbuf.paddr); 268 htt->txbuf.vaddr_txbuff_64 = NULL; 269} 270 271static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 272{ 273 struct ath10k *ar = htt->ar; 274 size_t size; 275 276 size = htt->max_num_pending_tx * 277 sizeof(struct ath10k_htt_txbuf_64); 278 279 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 280 &htt->txbuf.paddr, 281 GFP_KERNEL); 282 if (!htt->txbuf.vaddr_txbuff_64) 283 return -ENOMEM; 284 285 htt->txbuf.size = size; 286 287 return 0; 288} 289 290static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 291{ 292 size_t size; 293 294 if (!htt->frag_desc.vaddr_desc_32) 295 return; 296 297 size = htt->max_num_pending_tx * 298 sizeof(struct htt_msdu_ext_desc); 299 300 dma_free_coherent(htt->ar->dev, 301 size, 302 htt->frag_desc.vaddr_desc_32, 303 htt->frag_desc.paddr); 304 305 htt->frag_desc.vaddr_desc_32 = NULL; 306} 307 308static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 309{ 310 struct ath10k *ar = htt->ar; 311 size_t size; 312 313 if (!ar->hw_params.continuous_frag_desc) 314 return 0; 315 316 size = htt->max_num_pending_tx * 317 sizeof(struct htt_msdu_ext_desc); 318 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 319 &htt->frag_desc.paddr, 320 GFP_KERNEL); 321 if (!htt->frag_desc.vaddr_desc_32) { 322 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 323 return -ENOMEM; 324 } 325 htt->frag_desc.size = size; 326 327 return 0; 328} 329 330static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 331{ 332 size_t size; 333 334 if (!htt->frag_desc.vaddr_desc_64) 335 return; 336 337 size = htt->max_num_pending_tx * 338 sizeof(struct htt_msdu_ext_desc_64); 339 340 dma_free_coherent(htt->ar->dev, 341 size, 342 htt->frag_desc.vaddr_desc_64, 343 htt->frag_desc.paddr); 344 345 htt->frag_desc.vaddr_desc_64 = NULL; 346} 347 348static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 349{ 350 struct ath10k *ar = htt->ar; 351 size_t size; 352 353 if (!ar->hw_params.continuous_frag_desc) 354 return 0; 355 356 size = htt->max_num_pending_tx * 357 sizeof(struct htt_msdu_ext_desc_64); 358 359 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 360 &htt->frag_desc.paddr, 361 GFP_KERNEL); 362 if (!htt->frag_desc.vaddr_desc_64) { 363 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 364 return -ENOMEM; 365 } 366 htt->frag_desc.size = size; 367 368 return 0; 369} 370 371static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 372{ 373 struct ath10k *ar = htt->ar; 374 size_t size; 375 376 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 377 ar->running_fw->fw_file.fw_features)) 378 return; 379 380 size = sizeof(*htt->tx_q_state.vaddr); 381 382 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 383 kfree(htt->tx_q_state.vaddr); 384} 385 386static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 387{ 388 struct ath10k *ar = htt->ar; 389 size_t size; 390 int ret; 391 392 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 393 ar->running_fw->fw_file.fw_features)) 394 return 0; 395 396 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 397 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 398 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 399 400 size = sizeof(*htt->tx_q_state.vaddr); 401 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 402 if (!htt->tx_q_state.vaddr) 403 return -ENOMEM; 404 405 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 406 size, DMA_TO_DEVICE); 407 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 408 if (ret) { 409 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 410 kfree(htt->tx_q_state.vaddr); 411 return -EIO; 412 } 413 414 return 0; 415} 416 417static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 418{ 419 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 420 kfifo_free(&htt->txdone_fifo); 421} 422 423static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 424{ 425 int ret; 426 size_t size; 427 428 size = roundup_pow_of_two(htt->max_num_pending_tx); 429 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 430 return ret; 431} 432 433static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 434{ 435 struct ath10k *ar = htt->ar; 436 int ret; 437 438 ret = ath10k_htt_alloc_txbuff(htt); 439 if (ret) { 440 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 441 return ret; 442 } 443 444 ret = ath10k_htt_alloc_frag_desc(htt); 445 if (ret) { 446 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 447 goto free_txbuf; 448 } 449 450 ret = ath10k_htt_tx_alloc_txq(htt); 451 if (ret) { 452 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 453 goto free_frag_desc; 454 } 455 456 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 457 if (ret) { 458 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 459 goto free_txq; 460 } 461 462 return 0; 463 464free_txq: 465 ath10k_htt_tx_free_txq(htt); 466 467free_frag_desc: 468 ath10k_htt_free_frag_desc(htt); 469 470free_txbuf: 471 ath10k_htt_free_txbuff(htt); 472 473 return ret; 474} 475 476int ath10k_htt_tx_start(struct ath10k_htt *htt) 477{ 478 struct ath10k *ar = htt->ar; 479 int ret; 480 481 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 482 htt->max_num_pending_tx); 483 484 spin_lock_init(&htt->tx_lock); 485 idr_init(&htt->pending_tx); 486 487 if (htt->tx_mem_allocated) 488 return 0; 489 490 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 491 return 0; 492 493 ret = ath10k_htt_tx_alloc_buf(htt); 494 if (ret) 495 goto free_idr_pending_tx; 496 497 htt->tx_mem_allocated = true; 498 499 return 0; 500 501free_idr_pending_tx: 502 idr_destroy(&htt->pending_tx); 503 504 return ret; 505} 506 507static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 508{ 509 struct ath10k *ar = ctx; 510 struct ath10k_htt *htt = &ar->htt; 511 struct htt_tx_done tx_done = {0}; 512 513 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id); 514 515 tx_done.msdu_id = msdu_id; 516 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 517 518 ath10k_txrx_tx_unref(htt, &tx_done); 519 520 return 0; 521} 522 523void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 524{ 525 if (!htt->tx_mem_allocated) 526 return; 527 528 ath10k_htt_free_txbuff(htt); 529 ath10k_htt_tx_free_txq(htt); 530 ath10k_htt_free_frag_desc(htt); 531 ath10k_htt_tx_free_txdone_fifo(htt); 532 htt->tx_mem_allocated = false; 533} 534 535static void ath10k_htt_flush_tx_queue(struct ath10k_htt *htt) 536{ 537 ath10k_htc_stop_hl(htt->ar); 538 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 539} 540 541void ath10k_htt_tx_stop(struct ath10k_htt *htt) 542{ 543 ath10k_htt_flush_tx_queue(htt); 544 idr_destroy(&htt->pending_tx); 545} 546 547void ath10k_htt_tx_free(struct ath10k_htt *htt) 548{ 549 ath10k_htt_tx_stop(htt); 550 ath10k_htt_tx_destroy(htt); 551} 552 553void ath10k_htt_op_ep_tx_credits(struct ath10k *ar) 554{ 555 queue_work(ar->workqueue, &ar->bundle_tx_work); 556} 557 558void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 559{ 560 struct ath10k_htt *htt = &ar->htt; 561 struct htt_tx_done tx_done = {0}; 562 struct htt_cmd_hdr *htt_hdr; 563 struct htt_data_tx_desc *desc_hdr = NULL; 564 u16 flags1 = 0; 565 u8 msg_type = 0; 566 567 if (htt->disable_tx_comp) { 568 htt_hdr = (struct htt_cmd_hdr *)skb->data; 569 msg_type = htt_hdr->msg_type; 570 571 if (msg_type == HTT_H2T_MSG_TYPE_TX_FRM) { 572 desc_hdr = (struct htt_data_tx_desc *) 573 (skb->data + sizeof(*htt_hdr)); 574 flags1 = __le16_to_cpu(desc_hdr->flags1); 575 } 576 } 577 578 dev_kfree_skb_any(skb); 579 580 if ((!htt->disable_tx_comp) || (msg_type != HTT_H2T_MSG_TYPE_TX_FRM)) 581 return; 582 583 ath10k_dbg(ar, ATH10K_DBG_HTT, 584 "htt tx complete msdu id:%u ,flags1:%x\n", 585 __le16_to_cpu(desc_hdr->id), flags1); 586 587 if (flags1 & HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE) 588 return; 589 590 tx_done.status = HTT_TX_COMPL_STATE_ACK; 591 tx_done.msdu_id = __le16_to_cpu(desc_hdr->id); 592 ath10k_txrx_tx_unref(&ar->htt, &tx_done); 593} 594 595void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 596{ 597 dev_kfree_skb_any(skb); 598} 599EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 600 601int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 602{ 603 struct ath10k *ar = htt->ar; 604 struct sk_buff *skb; 605 struct htt_cmd *cmd; 606 int len = 0; 607 int ret; 608 609 len += sizeof(cmd->hdr); 610 len += sizeof(cmd->ver_req); 611 612 skb = ath10k_htc_alloc_skb(ar, len); 613 if (!skb) 614 return -ENOMEM; 615 616 skb_put(skb, len); 617 cmd = (struct htt_cmd *)skb->data; 618 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 619 620 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 621 if (ret) { 622 dev_kfree_skb_any(skb); 623 return ret; 624 } 625 626 return 0; 627} 628 629int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 630 u64 cookie) 631{ 632 struct ath10k *ar = htt->ar; 633 struct htt_stats_req *req; 634 struct sk_buff *skb; 635 struct htt_cmd *cmd; 636 int len = 0, ret; 637 638 len += sizeof(cmd->hdr); 639 len += sizeof(cmd->stats_req); 640 641 skb = ath10k_htc_alloc_skb(ar, len); 642 if (!skb) 643 return -ENOMEM; 644 645 skb_put(skb, len); 646 cmd = (struct htt_cmd *)skb->data; 647 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 648 649 req = &cmd->stats_req; 650 651 memset(req, 0, sizeof(*req)); 652 653 /* currently we support only max 24 bit masks so no need to worry 654 * about endian support 655 */ 656 memcpy(req->upload_types, &mask, 3); 657 memcpy(req->reset_types, &reset_mask, 3); 658 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 659 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 660 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 661 662 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 663 if (ret) { 664 ath10k_warn(ar, "failed to send htt type stats request: %d", 665 ret); 666 dev_kfree_skb_any(skb); 667 return ret; 668 } 669 670 return 0; 671} 672 673static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 674{ 675 struct ath10k *ar = htt->ar; 676 struct sk_buff *skb; 677 struct htt_cmd *cmd; 678 struct htt_frag_desc_bank_cfg32 *cfg; 679 int ret, size; 680 u8 info; 681 682 if (!ar->hw_params.continuous_frag_desc) 683 return 0; 684 685 if (!htt->frag_desc.paddr) { 686 ath10k_warn(ar, "invalid frag desc memory\n"); 687 return -EINVAL; 688 } 689 690 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 691 skb = ath10k_htc_alloc_skb(ar, size); 692 if (!skb) 693 return -ENOMEM; 694 695 skb_put(skb, size); 696 cmd = (struct htt_cmd *)skb->data; 697 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 698 699 info = 0; 700 info |= SM(htt->tx_q_state.type, 701 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 702 703 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 704 ar->running_fw->fw_file.fw_features)) 705 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 706 707 cfg = &cmd->frag_desc_bank_cfg32; 708 cfg->info = info; 709 cfg->num_banks = 1; 710 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 711 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 712 cfg->bank_id[0].bank_min_id = 0; 713 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 714 1); 715 716 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 717 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 718 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 719 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 720 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 721 722 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 723 724 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 725 if (ret) { 726 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 727 ret); 728 dev_kfree_skb_any(skb); 729 return ret; 730 } 731 732 return 0; 733} 734 735static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 736{ 737 struct ath10k *ar = htt->ar; 738 struct sk_buff *skb; 739 struct htt_cmd *cmd; 740 struct htt_frag_desc_bank_cfg64 *cfg; 741 int ret, size; 742 u8 info; 743 744 if (!ar->hw_params.continuous_frag_desc) 745 return 0; 746 747 if (!htt->frag_desc.paddr) { 748 ath10k_warn(ar, "invalid frag desc memory\n"); 749 return -EINVAL; 750 } 751 752 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 753 skb = ath10k_htc_alloc_skb(ar, size); 754 if (!skb) 755 return -ENOMEM; 756 757 skb_put(skb, size); 758 cmd = (struct htt_cmd *)skb->data; 759 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 760 761 info = 0; 762 info |= SM(htt->tx_q_state.type, 763 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 764 765 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 766 ar->running_fw->fw_file.fw_features)) 767 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 768 769 cfg = &cmd->frag_desc_bank_cfg64; 770 cfg->info = info; 771 cfg->num_banks = 1; 772 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 773 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 774 cfg->bank_id[0].bank_min_id = 0; 775 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 776 1); 777 778 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 779 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 780 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 781 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 782 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 783 784 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 785 786 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 787 if (ret) { 788 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 789 ret); 790 dev_kfree_skb_any(skb); 791 return ret; 792 } 793 794 return 0; 795} 796 797static void ath10k_htt_fill_rx_desc_offset_32(void *rx_ring) 798{ 799 struct htt_rx_ring_setup_ring32 *ring = 800 (struct htt_rx_ring_setup_ring32 *)rx_ring; 801 802#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 803 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 804 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 805 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 806 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 807 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 808 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 809 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 810 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 811 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 812 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 813#undef desc_offset 814} 815 816static void ath10k_htt_fill_rx_desc_offset_64(void *rx_ring) 817{ 818 struct htt_rx_ring_setup_ring64 *ring = 819 (struct htt_rx_ring_setup_ring64 *)rx_ring; 820 821#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 822 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 823 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 824 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 825 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 826 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 827 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 828 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 829 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 830 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 831 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 832#undef desc_offset 833} 834 835static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 836{ 837 struct ath10k *ar = htt->ar; 838 struct sk_buff *skb; 839 struct htt_cmd *cmd; 840 struct htt_rx_ring_setup_ring32 *ring; 841 const int num_rx_ring = 1; 842 u16 flags; 843 u32 fw_idx; 844 int len; 845 int ret; 846 847 /* 848 * the HW expects the buffer to be an integral number of 4-byte 849 * "words" 850 */ 851 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 852 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 853 854 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 855 + (sizeof(*ring) * num_rx_ring); 856 skb = ath10k_htc_alloc_skb(ar, len); 857 if (!skb) 858 return -ENOMEM; 859 860 skb_put(skb, len); 861 862 cmd = (struct htt_cmd *)skb->data; 863 ring = &cmd->rx_setup_32.rings[0]; 864 865 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 866 cmd->rx_setup_32.hdr.num_rings = 1; 867 868 /* FIXME: do we need all of this? */ 869 flags = 0; 870 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 871 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 872 flags |= HTT_RX_RING_FLAGS_PPDU_START; 873 flags |= HTT_RX_RING_FLAGS_PPDU_END; 874 flags |= HTT_RX_RING_FLAGS_MPDU_START; 875 flags |= HTT_RX_RING_FLAGS_MPDU_END; 876 flags |= HTT_RX_RING_FLAGS_MSDU_START; 877 flags |= HTT_RX_RING_FLAGS_MSDU_END; 878 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 879 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 880 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 881 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 882 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 883 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 884 flags |= HTT_RX_RING_FLAGS_NULL_RX; 885 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 886 887 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 888 889 ring->fw_idx_shadow_reg_paddr = 890 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 891 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 892 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 893 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 894 ring->flags = __cpu_to_le16(flags); 895 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 896 897 ath10k_htt_fill_rx_desc_offset_32(ring); 898 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 899 if (ret) { 900 dev_kfree_skb_any(skb); 901 return ret; 902 } 903 904 return 0; 905} 906 907static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 908{ 909 struct ath10k *ar = htt->ar; 910 struct sk_buff *skb; 911 struct htt_cmd *cmd; 912 struct htt_rx_ring_setup_ring64 *ring; 913 const int num_rx_ring = 1; 914 u16 flags; 915 u32 fw_idx; 916 int len; 917 int ret; 918 919 /* HW expects the buffer to be an integral number of 4-byte 920 * "words" 921 */ 922 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 923 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 924 925 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 926 + (sizeof(*ring) * num_rx_ring); 927 skb = ath10k_htc_alloc_skb(ar, len); 928 if (!skb) 929 return -ENOMEM; 930 931 skb_put(skb, len); 932 933 cmd = (struct htt_cmd *)skb->data; 934 ring = &cmd->rx_setup_64.rings[0]; 935 936 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 937 cmd->rx_setup_64.hdr.num_rings = 1; 938 939 flags = 0; 940 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 941 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 942 flags |= HTT_RX_RING_FLAGS_PPDU_START; 943 flags |= HTT_RX_RING_FLAGS_PPDU_END; 944 flags |= HTT_RX_RING_FLAGS_MPDU_START; 945 flags |= HTT_RX_RING_FLAGS_MPDU_END; 946 flags |= HTT_RX_RING_FLAGS_MSDU_START; 947 flags |= HTT_RX_RING_FLAGS_MSDU_END; 948 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 949 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 950 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 951 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 952 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 953 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 954 flags |= HTT_RX_RING_FLAGS_NULL_RX; 955 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 956 957 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 958 959 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 960 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 961 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 962 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 963 ring->flags = __cpu_to_le16(flags); 964 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 965 966 ath10k_htt_fill_rx_desc_offset_64(ring); 967 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 968 if (ret) { 969 dev_kfree_skb_any(skb); 970 return ret; 971 } 972 973 return 0; 974} 975 976static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt) 977{ 978 struct ath10k *ar = htt->ar; 979 struct sk_buff *skb; 980 struct htt_cmd *cmd; 981 struct htt_rx_ring_setup_ring32 *ring; 982 const int num_rx_ring = 1; 983 u16 flags; 984 int len; 985 int ret; 986 987 /* 988 * the HW expects the buffer to be an integral number of 4-byte 989 * "words" 990 */ 991 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 992 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 993 994 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 995 + (sizeof(*ring) * num_rx_ring); 996 skb = ath10k_htc_alloc_skb(ar, len); 997 if (!skb) 998 return -ENOMEM; 999 1000 skb_put(skb, len); 1001 1002 cmd = (struct htt_cmd *)skb->data; 1003 ring = &cmd->rx_setup_32.rings[0]; 1004 1005 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 1006 cmd->rx_setup_32.hdr.num_rings = 1; 1007 1008 flags = 0; 1009 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 1010 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 1011 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 1012 1013 memset(ring, 0, sizeof(*ring)); 1014 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN); 1015 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 1016 ring->flags = __cpu_to_le16(flags); 1017 1018 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1019 if (ret) { 1020 dev_kfree_skb_any(skb); 1021 return ret; 1022 } 1023 1024 return 0; 1025} 1026 1027static int ath10k_htt_h2t_aggr_cfg_msg_32(struct ath10k_htt *htt, 1028 u8 max_subfrms_ampdu, 1029 u8 max_subfrms_amsdu) 1030{ 1031 struct ath10k *ar = htt->ar; 1032 struct htt_aggr_conf *aggr_conf; 1033 struct sk_buff *skb; 1034 struct htt_cmd *cmd; 1035 int len; 1036 int ret; 1037 1038 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1039 1040 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1041 return -EINVAL; 1042 1043 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1044 return -EINVAL; 1045 1046 len = sizeof(cmd->hdr); 1047 len += sizeof(cmd->aggr_conf); 1048 1049 skb = ath10k_htc_alloc_skb(ar, len); 1050 if (!skb) 1051 return -ENOMEM; 1052 1053 skb_put(skb, len); 1054 cmd = (struct htt_cmd *)skb->data; 1055 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1056 1057 aggr_conf = &cmd->aggr_conf; 1058 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1059 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1060 1061 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1062 aggr_conf->max_num_amsdu_subframes, 1063 aggr_conf->max_num_ampdu_subframes); 1064 1065 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1066 if (ret) { 1067 dev_kfree_skb_any(skb); 1068 return ret; 1069 } 1070 1071 return 0; 1072} 1073 1074static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt, 1075 u8 max_subfrms_ampdu, 1076 u8 max_subfrms_amsdu) 1077{ 1078 struct ath10k *ar = htt->ar; 1079 struct htt_aggr_conf_v2 *aggr_conf; 1080 struct sk_buff *skb; 1081 struct htt_cmd *cmd; 1082 int len; 1083 int ret; 1084 1085 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1086 1087 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1088 return -EINVAL; 1089 1090 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1091 return -EINVAL; 1092 1093 len = sizeof(cmd->hdr); 1094 len += sizeof(cmd->aggr_conf_v2); 1095 1096 skb = ath10k_htc_alloc_skb(ar, len); 1097 if (!skb) 1098 return -ENOMEM; 1099 1100 skb_put(skb, len); 1101 cmd = (struct htt_cmd *)skb->data; 1102 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1103 1104 aggr_conf = &cmd->aggr_conf_v2; 1105 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1106 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1107 1108 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1109 aggr_conf->max_num_amsdu_subframes, 1110 aggr_conf->max_num_ampdu_subframes); 1111 1112 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1113 if (ret) { 1114 dev_kfree_skb_any(skb); 1115 return ret; 1116 } 1117 1118 return 0; 1119} 1120 1121int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1122 __le32 token, 1123 __le16 fetch_seq_num, 1124 struct htt_tx_fetch_record *records, 1125 size_t num_records) 1126{ 1127 struct sk_buff *skb; 1128 struct htt_cmd *cmd; 1129 const u16 resp_id = 0; 1130 int len = 0; 1131 int ret; 1132 1133 /* Response IDs are echo-ed back only for host driver convienence 1134 * purposes. They aren't used for anything in the driver yet so use 0. 1135 */ 1136 1137 len += sizeof(cmd->hdr); 1138 len += sizeof(cmd->tx_fetch_resp); 1139 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1140 1141 skb = ath10k_htc_alloc_skb(ar, len); 1142 if (!skb) 1143 return -ENOMEM; 1144 1145 skb_put(skb, len); 1146 cmd = (struct htt_cmd *)skb->data; 1147 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1148 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1149 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1150 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1151 cmd->tx_fetch_resp.token = token; 1152 1153 memcpy(cmd->tx_fetch_resp.records, records, 1154 sizeof(records[0]) * num_records); 1155 1156 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1157 if (ret) { 1158 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1159 goto err_free_skb; 1160 } 1161 1162 return 0; 1163 1164err_free_skb: 1165 dev_kfree_skb_any(skb); 1166 1167 return ret; 1168} 1169 1170static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1171{ 1172 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1173 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1174 struct ath10k_vif *arvif; 1175 1176 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1177 return ar->scan.vdev_id; 1178 } else if (cb->vif) { 1179 arvif = (void *)cb->vif->drv_priv; 1180 return arvif->vdev_id; 1181 } else if (ar->monitor_started) { 1182 return ar->monitor_vdev_id; 1183 } else { 1184 return 0; 1185 } 1186} 1187 1188static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1189{ 1190 struct ieee80211_hdr *hdr = (void *)skb->data; 1191 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1192 1193 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1194 return HTT_DATA_TX_EXT_TID_MGMT; 1195 else if (cb->flags & ATH10K_SKB_F_QOS) 1196 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1197 else 1198 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1199} 1200 1201int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1202{ 1203 struct ath10k *ar = htt->ar; 1204 struct device *dev = ar->dev; 1205 struct sk_buff *txdesc = NULL; 1206 struct htt_cmd *cmd; 1207 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1208 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1209 int len = 0; 1210 int msdu_id = -1; 1211 int res; 1212 const u8 *peer_addr; 1213 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1214 1215 len += sizeof(cmd->hdr); 1216 len += sizeof(cmd->mgmt_tx); 1217 1218 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1219 if (res < 0) 1220 goto err; 1221 1222 msdu_id = res; 1223 1224 if ((ieee80211_is_action(hdr->frame_control) || 1225 ieee80211_is_deauth(hdr->frame_control) || 1226 ieee80211_is_disassoc(hdr->frame_control)) && 1227 ieee80211_has_protected(hdr->frame_control)) { 1228 peer_addr = hdr->addr1; 1229 if (is_multicast_ether_addr(peer_addr)) { 1230 skb_put(msdu, sizeof(struct ieee80211_mmie_16)); 1231 } else { 1232 if (skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP || 1233 skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP_256) 1234 skb_put(msdu, IEEE80211_GCMP_MIC_LEN); 1235 else 1236 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1237 } 1238 } 1239 1240 txdesc = ath10k_htc_alloc_skb(ar, len); 1241 if (!txdesc) { 1242 res = -ENOMEM; 1243 goto err_free_msdu_id; 1244 } 1245 1246 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1247 DMA_TO_DEVICE); 1248 res = dma_mapping_error(dev, skb_cb->paddr); 1249 if (res) { 1250 res = -EIO; 1251 goto err_free_txdesc; 1252 } 1253 1254 skb_put(txdesc, len); 1255 cmd = (struct htt_cmd *)txdesc->data; 1256 memset(cmd, 0, len); 1257 1258 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1259 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1260 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1261 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1262 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1263 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1264 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1265 1266 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1267 if (res) 1268 goto err_unmap_msdu; 1269 1270 return 0; 1271 1272err_unmap_msdu: 1273 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) 1274 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1275err_free_txdesc: 1276 dev_kfree_skb_any(txdesc); 1277err_free_msdu_id: 1278 spin_lock_bh(&htt->tx_lock); 1279 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1280 spin_unlock_bh(&htt->tx_lock); 1281err: 1282 return res; 1283} 1284 1285#define HTT_TX_HL_NEEDED_HEADROOM \ 1286 (unsigned int)(sizeof(struct htt_cmd_hdr) + \ 1287 sizeof(struct htt_data_tx_desc) + \ 1288 sizeof(struct ath10k_htc_hdr)) 1289 1290static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1291 struct sk_buff *msdu) 1292{ 1293 struct ath10k *ar = htt->ar; 1294 int res, data_len; 1295 struct htt_cmd_hdr *cmd_hdr; 1296 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1297 struct htt_data_tx_desc *tx_desc; 1298 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1299 struct sk_buff *tmp_skb; 1300 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1301 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1302 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1303 u8 flags0 = 0; 1304 u16 flags1 = 0; 1305 u16 msdu_id = 0; 1306 1307 if ((ieee80211_is_action(hdr->frame_control) || 1308 ieee80211_is_deauth(hdr->frame_control) || 1309 ieee80211_is_disassoc(hdr->frame_control)) && 1310 ieee80211_has_protected(hdr->frame_control)) { 1311 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1312 } 1313 1314 data_len = msdu->len; 1315 1316 switch (txmode) { 1317 case ATH10K_HW_TXRX_RAW: 1318 case ATH10K_HW_TXRX_NATIVE_WIFI: 1319 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1320 fallthrough; 1321 case ATH10K_HW_TXRX_ETHERNET: 1322 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1323 break; 1324 case ATH10K_HW_TXRX_MGMT: 1325 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1326 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1327 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1328 1329 if (htt->disable_tx_comp) 1330 flags1 |= HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE; 1331 break; 1332 } 1333 1334 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1335 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1336 1337 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1338 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1339 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1340 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1341 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1342 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1343 } 1344 1345 /* Prepend the HTT header and TX desc struct to the data message 1346 * and realloc the skb if it does not have enough headroom. 1347 */ 1348 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) { 1349 tmp_skb = msdu; 1350 1351 ath10k_dbg(htt->ar, ATH10K_DBG_HTT, 1352 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n", 1353 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM); 1354 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM); 1355 kfree_skb(tmp_skb); 1356 if (!msdu) { 1357 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n"); 1358 res = -ENOMEM; 1359 goto out; 1360 } 1361 } 1362 1363 if (ar->bus_param.hl_msdu_ids) { 1364 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1365 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1366 if (res < 0) { 1367 ath10k_err(ar, "msdu_id allocation failed %d\n", res); 1368 goto out; 1369 } 1370 msdu_id = res; 1371 } 1372 1373 /* As msdu is freed by mac80211 (in ieee80211_tx_status()) and by 1374 * ath10k (in ath10k_htt_htc_tx_complete()) we have to increase 1375 * reference by one to avoid a use-after-free case and a double 1376 * free. 1377 */ 1378 skb_get(msdu); 1379 1380 skb_push(msdu, sizeof(*cmd_hdr)); 1381 skb_push(msdu, sizeof(*tx_desc)); 1382 cmd_hdr = (struct htt_cmd_hdr *)msdu->data; 1383 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr)); 1384 1385 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1386 tx_desc->flags0 = flags0; 1387 tx_desc->flags1 = __cpu_to_le16(flags1); 1388 tx_desc->len = __cpu_to_le16(data_len); 1389 tx_desc->id = __cpu_to_le16(msdu_id); 1390 tx_desc->frags_paddr = 0; /* always zero */ 1391 /* Initialize peer_id to INVALID_PEER because this is NOT 1392 * Reinjection path 1393 */ 1394 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID); 1395 1396 res = ath10k_htc_send_hl(&htt->ar->htc, htt->eid, msdu); 1397 1398out: 1399 return res; 1400} 1401 1402static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1403 enum ath10k_hw_txrx_mode txmode, 1404 struct sk_buff *msdu) 1405{ 1406 struct ath10k *ar = htt->ar; 1407 struct device *dev = ar->dev; 1408 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1409 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1410 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1411 struct ath10k_hif_sg_item sg_items[2]; 1412 struct ath10k_htt_txbuf_32 *txbuf; 1413 struct htt_data_tx_desc_frag *frags; 1414 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1415 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1416 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1417 int prefetch_len; 1418 int res; 1419 u8 flags0 = 0; 1420 u16 msdu_id, flags1 = 0; 1421 u16 freq = 0; 1422 u32 frags_paddr = 0; 1423 u32 txbuf_paddr; 1424 struct htt_msdu_ext_desc *ext_desc = NULL; 1425 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1426 1427 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1428 if (res < 0) 1429 goto err; 1430 1431 msdu_id = res; 1432 1433 prefetch_len = min(htt->prefetch_len, msdu->len); 1434 prefetch_len = roundup(prefetch_len, 4); 1435 1436 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1437 txbuf_paddr = htt->txbuf.paddr + 1438 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1439 1440 if ((ieee80211_is_action(hdr->frame_control) || 1441 ieee80211_is_deauth(hdr->frame_control) || 1442 ieee80211_is_disassoc(hdr->frame_control)) && 1443 ieee80211_has_protected(hdr->frame_control)) { 1444 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1445 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1446 txmode == ATH10K_HW_TXRX_RAW && 1447 ieee80211_has_protected(hdr->frame_control)) { 1448 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1449 } 1450 1451 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1452 DMA_TO_DEVICE); 1453 res = dma_mapping_error(dev, skb_cb->paddr); 1454 if (res) { 1455 res = -EIO; 1456 goto err_free_msdu_id; 1457 } 1458 1459 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1460 freq = ar->scan.roc_freq; 1461 1462 switch (txmode) { 1463 case ATH10K_HW_TXRX_RAW: 1464 case ATH10K_HW_TXRX_NATIVE_WIFI: 1465 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1466 fallthrough; 1467 case ATH10K_HW_TXRX_ETHERNET: 1468 if (ar->hw_params.continuous_frag_desc) { 1469 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1470 memset(&ext_desc_t[msdu_id], 0, 1471 sizeof(struct htt_msdu_ext_desc)); 1472 frags = (struct htt_data_tx_desc_frag *) 1473 &ext_desc_t[msdu_id].frags; 1474 ext_desc = &ext_desc_t[msdu_id]; 1475 frags[0].tword_addr.paddr_lo = 1476 __cpu_to_le32(skb_cb->paddr); 1477 frags[0].tword_addr.paddr_hi = 0; 1478 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1479 1480 frags_paddr = htt->frag_desc.paddr + 1481 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1482 } else { 1483 frags = txbuf->frags; 1484 frags[0].dword_addr.paddr = 1485 __cpu_to_le32(skb_cb->paddr); 1486 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1487 frags[1].dword_addr.paddr = 0; 1488 frags[1].dword_addr.len = 0; 1489 1490 frags_paddr = txbuf_paddr; 1491 } 1492 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1493 break; 1494 case ATH10K_HW_TXRX_MGMT: 1495 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1496 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1497 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1498 1499 frags_paddr = skb_cb->paddr; 1500 break; 1501 } 1502 1503 /* Normally all commands go through HTC which manages tx credits for 1504 * each endpoint and notifies when tx is completed. 1505 * 1506 * HTT endpoint is creditless so there's no need to care about HTC 1507 * flags. In that case it is trivial to fill the HTC header here. 1508 * 1509 * MSDU transmission is considered completed upon HTT event. This 1510 * implies no relevant resources can be freed until after the event is 1511 * received. That's why HTC tx completion handler itself is ignored by 1512 * setting NULL to transfer_context for all sg items. 1513 * 1514 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1515 * as it's a waste of resources. By bypassing HTC it is possible to 1516 * avoid extra memory allocations, compress data structures and thus 1517 * improve performance. 1518 */ 1519 1520 txbuf->htc_hdr.eid = htt->eid; 1521 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1522 sizeof(txbuf->cmd_tx) + 1523 prefetch_len); 1524 txbuf->htc_hdr.flags = 0; 1525 1526 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1527 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1528 1529 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1530 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1531 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1532 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1533 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1534 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1535 if (ar->hw_params.continuous_frag_desc) 1536 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1537 } 1538 1539 /* Prevent firmware from sending up tx inspection requests. There's 1540 * nothing ath10k can do with frames requested for inspection so force 1541 * it to simply rely a regular tx completion with discard status. 1542 */ 1543 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1544 1545 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1546 txbuf->cmd_tx.flags0 = flags0; 1547 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1548 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1549 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1550 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1551 if (ath10k_mac_tx_frm_has_freq(ar)) { 1552 txbuf->cmd_tx.offchan_tx.peerid = 1553 __cpu_to_le16(HTT_INVALID_PEERID); 1554 txbuf->cmd_tx.offchan_tx.freq = 1555 __cpu_to_le16(freq); 1556 } else { 1557 txbuf->cmd_tx.peerid = 1558 __cpu_to_le32(HTT_INVALID_PEERID); 1559 } 1560 1561 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1562 ath10k_dbg(ar, ATH10K_DBG_HTT, 1563 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", 1564 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1565 &skb_cb->paddr, vdev_id, tid, freq); 1566 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1567 msdu->data, msdu->len); 1568 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1569 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1570 1571 sg_items[0].transfer_id = 0; 1572 sg_items[0].transfer_context = NULL; 1573 sg_items[0].vaddr = &txbuf->htc_hdr; 1574 sg_items[0].paddr = txbuf_paddr + 1575 sizeof(txbuf->frags); 1576 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1577 sizeof(txbuf->cmd_hdr) + 1578 sizeof(txbuf->cmd_tx); 1579 1580 sg_items[1].transfer_id = 0; 1581 sg_items[1].transfer_context = NULL; 1582 sg_items[1].vaddr = msdu->data; 1583 sg_items[1].paddr = skb_cb->paddr; 1584 sg_items[1].len = prefetch_len; 1585 1586 res = ath10k_hif_tx_sg(htt->ar, 1587 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1588 sg_items, ARRAY_SIZE(sg_items)); 1589 if (res) 1590 goto err_unmap_msdu; 1591 1592 return 0; 1593 1594err_unmap_msdu: 1595 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1596err_free_msdu_id: 1597 spin_lock_bh(&htt->tx_lock); 1598 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1599 spin_unlock_bh(&htt->tx_lock); 1600err: 1601 return res; 1602} 1603 1604static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1605 enum ath10k_hw_txrx_mode txmode, 1606 struct sk_buff *msdu) 1607{ 1608 struct ath10k *ar = htt->ar; 1609 struct device *dev = ar->dev; 1610 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1611 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1612 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1613 struct ath10k_hif_sg_item sg_items[2]; 1614 struct ath10k_htt_txbuf_64 *txbuf; 1615 struct htt_data_tx_desc_frag *frags; 1616 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1617 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1618 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1619 int prefetch_len; 1620 int res; 1621 u8 flags0 = 0; 1622 u16 msdu_id, flags1 = 0; 1623 u16 freq = 0; 1624 dma_addr_t frags_paddr = 0; 1625 dma_addr_t txbuf_paddr; 1626 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1627 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1628 1629 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1630 if (res < 0) 1631 goto err; 1632 1633 msdu_id = res; 1634 1635 prefetch_len = min(htt->prefetch_len, msdu->len); 1636 prefetch_len = roundup(prefetch_len, 4); 1637 1638 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1639 txbuf_paddr = htt->txbuf.paddr + 1640 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1641 1642 if ((ieee80211_is_action(hdr->frame_control) || 1643 ieee80211_is_deauth(hdr->frame_control) || 1644 ieee80211_is_disassoc(hdr->frame_control)) && 1645 ieee80211_has_protected(hdr->frame_control)) { 1646 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1647 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1648 txmode == ATH10K_HW_TXRX_RAW && 1649 ieee80211_has_protected(hdr->frame_control)) { 1650 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1651 } 1652 1653 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1654 DMA_TO_DEVICE); 1655 res = dma_mapping_error(dev, skb_cb->paddr); 1656 if (res) { 1657 res = -EIO; 1658 goto err_free_msdu_id; 1659 } 1660 1661 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1662 freq = ar->scan.roc_freq; 1663 1664 switch (txmode) { 1665 case ATH10K_HW_TXRX_RAW: 1666 case ATH10K_HW_TXRX_NATIVE_WIFI: 1667 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1668 fallthrough; 1669 case ATH10K_HW_TXRX_ETHERNET: 1670 if (ar->hw_params.continuous_frag_desc) { 1671 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1672 memset(&ext_desc_t[msdu_id], 0, 1673 sizeof(struct htt_msdu_ext_desc_64)); 1674 frags = (struct htt_data_tx_desc_frag *) 1675 &ext_desc_t[msdu_id].frags; 1676 ext_desc = &ext_desc_t[msdu_id]; 1677 frags[0].tword_addr.paddr_lo = 1678 __cpu_to_le32(skb_cb->paddr); 1679 frags[0].tword_addr.paddr_hi = 1680 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1681 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1682 1683 frags_paddr = htt->frag_desc.paddr + 1684 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1685 } else { 1686 frags = txbuf->frags; 1687 frags[0].tword_addr.paddr_lo = 1688 __cpu_to_le32(skb_cb->paddr); 1689 frags[0].tword_addr.paddr_hi = 1690 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1691 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1692 frags[1].tword_addr.paddr_lo = 0; 1693 frags[1].tword_addr.paddr_hi = 0; 1694 frags[1].tword_addr.len_16 = 0; 1695 } 1696 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1697 break; 1698 case ATH10K_HW_TXRX_MGMT: 1699 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1700 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1701 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1702 1703 frags_paddr = skb_cb->paddr; 1704 break; 1705 } 1706 1707 /* Normally all commands go through HTC which manages tx credits for 1708 * each endpoint and notifies when tx is completed. 1709 * 1710 * HTT endpoint is creditless so there's no need to care about HTC 1711 * flags. In that case it is trivial to fill the HTC header here. 1712 * 1713 * MSDU transmission is considered completed upon HTT event. This 1714 * implies no relevant resources can be freed until after the event is 1715 * received. That's why HTC tx completion handler itself is ignored by 1716 * setting NULL to transfer_context for all sg items. 1717 * 1718 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1719 * as it's a waste of resources. By bypassing HTC it is possible to 1720 * avoid extra memory allocations, compress data structures and thus 1721 * improve performance. 1722 */ 1723 1724 txbuf->htc_hdr.eid = htt->eid; 1725 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1726 sizeof(txbuf->cmd_tx) + 1727 prefetch_len); 1728 txbuf->htc_hdr.flags = 0; 1729 1730 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1731 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1732 1733 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1734 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1735 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1736 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1737 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1738 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1739 if (ar->hw_params.continuous_frag_desc) { 1740 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1741 ext_desc->tso_flag[3] |= 1742 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1743 } 1744 } 1745 1746 /* Prevent firmware from sending up tx inspection requests. There's 1747 * nothing ath10k can do with frames requested for inspection so force 1748 * it to simply rely a regular tx completion with discard status. 1749 */ 1750 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1751 1752 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1753 txbuf->cmd_tx.flags0 = flags0; 1754 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1755 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1756 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1757 1758 /* fill fragment descriptor */ 1759 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1760 if (ath10k_mac_tx_frm_has_freq(ar)) { 1761 txbuf->cmd_tx.offchan_tx.peerid = 1762 __cpu_to_le16(HTT_INVALID_PEERID); 1763 txbuf->cmd_tx.offchan_tx.freq = 1764 __cpu_to_le16(freq); 1765 } else { 1766 txbuf->cmd_tx.peerid = 1767 __cpu_to_le32(HTT_INVALID_PEERID); 1768 } 1769 1770 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1771 ath10k_dbg(ar, ATH10K_DBG_HTT, 1772 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", 1773 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1774 &skb_cb->paddr, vdev_id, tid, freq); 1775 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1776 msdu->data, msdu->len); 1777 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1778 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1779 1780 sg_items[0].transfer_id = 0; 1781 sg_items[0].transfer_context = NULL; 1782 sg_items[0].vaddr = &txbuf->htc_hdr; 1783 sg_items[0].paddr = txbuf_paddr + 1784 sizeof(txbuf->frags); 1785 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1786 sizeof(txbuf->cmd_hdr) + 1787 sizeof(txbuf->cmd_tx); 1788 1789 sg_items[1].transfer_id = 0; 1790 sg_items[1].transfer_context = NULL; 1791 sg_items[1].vaddr = msdu->data; 1792 sg_items[1].paddr = skb_cb->paddr; 1793 sg_items[1].len = prefetch_len; 1794 1795 res = ath10k_hif_tx_sg(htt->ar, 1796 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1797 sg_items, ARRAY_SIZE(sg_items)); 1798 if (res) 1799 goto err_unmap_msdu; 1800 1801 return 0; 1802 1803err_unmap_msdu: 1804 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1805err_free_msdu_id: 1806 spin_lock_bh(&htt->tx_lock); 1807 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1808 spin_unlock_bh(&htt->tx_lock); 1809err: 1810 return res; 1811} 1812 1813static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1814 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1815 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1816 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1817 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1818 .htt_tx = ath10k_htt_tx_32, 1819 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1820 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1821 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1822}; 1823 1824static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1825 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1826 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1827 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1828 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1829 .htt_tx = ath10k_htt_tx_64, 1830 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1831 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1832 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2, 1833}; 1834 1835static const struct ath10k_htt_tx_ops htt_tx_ops_hl = { 1836 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl, 1837 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1838 .htt_tx = ath10k_htt_tx_hl, 1839 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1840 .htt_flush_tx = ath10k_htt_flush_tx_queue, 1841}; 1842 1843void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1844{ 1845 struct ath10k *ar = htt->ar; 1846 1847 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 1848 htt->tx_ops = &htt_tx_ops_hl; 1849 else if (ar->hw_params.target_64bit) 1850 htt->tx_ops = &htt_tx_ops_64; 1851 else 1852 htt->tx_ops = &htt_tx_ops_32; 1853} 1854