1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * FarSync WAN driver for Linux (2.6.x kernel version) 4 * 5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards 6 * 7 * Copyright (C) 2001-2004 FarSite Communications Ltd. 8 * www.farsite.co.uk 9 * 10 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> 11 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> 12 */ 13 14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/version.h> 19#include <linux/pci.h> 20#include <linux/sched.h> 21#include <linux/slab.h> 22#include <linux/ioport.h> 23#include <linux/init.h> 24#include <linux/interrupt.h> 25#include <linux/delay.h> 26#include <linux/if.h> 27#include <linux/hdlc.h> 28#include <asm/io.h> 29#include <linux/uaccess.h> 30 31#include "farsync.h" 32 33/* 34 * Module info 35 */ 36MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); 37MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); 38MODULE_LICENSE("GPL"); 39 40/* Driver configuration and global parameters 41 * ========================================== 42 */ 43 44/* Number of ports (per card) and cards supported 45 */ 46#define FST_MAX_PORTS 4 47#define FST_MAX_CARDS 32 48 49/* Default parameters for the link 50 */ 51#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is 52 * useful */ 53#define FST_TXQ_DEPTH 16 /* This one is for the buffering 54 * of frames on the way down to the card 55 * so that we can keep the card busy 56 * and maximise throughput 57 */ 58#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control 59 * network layer */ 60#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow 61 * control from network layer */ 62#define FST_MAX_MTU 8000 /* Huge but possible */ 63#define FST_DEF_MTU 1500 /* Common sane value */ 64 65#define FST_TX_TIMEOUT (2*HZ) 66 67#ifdef ARPHRD_RAWHDLC 68#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ 69#else 70#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ 71#endif 72 73/* 74 * Modules parameters and associated variables 75 */ 76static int fst_txq_low = FST_LOW_WATER_MARK; 77static int fst_txq_high = FST_HIGH_WATER_MARK; 78static int fst_max_reads = 7; 79static int fst_excluded_cards = 0; 80static int fst_excluded_list[FST_MAX_CARDS]; 81 82module_param(fst_txq_low, int, 0); 83module_param(fst_txq_high, int, 0); 84module_param(fst_max_reads, int, 0); 85module_param(fst_excluded_cards, int, 0); 86module_param_array(fst_excluded_list, int, NULL, 0); 87 88/* Card shared memory layout 89 * ========================= 90 */ 91#pragma pack(1) 92 93/* This information is derived in part from the FarSite FarSync Smc.h 94 * file. Unfortunately various name clashes and the non-portability of the 95 * bit field declarations in that file have meant that I have chosen to 96 * recreate the information here. 97 * 98 * The SMC (Shared Memory Configuration) has a version number that is 99 * incremented every time there is a significant change. This number can 100 * be used to check that we have not got out of step with the firmware 101 * contained in the .CDE files. 102 */ 103#define SMC_VERSION 24 104 105#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ 106 107#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main 108 * configuration structure */ 109#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA 110 * buffers */ 111 112#define LEN_TX_BUFFER 8192 /* Size of packet buffers */ 113#define LEN_RX_BUFFER 8192 114 115#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ 116#define LEN_SMALL_RX_BUFFER 256 117 118#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ 119#define NUM_RX_BUFFER 8 120 121/* Interrupt retry time in milliseconds */ 122#define INT_RETRY_TIME 2 123 124/* The Am186CH/CC processors support a SmartDMA mode using circular pools 125 * of buffer descriptors. The structure is almost identical to that used 126 * in the LANCE Ethernet controllers. Details available as PDF from the 127 * AMD web site: https://www.amd.com/products/epd/processors/\ 128 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf 129 */ 130struct txdesc { /* Transmit descriptor */ 131 volatile u16 ladr; /* Low order address of packet. This is a 132 * linear address in the Am186 memory space 133 */ 134 volatile u8 hadr; /* High order address. Low 4 bits only, high 4 135 * bits must be zero 136 */ 137 volatile u8 bits; /* Status and config */ 138 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. 139 * Transmit terminal count interrupt enable in 140 * top bit. 141 */ 142 u16 unused; /* Not used in Tx */ 143}; 144 145struct rxdesc { /* Receive descriptor */ 146 volatile u16 ladr; /* Low order address of packet */ 147 volatile u8 hadr; /* High order address */ 148 volatile u8 bits; /* Status and config */ 149 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. 150 * Receive terminal count interrupt enable in 151 * top bit. 152 */ 153 volatile u16 mcnt; /* Message byte count (15 bits) */ 154}; 155 156/* Convert a length into the 15 bit 2's complement */ 157/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ 158/* Since we need to set the high bit to enable the completion interrupt this 159 * can be made a lot simpler 160 */ 161#define cnv_bcnt(len) (-(len)) 162 163/* Status and config bits for the above */ 164#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ 165#define TX_STP 0x02 /* Tx: start of packet */ 166#define TX_ENP 0x01 /* Tx: end of packet */ 167#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ 168#define RX_FRAM 0x20 /* Rx: framing error */ 169#define RX_OFLO 0x10 /* Rx: overflow error */ 170#define RX_CRC 0x08 /* Rx: CRC error */ 171#define RX_HBUF 0x04 /* Rx: buffer error */ 172#define RX_STP 0x02 /* Rx: start of packet */ 173#define RX_ENP 0x01 /* Rx: end of packet */ 174 175/* Interrupts from the card are caused by various events which are presented 176 * in a circular buffer as several events may be processed on one physical int 177 */ 178#define MAX_CIRBUFF 32 179 180struct cirbuff { 181 u8 rdindex; /* read, then increment and wrap */ 182 u8 wrindex; /* write, then increment and wrap */ 183 u8 evntbuff[MAX_CIRBUFF]; 184}; 185 186/* Interrupt event codes. 187 * Where appropriate the two low order bits indicate the port number 188 */ 189#define CTLA_CHG 0x18 /* Control signal changed */ 190#define CTLB_CHG 0x19 191#define CTLC_CHG 0x1A 192#define CTLD_CHG 0x1B 193 194#define INIT_CPLT 0x20 /* Initialisation complete */ 195#define INIT_FAIL 0x21 /* Initialisation failed */ 196 197#define ABTA_SENT 0x24 /* Abort sent */ 198#define ABTB_SENT 0x25 199#define ABTC_SENT 0x26 200#define ABTD_SENT 0x27 201 202#define TXA_UNDF 0x28 /* Transmission underflow */ 203#define TXB_UNDF 0x29 204#define TXC_UNDF 0x2A 205#define TXD_UNDF 0x2B 206 207#define F56_INT 0x2C 208#define M32_INT 0x2D 209 210#define TE1_ALMA 0x30 211 212/* Port physical configuration. See farsync.h for field values */ 213struct port_cfg { 214 u16 lineInterface; /* Physical interface type */ 215 u8 x25op; /* Unused at present */ 216 u8 internalClock; /* 1 => internal clock, 0 => external */ 217 u8 transparentMode; /* 1 => on, 0 => off */ 218 u8 invertClock; /* 0 => normal, 1 => inverted */ 219 u8 padBytes[6]; /* Padding */ 220 u32 lineSpeed; /* Speed in bps */ 221}; 222 223/* TE1 port physical configuration */ 224struct su_config { 225 u32 dataRate; 226 u8 clocking; 227 u8 framing; 228 u8 structure; 229 u8 interface; 230 u8 coding; 231 u8 lineBuildOut; 232 u8 equalizer; 233 u8 transparentMode; 234 u8 loopMode; 235 u8 range; 236 u8 txBufferMode; 237 u8 rxBufferMode; 238 u8 startingSlot; 239 u8 losThreshold; 240 u8 enableIdleCode; 241 u8 idleCode; 242 u8 spare[44]; 243}; 244 245/* TE1 Status */ 246struct su_status { 247 u32 receiveBufferDelay; 248 u32 framingErrorCount; 249 u32 codeViolationCount; 250 u32 crcErrorCount; 251 u32 lineAttenuation; 252 u8 portStarted; 253 u8 lossOfSignal; 254 u8 receiveRemoteAlarm; 255 u8 alarmIndicationSignal; 256 u8 spare[40]; 257}; 258 259/* Finally sling all the above together into the shared memory structure. 260 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been 261 * evolving under NT for some time so I guess we're stuck with it. 262 * The structure starts at offset SMC_BASE. 263 * See farsync.h for some field values. 264 */ 265struct fst_shared { 266 /* DMA descriptor rings */ 267 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; 268 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; 269 270 /* Obsolete small buffers */ 271 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; 272 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; 273 274 u8 taskStatus; /* 0x00 => initialising, 0x01 => running, 275 * 0xFF => halted 276 */ 277 278 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, 279 * set to 0xEE by host to acknowledge interrupt 280 */ 281 282 u16 smcVersion; /* Must match SMC_VERSION */ 283 284 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major 285 * version, RR = revision and BB = build 286 */ 287 288 u16 txa_done; /* Obsolete completion flags */ 289 u16 rxa_done; 290 u16 txb_done; 291 u16 rxb_done; 292 u16 txc_done; 293 u16 rxc_done; 294 u16 txd_done; 295 u16 rxd_done; 296 297 u16 mailbox[4]; /* Diagnostics mailbox. Not used */ 298 299 struct cirbuff interruptEvent; /* interrupt causes */ 300 301 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ 302 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ 303 304 struct port_cfg portConfig[FST_MAX_PORTS]; 305 306 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ 307 308 u16 cableStatus; /* lsb: 0=> present, 1=> absent */ 309 310 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ 311 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ 312 313 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ 314 u16 cardMailbox[4]; /* Not used */ 315 316 /* Number of times the card thinks the host has 317 * missed an interrupt by not acknowledging 318 * within 2mS (I guess NT has problems) 319 */ 320 u32 interruptRetryCount; 321 322 /* Driver private data used as an ID. We'll not 323 * use this as I'd rather keep such things 324 * in main memory rather than on the PCI bus 325 */ 326 u32 portHandle[FST_MAX_PORTS]; 327 328 /* Count of Tx underflows for stats */ 329 u32 transmitBufferUnderflow[FST_MAX_PORTS]; 330 331 /* Debounced V.24 control input status */ 332 u32 v24DebouncedSts[FST_MAX_PORTS]; 333 334 /* Adapter debounce timers. Don't touch */ 335 u32 ctsTimer[FST_MAX_PORTS]; 336 u32 ctsTimerRun[FST_MAX_PORTS]; 337 u32 dcdTimer[FST_MAX_PORTS]; 338 u32 dcdTimerRun[FST_MAX_PORTS]; 339 340 u32 numberOfPorts; /* Number of ports detected at startup */ 341 342 u16 _reserved[64]; 343 344 u16 cardMode; /* Bit-mask to enable features: 345 * Bit 0: 1 enables LED identify mode 346 */ 347 348 u16 portScheduleOffset; 349 350 struct su_config suConfig; /* TE1 Bits */ 351 struct su_status suStatus; 352 353 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of 354 * the structure and marks the end of shared 355 * memory. Adapter code initializes it as 356 * END_SIG. 357 */ 358}; 359 360/* endOfSmcSignature value */ 361#define END_SIG 0x12345678 362 363/* Mailbox values. (portMailbox) */ 364#define NOP 0 /* No operation */ 365#define ACK 1 /* Positive acknowledgement to PC driver */ 366#define NAK 2 /* Negative acknowledgement to PC driver */ 367#define STARTPORT 3 /* Start an HDLC port */ 368#define STOPPORT 4 /* Stop an HDLC port */ 369#define ABORTTX 5 /* Abort the transmitter for a port */ 370#define SETV24O 6 /* Set V24 outputs */ 371 372/* PLX Chip Register Offsets */ 373#define CNTRL_9052 0x50 /* Control Register */ 374#define CNTRL_9054 0x6c /* Control Register */ 375 376#define INTCSR_9052 0x4c /* Interrupt control/status register */ 377#define INTCSR_9054 0x68 /* Interrupt control/status register */ 378 379/* 9054 DMA Registers */ 380/* 381 * Note that we will be using DMA Channel 0 for copying rx data 382 * and Channel 1 for copying tx data 383 */ 384#define DMAMODE0 0x80 385#define DMAPADR0 0x84 386#define DMALADR0 0x88 387#define DMASIZ0 0x8c 388#define DMADPR0 0x90 389#define DMAMODE1 0x94 390#define DMAPADR1 0x98 391#define DMALADR1 0x9c 392#define DMASIZ1 0xa0 393#define DMADPR1 0xa4 394#define DMACSR0 0xa8 395#define DMACSR1 0xa9 396#define DMAARB 0xac 397#define DMATHR 0xb0 398#define DMADAC0 0xb4 399#define DMADAC1 0xb8 400#define DMAMARBR 0xac 401 402#define FST_MIN_DMA_LEN 64 403#define FST_RX_DMA_INT 0x01 404#define FST_TX_DMA_INT 0x02 405#define FST_CARD_INT 0x04 406 407/* Larger buffers are positioned in memory at offset BFM_BASE */ 408struct buf_window { 409 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; 410 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; 411}; 412 413/* Calculate offset of a buffer object within the shared memory window */ 414#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) 415 416#pragma pack() 417 418/* Device driver private information 419 * ================================= 420 */ 421/* Per port (line or channel) information 422 */ 423struct fst_port_info { 424 struct net_device *dev; /* Device struct - must be first */ 425 struct fst_card_info *card; /* Card we're associated with */ 426 int index; /* Port index on the card */ 427 int hwif; /* Line hardware (lineInterface copy) */ 428 int run; /* Port is running */ 429 int mode; /* Normal or FarSync raw */ 430 int rxpos; /* Next Rx buffer to use */ 431 int txpos; /* Next Tx buffer to use */ 432 int txipos; /* Next Tx buffer to check for free */ 433 int start; /* Indication of start/stop to network */ 434 /* 435 * A sixteen entry transmit queue 436 */ 437 int txqs; /* index to get next buffer to tx */ 438 int txqe; /* index to queue next packet */ 439 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ 440 int rxqdepth; 441}; 442 443/* Per card information 444 */ 445struct fst_card_info { 446 char __iomem *mem; /* Card memory mapped to kernel space */ 447 char __iomem *ctlmem; /* Control memory for PCI cards */ 448 unsigned int phys_mem; /* Physical memory window address */ 449 unsigned int phys_ctlmem; /* Physical control memory address */ 450 unsigned int irq; /* Interrupt request line number */ 451 unsigned int nports; /* Number of serial ports */ 452 unsigned int type; /* Type index of card */ 453 unsigned int state; /* State of card */ 454 spinlock_t card_lock; /* Lock for SMP access */ 455 unsigned short pci_conf; /* PCI card config in I/O space */ 456 /* Per port info */ 457 struct fst_port_info ports[FST_MAX_PORTS]; 458 struct pci_dev *device; /* Information about the pci device */ 459 int card_no; /* Inst of the card on the system */ 460 int family; /* TxP or TxU */ 461 int dmarx_in_progress; 462 int dmatx_in_progress; 463 unsigned long int_count; 464 unsigned long int_time_ave; 465 void *rx_dma_handle_host; 466 dma_addr_t rx_dma_handle_card; 467 void *tx_dma_handle_host; 468 dma_addr_t tx_dma_handle_card; 469 struct sk_buff *dma_skb_rx; 470 struct fst_port_info *dma_port_rx; 471 struct fst_port_info *dma_port_tx; 472 int dma_len_rx; 473 int dma_len_tx; 474 int dma_txpos; 475 int dma_rxpos; 476}; 477 478/* Convert an HDLC device pointer into a port info pointer and similar */ 479#define dev_to_port(D) (dev_to_hdlc(D)->priv) 480#define port_to_dev(P) ((P)->dev) 481 482 483/* 484 * Shared memory window access macros 485 * 486 * We have a nice memory based structure above, which could be directly 487 * mapped on i386 but might not work on other architectures unless we use 488 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take 489 * physical offsets so we have to convert. The only saving grace is that 490 * this should all collapse back to a simple indirection eventually. 491 */ 492#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) 493 494#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) 495#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) 496#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) 497 498#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) 499#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) 500#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) 501 502/* 503 * Debug support 504 */ 505#if FST_DEBUG 506 507static int fst_debug_mask = { FST_DEBUG }; 508 509/* Most common debug activity is to print something if the corresponding bit 510 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to 511 * support variable numbers of macro parameters. The inverted if prevents us 512 * eating someone else's else clause. 513 */ 514#define dbg(F, fmt, args...) \ 515do { \ 516 if (fst_debug_mask & (F)) \ 517 printk(KERN_DEBUG pr_fmt(fmt), ##args); \ 518} while (0) 519#else 520#define dbg(F, fmt, args...) \ 521do { \ 522 if (0) \ 523 printk(KERN_DEBUG pr_fmt(fmt), ##args); \ 524} while (0) 525#endif 526 527/* 528 * PCI ID lookup table 529 */ 530static const struct pci_device_id fst_pci_dev_id[] = { 531 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, 532 PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, 533 534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, 535 PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, 536 537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, 538 PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, 539 540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, 541 PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, 542 543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, 544 PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, 545 546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, 547 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 548 549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, 550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 551 {0,} /* End */ 552}; 553 554MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); 555 556/* 557 * Device Driver Work Queues 558 * 559 * So that we don't spend too much time processing events in the 560 * Interrupt Service routine, we will declare a work queue per Card 561 * and make the ISR schedule a task in the queue for later execution. 562 * In the 2.4 Kernel we used to use the immediate queue for BH's 563 * Now that they are gone, tasklets seem to be much better than work 564 * queues. 565 */ 566 567static void do_bottom_half_tx(struct fst_card_info *card); 568static void do_bottom_half_rx(struct fst_card_info *card); 569static void fst_process_tx_work_q(unsigned long work_q); 570static void fst_process_int_work_q(unsigned long work_q); 571 572static DECLARE_TASKLET_OLD(fst_tx_task, fst_process_tx_work_q); 573static DECLARE_TASKLET_OLD(fst_int_task, fst_process_int_work_q); 574 575static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; 576static spinlock_t fst_work_q_lock; 577static u64 fst_work_txq; 578static u64 fst_work_intq; 579 580static void 581fst_q_work_item(u64 * queue, int card_index) 582{ 583 unsigned long flags; 584 u64 mask; 585 586 /* 587 * Grab the queue exclusively 588 */ 589 spin_lock_irqsave(&fst_work_q_lock, flags); 590 591 /* 592 * Making an entry in the queue is simply a matter of setting 593 * a bit for the card indicating that there is work to do in the 594 * bottom half for the card. Note the limitation of 64 cards. 595 * That ought to be enough 596 */ 597 mask = (u64)1 << card_index; 598 *queue |= mask; 599 spin_unlock_irqrestore(&fst_work_q_lock, flags); 600} 601 602static void 603fst_process_tx_work_q(unsigned long /*void **/work_q) 604{ 605 unsigned long flags; 606 u64 work_txq; 607 int i; 608 609 /* 610 * Grab the queue exclusively 611 */ 612 dbg(DBG_TX, "fst_process_tx_work_q\n"); 613 spin_lock_irqsave(&fst_work_q_lock, flags); 614 work_txq = fst_work_txq; 615 fst_work_txq = 0; 616 spin_unlock_irqrestore(&fst_work_q_lock, flags); 617 618 /* 619 * Call the bottom half for each card with work waiting 620 */ 621 for (i = 0; i < FST_MAX_CARDS; i++) { 622 if (work_txq & 0x01) { 623 if (fst_card_array[i] != NULL) { 624 dbg(DBG_TX, "Calling tx bh for card %d\n", i); 625 do_bottom_half_tx(fst_card_array[i]); 626 } 627 } 628 work_txq = work_txq >> 1; 629 } 630} 631 632static void 633fst_process_int_work_q(unsigned long /*void **/work_q) 634{ 635 unsigned long flags; 636 u64 work_intq; 637 int i; 638 639 /* 640 * Grab the queue exclusively 641 */ 642 dbg(DBG_INTR, "fst_process_int_work_q\n"); 643 spin_lock_irqsave(&fst_work_q_lock, flags); 644 work_intq = fst_work_intq; 645 fst_work_intq = 0; 646 spin_unlock_irqrestore(&fst_work_q_lock, flags); 647 648 /* 649 * Call the bottom half for each card with work waiting 650 */ 651 for (i = 0; i < FST_MAX_CARDS; i++) { 652 if (work_intq & 0x01) { 653 if (fst_card_array[i] != NULL) { 654 dbg(DBG_INTR, 655 "Calling rx & tx bh for card %d\n", i); 656 do_bottom_half_rx(fst_card_array[i]); 657 do_bottom_half_tx(fst_card_array[i]); 658 } 659 } 660 work_intq = work_intq >> 1; 661 } 662} 663 664/* Card control functions 665 * ====================== 666 */ 667/* Place the processor in reset state 668 * 669 * Used to be a simple write to card control space but a glitch in the latest 670 * AMD Am186CH processor means that we now have to do it by asserting and de- 671 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register 672 * at offset 9052_CNTRL. Note the updates for the TXU. 673 */ 674static inline void 675fst_cpureset(struct fst_card_info *card) 676{ 677 unsigned char interrupt_line_register; 678 unsigned int regval; 679 680 if (card->family == FST_FAMILY_TXU) { 681 if (pci_read_config_byte 682 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { 683 dbg(DBG_ASS, 684 "Error in reading interrupt line register\n"); 685 } 686 /* 687 * Assert PLX software reset and Am186 hardware reset 688 * and then deassert the PLX software reset but 186 still in reset 689 */ 690 outw(0x440f, card->pci_conf + CNTRL_9054 + 2); 691 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 692 /* 693 * We are delaying here to allow the 9054 to reset itself 694 */ 695 usleep_range(10, 20); 696 outw(0x240f, card->pci_conf + CNTRL_9054 + 2); 697 /* 698 * We are delaying here to allow the 9054 to reload its eeprom 699 */ 700 usleep_range(10, 20); 701 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 702 703 if (pci_write_config_byte 704 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { 705 dbg(DBG_ASS, 706 "Error in writing interrupt line register\n"); 707 } 708 709 } else { 710 regval = inl(card->pci_conf + CNTRL_9052); 711 712 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); 713 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); 714 } 715} 716 717/* Release the processor from reset 718 */ 719static inline void 720fst_cpurelease(struct fst_card_info *card) 721{ 722 if (card->family == FST_FAMILY_TXU) { 723 /* 724 * Force posted writes to complete 725 */ 726 (void) readb(card->mem); 727 728 /* 729 * Release LRESET DO = 1 730 * Then release Local Hold, DO = 1 731 */ 732 outw(0x040e, card->pci_conf + CNTRL_9054 + 2); 733 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 734 } else { 735 (void) readb(card->ctlmem); 736 } 737} 738 739/* Clear the cards interrupt flag 740 */ 741static inline void 742fst_clear_intr(struct fst_card_info *card) 743{ 744 if (card->family == FST_FAMILY_TXU) { 745 (void) readb(card->ctlmem); 746 } else { 747 /* Poke the appropriate PLX chip register (same as enabling interrupts) 748 */ 749 outw(0x0543, card->pci_conf + INTCSR_9052); 750 } 751} 752 753/* Enable card interrupts 754 */ 755static inline void 756fst_enable_intr(struct fst_card_info *card) 757{ 758 if (card->family == FST_FAMILY_TXU) { 759 outl(0x0f0c0900, card->pci_conf + INTCSR_9054); 760 } else { 761 outw(0x0543, card->pci_conf + INTCSR_9052); 762 } 763} 764 765/* Disable card interrupts 766 */ 767static inline void 768fst_disable_intr(struct fst_card_info *card) 769{ 770 if (card->family == FST_FAMILY_TXU) { 771 outl(0x00000000, card->pci_conf + INTCSR_9054); 772 } else { 773 outw(0x0000, card->pci_conf + INTCSR_9052); 774 } 775} 776 777/* Process the result of trying to pass a received frame up the stack 778 */ 779static void 780fst_process_rx_status(int rx_status, char *name) 781{ 782 switch (rx_status) { 783 case NET_RX_SUCCESS: 784 { 785 /* 786 * Nothing to do here 787 */ 788 break; 789 } 790 case NET_RX_DROP: 791 { 792 dbg(DBG_ASS, "%s: Received packet dropped\n", name); 793 break; 794 } 795 } 796} 797 798/* Initilaise DMA for PLX 9054 799 */ 800static inline void 801fst_init_dma(struct fst_card_info *card) 802{ 803 /* 804 * This is only required for the PLX 9054 805 */ 806 if (card->family == FST_FAMILY_TXU) { 807 pci_set_master(card->device); 808 outl(0x00020441, card->pci_conf + DMAMODE0); 809 outl(0x00020441, card->pci_conf + DMAMODE1); 810 outl(0x0, card->pci_conf + DMATHR); 811 } 812} 813 814/* Tx dma complete interrupt 815 */ 816static void 817fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 818 int len, int txpos) 819{ 820 struct net_device *dev = port_to_dev(port); 821 822 /* 823 * Everything is now set, just tell the card to go 824 */ 825 dbg(DBG_TX, "fst_tx_dma_complete\n"); 826 FST_WRB(card, txDescrRing[port->index][txpos].bits, 827 DMA_OWN | TX_STP | TX_ENP); 828 dev->stats.tx_packets++; 829 dev->stats.tx_bytes += len; 830 netif_trans_update(dev); 831} 832 833/* 834 * Mark it for our own raw sockets interface 835 */ 836static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) 837{ 838 skb->dev = dev; 839 skb_reset_mac_header(skb); 840 skb->pkt_type = PACKET_HOST; 841 return htons(ETH_P_CUST); 842} 843 844/* Rx dma complete interrupt 845 */ 846static void 847fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 848 int len, struct sk_buff *skb, int rxp) 849{ 850 struct net_device *dev = port_to_dev(port); 851 int pi; 852 int rx_status; 853 854 dbg(DBG_TX, "fst_rx_dma_complete\n"); 855 pi = port->index; 856 skb_put_data(skb, card->rx_dma_handle_host, len); 857 858 /* Reset buffer descriptor */ 859 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 860 861 /* Update stats */ 862 dev->stats.rx_packets++; 863 dev->stats.rx_bytes += len; 864 865 /* Push upstream */ 866 dbg(DBG_RX, "Pushing the frame up the stack\n"); 867 if (port->mode == FST_RAW) 868 skb->protocol = farsync_type_trans(skb, dev); 869 else 870 skb->protocol = hdlc_type_trans(skb, dev); 871 rx_status = netif_rx(skb); 872 fst_process_rx_status(rx_status, port_to_dev(port)->name); 873 if (rx_status == NET_RX_DROP) 874 dev->stats.rx_dropped++; 875} 876 877/* 878 * Receive a frame through the DMA 879 */ 880static inline void 881fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len) 882{ 883 /* 884 * This routine will setup the DMA and start it 885 */ 886 887 dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len); 888 if (card->dmarx_in_progress) { 889 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); 890 } 891 892 outl(dma, card->pci_conf + DMAPADR0); /* Copy to here */ 893 outl(mem, card->pci_conf + DMALADR0); /* from here */ 894 outl(len, card->pci_conf + DMASIZ0); /* for this length */ 895 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ 896 897 /* 898 * We use the dmarx_in_progress flag to flag the channel as busy 899 */ 900 card->dmarx_in_progress = 1; 901 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ 902} 903 904/* 905 * Send a frame through the DMA 906 */ 907static inline void 908fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len) 909{ 910 /* 911 * This routine will setup the DMA and start it. 912 */ 913 914 dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len); 915 if (card->dmatx_in_progress) { 916 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); 917 } 918 919 outl(dma, card->pci_conf + DMAPADR1); /* Copy from here */ 920 outl(mem, card->pci_conf + DMALADR1); /* to here */ 921 outl(len, card->pci_conf + DMASIZ1); /* for this length */ 922 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ 923 924 /* 925 * We use the dmatx_in_progress to flag the channel as busy 926 */ 927 card->dmatx_in_progress = 1; 928 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ 929} 930 931/* Issue a Mailbox command for a port. 932 * Note we issue them on a fire and forget basis, not expecting to see an 933 * error and not waiting for completion. 934 */ 935static void 936fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) 937{ 938 struct fst_card_info *card; 939 unsigned short mbval; 940 unsigned long flags; 941 int safety; 942 943 card = port->card; 944 spin_lock_irqsave(&card->card_lock, flags); 945 mbval = FST_RDW(card, portMailbox[port->index][0]); 946 947 safety = 0; 948 /* Wait for any previous command to complete */ 949 while (mbval > NAK) { 950 spin_unlock_irqrestore(&card->card_lock, flags); 951 schedule_timeout_uninterruptible(1); 952 spin_lock_irqsave(&card->card_lock, flags); 953 954 if (++safety > 2000) { 955 pr_err("Mailbox safety timeout\n"); 956 break; 957 } 958 959 mbval = FST_RDW(card, portMailbox[port->index][0]); 960 } 961 if (safety > 0) { 962 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); 963 } 964 if (mbval == NAK) { 965 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); 966 } 967 968 FST_WRW(card, portMailbox[port->index][0], cmd); 969 970 if (cmd == ABORTTX || cmd == STARTPORT) { 971 port->txpos = 0; 972 port->txipos = 0; 973 port->start = 0; 974 } 975 976 spin_unlock_irqrestore(&card->card_lock, flags); 977} 978 979/* Port output signals control 980 */ 981static inline void 982fst_op_raise(struct fst_port_info *port, unsigned int outputs) 983{ 984 outputs |= FST_RDL(port->card, v24OpSts[port->index]); 985 FST_WRL(port->card, v24OpSts[port->index], outputs); 986 987 if (port->run) 988 fst_issue_cmd(port, SETV24O); 989} 990 991static inline void 992fst_op_lower(struct fst_port_info *port, unsigned int outputs) 993{ 994 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); 995 FST_WRL(port->card, v24OpSts[port->index], outputs); 996 997 if (port->run) 998 fst_issue_cmd(port, SETV24O); 999} 1000 1001/* 1002 * Setup port Rx buffers 1003 */ 1004static void 1005fst_rx_config(struct fst_port_info *port) 1006{ 1007 int i; 1008 int pi; 1009 unsigned int offset; 1010 unsigned long flags; 1011 struct fst_card_info *card; 1012 1013 pi = port->index; 1014 card = port->card; 1015 spin_lock_irqsave(&card->card_lock, flags); 1016 for (i = 0; i < NUM_RX_BUFFER; i++) { 1017 offset = BUF_OFFSET(rxBuffer[pi][i][0]); 1018 1019 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset); 1020 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1021 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); 1022 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); 1023 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); 1024 } 1025 port->rxpos = 0; 1026 spin_unlock_irqrestore(&card->card_lock, flags); 1027} 1028 1029/* 1030 * Setup port Tx buffers 1031 */ 1032static void 1033fst_tx_config(struct fst_port_info *port) 1034{ 1035 int i; 1036 int pi; 1037 unsigned int offset; 1038 unsigned long flags; 1039 struct fst_card_info *card; 1040 1041 pi = port->index; 1042 card = port->card; 1043 spin_lock_irqsave(&card->card_lock, flags); 1044 for (i = 0; i < NUM_TX_BUFFER; i++) { 1045 offset = BUF_OFFSET(txBuffer[pi][i][0]); 1046 1047 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset); 1048 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1049 FST_WRW(card, txDescrRing[pi][i].bcnt, 0); 1050 FST_WRB(card, txDescrRing[pi][i].bits, 0); 1051 } 1052 port->txpos = 0; 1053 port->txipos = 0; 1054 port->start = 0; 1055 spin_unlock_irqrestore(&card->card_lock, flags); 1056} 1057 1058/* TE1 Alarm change interrupt event 1059 */ 1060static void 1061fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) 1062{ 1063 u8 los; 1064 u8 rra; 1065 u8 ais; 1066 1067 los = FST_RDB(card, suStatus.lossOfSignal); 1068 rra = FST_RDB(card, suStatus.receiveRemoteAlarm); 1069 ais = FST_RDB(card, suStatus.alarmIndicationSignal); 1070 1071 if (los) { 1072 /* 1073 * Lost the link 1074 */ 1075 if (netif_carrier_ok(port_to_dev(port))) { 1076 dbg(DBG_INTR, "Net carrier off\n"); 1077 netif_carrier_off(port_to_dev(port)); 1078 } 1079 } else { 1080 /* 1081 * Link available 1082 */ 1083 if (!netif_carrier_ok(port_to_dev(port))) { 1084 dbg(DBG_INTR, "Net carrier on\n"); 1085 netif_carrier_on(port_to_dev(port)); 1086 } 1087 } 1088 1089 if (los) 1090 dbg(DBG_INTR, "Assert LOS Alarm\n"); 1091 else 1092 dbg(DBG_INTR, "De-assert LOS Alarm\n"); 1093 if (rra) 1094 dbg(DBG_INTR, "Assert RRA Alarm\n"); 1095 else 1096 dbg(DBG_INTR, "De-assert RRA Alarm\n"); 1097 1098 if (ais) 1099 dbg(DBG_INTR, "Assert AIS Alarm\n"); 1100 else 1101 dbg(DBG_INTR, "De-assert AIS Alarm\n"); 1102} 1103 1104/* Control signal change interrupt event 1105 */ 1106static void 1107fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) 1108{ 1109 int signals; 1110 1111 signals = FST_RDL(card, v24DebouncedSts[port->index]); 1112 1113 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 1114 ? IPSTS_INDICATE : IPSTS_DCD)) { 1115 if (!netif_carrier_ok(port_to_dev(port))) { 1116 dbg(DBG_INTR, "DCD active\n"); 1117 netif_carrier_on(port_to_dev(port)); 1118 } 1119 } else { 1120 if (netif_carrier_ok(port_to_dev(port))) { 1121 dbg(DBG_INTR, "DCD lost\n"); 1122 netif_carrier_off(port_to_dev(port)); 1123 } 1124 } 1125} 1126 1127/* Log Rx Errors 1128 */ 1129static void 1130fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1131 unsigned char dmabits, int rxp, unsigned short len) 1132{ 1133 struct net_device *dev = port_to_dev(port); 1134 1135 /* 1136 * Increment the appropriate error counter 1137 */ 1138 dev->stats.rx_errors++; 1139 if (dmabits & RX_OFLO) { 1140 dev->stats.rx_fifo_errors++; 1141 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", 1142 card->card_no, port->index, rxp); 1143 } 1144 if (dmabits & RX_CRC) { 1145 dev->stats.rx_crc_errors++; 1146 dbg(DBG_ASS, "Rx crc error on card %d port %d\n", 1147 card->card_no, port->index); 1148 } 1149 if (dmabits & RX_FRAM) { 1150 dev->stats.rx_frame_errors++; 1151 dbg(DBG_ASS, "Rx frame error on card %d port %d\n", 1152 card->card_no, port->index); 1153 } 1154 if (dmabits == (RX_STP | RX_ENP)) { 1155 dev->stats.rx_length_errors++; 1156 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", 1157 len, card->card_no, port->index); 1158 } 1159} 1160 1161/* Rx Error Recovery 1162 */ 1163static void 1164fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1165 unsigned char dmabits, int rxp, unsigned short len) 1166{ 1167 int i; 1168 int pi; 1169 1170 pi = port->index; 1171 /* 1172 * Discard buffer descriptors until we see the start of the 1173 * next frame. Note that for long frames this could be in 1174 * a subsequent interrupt. 1175 */ 1176 i = 0; 1177 while ((dmabits & (DMA_OWN | RX_STP)) == 0) { 1178 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1179 rxp = (rxp+1) % NUM_RX_BUFFER; 1180 if (++i > NUM_RX_BUFFER) { 1181 dbg(DBG_ASS, "intr_rx: Discarding more bufs" 1182 " than we have\n"); 1183 break; 1184 } 1185 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1186 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); 1187 } 1188 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); 1189 1190 /* Discard the terminal buffer */ 1191 if (!(dmabits & DMA_OWN)) { 1192 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1193 rxp = (rxp+1) % NUM_RX_BUFFER; 1194 } 1195 port->rxpos = rxp; 1196 return; 1197 1198} 1199 1200/* Rx complete interrupt 1201 */ 1202static void 1203fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) 1204{ 1205 unsigned char dmabits; 1206 int pi; 1207 int rxp; 1208 int rx_status; 1209 unsigned short len; 1210 struct sk_buff *skb; 1211 struct net_device *dev = port_to_dev(port); 1212 1213 /* Check we have a buffer to process */ 1214 pi = port->index; 1215 rxp = port->rxpos; 1216 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1217 if (dmabits & DMA_OWN) { 1218 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", 1219 pi, rxp); 1220 return; 1221 } 1222 if (card->dmarx_in_progress) { 1223 return; 1224 } 1225 1226 /* Get buffer length */ 1227 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); 1228 /* Discard the CRC */ 1229 len -= 2; 1230 if (len == 0) { 1231 /* 1232 * This seems to happen on the TE1 interface sometimes 1233 * so throw the frame away and log the event. 1234 */ 1235 pr_err("Frame received with 0 length. Card %d Port %d\n", 1236 card->card_no, port->index); 1237 /* Return descriptor to card */ 1238 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1239 1240 rxp = (rxp+1) % NUM_RX_BUFFER; 1241 port->rxpos = rxp; 1242 return; 1243 } 1244 1245 /* Check buffer length and for other errors. We insist on one packet 1246 * in one buffer. This simplifies things greatly and since we've 1247 * allocated 8K it shouldn't be a real world limitation 1248 */ 1249 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); 1250 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { 1251 fst_log_rx_error(card, port, dmabits, rxp, len); 1252 fst_recover_rx_error(card, port, dmabits, rxp, len); 1253 return; 1254 } 1255 1256 /* Allocate SKB */ 1257 if ((skb = dev_alloc_skb(len)) == NULL) { 1258 dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); 1259 1260 dev->stats.rx_dropped++; 1261 1262 /* Return descriptor to card */ 1263 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1264 1265 rxp = (rxp+1) % NUM_RX_BUFFER; 1266 port->rxpos = rxp; 1267 return; 1268 } 1269 1270 /* 1271 * We know the length we need to receive, len. 1272 * It's not worth using the DMA for reads of less than 1273 * FST_MIN_DMA_LEN 1274 */ 1275 1276 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) { 1277 memcpy_fromio(skb_put(skb, len), 1278 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), 1279 len); 1280 1281 /* Reset buffer descriptor */ 1282 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1283 1284 /* Update stats */ 1285 dev->stats.rx_packets++; 1286 dev->stats.rx_bytes += len; 1287 1288 /* Push upstream */ 1289 dbg(DBG_RX, "Pushing frame up the stack\n"); 1290 if (port->mode == FST_RAW) 1291 skb->protocol = farsync_type_trans(skb, dev); 1292 else 1293 skb->protocol = hdlc_type_trans(skb, dev); 1294 rx_status = netif_rx(skb); 1295 fst_process_rx_status(rx_status, port_to_dev(port)->name); 1296 if (rx_status == NET_RX_DROP) 1297 dev->stats.rx_dropped++; 1298 } else { 1299 card->dma_skb_rx = skb; 1300 card->dma_port_rx = port; 1301 card->dma_len_rx = len; 1302 card->dma_rxpos = rxp; 1303 fst_rx_dma(card, card->rx_dma_handle_card, 1304 BUF_OFFSET(rxBuffer[pi][rxp][0]), len); 1305 } 1306 if (rxp != port->rxpos) { 1307 dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); 1308 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); 1309 } 1310 rxp = (rxp+1) % NUM_RX_BUFFER; 1311 port->rxpos = rxp; 1312} 1313 1314/* 1315 * The bottom halfs to the ISR 1316 * 1317 */ 1318 1319static void 1320do_bottom_half_tx(struct fst_card_info *card) 1321{ 1322 struct fst_port_info *port; 1323 int pi; 1324 int txq_length; 1325 struct sk_buff *skb; 1326 unsigned long flags; 1327 struct net_device *dev; 1328 1329 /* 1330 * Find a free buffer for the transmit 1331 * Step through each port on this card 1332 */ 1333 1334 dbg(DBG_TX, "do_bottom_half_tx\n"); 1335 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1336 if (!port->run) 1337 continue; 1338 1339 dev = port_to_dev(port); 1340 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) & 1341 DMA_OWN) && 1342 !(card->dmatx_in_progress)) { 1343 /* 1344 * There doesn't seem to be a txdone event per-se 1345 * We seem to have to deduce it, by checking the DMA_OWN 1346 * bit on the next buffer we think we can use 1347 */ 1348 spin_lock_irqsave(&card->card_lock, flags); 1349 if ((txq_length = port->txqe - port->txqs) < 0) { 1350 /* 1351 * This is the case where one has wrapped and the 1352 * maths gives us a negative number 1353 */ 1354 txq_length = txq_length + FST_TXQ_DEPTH; 1355 } 1356 spin_unlock_irqrestore(&card->card_lock, flags); 1357 if (txq_length > 0) { 1358 /* 1359 * There is something to send 1360 */ 1361 spin_lock_irqsave(&card->card_lock, flags); 1362 skb = port->txq[port->txqs]; 1363 port->txqs++; 1364 if (port->txqs == FST_TXQ_DEPTH) { 1365 port->txqs = 0; 1366 } 1367 spin_unlock_irqrestore(&card->card_lock, flags); 1368 /* 1369 * copy the data and set the required indicators on the 1370 * card. 1371 */ 1372 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, 1373 cnv_bcnt(skb->len)); 1374 if ((skb->len < FST_MIN_DMA_LEN) || 1375 (card->family == FST_FAMILY_TXP)) { 1376 /* Enqueue the packet with normal io */ 1377 memcpy_toio(card->mem + 1378 BUF_OFFSET(txBuffer[pi] 1379 [port-> 1380 txpos][0]), 1381 skb->data, skb->len); 1382 FST_WRB(card, 1383 txDescrRing[pi][port->txpos]. 1384 bits, 1385 DMA_OWN | TX_STP | TX_ENP); 1386 dev->stats.tx_packets++; 1387 dev->stats.tx_bytes += skb->len; 1388 netif_trans_update(dev); 1389 } else { 1390 /* Or do it through dma */ 1391 memcpy(card->tx_dma_handle_host, 1392 skb->data, skb->len); 1393 card->dma_port_tx = port; 1394 card->dma_len_tx = skb->len; 1395 card->dma_txpos = port->txpos; 1396 fst_tx_dma(card, 1397 card->tx_dma_handle_card, 1398 BUF_OFFSET(txBuffer[pi] 1399 [port->txpos][0]), 1400 skb->len); 1401 } 1402 if (++port->txpos >= NUM_TX_BUFFER) 1403 port->txpos = 0; 1404 /* 1405 * If we have flow control on, can we now release it? 1406 */ 1407 if (port->start) { 1408 if (txq_length < fst_txq_low) { 1409 netif_wake_queue(port_to_dev 1410 (port)); 1411 port->start = 0; 1412 } 1413 } 1414 dev_kfree_skb(skb); 1415 } else { 1416 /* 1417 * Nothing to send so break out of the while loop 1418 */ 1419 break; 1420 } 1421 } 1422 } 1423} 1424 1425static void 1426do_bottom_half_rx(struct fst_card_info *card) 1427{ 1428 struct fst_port_info *port; 1429 int pi; 1430 int rx_count = 0; 1431 1432 /* Check for rx completions on all ports on this card */ 1433 dbg(DBG_RX, "do_bottom_half_rx\n"); 1434 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1435 if (!port->run) 1436 continue; 1437 1438 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) 1439 & DMA_OWN) && !(card->dmarx_in_progress)) { 1440 if (rx_count > fst_max_reads) { 1441 /* 1442 * Don't spend forever in receive processing 1443 * Schedule another event 1444 */ 1445 fst_q_work_item(&fst_work_intq, card->card_no); 1446 tasklet_schedule(&fst_int_task); 1447 break; /* Leave the loop */ 1448 } 1449 fst_intr_rx(card, port); 1450 rx_count++; 1451 } 1452 } 1453} 1454 1455/* 1456 * The interrupt service routine 1457 * Dev_id is our fst_card_info pointer 1458 */ 1459static irqreturn_t 1460fst_intr(int dummy, void *dev_id) 1461{ 1462 struct fst_card_info *card = dev_id; 1463 struct fst_port_info *port; 1464 int rdidx; /* Event buffer indices */ 1465 int wridx; 1466 int event; /* Actual event for processing */ 1467 unsigned int dma_intcsr = 0; 1468 unsigned int do_card_interrupt; 1469 unsigned int int_retry_count; 1470 1471 /* 1472 * Check to see if the interrupt was for this card 1473 * return if not 1474 * Note that the call to clear the interrupt is important 1475 */ 1476 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); 1477 if (card->state != FST_RUNNING) { 1478 pr_err("Interrupt received for card %d in a non running state (%d)\n", 1479 card->card_no, card->state); 1480 1481 /* 1482 * It is possible to really be running, i.e. we have re-loaded 1483 * a running card 1484 * Clear and reprime the interrupt source 1485 */ 1486 fst_clear_intr(card); 1487 return IRQ_HANDLED; 1488 } 1489 1490 /* Clear and reprime the interrupt source */ 1491 fst_clear_intr(card); 1492 1493 /* 1494 * Is the interrupt for this card (handshake == 1) 1495 */ 1496 do_card_interrupt = 0; 1497 if (FST_RDB(card, interruptHandshake) == 1) { 1498 do_card_interrupt += FST_CARD_INT; 1499 /* Set the software acknowledge */ 1500 FST_WRB(card, interruptHandshake, 0xEE); 1501 } 1502 if (card->family == FST_FAMILY_TXU) { 1503 /* 1504 * Is it a DMA Interrupt 1505 */ 1506 dma_intcsr = inl(card->pci_conf + INTCSR_9054); 1507 if (dma_intcsr & 0x00200000) { 1508 /* 1509 * DMA Channel 0 (Rx transfer complete) 1510 */ 1511 dbg(DBG_RX, "DMA Rx xfer complete\n"); 1512 outb(0x8, card->pci_conf + DMACSR0); 1513 fst_rx_dma_complete(card, card->dma_port_rx, 1514 card->dma_len_rx, card->dma_skb_rx, 1515 card->dma_rxpos); 1516 card->dmarx_in_progress = 0; 1517 do_card_interrupt += FST_RX_DMA_INT; 1518 } 1519 if (dma_intcsr & 0x00400000) { 1520 /* 1521 * DMA Channel 1 (Tx transfer complete) 1522 */ 1523 dbg(DBG_TX, "DMA Tx xfer complete\n"); 1524 outb(0x8, card->pci_conf + DMACSR1); 1525 fst_tx_dma_complete(card, card->dma_port_tx, 1526 card->dma_len_tx, card->dma_txpos); 1527 card->dmatx_in_progress = 0; 1528 do_card_interrupt += FST_TX_DMA_INT; 1529 } 1530 } 1531 1532 /* 1533 * Have we been missing Interrupts 1534 */ 1535 int_retry_count = FST_RDL(card, interruptRetryCount); 1536 if (int_retry_count) { 1537 dbg(DBG_ASS, "Card %d int_retry_count is %d\n", 1538 card->card_no, int_retry_count); 1539 FST_WRL(card, interruptRetryCount, 0); 1540 } 1541 1542 if (!do_card_interrupt) { 1543 return IRQ_HANDLED; 1544 } 1545 1546 /* Scehdule the bottom half of the ISR */ 1547 fst_q_work_item(&fst_work_intq, card->card_no); 1548 tasklet_schedule(&fst_int_task); 1549 1550 /* Drain the event queue */ 1551 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; 1552 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; 1553 while (rdidx != wridx) { 1554 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); 1555 port = &card->ports[event & 0x03]; 1556 1557 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); 1558 1559 switch (event) { 1560 case TE1_ALMA: 1561 dbg(DBG_INTR, "TE1 Alarm intr\n"); 1562 if (port->run) 1563 fst_intr_te1_alarm(card, port); 1564 break; 1565 1566 case CTLA_CHG: 1567 case CTLB_CHG: 1568 case CTLC_CHG: 1569 case CTLD_CHG: 1570 if (port->run) 1571 fst_intr_ctlchg(card, port); 1572 break; 1573 1574 case ABTA_SENT: 1575 case ABTB_SENT: 1576 case ABTC_SENT: 1577 case ABTD_SENT: 1578 dbg(DBG_TX, "Abort complete port %d\n", port->index); 1579 break; 1580 1581 case TXA_UNDF: 1582 case TXB_UNDF: 1583 case TXC_UNDF: 1584 case TXD_UNDF: 1585 /* Difficult to see how we'd get this given that we 1586 * always load up the entire packet for DMA. 1587 */ 1588 dbg(DBG_TX, "Tx underflow port %d\n", port->index); 1589 port_to_dev(port)->stats.tx_errors++; 1590 port_to_dev(port)->stats.tx_fifo_errors++; 1591 dbg(DBG_ASS, "Tx underflow on card %d port %d\n", 1592 card->card_no, port->index); 1593 break; 1594 1595 case INIT_CPLT: 1596 dbg(DBG_INIT, "Card init OK intr\n"); 1597 break; 1598 1599 case INIT_FAIL: 1600 dbg(DBG_INIT, "Card init FAILED intr\n"); 1601 card->state = FST_IFAILED; 1602 break; 1603 1604 default: 1605 pr_err("intr: unknown card event %d. ignored\n", event); 1606 break; 1607 } 1608 1609 /* Bump and wrap the index */ 1610 if (++rdidx >= MAX_CIRBUFF) 1611 rdidx = 0; 1612 } 1613 FST_WRB(card, interruptEvent.rdindex, rdidx); 1614 return IRQ_HANDLED; 1615} 1616 1617/* Check that the shared memory configuration is one that we can handle 1618 * and that some basic parameters are correct 1619 */ 1620static void 1621check_started_ok(struct fst_card_info *card) 1622{ 1623 int i; 1624 1625 /* Check structure version and end marker */ 1626 if (FST_RDW(card, smcVersion) != SMC_VERSION) { 1627 pr_err("Bad shared memory version %d expected %d\n", 1628 FST_RDW(card, smcVersion), SMC_VERSION); 1629 card->state = FST_BADVERSION; 1630 return; 1631 } 1632 if (FST_RDL(card, endOfSmcSignature) != END_SIG) { 1633 pr_err("Missing shared memory signature\n"); 1634 card->state = FST_BADVERSION; 1635 return; 1636 } 1637 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ 1638 if ((i = FST_RDB(card, taskStatus)) == 0x01) { 1639 card->state = FST_RUNNING; 1640 } else if (i == 0xFF) { 1641 pr_err("Firmware initialisation failed. Card halted\n"); 1642 card->state = FST_HALTED; 1643 return; 1644 } else if (i != 0x00) { 1645 pr_err("Unknown firmware status 0x%x\n", i); 1646 card->state = FST_HALTED; 1647 return; 1648 } 1649 1650 /* Finally check the number of ports reported by firmware against the 1651 * number we assumed at card detection. Should never happen with 1652 * existing firmware etc so we just report it for the moment. 1653 */ 1654 if (FST_RDL(card, numberOfPorts) != card->nports) { 1655 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n", 1656 card->card_no, 1657 FST_RDL(card, numberOfPorts), card->nports); 1658 } 1659} 1660 1661static int 1662set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, 1663 struct fstioc_info *info) 1664{ 1665 int err; 1666 unsigned char my_framing; 1667 1668 /* Set things according to the user set valid flags 1669 * Several of the old options have been invalidated/replaced by the 1670 * generic hdlc package. 1671 */ 1672 err = 0; 1673 if (info->valid & FSTVAL_PROTO) { 1674 if (info->proto == FST_RAW) 1675 port->mode = FST_RAW; 1676 else 1677 port->mode = FST_GEN_HDLC; 1678 } 1679 1680 if (info->valid & FSTVAL_CABLE) 1681 err = -EINVAL; 1682 1683 if (info->valid & FSTVAL_SPEED) 1684 err = -EINVAL; 1685 1686 if (info->valid & FSTVAL_PHASE) 1687 FST_WRB(card, portConfig[port->index].invertClock, 1688 info->invertClock); 1689 if (info->valid & FSTVAL_MODE) 1690 FST_WRW(card, cardMode, info->cardMode); 1691 if (info->valid & FSTVAL_TE1) { 1692 FST_WRL(card, suConfig.dataRate, info->lineSpeed); 1693 FST_WRB(card, suConfig.clocking, info->clockSource); 1694 my_framing = FRAMING_E1; 1695 if (info->framing == E1) 1696 my_framing = FRAMING_E1; 1697 if (info->framing == T1) 1698 my_framing = FRAMING_T1; 1699 if (info->framing == J1) 1700 my_framing = FRAMING_J1; 1701 FST_WRB(card, suConfig.framing, my_framing); 1702 FST_WRB(card, suConfig.structure, info->structure); 1703 FST_WRB(card, suConfig.interface, info->interface); 1704 FST_WRB(card, suConfig.coding, info->coding); 1705 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); 1706 FST_WRB(card, suConfig.equalizer, info->equalizer); 1707 FST_WRB(card, suConfig.transparentMode, info->transparentMode); 1708 FST_WRB(card, suConfig.loopMode, info->loopMode); 1709 FST_WRB(card, suConfig.range, info->range); 1710 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); 1711 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); 1712 FST_WRB(card, suConfig.startingSlot, info->startingSlot); 1713 FST_WRB(card, suConfig.losThreshold, info->losThreshold); 1714 if (info->idleCode) 1715 FST_WRB(card, suConfig.enableIdleCode, 1); 1716 else 1717 FST_WRB(card, suConfig.enableIdleCode, 0); 1718 FST_WRB(card, suConfig.idleCode, info->idleCode); 1719#if FST_DEBUG 1720 if (info->valid & FSTVAL_TE1) { 1721 printk("Setting TE1 data\n"); 1722 printk("Line Speed = %d\n", info->lineSpeed); 1723 printk("Start slot = %d\n", info->startingSlot); 1724 printk("Clock source = %d\n", info->clockSource); 1725 printk("Framing = %d\n", my_framing); 1726 printk("Structure = %d\n", info->structure); 1727 printk("interface = %d\n", info->interface); 1728 printk("Coding = %d\n", info->coding); 1729 printk("Line build out = %d\n", info->lineBuildOut); 1730 printk("Equaliser = %d\n", info->equalizer); 1731 printk("Transparent mode = %d\n", 1732 info->transparentMode); 1733 printk("Loop mode = %d\n", info->loopMode); 1734 printk("Range = %d\n", info->range); 1735 printk("Tx Buffer mode = %d\n", info->txBufferMode); 1736 printk("Rx Buffer mode = %d\n", info->rxBufferMode); 1737 printk("LOS Threshold = %d\n", info->losThreshold); 1738 printk("Idle Code = %d\n", info->idleCode); 1739 } 1740#endif 1741 } 1742#if FST_DEBUG 1743 if (info->valid & FSTVAL_DEBUG) { 1744 fst_debug_mask = info->debug; 1745 } 1746#endif 1747 1748 return err; 1749} 1750 1751static void 1752gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, 1753 struct fstioc_info *info) 1754{ 1755 int i; 1756 1757 memset(info, 0, sizeof (struct fstioc_info)); 1758 1759 i = port->index; 1760 info->kernelVersion = LINUX_VERSION_CODE; 1761 info->nports = card->nports; 1762 info->type = card->type; 1763 info->state = card->state; 1764 info->proto = FST_GEN_HDLC; 1765 info->index = i; 1766#if FST_DEBUG 1767 info->debug = fst_debug_mask; 1768#endif 1769 1770 /* Only mark information as valid if card is running. 1771 * Copy the data anyway in case it is useful for diagnostics 1772 */ 1773 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) 1774#if FST_DEBUG 1775 | FSTVAL_DEBUG 1776#endif 1777 ; 1778 1779 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); 1780 info->internalClock = FST_RDB(card, portConfig[i].internalClock); 1781 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); 1782 info->invertClock = FST_RDB(card, portConfig[i].invertClock); 1783 info->v24IpSts = FST_RDL(card, v24IpSts[i]); 1784 info->v24OpSts = FST_RDL(card, v24OpSts[i]); 1785 info->clockStatus = FST_RDW(card, clockStatus[i]); 1786 info->cableStatus = FST_RDW(card, cableStatus); 1787 info->cardMode = FST_RDW(card, cardMode); 1788 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); 1789 1790 /* 1791 * The T2U can report cable presence for both A or B 1792 * in bits 0 and 1 of cableStatus. See which port we are and 1793 * do the mapping. 1794 */ 1795 if (card->family == FST_FAMILY_TXU) { 1796 if (port->index == 0) { 1797 /* 1798 * Port A 1799 */ 1800 info->cableStatus = info->cableStatus & 1; 1801 } else { 1802 /* 1803 * Port B 1804 */ 1805 info->cableStatus = info->cableStatus >> 1; 1806 info->cableStatus = info->cableStatus & 1; 1807 } 1808 } 1809 /* 1810 * Some additional bits if we are TE1 1811 */ 1812 if (card->type == FST_TYPE_TE1) { 1813 info->lineSpeed = FST_RDL(card, suConfig.dataRate); 1814 info->clockSource = FST_RDB(card, suConfig.clocking); 1815 info->framing = FST_RDB(card, suConfig.framing); 1816 info->structure = FST_RDB(card, suConfig.structure); 1817 info->interface = FST_RDB(card, suConfig.interface); 1818 info->coding = FST_RDB(card, suConfig.coding); 1819 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); 1820 info->equalizer = FST_RDB(card, suConfig.equalizer); 1821 info->loopMode = FST_RDB(card, suConfig.loopMode); 1822 info->range = FST_RDB(card, suConfig.range); 1823 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); 1824 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); 1825 info->startingSlot = FST_RDB(card, suConfig.startingSlot); 1826 info->losThreshold = FST_RDB(card, suConfig.losThreshold); 1827 if (FST_RDB(card, suConfig.enableIdleCode)) 1828 info->idleCode = FST_RDB(card, suConfig.idleCode); 1829 else 1830 info->idleCode = 0; 1831 info->receiveBufferDelay = 1832 FST_RDL(card, suStatus.receiveBufferDelay); 1833 info->framingErrorCount = 1834 FST_RDL(card, suStatus.framingErrorCount); 1835 info->codeViolationCount = 1836 FST_RDL(card, suStatus.codeViolationCount); 1837 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); 1838 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); 1839 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); 1840 info->receiveRemoteAlarm = 1841 FST_RDB(card, suStatus.receiveRemoteAlarm); 1842 info->alarmIndicationSignal = 1843 FST_RDB(card, suStatus.alarmIndicationSignal); 1844 } 1845} 1846 1847static int 1848fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, 1849 struct ifreq *ifr) 1850{ 1851 sync_serial_settings sync; 1852 int i; 1853 1854 if (ifr->ifr_settings.size != sizeof (sync)) { 1855 return -ENOMEM; 1856 } 1857 1858 if (copy_from_user 1859 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) { 1860 return -EFAULT; 1861 } 1862 1863 if (sync.loopback) 1864 return -EINVAL; 1865 1866 i = port->index; 1867 1868 switch (ifr->ifr_settings.type) { 1869 case IF_IFACE_V35: 1870 FST_WRW(card, portConfig[i].lineInterface, V35); 1871 port->hwif = V35; 1872 break; 1873 1874 case IF_IFACE_V24: 1875 FST_WRW(card, portConfig[i].lineInterface, V24); 1876 port->hwif = V24; 1877 break; 1878 1879 case IF_IFACE_X21: 1880 FST_WRW(card, portConfig[i].lineInterface, X21); 1881 port->hwif = X21; 1882 break; 1883 1884 case IF_IFACE_X21D: 1885 FST_WRW(card, portConfig[i].lineInterface, X21D); 1886 port->hwif = X21D; 1887 break; 1888 1889 case IF_IFACE_T1: 1890 FST_WRW(card, portConfig[i].lineInterface, T1); 1891 port->hwif = T1; 1892 break; 1893 1894 case IF_IFACE_E1: 1895 FST_WRW(card, portConfig[i].lineInterface, E1); 1896 port->hwif = E1; 1897 break; 1898 1899 case IF_IFACE_SYNC_SERIAL: 1900 break; 1901 1902 default: 1903 return -EINVAL; 1904 } 1905 1906 switch (sync.clock_type) { 1907 case CLOCK_EXT: 1908 FST_WRB(card, portConfig[i].internalClock, EXTCLK); 1909 break; 1910 1911 case CLOCK_INT: 1912 FST_WRB(card, portConfig[i].internalClock, INTCLK); 1913 break; 1914 1915 default: 1916 return -EINVAL; 1917 } 1918 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); 1919 return 0; 1920} 1921 1922static int 1923fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, 1924 struct ifreq *ifr) 1925{ 1926 sync_serial_settings sync; 1927 int i; 1928 1929 /* First check what line type is set, we'll default to reporting X.21 1930 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be 1931 * changed 1932 */ 1933 switch (port->hwif) { 1934 case E1: 1935 ifr->ifr_settings.type = IF_IFACE_E1; 1936 break; 1937 case T1: 1938 ifr->ifr_settings.type = IF_IFACE_T1; 1939 break; 1940 case V35: 1941 ifr->ifr_settings.type = IF_IFACE_V35; 1942 break; 1943 case V24: 1944 ifr->ifr_settings.type = IF_IFACE_V24; 1945 break; 1946 case X21D: 1947 ifr->ifr_settings.type = IF_IFACE_X21D; 1948 break; 1949 case X21: 1950 default: 1951 ifr->ifr_settings.type = IF_IFACE_X21; 1952 break; 1953 } 1954 if (ifr->ifr_settings.size == 0) { 1955 return 0; /* only type requested */ 1956 } 1957 if (ifr->ifr_settings.size < sizeof (sync)) { 1958 return -ENOMEM; 1959 } 1960 1961 i = port->index; 1962 memset(&sync, 0, sizeof(sync)); 1963 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); 1964 /* Lucky card and linux use same encoding here */ 1965 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == 1966 INTCLK ? CLOCK_INT : CLOCK_EXT; 1967 sync.loopback = 0; 1968 1969 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) { 1970 return -EFAULT; 1971 } 1972 1973 ifr->ifr_settings.size = sizeof (sync); 1974 return 0; 1975} 1976 1977static int 1978fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1979{ 1980 struct fst_card_info *card; 1981 struct fst_port_info *port; 1982 struct fstioc_write wrthdr; 1983 struct fstioc_info info; 1984 unsigned long flags; 1985 void *buf; 1986 1987 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data); 1988 1989 port = dev_to_port(dev); 1990 card = port->card; 1991 1992 if (!capable(CAP_NET_ADMIN)) 1993 return -EPERM; 1994 1995 switch (cmd) { 1996 case FSTCPURESET: 1997 fst_cpureset(card); 1998 card->state = FST_RESET; 1999 return 0; 2000 2001 case FSTCPURELEASE: 2002 fst_cpurelease(card); 2003 card->state = FST_STARTING; 2004 return 0; 2005 2006 case FSTWRITE: /* Code write (download) */ 2007 2008 /* First copy in the header with the length and offset of data 2009 * to write 2010 */ 2011 if (ifr->ifr_data == NULL) { 2012 return -EINVAL; 2013 } 2014 if (copy_from_user(&wrthdr, ifr->ifr_data, 2015 sizeof (struct fstioc_write))) { 2016 return -EFAULT; 2017 } 2018 2019 /* Sanity check the parameters. We don't support partial writes 2020 * when going over the top 2021 */ 2022 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE || 2023 wrthdr.size + wrthdr.offset > FST_MEMSIZE) { 2024 return -ENXIO; 2025 } 2026 2027 /* Now copy the data to the card. */ 2028 2029 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write), 2030 wrthdr.size); 2031 if (IS_ERR(buf)) 2032 return PTR_ERR(buf); 2033 2034 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); 2035 kfree(buf); 2036 2037 /* Writes to the memory of a card in the reset state constitute 2038 * a download 2039 */ 2040 if (card->state == FST_RESET) { 2041 card->state = FST_DOWNLOAD; 2042 } 2043 return 0; 2044 2045 case FSTGETCONF: 2046 2047 /* If card has just been started check the shared memory config 2048 * version and marker 2049 */ 2050 if (card->state == FST_STARTING) { 2051 check_started_ok(card); 2052 2053 /* If everything checked out enable card interrupts */ 2054 if (card->state == FST_RUNNING) { 2055 spin_lock_irqsave(&card->card_lock, flags); 2056 fst_enable_intr(card); 2057 FST_WRB(card, interruptHandshake, 0xEE); 2058 spin_unlock_irqrestore(&card->card_lock, flags); 2059 } 2060 } 2061 2062 if (ifr->ifr_data == NULL) { 2063 return -EINVAL; 2064 } 2065 2066 gather_conf_info(card, port, &info); 2067 2068 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) { 2069 return -EFAULT; 2070 } 2071 return 0; 2072 2073 case FSTSETCONF: 2074 2075 /* 2076 * Most of the settings have been moved to the generic ioctls 2077 * this just covers debug and board ident now 2078 */ 2079 2080 if (card->state != FST_RUNNING) { 2081 pr_err("Attempt to configure card %d in non-running state (%d)\n", 2082 card->card_no, card->state); 2083 return -EIO; 2084 } 2085 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) { 2086 return -EFAULT; 2087 } 2088 2089 return set_conf_from_info(card, port, &info); 2090 2091 case SIOCWANDEV: 2092 switch (ifr->ifr_settings.type) { 2093 case IF_GET_IFACE: 2094 return fst_get_iface(card, port, ifr); 2095 2096 case IF_IFACE_SYNC_SERIAL: 2097 case IF_IFACE_V35: 2098 case IF_IFACE_V24: 2099 case IF_IFACE_X21: 2100 case IF_IFACE_X21D: 2101 case IF_IFACE_T1: 2102 case IF_IFACE_E1: 2103 return fst_set_iface(card, port, ifr); 2104 2105 case IF_PROTO_RAW: 2106 port->mode = FST_RAW; 2107 return 0; 2108 2109 case IF_GET_PROTO: 2110 if (port->mode == FST_RAW) { 2111 ifr->ifr_settings.type = IF_PROTO_RAW; 2112 return 0; 2113 } 2114 return hdlc_ioctl(dev, ifr, cmd); 2115 2116 default: 2117 port->mode = FST_GEN_HDLC; 2118 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", 2119 ifr->ifr_settings.type); 2120 return hdlc_ioctl(dev, ifr, cmd); 2121 } 2122 2123 default: 2124 /* Not one of ours. Pass through to HDLC package */ 2125 return hdlc_ioctl(dev, ifr, cmd); 2126 } 2127} 2128 2129static void 2130fst_openport(struct fst_port_info *port) 2131{ 2132 int signals; 2133 2134 /* Only init things if card is actually running. This allows open to 2135 * succeed for downloads etc. 2136 */ 2137 if (port->card->state == FST_RUNNING) { 2138 if (port->run) { 2139 dbg(DBG_OPEN, "open: found port already running\n"); 2140 2141 fst_issue_cmd(port, STOPPORT); 2142 port->run = 0; 2143 } 2144 2145 fst_rx_config(port); 2146 fst_tx_config(port); 2147 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); 2148 2149 fst_issue_cmd(port, STARTPORT); 2150 port->run = 1; 2151 2152 signals = FST_RDL(port->card, v24DebouncedSts[port->index]); 2153 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 2154 ? IPSTS_INDICATE : IPSTS_DCD)) 2155 netif_carrier_on(port_to_dev(port)); 2156 else 2157 netif_carrier_off(port_to_dev(port)); 2158 2159 port->txqe = 0; 2160 port->txqs = 0; 2161 } 2162 2163} 2164 2165static void 2166fst_closeport(struct fst_port_info *port) 2167{ 2168 if (port->card->state == FST_RUNNING) { 2169 if (port->run) { 2170 port->run = 0; 2171 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); 2172 2173 fst_issue_cmd(port, STOPPORT); 2174 } else { 2175 dbg(DBG_OPEN, "close: port not running\n"); 2176 } 2177 } 2178} 2179 2180static int 2181fst_open(struct net_device *dev) 2182{ 2183 int err; 2184 struct fst_port_info *port; 2185 2186 port = dev_to_port(dev); 2187 if (!try_module_get(THIS_MODULE)) 2188 return -EBUSY; 2189 2190 if (port->mode != FST_RAW) { 2191 err = hdlc_open(dev); 2192 if (err) { 2193 module_put(THIS_MODULE); 2194 return err; 2195 } 2196 } 2197 2198 fst_openport(port); 2199 netif_wake_queue(dev); 2200 return 0; 2201} 2202 2203static int 2204fst_close(struct net_device *dev) 2205{ 2206 struct fst_port_info *port; 2207 struct fst_card_info *card; 2208 unsigned char tx_dma_done; 2209 unsigned char rx_dma_done; 2210 2211 port = dev_to_port(dev); 2212 card = port->card; 2213 2214 tx_dma_done = inb(card->pci_conf + DMACSR1); 2215 rx_dma_done = inb(card->pci_conf + DMACSR0); 2216 dbg(DBG_OPEN, 2217 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", 2218 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, 2219 rx_dma_done); 2220 2221 netif_stop_queue(dev); 2222 fst_closeport(dev_to_port(dev)); 2223 if (port->mode != FST_RAW) { 2224 hdlc_close(dev); 2225 } 2226 module_put(THIS_MODULE); 2227 return 0; 2228} 2229 2230static int 2231fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) 2232{ 2233 /* 2234 * Setting currently fixed in FarSync card so we check and forget 2235 */ 2236 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) 2237 return -EINVAL; 2238 return 0; 2239} 2240 2241static void 2242fst_tx_timeout(struct net_device *dev, unsigned int txqueue) 2243{ 2244 struct fst_port_info *port; 2245 struct fst_card_info *card; 2246 2247 port = dev_to_port(dev); 2248 card = port->card; 2249 dev->stats.tx_errors++; 2250 dev->stats.tx_aborted_errors++; 2251 dbg(DBG_ASS, "Tx timeout card %d port %d\n", 2252 card->card_no, port->index); 2253 fst_issue_cmd(port, ABORTTX); 2254 2255 netif_trans_update(dev); 2256 netif_wake_queue(dev); 2257 port->start = 0; 2258} 2259 2260static netdev_tx_t 2261fst_start_xmit(struct sk_buff *skb, struct net_device *dev) 2262{ 2263 struct fst_card_info *card; 2264 struct fst_port_info *port; 2265 unsigned long flags; 2266 int txq_length; 2267 2268 port = dev_to_port(dev); 2269 card = port->card; 2270 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); 2271 2272 /* Drop packet with error if we don't have carrier */ 2273 if (!netif_carrier_ok(dev)) { 2274 dev_kfree_skb(skb); 2275 dev->stats.tx_errors++; 2276 dev->stats.tx_carrier_errors++; 2277 dbg(DBG_ASS, 2278 "Tried to transmit but no carrier on card %d port %d\n", 2279 card->card_no, port->index); 2280 return NETDEV_TX_OK; 2281 } 2282 2283 /* Drop it if it's too big! MTU failure ? */ 2284 if (skb->len > LEN_TX_BUFFER) { 2285 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, 2286 LEN_TX_BUFFER); 2287 dev_kfree_skb(skb); 2288 dev->stats.tx_errors++; 2289 return NETDEV_TX_OK; 2290 } 2291 2292 /* 2293 * We are always going to queue the packet 2294 * so that the bottom half is the only place we tx from 2295 * Check there is room in the port txq 2296 */ 2297 spin_lock_irqsave(&card->card_lock, flags); 2298 if ((txq_length = port->txqe - port->txqs) < 0) { 2299 /* 2300 * This is the case where the next free has wrapped but the 2301 * last used hasn't 2302 */ 2303 txq_length = txq_length + FST_TXQ_DEPTH; 2304 } 2305 spin_unlock_irqrestore(&card->card_lock, flags); 2306 if (txq_length > fst_txq_high) { 2307 /* 2308 * We have got enough buffers in the pipeline. Ask the network 2309 * layer to stop sending frames down 2310 */ 2311 netif_stop_queue(dev); 2312 port->start = 1; /* I'm using this to signal stop sent up */ 2313 } 2314 2315 if (txq_length == FST_TXQ_DEPTH - 1) { 2316 /* 2317 * This shouldn't have happened but such is life 2318 */ 2319 dev_kfree_skb(skb); 2320 dev->stats.tx_errors++; 2321 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", 2322 card->card_no, port->index); 2323 return NETDEV_TX_OK; 2324 } 2325 2326 /* 2327 * queue the buffer 2328 */ 2329 spin_lock_irqsave(&card->card_lock, flags); 2330 port->txq[port->txqe] = skb; 2331 port->txqe++; 2332 if (port->txqe == FST_TXQ_DEPTH) 2333 port->txqe = 0; 2334 spin_unlock_irqrestore(&card->card_lock, flags); 2335 2336 /* Scehdule the bottom half which now does transmit processing */ 2337 fst_q_work_item(&fst_work_txq, card->card_no); 2338 tasklet_schedule(&fst_tx_task); 2339 2340 return NETDEV_TX_OK; 2341} 2342 2343/* 2344 * Card setup having checked hardware resources. 2345 * Should be pretty bizarre if we get an error here (kernel memory 2346 * exhaustion is one possibility). If we do see a problem we report it 2347 * via a printk and leave the corresponding interface and all that follow 2348 * disabled. 2349 */ 2350static char *type_strings[] = { 2351 "no hardware", /* Should never be seen */ 2352 "FarSync T2P", 2353 "FarSync T4P", 2354 "FarSync T1U", 2355 "FarSync T2U", 2356 "FarSync T4U", 2357 "FarSync TE1" 2358}; 2359 2360static int 2361fst_init_card(struct fst_card_info *card) 2362{ 2363 int i; 2364 int err; 2365 2366 /* We're working on a number of ports based on the card ID. If the 2367 * firmware detects something different later (should never happen) 2368 * we'll have to revise it in some way then. 2369 */ 2370 for (i = 0; i < card->nports; i++) { 2371 err = register_hdlc_device(card->ports[i].dev); 2372 if (err < 0) { 2373 pr_err("Cannot register HDLC device for port %d (errno %d)\n", 2374 i, -err); 2375 while (i--) 2376 unregister_hdlc_device(card->ports[i].dev); 2377 return err; 2378 } 2379 } 2380 2381 pr_info("%s-%s: %s IRQ%d, %d ports\n", 2382 port_to_dev(&card->ports[0])->name, 2383 port_to_dev(&card->ports[card->nports - 1])->name, 2384 type_strings[card->type], card->irq, card->nports); 2385 return 0; 2386} 2387 2388static const struct net_device_ops fst_ops = { 2389 .ndo_open = fst_open, 2390 .ndo_stop = fst_close, 2391 .ndo_start_xmit = hdlc_start_xmit, 2392 .ndo_do_ioctl = fst_ioctl, 2393 .ndo_tx_timeout = fst_tx_timeout, 2394}; 2395 2396/* 2397 * Initialise card when detected. 2398 * Returns 0 to indicate success, or errno otherwise. 2399 */ 2400static int 2401fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2402{ 2403 static int no_of_cards_added = 0; 2404 struct fst_card_info *card; 2405 int err = 0; 2406 int i; 2407 2408 printk_once(KERN_INFO 2409 pr_fmt("FarSync WAN driver " FST_USER_VERSION 2410 " (c) 2001-2004 FarSite Communications Ltd.\n")); 2411#if FST_DEBUG 2412 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); 2413#endif 2414 /* 2415 * We are going to be clever and allow certain cards not to be 2416 * configured. An exclude list can be provided in /etc/modules.conf 2417 */ 2418 if (fst_excluded_cards != 0) { 2419 /* 2420 * There are cards to exclude 2421 * 2422 */ 2423 for (i = 0; i < fst_excluded_cards; i++) { 2424 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) { 2425 pr_info("FarSync PCI device %d not assigned\n", 2426 (pdev->devfn) >> 3); 2427 return -EBUSY; 2428 } 2429 } 2430 } 2431 2432 /* Allocate driver private data */ 2433 card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL); 2434 if (card == NULL) 2435 return -ENOMEM; 2436 2437 /* Try to enable the device */ 2438 if ((err = pci_enable_device(pdev)) != 0) { 2439 pr_err("Failed to enable card. Err %d\n", -err); 2440 goto enable_fail; 2441 } 2442 2443 if ((err = pci_request_regions(pdev, "FarSync")) !=0) { 2444 pr_err("Failed to allocate regions. Err %d\n", -err); 2445 goto regions_fail; 2446 } 2447 2448 /* Get virtual addresses of memory regions */ 2449 card->pci_conf = pci_resource_start(pdev, 1); 2450 card->phys_mem = pci_resource_start(pdev, 2); 2451 card->phys_ctlmem = pci_resource_start(pdev, 3); 2452 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) { 2453 pr_err("Physical memory remap failed\n"); 2454 err = -ENODEV; 2455 goto ioremap_physmem_fail; 2456 } 2457 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) { 2458 pr_err("Control memory remap failed\n"); 2459 err = -ENODEV; 2460 goto ioremap_ctlmem_fail; 2461 } 2462 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); 2463 2464 /* Register the interrupt handler */ 2465 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { 2466 pr_err("Unable to register interrupt %d\n", card->irq); 2467 err = -ENODEV; 2468 goto irq_fail; 2469 } 2470 2471 /* Record info we need */ 2472 card->irq = pdev->irq; 2473 card->type = ent->driver_data; 2474 card->family = ((ent->driver_data == FST_TYPE_T2P) || 2475 (ent->driver_data == FST_TYPE_T4P)) 2476 ? FST_FAMILY_TXP : FST_FAMILY_TXU; 2477 if ((ent->driver_data == FST_TYPE_T1U) || 2478 (ent->driver_data == FST_TYPE_TE1)) 2479 card->nports = 1; 2480 else 2481 card->nports = ((ent->driver_data == FST_TYPE_T2P) || 2482 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; 2483 2484 card->state = FST_UNINIT; 2485 spin_lock_init ( &card->card_lock ); 2486 2487 for ( i = 0 ; i < card->nports ; i++ ) { 2488 struct net_device *dev = alloc_hdlcdev(&card->ports[i]); 2489 hdlc_device *hdlc; 2490 if (!dev) { 2491 while (i--) 2492 free_netdev(card->ports[i].dev); 2493 pr_err("FarSync: out of memory\n"); 2494 err = -ENOMEM; 2495 goto hdlcdev_fail; 2496 } 2497 card->ports[i].dev = dev; 2498 card->ports[i].card = card; 2499 card->ports[i].index = i; 2500 card->ports[i].run = 0; 2501 2502 hdlc = dev_to_hdlc(dev); 2503 2504 /* Fill in the net device info */ 2505 /* Since this is a PCI setup this is purely 2506 * informational. Give them the buffer addresses 2507 * and basic card I/O. 2508 */ 2509 dev->mem_start = card->phys_mem 2510 + BUF_OFFSET ( txBuffer[i][0][0]); 2511 dev->mem_end = card->phys_mem 2512 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER - 1][LEN_RX_BUFFER - 1]); 2513 dev->base_addr = card->pci_conf; 2514 dev->irq = card->irq; 2515 2516 dev->netdev_ops = &fst_ops; 2517 dev->tx_queue_len = FST_TX_QUEUE_LEN; 2518 dev->watchdog_timeo = FST_TX_TIMEOUT; 2519 hdlc->attach = fst_attach; 2520 hdlc->xmit = fst_start_xmit; 2521 } 2522 2523 card->device = pdev; 2524 2525 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, 2526 card->nports, card->irq); 2527 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", 2528 card->pci_conf, card->phys_mem, card->phys_ctlmem); 2529 2530 /* Reset the card's processor */ 2531 fst_cpureset(card); 2532 card->state = FST_RESET; 2533 2534 /* Initialise DMA (if required) */ 2535 fst_init_dma(card); 2536 2537 /* Record driver data for later use */ 2538 pci_set_drvdata(pdev, card); 2539 2540 /* Remainder of card setup */ 2541 if (no_of_cards_added >= FST_MAX_CARDS) { 2542 pr_err("FarSync: too many cards\n"); 2543 err = -ENOMEM; 2544 goto card_array_fail; 2545 } 2546 fst_card_array[no_of_cards_added] = card; 2547 card->card_no = no_of_cards_added++; /* Record instance and bump it */ 2548 err = fst_init_card(card); 2549 if (err) 2550 goto init_card_fail; 2551 if (card->family == FST_FAMILY_TXU) { 2552 /* 2553 * Allocate a dma buffer for transmit and receives 2554 */ 2555 card->rx_dma_handle_host = 2556 dma_alloc_coherent(&card->device->dev, FST_MAX_MTU, 2557 &card->rx_dma_handle_card, GFP_KERNEL); 2558 if (card->rx_dma_handle_host == NULL) { 2559 pr_err("Could not allocate rx dma buffer\n"); 2560 err = -ENOMEM; 2561 goto rx_dma_fail; 2562 } 2563 card->tx_dma_handle_host = 2564 dma_alloc_coherent(&card->device->dev, FST_MAX_MTU, 2565 &card->tx_dma_handle_card, GFP_KERNEL); 2566 if (card->tx_dma_handle_host == NULL) { 2567 pr_err("Could not allocate tx dma buffer\n"); 2568 err = -ENOMEM; 2569 goto tx_dma_fail; 2570 } 2571 } 2572 return 0; /* Success */ 2573 2574tx_dma_fail: 2575 dma_free_coherent(&card->device->dev, FST_MAX_MTU, 2576 card->rx_dma_handle_host, card->rx_dma_handle_card); 2577rx_dma_fail: 2578 fst_disable_intr(card); 2579 for (i = 0 ; i < card->nports ; i++) 2580 unregister_hdlc_device(card->ports[i].dev); 2581init_card_fail: 2582 fst_card_array[card->card_no] = NULL; 2583card_array_fail: 2584 for (i = 0 ; i < card->nports ; i++) 2585 free_netdev(card->ports[i].dev); 2586hdlcdev_fail: 2587 free_irq(card->irq, card); 2588irq_fail: 2589 iounmap(card->ctlmem); 2590ioremap_ctlmem_fail: 2591 iounmap(card->mem); 2592ioremap_physmem_fail: 2593 pci_release_regions(pdev); 2594regions_fail: 2595 pci_disable_device(pdev); 2596enable_fail: 2597 kfree(card); 2598 return err; 2599} 2600 2601/* 2602 * Cleanup and close down a card 2603 */ 2604static void 2605fst_remove_one(struct pci_dev *pdev) 2606{ 2607 struct fst_card_info *card; 2608 int i; 2609 2610 card = pci_get_drvdata(pdev); 2611 2612 for (i = 0; i < card->nports; i++) { 2613 struct net_device *dev = port_to_dev(&card->ports[i]); 2614 unregister_hdlc_device(dev); 2615 free_netdev(dev); 2616 } 2617 2618 fst_disable_intr(card); 2619 free_irq(card->irq, card); 2620 2621 iounmap(card->ctlmem); 2622 iounmap(card->mem); 2623 pci_release_regions(pdev); 2624 if (card->family == FST_FAMILY_TXU) { 2625 /* 2626 * Free dma buffers 2627 */ 2628 dma_free_coherent(&card->device->dev, FST_MAX_MTU, 2629 card->rx_dma_handle_host, 2630 card->rx_dma_handle_card); 2631 dma_free_coherent(&card->device->dev, FST_MAX_MTU, 2632 card->tx_dma_handle_host, 2633 card->tx_dma_handle_card); 2634 } 2635 fst_card_array[card->card_no] = NULL; 2636 kfree(card); 2637} 2638 2639static struct pci_driver fst_driver = { 2640 .name = FST_NAME, 2641 .id_table = fst_pci_dev_id, 2642 .probe = fst_add_one, 2643 .remove = fst_remove_one, 2644}; 2645 2646static int __init 2647fst_init(void) 2648{ 2649 int i; 2650 2651 for (i = 0; i < FST_MAX_CARDS; i++) 2652 fst_card_array[i] = NULL; 2653 spin_lock_init(&fst_work_q_lock); 2654 return pci_register_driver(&fst_driver); 2655} 2656 2657static void __exit 2658fst_cleanup_module(void) 2659{ 2660 pr_info("FarSync WAN driver unloading\n"); 2661 pci_unregister_driver(&fst_driver); 2662} 2663 2664module_init(fst_init); 2665module_exit(fst_cleanup_module); 2666