1/* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: pv-drivers@vmware.com 24 * 25 */ 26 27#include <linux/module.h> 28#include <net/ip6_checksum.h> 29 30#include "vmxnet3_int.h" 31 32char vmxnet3_driver_name[] = "vmxnet3"; 33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34 35/* 36 * PCI Device ID Table 37 * Last entry must be all 0s 38 */ 39static const struct pci_device_id vmxnet3_pciid_table[] = { 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41 {0} 42}; 43 44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45 46static int enable_mq = 1; 47 48static void 49vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 50 51/* 52 * Enable/Disable the given intr 53 */ 54static void 55vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 56{ 57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 58} 59 60 61static void 62vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 63{ 64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 65} 66 67 68/* 69 * Enable/Disable all intrs used by the device 70 */ 71static void 72vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 73{ 74 int i; 75 76 for (i = 0; i < adapter->intr.num_intrs; i++) 77 vmxnet3_enable_intr(adapter, i); 78 adapter->shared->devRead.intrConf.intrCtrl &= 79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 80} 81 82 83static void 84vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 85{ 86 int i; 87 88 adapter->shared->devRead.intrConf.intrCtrl |= 89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 90 for (i = 0; i < adapter->intr.num_intrs; i++) 91 vmxnet3_disable_intr(adapter, i); 92} 93 94 95static void 96vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 97{ 98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 99} 100 101 102static bool 103vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 104{ 105 return tq->stopped; 106} 107 108 109static void 110vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 111{ 112 tq->stopped = false; 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 114} 115 116 117static void 118vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 119{ 120 tq->stopped = false; 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 122} 123 124 125static void 126vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 127{ 128 tq->stopped = true; 129 tq->num_stop++; 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 131} 132 133 134/* 135 * Check the link state. This may start or stop the tx queue. 136 */ 137static void 138vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 139{ 140 u32 ret; 141 int i; 142 unsigned long flags; 143 144 spin_lock_irqsave(&adapter->cmd_lock, flags); 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 148 149 adapter->link_speed = ret >> 16; 150 if (ret & 1) { /* Link is up. */ 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n", 152 adapter->link_speed); 153 netif_carrier_on(adapter->netdev); 154 155 if (affectTxQueue) { 156 for (i = 0; i < adapter->num_tx_queues; i++) 157 vmxnet3_tq_start(&adapter->tx_queue[i], 158 adapter); 159 } 160 } else { 161 netdev_info(adapter->netdev, "NIC Link is Down\n"); 162 netif_carrier_off(adapter->netdev); 163 164 if (affectTxQueue) { 165 for (i = 0; i < adapter->num_tx_queues; i++) 166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 167 } 168 } 169} 170 171static void 172vmxnet3_process_events(struct vmxnet3_adapter *adapter) 173{ 174 int i; 175 unsigned long flags; 176 u32 events = le32_to_cpu(adapter->shared->ecr); 177 if (!events) 178 return; 179 180 vmxnet3_ack_events(adapter, events); 181 182 /* Check if link state has changed */ 183 if (events & VMXNET3_ECR_LINK) 184 vmxnet3_check_link(adapter, true); 185 186 /* Check if there is an error on xmit/recv queues */ 187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 188 spin_lock_irqsave(&adapter->cmd_lock, flags); 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 190 VMXNET3_CMD_GET_QUEUE_STATUS); 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 192 193 for (i = 0; i < adapter->num_tx_queues; i++) 194 if (adapter->tqd_start[i].status.stopped) 195 dev_err(&adapter->netdev->dev, 196 "%s: tq[%d] error 0x%x\n", 197 adapter->netdev->name, i, le32_to_cpu( 198 adapter->tqd_start[i].status.error)); 199 for (i = 0; i < adapter->num_rx_queues; i++) 200 if (adapter->rqd_start[i].status.stopped) 201 dev_err(&adapter->netdev->dev, 202 "%s: rq[%d] error 0x%x\n", 203 adapter->netdev->name, i, 204 adapter->rqd_start[i].status.error); 205 206 schedule_work(&adapter->work); 207 } 208} 209 210#ifdef __BIG_ENDIAN_BITFIELD 211/* 212 * The device expects the bitfields in shared structures to be written in 213 * little endian. When CPU is big endian, the following routines are used to 214 * correctly read and write into ABI. 215 * The general technique used here is : double word bitfields are defined in 216 * opposite order for big endian architecture. Then before reading them in 217 * driver the complete double word is translated using le32_to_cpu. Similarly 218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 219 * double words into required format. 220 * In order to avoid touching bits in shared structure more than once, temporary 221 * descriptors are used. These are passed as srcDesc to following functions. 222 */ 223static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 224 struct Vmxnet3_RxDesc *dstDesc) 225{ 226 u32 *src = (u32 *)srcDesc + 2; 227 u32 *dst = (u32 *)dstDesc + 2; 228 dstDesc->addr = le64_to_cpu(srcDesc->addr); 229 *dst = le32_to_cpu(*src); 230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 231} 232 233static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 234 struct Vmxnet3_TxDesc *dstDesc) 235{ 236 int i; 237 u32 *src = (u32 *)(srcDesc + 1); 238 u32 *dst = (u32 *)(dstDesc + 1); 239 240 /* Working backwards so that the gen bit is set at the end. */ 241 for (i = 2; i > 0; i--) { 242 src--; 243 dst--; 244 *dst = cpu_to_le32(*src); 245 } 246} 247 248 249static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 250 struct Vmxnet3_RxCompDesc *dstDesc) 251{ 252 int i = 0; 253 u32 *src = (u32 *)srcDesc; 254 u32 *dst = (u32 *)dstDesc; 255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 256 *dst = le32_to_cpu(*src); 257 src++; 258 dst++; 259 } 260} 261 262 263/* Used to read bitfield values from double words. */ 264static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 265{ 266 u32 temp = le32_to_cpu(*bitfield); 267 u32 mask = ((1 << size) - 1) << pos; 268 temp &= mask; 269 temp >>= pos; 270 return temp; 271} 272 273 274 275#endif /* __BIG_ENDIAN_BITFIELD */ 276 277#ifdef __BIG_ENDIAN_BITFIELD 278 279# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 282# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 285# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 287 VMXNET3_TCD_GEN_SIZE) 288# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 290# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 291 (dstrcd) = (tmp); \ 292 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 293 } while (0) 294# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 295 (dstrxd) = (tmp); \ 296 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 297 } while (0) 298 299#else 300 301# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 302# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 303# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 304# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 305# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 306# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 307 308#endif /* __BIG_ENDIAN_BITFIELD */ 309 310 311static void 312vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 313 struct pci_dev *pdev) 314{ 315 if (tbi->map_type == VMXNET3_MAP_SINGLE) 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len, 317 PCI_DMA_TODEVICE); 318 else if (tbi->map_type == VMXNET3_MAP_PAGE) 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len, 320 PCI_DMA_TODEVICE); 321 else 322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 323 324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 325} 326 327 328static int 329vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 331{ 332 struct sk_buff *skb; 333 int entries = 0; 334 335 /* no out of order completion */ 336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 338 339 skb = tq->buf_info[eop_idx].skb; 340 BUG_ON(skb == NULL); 341 tq->buf_info[eop_idx].skb = NULL; 342 343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 344 345 while (tq->tx_ring.next2comp != eop_idx) { 346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 347 pdev); 348 349 /* update next2comp w/o tx_lock. Since we are marking more, 350 * instead of less, tx ring entries avail, the worst case is 351 * that the tx routine incorrectly re-queues a pkt due to 352 * insufficient tx ring entries. 353 */ 354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 355 entries++; 356 } 357 358 dev_kfree_skb_any(skb); 359 return entries; 360} 361 362 363static int 364vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 365 struct vmxnet3_adapter *adapter) 366{ 367 int completed = 0; 368 union Vmxnet3_GenericDesc *gdesc; 369 370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 372 /* Prevent any &gdesc->tcd field from being (speculatively) 373 * read before (&gdesc->tcd)->gen is read. 374 */ 375 dma_rmb(); 376 377 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 378 &gdesc->tcd), tq, adapter->pdev, 379 adapter); 380 381 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 383 } 384 385 if (completed) { 386 spin_lock(&tq->tx_lock); 387 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 388 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 389 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 390 netif_carrier_ok(adapter->netdev))) { 391 vmxnet3_tq_wake(tq, adapter); 392 } 393 spin_unlock(&tq->tx_lock); 394 } 395 return completed; 396} 397 398 399static void 400vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 401 struct vmxnet3_adapter *adapter) 402{ 403 int i; 404 405 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 406 struct vmxnet3_tx_buf_info *tbi; 407 408 tbi = tq->buf_info + tq->tx_ring.next2comp; 409 410 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 411 if (tbi->skb) { 412 dev_kfree_skb_any(tbi->skb); 413 tbi->skb = NULL; 414 } 415 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 416 } 417 418 /* sanity check, verify all buffers are indeed unmapped and freed */ 419 for (i = 0; i < tq->tx_ring.size; i++) { 420 BUG_ON(tq->buf_info[i].skb != NULL || 421 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 422 } 423 424 tq->tx_ring.gen = VMXNET3_INIT_GEN; 425 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 426 427 tq->comp_ring.gen = VMXNET3_INIT_GEN; 428 tq->comp_ring.next2proc = 0; 429} 430 431 432static void 433vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 434 struct vmxnet3_adapter *adapter) 435{ 436 if (tq->tx_ring.base) { 437 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size * 438 sizeof(struct Vmxnet3_TxDesc), 439 tq->tx_ring.base, tq->tx_ring.basePA); 440 tq->tx_ring.base = NULL; 441 } 442 if (tq->data_ring.base) { 443 dma_free_coherent(&adapter->pdev->dev, 444 tq->data_ring.size * tq->txdata_desc_size, 445 tq->data_ring.base, tq->data_ring.basePA); 446 tq->data_ring.base = NULL; 447 } 448 if (tq->comp_ring.base) { 449 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size * 450 sizeof(struct Vmxnet3_TxCompDesc), 451 tq->comp_ring.base, tq->comp_ring.basePA); 452 tq->comp_ring.base = NULL; 453 } 454 if (tq->buf_info) { 455 dma_free_coherent(&adapter->pdev->dev, 456 tq->tx_ring.size * sizeof(tq->buf_info[0]), 457 tq->buf_info, tq->buf_info_pa); 458 tq->buf_info = NULL; 459 } 460} 461 462 463/* Destroy all tx queues */ 464void 465vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 466{ 467 int i; 468 469 for (i = 0; i < adapter->num_tx_queues; i++) 470 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 471} 472 473 474static void 475vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 476 struct vmxnet3_adapter *adapter) 477{ 478 int i; 479 480 /* reset the tx ring contents to 0 and reset the tx ring states */ 481 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 482 sizeof(struct Vmxnet3_TxDesc)); 483 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 484 tq->tx_ring.gen = VMXNET3_INIT_GEN; 485 486 memset(tq->data_ring.base, 0, 487 tq->data_ring.size * tq->txdata_desc_size); 488 489 /* reset the tx comp ring contents to 0 and reset comp ring states */ 490 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 491 sizeof(struct Vmxnet3_TxCompDesc)); 492 tq->comp_ring.next2proc = 0; 493 tq->comp_ring.gen = VMXNET3_INIT_GEN; 494 495 /* reset the bookkeeping data */ 496 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 497 for (i = 0; i < tq->tx_ring.size; i++) 498 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 499 500 /* stats are not reset */ 501} 502 503 504static int 505vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 506 struct vmxnet3_adapter *adapter) 507{ 508 size_t sz; 509 510 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 511 tq->comp_ring.base || tq->buf_info); 512 513 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 514 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc), 515 &tq->tx_ring.basePA, GFP_KERNEL); 516 if (!tq->tx_ring.base) { 517 netdev_err(adapter->netdev, "failed to allocate tx ring\n"); 518 goto err; 519 } 520 521 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 522 tq->data_ring.size * tq->txdata_desc_size, 523 &tq->data_ring.basePA, GFP_KERNEL); 524 if (!tq->data_ring.base) { 525 netdev_err(adapter->netdev, "failed to allocate tx data ring\n"); 526 goto err; 527 } 528 529 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 530 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc), 531 &tq->comp_ring.basePA, GFP_KERNEL); 532 if (!tq->comp_ring.base) { 533 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n"); 534 goto err; 535 } 536 537 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]); 538 tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz, 539 &tq->buf_info_pa, GFP_KERNEL); 540 if (!tq->buf_info) 541 goto err; 542 543 return 0; 544 545err: 546 vmxnet3_tq_destroy(tq, adapter); 547 return -ENOMEM; 548} 549 550static void 551vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 552{ 553 int i; 554 555 for (i = 0; i < adapter->num_tx_queues; i++) 556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 557} 558 559/* 560 * starting from ring->next2fill, allocate rx buffers for the given ring 561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 562 * are allocated or allocation fails 563 */ 564 565static int 566vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 567 int num_to_alloc, struct vmxnet3_adapter *adapter) 568{ 569 int num_allocated = 0; 570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 572 u32 val; 573 574 while (num_allocated <= num_to_alloc) { 575 struct vmxnet3_rx_buf_info *rbi; 576 union Vmxnet3_GenericDesc *gd; 577 578 rbi = rbi_base + ring->next2fill; 579 gd = ring->base + ring->next2fill; 580 581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 582 if (rbi->skb == NULL) { 583 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev, 584 rbi->len, 585 GFP_KERNEL); 586 if (unlikely(rbi->skb == NULL)) { 587 rq->stats.rx_buf_alloc_failure++; 588 break; 589 } 590 591 rbi->dma_addr = dma_map_single( 592 &adapter->pdev->dev, 593 rbi->skb->data, rbi->len, 594 PCI_DMA_FROMDEVICE); 595 if (dma_mapping_error(&adapter->pdev->dev, 596 rbi->dma_addr)) { 597 dev_kfree_skb_any(rbi->skb); 598 rbi->skb = NULL; 599 rq->stats.rx_buf_alloc_failure++; 600 break; 601 } 602 } else { 603 /* rx buffer skipped by the device */ 604 } 605 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 606 } else { 607 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 608 rbi->len != PAGE_SIZE); 609 610 if (rbi->page == NULL) { 611 rbi->page = alloc_page(GFP_ATOMIC); 612 if (unlikely(rbi->page == NULL)) { 613 rq->stats.rx_buf_alloc_failure++; 614 break; 615 } 616 rbi->dma_addr = dma_map_page( 617 &adapter->pdev->dev, 618 rbi->page, 0, PAGE_SIZE, 619 PCI_DMA_FROMDEVICE); 620 if (dma_mapping_error(&adapter->pdev->dev, 621 rbi->dma_addr)) { 622 put_page(rbi->page); 623 rbi->page = NULL; 624 rq->stats.rx_buf_alloc_failure++; 625 break; 626 } 627 } else { 628 /* rx buffers skipped by the device */ 629 } 630 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 631 } 632 633 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 634 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 635 | val | rbi->len); 636 637 /* Fill the last buffer but dont mark it ready, or else the 638 * device will think that the queue is full */ 639 if (num_allocated == num_to_alloc) 640 break; 641 642 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 643 num_allocated++; 644 vmxnet3_cmd_ring_adv_next2fill(ring); 645 } 646 647 netdev_dbg(adapter->netdev, 648 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n", 649 num_allocated, ring->next2fill, ring->next2comp); 650 651 /* so that the device can distinguish a full ring and an empty ring */ 652 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 653 654 return num_allocated; 655} 656 657 658static void 659vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 660 struct vmxnet3_rx_buf_info *rbi) 661{ 662 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags; 663 664 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 665 666 __skb_frag_set_page(frag, rbi->page); 667 skb_frag_off_set(frag, 0); 668 skb_frag_size_set(frag, rcd->len); 669 skb->data_len += rcd->len; 670 skb->truesize += PAGE_SIZE; 671 skb_shinfo(skb)->nr_frags++; 672} 673 674 675static int 676vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 677 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 678 struct vmxnet3_adapter *adapter) 679{ 680 u32 dw2, len; 681 unsigned long buf_offset; 682 int i; 683 union Vmxnet3_GenericDesc *gdesc; 684 struct vmxnet3_tx_buf_info *tbi = NULL; 685 686 BUG_ON(ctx->copy_size > skb_headlen(skb)); 687 688 /* use the previous gen bit for the SOP desc */ 689 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 690 691 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 692 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 693 694 /* no need to map the buffer if headers are copied */ 695 if (ctx->copy_size) { 696 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 697 tq->tx_ring.next2fill * 698 tq->txdata_desc_size); 699 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 700 ctx->sop_txd->dword[3] = 0; 701 702 tbi = tq->buf_info + tq->tx_ring.next2fill; 703 tbi->map_type = VMXNET3_MAP_NONE; 704 705 netdev_dbg(adapter->netdev, 706 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 707 tq->tx_ring.next2fill, 708 le64_to_cpu(ctx->sop_txd->txd.addr), 709 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 710 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 711 712 /* use the right gen for non-SOP desc */ 713 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 714 } 715 716 /* linear part can use multiple tx desc if it's big */ 717 len = skb_headlen(skb) - ctx->copy_size; 718 buf_offset = ctx->copy_size; 719 while (len) { 720 u32 buf_size; 721 722 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 723 buf_size = len; 724 dw2 |= len; 725 } else { 726 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 727 /* spec says that for TxDesc.len, 0 == 2^14 */ 728 } 729 730 tbi = tq->buf_info + tq->tx_ring.next2fill; 731 tbi->map_type = VMXNET3_MAP_SINGLE; 732 tbi->dma_addr = dma_map_single(&adapter->pdev->dev, 733 skb->data + buf_offset, buf_size, 734 PCI_DMA_TODEVICE); 735 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 736 return -EFAULT; 737 738 tbi->len = buf_size; 739 740 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 741 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 742 743 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 744 gdesc->dword[2] = cpu_to_le32(dw2); 745 gdesc->dword[3] = 0; 746 747 netdev_dbg(adapter->netdev, 748 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 749 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 750 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 751 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 752 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 753 754 len -= buf_size; 755 buf_offset += buf_size; 756 } 757 758 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 759 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 760 u32 buf_size; 761 762 buf_offset = 0; 763 len = skb_frag_size(frag); 764 while (len) { 765 tbi = tq->buf_info + tq->tx_ring.next2fill; 766 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 767 buf_size = len; 768 dw2 |= len; 769 } else { 770 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 771 /* spec says that for TxDesc.len, 0 == 2^14 */ 772 } 773 tbi->map_type = VMXNET3_MAP_PAGE; 774 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 775 buf_offset, buf_size, 776 DMA_TO_DEVICE); 777 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 778 return -EFAULT; 779 780 tbi->len = buf_size; 781 782 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 783 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 784 785 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 786 gdesc->dword[2] = cpu_to_le32(dw2); 787 gdesc->dword[3] = 0; 788 789 netdev_dbg(adapter->netdev, 790 "txd[%u]: 0x%llx %u %u\n", 791 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 792 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 793 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 794 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 795 796 len -= buf_size; 797 buf_offset += buf_size; 798 } 799 } 800 801 ctx->eop_txd = gdesc; 802 803 /* set the last buf_info for the pkt */ 804 tbi->skb = skb; 805 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 806 807 return 0; 808} 809 810 811/* Init all tx queues */ 812static void 813vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 814{ 815 int i; 816 817 for (i = 0; i < adapter->num_tx_queues; i++) 818 vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 819} 820 821 822/* 823 * parse relevant protocol headers: 824 * For a tso pkt, relevant headers are L2/3/4 including options 825 * For a pkt requesting csum offloading, they are L2/3 and may include L4 826 * if it's a TCP/UDP pkt 827 * 828 * Returns: 829 * -1: error happens during parsing 830 * 0: protocol headers parsed, but too big to be copied 831 * 1: protocol headers parsed and copied 832 * 833 * Other effects: 834 * 1. related *ctx fields are updated. 835 * 2. ctx->copy_size is # of bytes copied 836 * 3. the portion to be copied is guaranteed to be in the linear part 837 * 838 */ 839static int 840vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 841 struct vmxnet3_tx_ctx *ctx, 842 struct vmxnet3_adapter *adapter) 843{ 844 u8 protocol = 0; 845 846 if (ctx->mss) { /* TSO */ 847 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) { 848 ctx->l4_offset = skb_inner_transport_offset(skb); 849 ctx->l4_hdr_size = inner_tcp_hdrlen(skb); 850 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size; 851 } else { 852 ctx->l4_offset = skb_transport_offset(skb); 853 ctx->l4_hdr_size = tcp_hdrlen(skb); 854 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size; 855 } 856 } else { 857 if (skb->ip_summed == CHECKSUM_PARTIAL) { 858 /* For encap packets, skb_checksum_start_offset refers 859 * to inner L4 offset. Thus, below works for encap as 860 * well as non-encap case 861 */ 862 ctx->l4_offset = skb_checksum_start_offset(skb); 863 864 if (VMXNET3_VERSION_GE_4(adapter) && 865 skb->encapsulation) { 866 struct iphdr *iph = inner_ip_hdr(skb); 867 868 if (iph->version == 4) { 869 protocol = iph->protocol; 870 } else { 871 const struct ipv6hdr *ipv6h; 872 873 ipv6h = inner_ipv6_hdr(skb); 874 protocol = ipv6h->nexthdr; 875 } 876 } else { 877 if (ctx->ipv4) { 878 const struct iphdr *iph = ip_hdr(skb); 879 880 protocol = iph->protocol; 881 } else if (ctx->ipv6) { 882 const struct ipv6hdr *ipv6h; 883 884 ipv6h = ipv6_hdr(skb); 885 protocol = ipv6h->nexthdr; 886 } 887 } 888 889 switch (protocol) { 890 case IPPROTO_TCP: 891 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) : 892 tcp_hdrlen(skb); 893 break; 894 case IPPROTO_UDP: 895 ctx->l4_hdr_size = sizeof(struct udphdr); 896 break; 897 default: 898 ctx->l4_hdr_size = 0; 899 break; 900 } 901 902 ctx->copy_size = min(ctx->l4_offset + 903 ctx->l4_hdr_size, skb->len); 904 } else { 905 ctx->l4_offset = 0; 906 ctx->l4_hdr_size = 0; 907 /* copy as much as allowed */ 908 ctx->copy_size = min_t(unsigned int, 909 tq->txdata_desc_size, 910 skb_headlen(skb)); 911 } 912 913 if (skb->len <= VMXNET3_HDR_COPY_SIZE) 914 ctx->copy_size = skb->len; 915 916 /* make sure headers are accessible directly */ 917 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 918 goto err; 919 } 920 921 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) { 922 tq->stats.oversized_hdr++; 923 ctx->copy_size = 0; 924 return 0; 925 } 926 927 return 1; 928err: 929 return -1; 930} 931 932/* 933 * copy relevant protocol headers to the transmit ring: 934 * For a tso pkt, relevant headers are L2/3/4 including options 935 * For a pkt requesting csum offloading, they are L2/3 and may include L4 936 * if it's a TCP/UDP pkt 937 * 938 * 939 * Note that this requires that vmxnet3_parse_hdr be called first to set the 940 * appropriate bits in ctx first 941 */ 942static void 943vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 944 struct vmxnet3_tx_ctx *ctx, 945 struct vmxnet3_adapter *adapter) 946{ 947 struct Vmxnet3_TxDataDesc *tdd; 948 949 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base + 950 tq->tx_ring.next2fill * 951 tq->txdata_desc_size); 952 953 memcpy(tdd->data, skb->data, ctx->copy_size); 954 netdev_dbg(adapter->netdev, 955 "copy %u bytes to dataRing[%u]\n", 956 ctx->copy_size, tq->tx_ring.next2fill); 957} 958 959 960static void 961vmxnet3_prepare_inner_tso(struct sk_buff *skb, 962 struct vmxnet3_tx_ctx *ctx) 963{ 964 struct tcphdr *tcph = inner_tcp_hdr(skb); 965 struct iphdr *iph = inner_ip_hdr(skb); 966 967 if (iph->version == 4) { 968 iph->check = 0; 969 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 970 IPPROTO_TCP, 0); 971 } else { 972 struct ipv6hdr *iph = inner_ipv6_hdr(skb); 973 974 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 975 IPPROTO_TCP, 0); 976 } 977} 978 979static void 980vmxnet3_prepare_tso(struct sk_buff *skb, 981 struct vmxnet3_tx_ctx *ctx) 982{ 983 struct tcphdr *tcph = tcp_hdr(skb); 984 985 if (ctx->ipv4) { 986 struct iphdr *iph = ip_hdr(skb); 987 988 iph->check = 0; 989 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 990 IPPROTO_TCP, 0); 991 } else if (ctx->ipv6) { 992 tcp_v6_gso_csum_prep(skb); 993 } 994} 995 996static int txd_estimate(const struct sk_buff *skb) 997{ 998 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 999 int i; 1000 1001 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1002 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1003 1004 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); 1005 } 1006 return count; 1007} 1008 1009/* 1010 * Transmits a pkt thru a given tq 1011 * Returns: 1012 * NETDEV_TX_OK: descriptors are setup successfully 1013 * NETDEV_TX_OK: error occurred, the pkt is dropped 1014 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 1015 * 1016 * Side-effects: 1017 * 1. tx ring may be changed 1018 * 2. tq stats may be updated accordingly 1019 * 3. shared->txNumDeferred may be updated 1020 */ 1021 1022static int 1023vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 1024 struct vmxnet3_adapter *adapter, struct net_device *netdev) 1025{ 1026 int ret; 1027 u32 count; 1028 int num_pkts; 1029 int tx_num_deferred; 1030 unsigned long flags; 1031 struct vmxnet3_tx_ctx ctx; 1032 union Vmxnet3_GenericDesc *gdesc; 1033#ifdef __BIG_ENDIAN_BITFIELD 1034 /* Use temporary descriptor to avoid touching bits multiple times */ 1035 union Vmxnet3_GenericDesc tempTxDesc; 1036#endif 1037 1038 count = txd_estimate(skb); 1039 1040 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 1041 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6)); 1042 1043 ctx.mss = skb_shinfo(skb)->gso_size; 1044 if (ctx.mss) { 1045 if (skb_header_cloned(skb)) { 1046 if (unlikely(pskb_expand_head(skb, 0, 0, 1047 GFP_ATOMIC) != 0)) { 1048 tq->stats.drop_tso++; 1049 goto drop_pkt; 1050 } 1051 tq->stats.copy_skb_header++; 1052 } 1053 if (skb->encapsulation) { 1054 vmxnet3_prepare_inner_tso(skb, &ctx); 1055 } else { 1056 vmxnet3_prepare_tso(skb, &ctx); 1057 } 1058 } else { 1059 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 1060 1061 /* non-tso pkts must not use more than 1062 * VMXNET3_MAX_TXD_PER_PKT entries 1063 */ 1064 if (skb_linearize(skb) != 0) { 1065 tq->stats.drop_too_many_frags++; 1066 goto drop_pkt; 1067 } 1068 tq->stats.linearized++; 1069 1070 /* recalculate the # of descriptors to use */ 1071 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 1072 } 1073 } 1074 1075 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter); 1076 if (ret >= 0) { 1077 BUG_ON(ret <= 0 && ctx.copy_size != 0); 1078 /* hdrs parsed, check against other limits */ 1079 if (ctx.mss) { 1080 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size > 1081 VMXNET3_MAX_TX_BUF_SIZE)) { 1082 tq->stats.drop_oversized_hdr++; 1083 goto drop_pkt; 1084 } 1085 } else { 1086 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1087 if (unlikely(ctx.l4_offset + 1088 skb->csum_offset > 1089 VMXNET3_MAX_CSUM_OFFSET)) { 1090 tq->stats.drop_oversized_hdr++; 1091 goto drop_pkt; 1092 } 1093 } 1094 } 1095 } else { 1096 tq->stats.drop_hdr_inspect_err++; 1097 goto drop_pkt; 1098 } 1099 1100 spin_lock_irqsave(&tq->tx_lock, flags); 1101 1102 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 1103 tq->stats.tx_ring_full++; 1104 netdev_dbg(adapter->netdev, 1105 "tx queue stopped on %s, next2comp %u" 1106 " next2fill %u\n", adapter->netdev->name, 1107 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 1108 1109 vmxnet3_tq_stop(tq, adapter); 1110 spin_unlock_irqrestore(&tq->tx_lock, flags); 1111 return NETDEV_TX_BUSY; 1112 } 1113 1114 1115 vmxnet3_copy_hdr(skb, tq, &ctx, adapter); 1116 1117 /* fill tx descs related to addr & len */ 1118 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter)) 1119 goto unlock_drop_pkt; 1120 1121 /* setup the EOP desc */ 1122 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 1123 1124 /* setup the SOP desc */ 1125#ifdef __BIG_ENDIAN_BITFIELD 1126 gdesc = &tempTxDesc; 1127 gdesc->dword[2] = ctx.sop_txd->dword[2]; 1128 gdesc->dword[3] = ctx.sop_txd->dword[3]; 1129#else 1130 gdesc = ctx.sop_txd; 1131#endif 1132 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred); 1133 if (ctx.mss) { 1134 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) { 1135 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size; 1136 gdesc->txd.om = VMXNET3_OM_ENCAP; 1137 gdesc->txd.msscof = ctx.mss; 1138 1139 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1140 gdesc->txd.oco = 1; 1141 } else { 1142 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size; 1143 gdesc->txd.om = VMXNET3_OM_TSO; 1144 gdesc->txd.msscof = ctx.mss; 1145 } 1146 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss; 1147 } else { 1148 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1149 if (VMXNET3_VERSION_GE_4(adapter) && 1150 skb->encapsulation) { 1151 gdesc->txd.hlen = ctx.l4_offset + 1152 ctx.l4_hdr_size; 1153 gdesc->txd.om = VMXNET3_OM_ENCAP; 1154 gdesc->txd.msscof = 0; /* Reserved */ 1155 } else { 1156 gdesc->txd.hlen = ctx.l4_offset; 1157 gdesc->txd.om = VMXNET3_OM_CSUM; 1158 gdesc->txd.msscof = ctx.l4_offset + 1159 skb->csum_offset; 1160 } 1161 } else { 1162 gdesc->txd.om = 0; 1163 gdesc->txd.msscof = 0; 1164 } 1165 num_pkts = 1; 1166 } 1167 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts); 1168 tx_num_deferred += num_pkts; 1169 1170 if (skb_vlan_tag_present(skb)) { 1171 gdesc->txd.ti = 1; 1172 gdesc->txd.tci = skb_vlan_tag_get(skb); 1173 } 1174 1175 /* Ensure that the write to (&gdesc->txd)->gen will be observed after 1176 * all other writes to &gdesc->txd. 1177 */ 1178 dma_wmb(); 1179 1180 /* finally flips the GEN bit of the SOP desc. */ 1181 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1182 VMXNET3_TXD_GEN); 1183#ifdef __BIG_ENDIAN_BITFIELD 1184 /* Finished updating in bitfields of Tx Desc, so write them in original 1185 * place. 1186 */ 1187 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1188 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1189 gdesc = ctx.sop_txd; 1190#endif 1191 netdev_dbg(adapter->netdev, 1192 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1193 (u32)(ctx.sop_txd - 1194 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1195 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1196 1197 spin_unlock_irqrestore(&tq->tx_lock, flags); 1198 1199 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) { 1200 tq->shared->txNumDeferred = 0; 1201 VMXNET3_WRITE_BAR0_REG(adapter, 1202 VMXNET3_REG_TXPROD + tq->qid * 8, 1203 tq->tx_ring.next2fill); 1204 } 1205 1206 return NETDEV_TX_OK; 1207 1208unlock_drop_pkt: 1209 spin_unlock_irqrestore(&tq->tx_lock, flags); 1210drop_pkt: 1211 tq->stats.drop_total++; 1212 dev_kfree_skb_any(skb); 1213 return NETDEV_TX_OK; 1214} 1215 1216 1217static netdev_tx_t 1218vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1219{ 1220 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1221 1222 BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 1223 return vmxnet3_tq_xmit(skb, 1224 &adapter->tx_queue[skb->queue_mapping], 1225 adapter, netdev); 1226} 1227 1228 1229static void 1230vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1231 struct sk_buff *skb, 1232 union Vmxnet3_GenericDesc *gdesc) 1233{ 1234 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1235 if (gdesc->rcd.v4 && 1236 (le32_to_cpu(gdesc->dword[3]) & 1237 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) { 1238 skb->ip_summed = CHECKSUM_UNNECESSARY; 1239 if ((le32_to_cpu(gdesc->dword[0]) & 1240 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) { 1241 skb->csum_level = 1; 1242 } 1243 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) && 1244 !(le32_to_cpu(gdesc->dword[0]) & 1245 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1246 WARN_ON_ONCE(gdesc->rcd.frg && 1247 !(le32_to_cpu(gdesc->dword[0]) & 1248 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1249 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) & 1250 (1 << VMXNET3_RCD_TUC_SHIFT))) { 1251 skb->ip_summed = CHECKSUM_UNNECESSARY; 1252 if ((le32_to_cpu(gdesc->dword[0]) & 1253 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) { 1254 skb->csum_level = 1; 1255 } 1256 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) && 1257 !(le32_to_cpu(gdesc->dword[0]) & 1258 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1259 WARN_ON_ONCE(gdesc->rcd.frg && 1260 !(le32_to_cpu(gdesc->dword[0]) & 1261 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1262 } else { 1263 if (gdesc->rcd.csum) { 1264 skb->csum = htons(gdesc->rcd.csum); 1265 skb->ip_summed = CHECKSUM_PARTIAL; 1266 } else { 1267 skb_checksum_none_assert(skb); 1268 } 1269 } 1270 } else { 1271 skb_checksum_none_assert(skb); 1272 } 1273} 1274 1275 1276static void 1277vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1278 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1279{ 1280 rq->stats.drop_err++; 1281 if (!rcd->fcs) 1282 rq->stats.drop_fcs++; 1283 1284 rq->stats.drop_total++; 1285 1286 /* 1287 * We do not unmap and chain the rx buffer to the skb. 1288 * We basically pretend this buffer is not used and will be recycled 1289 * by vmxnet3_rq_alloc_rx_buf() 1290 */ 1291 1292 /* 1293 * ctx->skb may be NULL if this is the first and the only one 1294 * desc for the pkt 1295 */ 1296 if (ctx->skb) 1297 dev_kfree_skb_irq(ctx->skb); 1298 1299 ctx->skb = NULL; 1300} 1301 1302 1303static u32 1304vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb, 1305 union Vmxnet3_GenericDesc *gdesc) 1306{ 1307 u32 hlen, maplen; 1308 union { 1309 void *ptr; 1310 struct ethhdr *eth; 1311 struct vlan_ethhdr *veth; 1312 struct iphdr *ipv4; 1313 struct ipv6hdr *ipv6; 1314 struct tcphdr *tcp; 1315 } hdr; 1316 BUG_ON(gdesc->rcd.tcp == 0); 1317 1318 maplen = skb_headlen(skb); 1319 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen)) 1320 return 0; 1321 1322 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) || 1323 skb->protocol == cpu_to_be16(ETH_P_8021AD)) 1324 hlen = sizeof(struct vlan_ethhdr); 1325 else 1326 hlen = sizeof(struct ethhdr); 1327 1328 hdr.eth = eth_hdr(skb); 1329 if (gdesc->rcd.v4) { 1330 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) && 1331 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP)); 1332 hdr.ptr += hlen; 1333 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP); 1334 hlen = hdr.ipv4->ihl << 2; 1335 hdr.ptr += hdr.ipv4->ihl << 2; 1336 } else if (gdesc->rcd.v6) { 1337 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) && 1338 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6)); 1339 hdr.ptr += hlen; 1340 /* Use an estimated value, since we also need to handle 1341 * TSO case. 1342 */ 1343 if (hdr.ipv6->nexthdr != IPPROTO_TCP) 1344 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr); 1345 hlen = sizeof(struct ipv6hdr); 1346 hdr.ptr += sizeof(struct ipv6hdr); 1347 } else { 1348 /* Non-IP pkt, dont estimate header length */ 1349 return 0; 1350 } 1351 1352 if (hlen + sizeof(struct tcphdr) > maplen) 1353 return 0; 1354 1355 return (hlen + (hdr.tcp->doff << 2)); 1356} 1357 1358static int 1359vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1360 struct vmxnet3_adapter *adapter, int quota) 1361{ 1362 static const u32 rxprod_reg[2] = { 1363 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1364 }; 1365 u32 num_pkts = 0; 1366 bool skip_page_frags = false; 1367 bool encap_lro = false; 1368 struct Vmxnet3_RxCompDesc *rcd; 1369 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1370 u16 segCnt = 0, mss = 0; 1371#ifdef __BIG_ENDIAN_BITFIELD 1372 struct Vmxnet3_RxDesc rxCmdDesc; 1373 struct Vmxnet3_RxCompDesc rxComp; 1374#endif 1375 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1376 &rxComp); 1377 while (rcd->gen == rq->comp_ring.gen) { 1378 struct vmxnet3_rx_buf_info *rbi; 1379 struct sk_buff *skb, *new_skb = NULL; 1380 struct page *new_page = NULL; 1381 dma_addr_t new_dma_addr; 1382 int num_to_alloc; 1383 struct Vmxnet3_RxDesc *rxd; 1384 u32 idx, ring_idx; 1385 struct vmxnet3_cmd_ring *ring = NULL; 1386 if (num_pkts >= quota) { 1387 /* we may stop even before we see the EOP desc of 1388 * the current pkt 1389 */ 1390 break; 1391 } 1392 1393 /* Prevent any rcd field from being (speculatively) read before 1394 * rcd->gen is read. 1395 */ 1396 dma_rmb(); 1397 1398 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 && 1399 rcd->rqID != rq->dataRingQid); 1400 idx = rcd->rxdIdx; 1401 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID); 1402 ring = rq->rx_ring + ring_idx; 1403 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1404 &rxCmdDesc); 1405 rbi = rq->buf_info[ring_idx] + idx; 1406 1407 BUG_ON(rxd->addr != rbi->dma_addr || 1408 rxd->len != rbi->len); 1409 1410 if (unlikely(rcd->eop && rcd->err)) { 1411 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1412 goto rcd_done; 1413 } 1414 1415 if (rcd->sop) { /* first buf of the pkt */ 1416 bool rxDataRingUsed; 1417 u16 len; 1418 1419 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1420 (rcd->rqID != rq->qid && 1421 rcd->rqID != rq->dataRingQid)); 1422 1423 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1424 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1425 1426 if (unlikely(rcd->len == 0)) { 1427 /* Pretend the rx buffer is skipped. */ 1428 BUG_ON(!(rcd->sop && rcd->eop)); 1429 netdev_dbg(adapter->netdev, 1430 "rxRing[%u][%u] 0 length\n", 1431 ring_idx, idx); 1432 goto rcd_done; 1433 } 1434 1435 skip_page_frags = false; 1436 ctx->skb = rbi->skb; 1437 1438 rxDataRingUsed = 1439 VMXNET3_RX_DATA_RING(adapter, rcd->rqID); 1440 len = rxDataRingUsed ? rcd->len : rbi->len; 1441 new_skb = netdev_alloc_skb_ip_align(adapter->netdev, 1442 len); 1443 if (new_skb == NULL) { 1444 /* Skb allocation failed, do not handover this 1445 * skb to stack. Reuse it. Drop the existing pkt 1446 */ 1447 rq->stats.rx_buf_alloc_failure++; 1448 ctx->skb = NULL; 1449 rq->stats.drop_total++; 1450 skip_page_frags = true; 1451 goto rcd_done; 1452 } 1453 1454 if (rxDataRingUsed) { 1455 size_t sz; 1456 1457 BUG_ON(rcd->len > rq->data_ring.desc_size); 1458 1459 ctx->skb = new_skb; 1460 sz = rcd->rxdIdx * rq->data_ring.desc_size; 1461 memcpy(new_skb->data, 1462 &rq->data_ring.base[sz], rcd->len); 1463 } else { 1464 ctx->skb = rbi->skb; 1465 1466 new_dma_addr = 1467 dma_map_single(&adapter->pdev->dev, 1468 new_skb->data, rbi->len, 1469 PCI_DMA_FROMDEVICE); 1470 if (dma_mapping_error(&adapter->pdev->dev, 1471 new_dma_addr)) { 1472 dev_kfree_skb(new_skb); 1473 /* Skb allocation failed, do not 1474 * handover this skb to stack. Reuse 1475 * it. Drop the existing pkt. 1476 */ 1477 rq->stats.rx_buf_alloc_failure++; 1478 ctx->skb = NULL; 1479 rq->stats.drop_total++; 1480 skip_page_frags = true; 1481 goto rcd_done; 1482 } 1483 1484 dma_unmap_single(&adapter->pdev->dev, 1485 rbi->dma_addr, 1486 rbi->len, 1487 PCI_DMA_FROMDEVICE); 1488 1489 /* Immediate refill */ 1490 rbi->skb = new_skb; 1491 rbi->dma_addr = new_dma_addr; 1492 rxd->addr = cpu_to_le64(rbi->dma_addr); 1493 rxd->len = rbi->len; 1494 } 1495 1496#ifdef VMXNET3_RSS 1497 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE && 1498 (adapter->netdev->features & NETIF_F_RXHASH)) 1499 skb_set_hash(ctx->skb, 1500 le32_to_cpu(rcd->rssHash), 1501 PKT_HASH_TYPE_L3); 1502#endif 1503 skb_put(ctx->skb, rcd->len); 1504 1505 if (VMXNET3_VERSION_GE_2(adapter) && 1506 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) { 1507 struct Vmxnet3_RxCompDescExt *rcdlro; 1508 union Vmxnet3_GenericDesc *gdesc; 1509 1510 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd; 1511 gdesc = (union Vmxnet3_GenericDesc *)rcd; 1512 1513 segCnt = rcdlro->segCnt; 1514 WARN_ON_ONCE(segCnt == 0); 1515 mss = rcdlro->mss; 1516 if (unlikely(segCnt <= 1)) 1517 segCnt = 0; 1518 encap_lro = (le32_to_cpu(gdesc->dword[0]) & 1519 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)); 1520 } else { 1521 segCnt = 0; 1522 } 1523 } else { 1524 BUG_ON(ctx->skb == NULL && !skip_page_frags); 1525 1526 /* non SOP buffer must be type 1 in most cases */ 1527 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1528 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1529 1530 /* If an sop buffer was dropped, skip all 1531 * following non-sop fragments. They will be reused. 1532 */ 1533 if (skip_page_frags) 1534 goto rcd_done; 1535 1536 if (rcd->len) { 1537 new_page = alloc_page(GFP_ATOMIC); 1538 /* Replacement page frag could not be allocated. 1539 * Reuse this page. Drop the pkt and free the 1540 * skb which contained this page as a frag. Skip 1541 * processing all the following non-sop frags. 1542 */ 1543 if (unlikely(!new_page)) { 1544 rq->stats.rx_buf_alloc_failure++; 1545 dev_kfree_skb(ctx->skb); 1546 ctx->skb = NULL; 1547 skip_page_frags = true; 1548 goto rcd_done; 1549 } 1550 new_dma_addr = dma_map_page(&adapter->pdev->dev, 1551 new_page, 1552 0, PAGE_SIZE, 1553 PCI_DMA_FROMDEVICE); 1554 if (dma_mapping_error(&adapter->pdev->dev, 1555 new_dma_addr)) { 1556 put_page(new_page); 1557 rq->stats.rx_buf_alloc_failure++; 1558 dev_kfree_skb(ctx->skb); 1559 ctx->skb = NULL; 1560 skip_page_frags = true; 1561 goto rcd_done; 1562 } 1563 1564 dma_unmap_page(&adapter->pdev->dev, 1565 rbi->dma_addr, rbi->len, 1566 PCI_DMA_FROMDEVICE); 1567 1568 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1569 1570 /* Immediate refill */ 1571 rbi->page = new_page; 1572 rbi->dma_addr = new_dma_addr; 1573 rxd->addr = cpu_to_le64(rbi->dma_addr); 1574 rxd->len = rbi->len; 1575 } 1576 } 1577 1578 1579 skb = ctx->skb; 1580 if (rcd->eop) { 1581 u32 mtu = adapter->netdev->mtu; 1582 skb->len += skb->data_len; 1583 1584 vmxnet3_rx_csum(adapter, skb, 1585 (union Vmxnet3_GenericDesc *)rcd); 1586 skb->protocol = eth_type_trans(skb, adapter->netdev); 1587 if ((!rcd->tcp && !encap_lro) || 1588 !(adapter->netdev->features & NETIF_F_LRO)) 1589 goto not_lro; 1590 1591 if (segCnt != 0 && mss != 0) { 1592 skb_shinfo(skb)->gso_type = rcd->v4 ? 1593 SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1594 skb_shinfo(skb)->gso_size = mss; 1595 skb_shinfo(skb)->gso_segs = segCnt; 1596 } else if ((segCnt != 0 || skb->len > mtu) && !encap_lro) { 1597 u32 hlen; 1598 1599 hlen = vmxnet3_get_hdr_len(adapter, skb, 1600 (union Vmxnet3_GenericDesc *)rcd); 1601 if (hlen == 0) 1602 goto not_lro; 1603 1604 skb_shinfo(skb)->gso_type = 1605 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1606 if (segCnt != 0) { 1607 skb_shinfo(skb)->gso_segs = segCnt; 1608 skb_shinfo(skb)->gso_size = 1609 DIV_ROUND_UP(skb->len - 1610 hlen, segCnt); 1611 } else { 1612 skb_shinfo(skb)->gso_size = mtu - hlen; 1613 } 1614 } 1615not_lro: 1616 if (unlikely(rcd->ts)) 1617 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci); 1618 1619 if (adapter->netdev->features & NETIF_F_LRO) 1620 netif_receive_skb(skb); 1621 else 1622 napi_gro_receive(&rq->napi, skb); 1623 1624 ctx->skb = NULL; 1625 encap_lro = false; 1626 num_pkts++; 1627 } 1628 1629rcd_done: 1630 /* device may have skipped some rx descs */ 1631 ring->next2comp = idx; 1632 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 1633 ring = rq->rx_ring + ring_idx; 1634 1635 /* Ensure that the writes to rxd->gen bits will be observed 1636 * after all other writes to rxd objects. 1637 */ 1638 dma_wmb(); 1639 1640 while (num_to_alloc) { 1641 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 1642 &rxCmdDesc); 1643 BUG_ON(!rxd->addr); 1644 1645 /* Recv desc is ready to be used by the device */ 1646 rxd->gen = ring->gen; 1647 vmxnet3_cmd_ring_adv_next2fill(ring); 1648 num_to_alloc--; 1649 } 1650 1651 /* if needed, update the register */ 1652 if (unlikely(rq->shared->updateRxProd)) { 1653 VMXNET3_WRITE_BAR0_REG(adapter, 1654 rxprod_reg[ring_idx] + rq->qid * 8, 1655 ring->next2fill); 1656 } 1657 1658 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1659 vmxnet3_getRxComp(rcd, 1660 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1661 } 1662 1663 return num_pkts; 1664} 1665 1666 1667static void 1668vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1669 struct vmxnet3_adapter *adapter) 1670{ 1671 u32 i, ring_idx; 1672 struct Vmxnet3_RxDesc *rxd; 1673 1674 /* ring has already been cleaned up */ 1675 if (!rq->rx_ring[0].base) 1676 return; 1677 1678 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1679 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1680#ifdef __BIG_ENDIAN_BITFIELD 1681 struct Vmxnet3_RxDesc rxDesc; 1682#endif 1683 vmxnet3_getRxDesc(rxd, 1684 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1685 1686 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1687 rq->buf_info[ring_idx][i].skb) { 1688 dma_unmap_single(&adapter->pdev->dev, rxd->addr, 1689 rxd->len, PCI_DMA_FROMDEVICE); 1690 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1691 rq->buf_info[ring_idx][i].skb = NULL; 1692 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1693 rq->buf_info[ring_idx][i].page) { 1694 dma_unmap_page(&adapter->pdev->dev, rxd->addr, 1695 rxd->len, PCI_DMA_FROMDEVICE); 1696 put_page(rq->buf_info[ring_idx][i].page); 1697 rq->buf_info[ring_idx][i].page = NULL; 1698 } 1699 } 1700 1701 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1702 rq->rx_ring[ring_idx].next2fill = 1703 rq->rx_ring[ring_idx].next2comp = 0; 1704 } 1705 1706 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1707 rq->comp_ring.next2proc = 0; 1708} 1709 1710 1711static void 1712vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 1713{ 1714 int i; 1715 1716 for (i = 0; i < adapter->num_rx_queues; i++) 1717 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 1718} 1719 1720 1721static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1722 struct vmxnet3_adapter *adapter) 1723{ 1724 int i; 1725 int j; 1726 1727 /* all rx buffers must have already been freed */ 1728 for (i = 0; i < 2; i++) { 1729 if (rq->buf_info[i]) { 1730 for (j = 0; j < rq->rx_ring[i].size; j++) 1731 BUG_ON(rq->buf_info[i][j].page != NULL); 1732 } 1733 } 1734 1735 1736 for (i = 0; i < 2; i++) { 1737 if (rq->rx_ring[i].base) { 1738 dma_free_coherent(&adapter->pdev->dev, 1739 rq->rx_ring[i].size 1740 * sizeof(struct Vmxnet3_RxDesc), 1741 rq->rx_ring[i].base, 1742 rq->rx_ring[i].basePA); 1743 rq->rx_ring[i].base = NULL; 1744 } 1745 } 1746 1747 if (rq->data_ring.base) { 1748 dma_free_coherent(&adapter->pdev->dev, 1749 rq->rx_ring[0].size * rq->data_ring.desc_size, 1750 rq->data_ring.base, rq->data_ring.basePA); 1751 rq->data_ring.base = NULL; 1752 } 1753 1754 if (rq->comp_ring.base) { 1755 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size 1756 * sizeof(struct Vmxnet3_RxCompDesc), 1757 rq->comp_ring.base, rq->comp_ring.basePA); 1758 rq->comp_ring.base = NULL; 1759 } 1760 1761 if (rq->buf_info[0]) { 1762 size_t sz = sizeof(struct vmxnet3_rx_buf_info) * 1763 (rq->rx_ring[0].size + rq->rx_ring[1].size); 1764 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0], 1765 rq->buf_info_pa); 1766 rq->buf_info[0] = rq->buf_info[1] = NULL; 1767 } 1768} 1769 1770static void 1771vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter) 1772{ 1773 int i; 1774 1775 for (i = 0; i < adapter->num_rx_queues; i++) { 1776 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 1777 1778 if (rq->data_ring.base) { 1779 dma_free_coherent(&adapter->pdev->dev, 1780 (rq->rx_ring[0].size * 1781 rq->data_ring.desc_size), 1782 rq->data_ring.base, 1783 rq->data_ring.basePA); 1784 rq->data_ring.base = NULL; 1785 rq->data_ring.desc_size = 0; 1786 } 1787 } 1788} 1789 1790static int 1791vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1792 struct vmxnet3_adapter *adapter) 1793{ 1794 int i; 1795 1796 /* initialize buf_info */ 1797 for (i = 0; i < rq->rx_ring[0].size; i++) { 1798 1799 /* 1st buf for a pkt is skbuff */ 1800 if (i % adapter->rx_buf_per_pkt == 0) { 1801 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1802 rq->buf_info[0][i].len = adapter->skb_buf_size; 1803 } else { /* subsequent bufs for a pkt is frag */ 1804 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1805 rq->buf_info[0][i].len = PAGE_SIZE; 1806 } 1807 } 1808 for (i = 0; i < rq->rx_ring[1].size; i++) { 1809 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1810 rq->buf_info[1][i].len = PAGE_SIZE; 1811 } 1812 1813 /* reset internal state and allocate buffers for both rings */ 1814 for (i = 0; i < 2; i++) { 1815 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1816 1817 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1818 sizeof(struct Vmxnet3_RxDesc)); 1819 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1820 } 1821 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1822 adapter) == 0) { 1823 /* at least has 1 rx buffer for the 1st ring */ 1824 return -ENOMEM; 1825 } 1826 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1827 1828 /* reset the comp ring */ 1829 rq->comp_ring.next2proc = 0; 1830 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1831 sizeof(struct Vmxnet3_RxCompDesc)); 1832 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1833 1834 /* reset rxctx */ 1835 rq->rx_ctx.skb = NULL; 1836 1837 /* stats are not reset */ 1838 return 0; 1839} 1840 1841 1842static int 1843vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 1844{ 1845 int i, err = 0; 1846 1847 for (i = 0; i < adapter->num_rx_queues; i++) { 1848 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 1849 if (unlikely(err)) { 1850 dev_err(&adapter->netdev->dev, "%s: failed to " 1851 "initialize rx queue%i\n", 1852 adapter->netdev->name, i); 1853 break; 1854 } 1855 } 1856 return err; 1857 1858} 1859 1860 1861static int 1862vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1863{ 1864 int i; 1865 size_t sz; 1866 struct vmxnet3_rx_buf_info *bi; 1867 1868 for (i = 0; i < 2; i++) { 1869 1870 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1871 rq->rx_ring[i].base = dma_alloc_coherent( 1872 &adapter->pdev->dev, sz, 1873 &rq->rx_ring[i].basePA, 1874 GFP_KERNEL); 1875 if (!rq->rx_ring[i].base) { 1876 netdev_err(adapter->netdev, 1877 "failed to allocate rx ring %d\n", i); 1878 goto err; 1879 } 1880 } 1881 1882 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) { 1883 sz = rq->rx_ring[0].size * rq->data_ring.desc_size; 1884 rq->data_ring.base = 1885 dma_alloc_coherent(&adapter->pdev->dev, sz, 1886 &rq->data_ring.basePA, 1887 GFP_KERNEL); 1888 if (!rq->data_ring.base) { 1889 netdev_err(adapter->netdev, 1890 "rx data ring will be disabled\n"); 1891 adapter->rxdataring_enabled = false; 1892 } 1893 } else { 1894 rq->data_ring.base = NULL; 1895 rq->data_ring.desc_size = 0; 1896 } 1897 1898 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1899 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz, 1900 &rq->comp_ring.basePA, 1901 GFP_KERNEL); 1902 if (!rq->comp_ring.base) { 1903 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n"); 1904 goto err; 1905 } 1906 1907 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1908 rq->rx_ring[1].size); 1909 bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa, 1910 GFP_KERNEL); 1911 if (!bi) 1912 goto err; 1913 1914 rq->buf_info[0] = bi; 1915 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1916 1917 return 0; 1918 1919err: 1920 vmxnet3_rq_destroy(rq, adapter); 1921 return -ENOMEM; 1922} 1923 1924 1925static int 1926vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 1927{ 1928 int i, err = 0; 1929 1930 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 1931 1932 for (i = 0; i < adapter->num_rx_queues; i++) { 1933 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 1934 if (unlikely(err)) { 1935 dev_err(&adapter->netdev->dev, 1936 "%s: failed to create rx queue%i\n", 1937 adapter->netdev->name, i); 1938 goto err_out; 1939 } 1940 } 1941 1942 if (!adapter->rxdataring_enabled) 1943 vmxnet3_rq_destroy_all_rxdataring(adapter); 1944 1945 return err; 1946err_out: 1947 vmxnet3_rq_destroy_all(adapter); 1948 return err; 1949 1950} 1951 1952/* Multiple queue aware polling function for tx and rx */ 1953 1954static int 1955vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1956{ 1957 int rcd_done = 0, i; 1958 if (unlikely(adapter->shared->ecr)) 1959 vmxnet3_process_events(adapter); 1960 for (i = 0; i < adapter->num_tx_queues; i++) 1961 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1962 1963 for (i = 0; i < adapter->num_rx_queues; i++) 1964 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 1965 adapter, budget); 1966 return rcd_done; 1967} 1968 1969 1970static int 1971vmxnet3_poll(struct napi_struct *napi, int budget) 1972{ 1973 struct vmxnet3_rx_queue *rx_queue = container_of(napi, 1974 struct vmxnet3_rx_queue, napi); 1975 int rxd_done; 1976 1977 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1978 1979 if (rxd_done < budget) { 1980 napi_complete_done(napi, rxd_done); 1981 vmxnet3_enable_all_intrs(rx_queue->adapter); 1982 } 1983 return rxd_done; 1984} 1985 1986/* 1987 * NAPI polling function for MSI-X mode with multiple Rx queues 1988 * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 1989 */ 1990 1991static int 1992vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 1993{ 1994 struct vmxnet3_rx_queue *rq = container_of(napi, 1995 struct vmxnet3_rx_queue, napi); 1996 struct vmxnet3_adapter *adapter = rq->adapter; 1997 int rxd_done; 1998 1999 /* When sharing interrupt with corresponding tx queue, process 2000 * tx completions in that queue as well 2001 */ 2002 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 2003 struct vmxnet3_tx_queue *tq = 2004 &adapter->tx_queue[rq - adapter->rx_queue]; 2005 vmxnet3_tq_tx_complete(tq, adapter); 2006 } 2007 2008 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 2009 2010 if (rxd_done < budget) { 2011 napi_complete_done(napi, rxd_done); 2012 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 2013 } 2014 return rxd_done; 2015} 2016 2017 2018#ifdef CONFIG_PCI_MSI 2019 2020/* 2021 * Handle completion interrupts on tx queues 2022 * Returns whether or not the intr is handled 2023 */ 2024 2025static irqreturn_t 2026vmxnet3_msix_tx(int irq, void *data) 2027{ 2028 struct vmxnet3_tx_queue *tq = data; 2029 struct vmxnet3_adapter *adapter = tq->adapter; 2030 2031 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 2032 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 2033 2034 /* Handle the case where only one irq is allocate for all tx queues */ 2035 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 2036 int i; 2037 for (i = 0; i < adapter->num_tx_queues; i++) { 2038 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 2039 vmxnet3_tq_tx_complete(txq, adapter); 2040 } 2041 } else { 2042 vmxnet3_tq_tx_complete(tq, adapter); 2043 } 2044 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 2045 2046 return IRQ_HANDLED; 2047} 2048 2049 2050/* 2051 * Handle completion interrupts on rx queues. Returns whether or not the 2052 * intr is handled 2053 */ 2054 2055static irqreturn_t 2056vmxnet3_msix_rx(int irq, void *data) 2057{ 2058 struct vmxnet3_rx_queue *rq = data; 2059 struct vmxnet3_adapter *adapter = rq->adapter; 2060 2061 /* disable intr if needed */ 2062 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 2063 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 2064 napi_schedule(&rq->napi); 2065 2066 return IRQ_HANDLED; 2067} 2068 2069/* 2070 *---------------------------------------------------------------------------- 2071 * 2072 * vmxnet3_msix_event -- 2073 * 2074 * vmxnet3 msix event intr handler 2075 * 2076 * Result: 2077 * whether or not the intr is handled 2078 * 2079 *---------------------------------------------------------------------------- 2080 */ 2081 2082static irqreturn_t 2083vmxnet3_msix_event(int irq, void *data) 2084{ 2085 struct net_device *dev = data; 2086 struct vmxnet3_adapter *adapter = netdev_priv(dev); 2087 2088 /* disable intr if needed */ 2089 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 2090 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 2091 2092 if (adapter->shared->ecr) 2093 vmxnet3_process_events(adapter); 2094 2095 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 2096 2097 return IRQ_HANDLED; 2098} 2099 2100#endif /* CONFIG_PCI_MSI */ 2101 2102 2103/* Interrupt handler for vmxnet3 */ 2104static irqreturn_t 2105vmxnet3_intr(int irq, void *dev_id) 2106{ 2107 struct net_device *dev = dev_id; 2108 struct vmxnet3_adapter *adapter = netdev_priv(dev); 2109 2110 if (adapter->intr.type == VMXNET3_IT_INTX) { 2111 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 2112 if (unlikely(icr == 0)) 2113 /* not ours */ 2114 return IRQ_NONE; 2115 } 2116 2117 2118 /* disable intr if needed */ 2119 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 2120 vmxnet3_disable_all_intrs(adapter); 2121 2122 napi_schedule(&adapter->rx_queue[0].napi); 2123 2124 return IRQ_HANDLED; 2125} 2126 2127#ifdef CONFIG_NET_POLL_CONTROLLER 2128 2129/* netpoll callback. */ 2130static void 2131vmxnet3_netpoll(struct net_device *netdev) 2132{ 2133 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2134 2135 switch (adapter->intr.type) { 2136#ifdef CONFIG_PCI_MSI 2137 case VMXNET3_IT_MSIX: { 2138 int i; 2139 for (i = 0; i < adapter->num_rx_queues; i++) 2140 vmxnet3_msix_rx(0, &adapter->rx_queue[i]); 2141 break; 2142 } 2143#endif 2144 case VMXNET3_IT_MSI: 2145 default: 2146 vmxnet3_intr(0, adapter->netdev); 2147 break; 2148 } 2149 2150} 2151#endif /* CONFIG_NET_POLL_CONTROLLER */ 2152 2153static int 2154vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 2155{ 2156 struct vmxnet3_intr *intr = &adapter->intr; 2157 int err = 0, i; 2158 int vector = 0; 2159 2160#ifdef CONFIG_PCI_MSI 2161 if (adapter->intr.type == VMXNET3_IT_MSIX) { 2162 for (i = 0; i < adapter->num_tx_queues; i++) { 2163 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2164 sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 2165 adapter->netdev->name, vector); 2166 err = request_irq( 2167 intr->msix_entries[vector].vector, 2168 vmxnet3_msix_tx, 0, 2169 adapter->tx_queue[i].name, 2170 &adapter->tx_queue[i]); 2171 } else { 2172 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 2173 adapter->netdev->name, vector); 2174 } 2175 if (err) { 2176 dev_err(&adapter->netdev->dev, 2177 "Failed to request irq for MSIX, %s, " 2178 "error %d\n", 2179 adapter->tx_queue[i].name, err); 2180 return err; 2181 } 2182 2183 /* Handle the case where only 1 MSIx was allocated for 2184 * all tx queues */ 2185 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 2186 for (; i < adapter->num_tx_queues; i++) 2187 adapter->tx_queue[i].comp_ring.intr_idx 2188 = vector; 2189 vector++; 2190 break; 2191 } else { 2192 adapter->tx_queue[i].comp_ring.intr_idx 2193 = vector++; 2194 } 2195 } 2196 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 2197 vector = 0; 2198 2199 for (i = 0; i < adapter->num_rx_queues; i++) { 2200 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 2201 sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 2202 adapter->netdev->name, vector); 2203 else 2204 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 2205 adapter->netdev->name, vector); 2206 err = request_irq(intr->msix_entries[vector].vector, 2207 vmxnet3_msix_rx, 0, 2208 adapter->rx_queue[i].name, 2209 &(adapter->rx_queue[i])); 2210 if (err) { 2211 netdev_err(adapter->netdev, 2212 "Failed to request irq for MSIX, " 2213 "%s, error %d\n", 2214 adapter->rx_queue[i].name, err); 2215 return err; 2216 } 2217 2218 adapter->rx_queue[i].comp_ring.intr_idx = vector++; 2219 } 2220 2221 sprintf(intr->event_msi_vector_name, "%s-event-%d", 2222 adapter->netdev->name, vector); 2223 err = request_irq(intr->msix_entries[vector].vector, 2224 vmxnet3_msix_event, 0, 2225 intr->event_msi_vector_name, adapter->netdev); 2226 intr->event_intr_idx = vector; 2227 2228 } else if (intr->type == VMXNET3_IT_MSI) { 2229 adapter->num_rx_queues = 1; 2230 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 2231 adapter->netdev->name, adapter->netdev); 2232 } else { 2233#endif 2234 adapter->num_rx_queues = 1; 2235 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 2236 IRQF_SHARED, adapter->netdev->name, 2237 adapter->netdev); 2238#ifdef CONFIG_PCI_MSI 2239 } 2240#endif 2241 intr->num_intrs = vector + 1; 2242 if (err) { 2243 netdev_err(adapter->netdev, 2244 "Failed to request irq (intr type:%d), error %d\n", 2245 intr->type, err); 2246 } else { 2247 /* Number of rx queues will not change after this */ 2248 for (i = 0; i < adapter->num_rx_queues; i++) { 2249 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2250 rq->qid = i; 2251 rq->qid2 = i + adapter->num_rx_queues; 2252 rq->dataRingQid = i + 2 * adapter->num_rx_queues; 2253 } 2254 2255 /* init our intr settings */ 2256 for (i = 0; i < intr->num_intrs; i++) 2257 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 2258 if (adapter->intr.type != VMXNET3_IT_MSIX) { 2259 adapter->intr.event_intr_idx = 0; 2260 for (i = 0; i < adapter->num_tx_queues; i++) 2261 adapter->tx_queue[i].comp_ring.intr_idx = 0; 2262 adapter->rx_queue[0].comp_ring.intr_idx = 0; 2263 } 2264 2265 netdev_info(adapter->netdev, 2266 "intr type %u, mode %u, %u vectors allocated\n", 2267 intr->type, intr->mask_mode, intr->num_intrs); 2268 } 2269 2270 return err; 2271} 2272 2273 2274static void 2275vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 2276{ 2277 struct vmxnet3_intr *intr = &adapter->intr; 2278 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 2279 2280 switch (intr->type) { 2281#ifdef CONFIG_PCI_MSI 2282 case VMXNET3_IT_MSIX: 2283 { 2284 int i, vector = 0; 2285 2286 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2287 for (i = 0; i < adapter->num_tx_queues; i++) { 2288 free_irq(intr->msix_entries[vector++].vector, 2289 &(adapter->tx_queue[i])); 2290 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 2291 break; 2292 } 2293 } 2294 2295 for (i = 0; i < adapter->num_rx_queues; i++) { 2296 free_irq(intr->msix_entries[vector++].vector, 2297 &(adapter->rx_queue[i])); 2298 } 2299 2300 free_irq(intr->msix_entries[vector].vector, 2301 adapter->netdev); 2302 BUG_ON(vector >= intr->num_intrs); 2303 break; 2304 } 2305#endif 2306 case VMXNET3_IT_MSI: 2307 free_irq(adapter->pdev->irq, adapter->netdev); 2308 break; 2309 case VMXNET3_IT_INTX: 2310 free_irq(adapter->pdev->irq, adapter->netdev); 2311 break; 2312 default: 2313 BUG(); 2314 } 2315} 2316 2317 2318static void 2319vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 2320{ 2321 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2322 u16 vid; 2323 2324 /* allow untagged pkts */ 2325 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 2326 2327 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2328 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2329} 2330 2331 2332static int 2333vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 2334{ 2335 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2336 2337 if (!(netdev->flags & IFF_PROMISC)) { 2338 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2339 unsigned long flags; 2340 2341 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2342 spin_lock_irqsave(&adapter->cmd_lock, flags); 2343 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2344 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2345 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2346 } 2347 2348 set_bit(vid, adapter->active_vlans); 2349 2350 return 0; 2351} 2352 2353 2354static int 2355vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2356{ 2357 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2358 2359 if (!(netdev->flags & IFF_PROMISC)) { 2360 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2361 unsigned long flags; 2362 2363 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 2364 spin_lock_irqsave(&adapter->cmd_lock, flags); 2365 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2366 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2367 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2368 } 2369 2370 clear_bit(vid, adapter->active_vlans); 2371 2372 return 0; 2373} 2374 2375 2376static u8 * 2377vmxnet3_copy_mc(struct net_device *netdev) 2378{ 2379 u8 *buf = NULL; 2380 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 2381 2382 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 2383 if (sz <= 0xffff) { 2384 /* We may be called with BH disabled */ 2385 buf = kmalloc(sz, GFP_ATOMIC); 2386 if (buf) { 2387 struct netdev_hw_addr *ha; 2388 int i = 0; 2389 2390 netdev_for_each_mc_addr(ha, netdev) 2391 memcpy(buf + i++ * ETH_ALEN, ha->addr, 2392 ETH_ALEN); 2393 } 2394 } 2395 return buf; 2396} 2397 2398 2399static void 2400vmxnet3_set_mc(struct net_device *netdev) 2401{ 2402 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2403 unsigned long flags; 2404 struct Vmxnet3_RxFilterConf *rxConf = 2405 &adapter->shared->devRead.rxFilterConf; 2406 u8 *new_table = NULL; 2407 dma_addr_t new_table_pa = 0; 2408 bool new_table_pa_valid = false; 2409 u32 new_mode = VMXNET3_RXM_UCAST; 2410 2411 if (netdev->flags & IFF_PROMISC) { 2412 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2413 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 2414 2415 new_mode |= VMXNET3_RXM_PROMISC; 2416 } else { 2417 vmxnet3_restore_vlan(adapter); 2418 } 2419 2420 if (netdev->flags & IFF_BROADCAST) 2421 new_mode |= VMXNET3_RXM_BCAST; 2422 2423 if (netdev->flags & IFF_ALLMULTI) 2424 new_mode |= VMXNET3_RXM_ALL_MULTI; 2425 else 2426 if (!netdev_mc_empty(netdev)) { 2427 new_table = vmxnet3_copy_mc(netdev); 2428 if (new_table) { 2429 size_t sz = netdev_mc_count(netdev) * ETH_ALEN; 2430 2431 rxConf->mfTableLen = cpu_to_le16(sz); 2432 new_table_pa = dma_map_single( 2433 &adapter->pdev->dev, 2434 new_table, 2435 sz, 2436 PCI_DMA_TODEVICE); 2437 if (!dma_mapping_error(&adapter->pdev->dev, 2438 new_table_pa)) { 2439 new_mode |= VMXNET3_RXM_MCAST; 2440 new_table_pa_valid = true; 2441 rxConf->mfTablePA = cpu_to_le64( 2442 new_table_pa); 2443 } 2444 } 2445 if (!new_table_pa_valid) { 2446 netdev_info(netdev, 2447 "failed to copy mcast list, setting ALL_MULTI\n"); 2448 new_mode |= VMXNET3_RXM_ALL_MULTI; 2449 } 2450 } 2451 2452 if (!(new_mode & VMXNET3_RXM_MCAST)) { 2453 rxConf->mfTableLen = 0; 2454 rxConf->mfTablePA = 0; 2455 } 2456 2457 spin_lock_irqsave(&adapter->cmd_lock, flags); 2458 if (new_mode != rxConf->rxMode) { 2459 rxConf->rxMode = cpu_to_le32(new_mode); 2460 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2461 VMXNET3_CMD_UPDATE_RX_MODE); 2462 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2463 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2464 } 2465 2466 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2467 VMXNET3_CMD_UPDATE_MAC_FILTERS); 2468 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2469 2470 if (new_table_pa_valid) 2471 dma_unmap_single(&adapter->pdev->dev, new_table_pa, 2472 rxConf->mfTableLen, PCI_DMA_TODEVICE); 2473 kfree(new_table); 2474} 2475 2476void 2477vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 2478{ 2479 int i; 2480 2481 for (i = 0; i < adapter->num_rx_queues; i++) 2482 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 2483} 2484 2485 2486/* 2487 * Set up driver_shared based on settings in adapter. 2488 */ 2489 2490static void 2491vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2492{ 2493 struct Vmxnet3_DriverShared *shared = adapter->shared; 2494 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2495 struct Vmxnet3_TxQueueConf *tqc; 2496 struct Vmxnet3_RxQueueConf *rqc; 2497 int i; 2498 2499 memset(shared, 0, sizeof(*shared)); 2500 2501 /* driver settings */ 2502 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2503 devRead->misc.driverInfo.version = cpu_to_le32( 2504 VMXNET3_DRIVER_VERSION_NUM); 2505 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2506 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2507 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2508 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2509 *((u32 *)&devRead->misc.driverInfo.gos)); 2510 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2511 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2512 2513 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa); 2514 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2515 2516 /* set up feature flags */ 2517 if (adapter->netdev->features & NETIF_F_RXCSUM) 2518 devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2519 2520 if (adapter->netdev->features & NETIF_F_LRO) { 2521 devRead->misc.uptFeatures |= UPT1_F_LRO; 2522 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2523 } 2524 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2525 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2526 2527 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL | 2528 NETIF_F_GSO_UDP_TUNNEL_CSUM)) 2529 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD; 2530 2531 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2532 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2533 devRead->misc.queueDescLen = cpu_to_le32( 2534 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 2535 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2536 2537 /* tx queue settings */ 2538 devRead->misc.numTxQueues = adapter->num_tx_queues; 2539 for (i = 0; i < adapter->num_tx_queues; i++) { 2540 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2541 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 2542 tqc = &adapter->tqd_start[i].conf; 2543 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 2544 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 2545 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2546 tqc->ddPA = cpu_to_le64(tq->buf_info_pa); 2547 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 2548 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 2549 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size); 2550 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2551 tqc->ddLen = cpu_to_le32( 2552 sizeof(struct vmxnet3_tx_buf_info) * 2553 tqc->txRingSize); 2554 tqc->intrIdx = tq->comp_ring.intr_idx; 2555 } 2556 2557 /* rx queue settings */ 2558 devRead->misc.numRxQueues = adapter->num_rx_queues; 2559 for (i = 0; i < adapter->num_rx_queues; i++) { 2560 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2561 rqc = &adapter->rqd_start[i].conf; 2562 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 2563 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 2564 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2565 rqc->ddPA = cpu_to_le64(rq->buf_info_pa); 2566 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 2567 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 2568 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2569 rqc->ddLen = cpu_to_le32( 2570 sizeof(struct vmxnet3_rx_buf_info) * 2571 (rqc->rxRingSize[0] + 2572 rqc->rxRingSize[1])); 2573 rqc->intrIdx = rq->comp_ring.intr_idx; 2574 if (VMXNET3_VERSION_GE_3(adapter)) { 2575 rqc->rxDataRingBasePA = 2576 cpu_to_le64(rq->data_ring.basePA); 2577 rqc->rxDataRingDescSize = 2578 cpu_to_le16(rq->data_ring.desc_size); 2579 } 2580 } 2581 2582#ifdef VMXNET3_RSS 2583 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 2584 2585 if (adapter->rss) { 2586 struct UPT1_RSSConf *rssConf = adapter->rss_conf; 2587 2588 devRead->misc.uptFeatures |= UPT1_F_RSS; 2589 devRead->misc.numRxQueues = adapter->num_rx_queues; 2590 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 2591 UPT1_RSS_HASH_TYPE_IPV4 | 2592 UPT1_RSS_HASH_TYPE_TCP_IPV6 | 2593 UPT1_RSS_HASH_TYPE_IPV6; 2594 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 2595 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 2596 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 2597 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey)); 2598 2599 for (i = 0; i < rssConf->indTableSize; i++) 2600 rssConf->indTable[i] = ethtool_rxfh_indir_default( 2601 i, adapter->num_rx_queues); 2602 2603 devRead->rssConfDesc.confVer = 1; 2604 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf)); 2605 devRead->rssConfDesc.confPA = 2606 cpu_to_le64(adapter->rss_conf_pa); 2607 } 2608 2609#endif /* VMXNET3_RSS */ 2610 2611 /* intr settings */ 2612 devRead->intrConf.autoMask = adapter->intr.mask_mode == 2613 VMXNET3_IMM_AUTO; 2614 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2615 for (i = 0; i < adapter->intr.num_intrs; i++) 2616 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2617 2618 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 2619 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2620 2621 /* rx filter settings */ 2622 devRead->rxFilterConf.rxMode = 0; 2623 vmxnet3_restore_vlan(adapter); 2624 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2625 2626 /* the rest are already zeroed */ 2627} 2628 2629static void 2630vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter) 2631{ 2632 struct Vmxnet3_DriverShared *shared = adapter->shared; 2633 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 2634 unsigned long flags; 2635 2636 if (!VMXNET3_VERSION_GE_3(adapter)) 2637 return; 2638 2639 spin_lock_irqsave(&adapter->cmd_lock, flags); 2640 cmdInfo->varConf.confVer = 1; 2641 cmdInfo->varConf.confLen = 2642 cpu_to_le32(sizeof(*adapter->coal_conf)); 2643 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa); 2644 2645 if (adapter->default_coal_mode) { 2646 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2647 VMXNET3_CMD_GET_COALESCE); 2648 } else { 2649 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2650 VMXNET3_CMD_SET_COALESCE); 2651 } 2652 2653 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2654} 2655 2656static void 2657vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter) 2658{ 2659 struct Vmxnet3_DriverShared *shared = adapter->shared; 2660 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 2661 unsigned long flags; 2662 2663 if (!VMXNET3_VERSION_GE_4(adapter)) 2664 return; 2665 2666 spin_lock_irqsave(&adapter->cmd_lock, flags); 2667 2668 if (adapter->default_rss_fields) { 2669 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2670 VMXNET3_CMD_GET_RSS_FIELDS); 2671 adapter->rss_fields = 2672 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2673 } else { 2674 cmdInfo->setRssFields = adapter->rss_fields; 2675 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2676 VMXNET3_CMD_SET_RSS_FIELDS); 2677 /* Not all requested RSS may get applied, so get and 2678 * cache what was actually applied. 2679 */ 2680 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2681 VMXNET3_CMD_GET_RSS_FIELDS); 2682 adapter->rss_fields = 2683 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2684 } 2685 2686 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2687} 2688 2689int 2690vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2691{ 2692 int err, i; 2693 u32 ret; 2694 unsigned long flags; 2695 2696 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 2697 " ring sizes %u %u %u\n", adapter->netdev->name, 2698 adapter->skb_buf_size, adapter->rx_buf_per_pkt, 2699 adapter->tx_queue[0].tx_ring.size, 2700 adapter->rx_queue[0].rx_ring[0].size, 2701 adapter->rx_queue[0].rx_ring[1].size); 2702 2703 vmxnet3_tq_init_all(adapter); 2704 err = vmxnet3_rq_init_all(adapter); 2705 if (err) { 2706 netdev_err(adapter->netdev, 2707 "Failed to init rx queue error %d\n", err); 2708 goto rq_err; 2709 } 2710 2711 err = vmxnet3_request_irqs(adapter); 2712 if (err) { 2713 netdev_err(adapter->netdev, 2714 "Failed to setup irq for error %d\n", err); 2715 goto irq_err; 2716 } 2717 2718 vmxnet3_setup_driver_shared(adapter); 2719 2720 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2721 adapter->shared_pa)); 2722 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2723 adapter->shared_pa)); 2724 spin_lock_irqsave(&adapter->cmd_lock, flags); 2725 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2726 VMXNET3_CMD_ACTIVATE_DEV); 2727 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2728 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2729 2730 if (ret != 0) { 2731 netdev_err(adapter->netdev, 2732 "Failed to activate dev: error %u\n", ret); 2733 err = -EINVAL; 2734 goto activate_err; 2735 } 2736 2737 vmxnet3_init_coalesce(adapter); 2738 vmxnet3_init_rssfields(adapter); 2739 2740 for (i = 0; i < adapter->num_rx_queues; i++) { 2741 VMXNET3_WRITE_BAR0_REG(adapter, 2742 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 2743 adapter->rx_queue[i].rx_ring[0].next2fill); 2744 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 2745 (i * VMXNET3_REG_ALIGN)), 2746 adapter->rx_queue[i].rx_ring[1].next2fill); 2747 } 2748 2749 /* Apply the rx filter settins last. */ 2750 vmxnet3_set_mc(adapter->netdev); 2751 2752 /* 2753 * Check link state when first activating device. It will start the 2754 * tx queue if the link is up. 2755 */ 2756 vmxnet3_check_link(adapter, true); 2757 for (i = 0; i < adapter->num_rx_queues; i++) 2758 napi_enable(&adapter->rx_queue[i].napi); 2759 vmxnet3_enable_all_intrs(adapter); 2760 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2761 return 0; 2762 2763activate_err: 2764 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2765 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2766 vmxnet3_free_irqs(adapter); 2767irq_err: 2768rq_err: 2769 /* free up buffers we allocated */ 2770 vmxnet3_rq_cleanup_all(adapter); 2771 return err; 2772} 2773 2774 2775void 2776vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2777{ 2778 unsigned long flags; 2779 spin_lock_irqsave(&adapter->cmd_lock, flags); 2780 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 2781 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2782} 2783 2784 2785int 2786vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2787{ 2788 int i; 2789 unsigned long flags; 2790 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2791 return 0; 2792 2793 2794 spin_lock_irqsave(&adapter->cmd_lock, flags); 2795 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2796 VMXNET3_CMD_QUIESCE_DEV); 2797 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2798 vmxnet3_disable_all_intrs(adapter); 2799 2800 for (i = 0; i < adapter->num_rx_queues; i++) 2801 napi_disable(&adapter->rx_queue[i].napi); 2802 netif_tx_disable(adapter->netdev); 2803 adapter->link_speed = 0; 2804 netif_carrier_off(adapter->netdev); 2805 2806 vmxnet3_tq_cleanup_all(adapter); 2807 vmxnet3_rq_cleanup_all(adapter); 2808 vmxnet3_free_irqs(adapter); 2809 return 0; 2810} 2811 2812 2813static void 2814vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2815{ 2816 u32 tmp; 2817 2818 tmp = *(u32 *)mac; 2819 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2820 2821 tmp = (mac[5] << 8) | mac[4]; 2822 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2823} 2824 2825 2826static int 2827vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2828{ 2829 struct sockaddr *addr = p; 2830 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2831 2832 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2833 vmxnet3_write_mac_addr(adapter, addr->sa_data); 2834 2835 return 0; 2836} 2837 2838 2839/* ==================== initialization and cleanup routines ============ */ 2840 2841static int 2842vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter) 2843{ 2844 int err; 2845 unsigned long mmio_start, mmio_len; 2846 struct pci_dev *pdev = adapter->pdev; 2847 2848 err = pci_enable_device(pdev); 2849 if (err) { 2850 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err); 2851 return err; 2852 } 2853 2854 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2855 vmxnet3_driver_name); 2856 if (err) { 2857 dev_err(&pdev->dev, 2858 "Failed to request region for adapter: error %d\n", err); 2859 goto err_enable_device; 2860 } 2861 2862 pci_set_master(pdev); 2863 2864 mmio_start = pci_resource_start(pdev, 0); 2865 mmio_len = pci_resource_len(pdev, 0); 2866 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2867 if (!adapter->hw_addr0) { 2868 dev_err(&pdev->dev, "Failed to map bar0\n"); 2869 err = -EIO; 2870 goto err_ioremap; 2871 } 2872 2873 mmio_start = pci_resource_start(pdev, 1); 2874 mmio_len = pci_resource_len(pdev, 1); 2875 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2876 if (!adapter->hw_addr1) { 2877 dev_err(&pdev->dev, "Failed to map bar1\n"); 2878 err = -EIO; 2879 goto err_bar1; 2880 } 2881 return 0; 2882 2883err_bar1: 2884 iounmap(adapter->hw_addr0); 2885err_ioremap: 2886 pci_release_selected_regions(pdev, (1 << 2) - 1); 2887err_enable_device: 2888 pci_disable_device(pdev); 2889 return err; 2890} 2891 2892 2893static void 2894vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2895{ 2896 BUG_ON(!adapter->pdev); 2897 2898 iounmap(adapter->hw_addr0); 2899 iounmap(adapter->hw_addr1); 2900 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2901 pci_disable_device(adapter->pdev); 2902} 2903 2904 2905static void 2906vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2907{ 2908 size_t sz, i, ring0_size, ring1_size, comp_size; 2909 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2910 VMXNET3_MAX_ETH_HDR_SIZE) { 2911 adapter->skb_buf_size = adapter->netdev->mtu + 2912 VMXNET3_MAX_ETH_HDR_SIZE; 2913 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2914 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2915 2916 adapter->rx_buf_per_pkt = 1; 2917 } else { 2918 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2919 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2920 VMXNET3_MAX_ETH_HDR_SIZE; 2921 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2922 } 2923 2924 /* 2925 * for simplicity, force the ring0 size to be a multiple of 2926 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2927 */ 2928 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2929 ring0_size = adapter->rx_queue[0].rx_ring[0].size; 2930 ring0_size = (ring0_size + sz - 1) / sz * sz; 2931 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 2932 sz * sz); 2933 ring1_size = adapter->rx_queue[0].rx_ring[1].size; 2934 ring1_size = (ring1_size + sz - 1) / sz * sz; 2935 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE / 2936 sz * sz); 2937 comp_size = ring0_size + ring1_size; 2938 2939 for (i = 0; i < adapter->num_rx_queues; i++) { 2940 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2941 2942 rq->rx_ring[0].size = ring0_size; 2943 rq->rx_ring[1].size = ring1_size; 2944 rq->comp_ring.size = comp_size; 2945 } 2946} 2947 2948 2949int 2950vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2951 u32 rx_ring_size, u32 rx_ring2_size, 2952 u16 txdata_desc_size, u16 rxdata_desc_size) 2953{ 2954 int err = 0, i; 2955 2956 for (i = 0; i < adapter->num_tx_queues; i++) { 2957 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2958 tq->tx_ring.size = tx_ring_size; 2959 tq->data_ring.size = tx_ring_size; 2960 tq->comp_ring.size = tx_ring_size; 2961 tq->txdata_desc_size = txdata_desc_size; 2962 tq->shared = &adapter->tqd_start[i].ctrl; 2963 tq->stopped = true; 2964 tq->adapter = adapter; 2965 tq->qid = i; 2966 err = vmxnet3_tq_create(tq, adapter); 2967 /* 2968 * Too late to change num_tx_queues. We cannot do away with 2969 * lesser number of queues than what we asked for 2970 */ 2971 if (err) 2972 goto queue_err; 2973 } 2974 2975 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 2976 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2977 vmxnet3_adjust_rx_ring_size(adapter); 2978 2979 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 2980 for (i = 0; i < adapter->num_rx_queues; i++) { 2981 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2982 /* qid and qid2 for rx queues will be assigned later when num 2983 * of rx queues is finalized after allocating intrs */ 2984 rq->shared = &adapter->rqd_start[i].ctrl; 2985 rq->adapter = adapter; 2986 rq->data_ring.desc_size = rxdata_desc_size; 2987 err = vmxnet3_rq_create(rq, adapter); 2988 if (err) { 2989 if (i == 0) { 2990 netdev_err(adapter->netdev, 2991 "Could not allocate any rx queues. " 2992 "Aborting.\n"); 2993 goto queue_err; 2994 } else { 2995 netdev_info(adapter->netdev, 2996 "Number of rx queues changed " 2997 "to : %d.\n", i); 2998 adapter->num_rx_queues = i; 2999 err = 0; 3000 break; 3001 } 3002 } 3003 } 3004 3005 if (!adapter->rxdataring_enabled) 3006 vmxnet3_rq_destroy_all_rxdataring(adapter); 3007 3008 return err; 3009queue_err: 3010 vmxnet3_tq_destroy_all(adapter); 3011 return err; 3012} 3013 3014static int 3015vmxnet3_open(struct net_device *netdev) 3016{ 3017 struct vmxnet3_adapter *adapter; 3018 int err, i; 3019 3020 adapter = netdev_priv(netdev); 3021 3022 for (i = 0; i < adapter->num_tx_queues; i++) 3023 spin_lock_init(&adapter->tx_queue[i].tx_lock); 3024 3025 if (VMXNET3_VERSION_GE_3(adapter)) { 3026 unsigned long flags; 3027 u16 txdata_desc_size; 3028 3029 spin_lock_irqsave(&adapter->cmd_lock, flags); 3030 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3031 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 3032 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter, 3033 VMXNET3_REG_CMD); 3034 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3035 3036 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) || 3037 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) || 3038 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) { 3039 adapter->txdata_desc_size = 3040 sizeof(struct Vmxnet3_TxDataDesc); 3041 } else { 3042 adapter->txdata_desc_size = txdata_desc_size; 3043 } 3044 } else { 3045 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc); 3046 } 3047 3048 err = vmxnet3_create_queues(adapter, 3049 adapter->tx_ring_size, 3050 adapter->rx_ring_size, 3051 adapter->rx_ring2_size, 3052 adapter->txdata_desc_size, 3053 adapter->rxdata_desc_size); 3054 if (err) 3055 goto queue_err; 3056 3057 err = vmxnet3_activate_dev(adapter); 3058 if (err) 3059 goto activate_err; 3060 3061 return 0; 3062 3063activate_err: 3064 vmxnet3_rq_destroy_all(adapter); 3065 vmxnet3_tq_destroy_all(adapter); 3066queue_err: 3067 return err; 3068} 3069 3070 3071static int 3072vmxnet3_close(struct net_device *netdev) 3073{ 3074 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3075 3076 /* 3077 * Reset_work may be in the middle of resetting the device, wait for its 3078 * completion. 3079 */ 3080 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3081 usleep_range(1000, 2000); 3082 3083 vmxnet3_quiesce_dev(adapter); 3084 3085 vmxnet3_rq_destroy_all(adapter); 3086 vmxnet3_tq_destroy_all(adapter); 3087 3088 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3089 3090 3091 return 0; 3092} 3093 3094 3095void 3096vmxnet3_force_close(struct vmxnet3_adapter *adapter) 3097{ 3098 int i; 3099 3100 /* 3101 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 3102 * vmxnet3_close() will deadlock. 3103 */ 3104 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 3105 3106 /* we need to enable NAPI, otherwise dev_close will deadlock */ 3107 for (i = 0; i < adapter->num_rx_queues; i++) 3108 napi_enable(&adapter->rx_queue[i].napi); 3109 /* 3110 * Need to clear the quiesce bit to ensure that vmxnet3_close 3111 * can quiesce the device properly 3112 */ 3113 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3114 dev_close(adapter->netdev); 3115} 3116 3117 3118static int 3119vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 3120{ 3121 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3122 int err = 0; 3123 3124 netdev->mtu = new_mtu; 3125 3126 /* 3127 * Reset_work may be in the middle of resetting the device, wait for its 3128 * completion. 3129 */ 3130 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3131 usleep_range(1000, 2000); 3132 3133 if (netif_running(netdev)) { 3134 vmxnet3_quiesce_dev(adapter); 3135 vmxnet3_reset_dev(adapter); 3136 3137 /* we need to re-create the rx queue based on the new mtu */ 3138 vmxnet3_rq_destroy_all(adapter); 3139 vmxnet3_adjust_rx_ring_size(adapter); 3140 err = vmxnet3_rq_create_all(adapter); 3141 if (err) { 3142 netdev_err(netdev, 3143 "failed to re-create rx queues, " 3144 " error %d. Closing it.\n", err); 3145 goto out; 3146 } 3147 3148 err = vmxnet3_activate_dev(adapter); 3149 if (err) { 3150 netdev_err(netdev, 3151 "failed to re-activate, error %d. " 3152 "Closing it\n", err); 3153 goto out; 3154 } 3155 } 3156 3157out: 3158 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3159 if (err) 3160 vmxnet3_force_close(adapter); 3161 3162 return err; 3163} 3164 3165 3166static void 3167vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 3168{ 3169 struct net_device *netdev = adapter->netdev; 3170 3171 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3172 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3173 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3174 NETIF_F_LRO; 3175 3176 if (VMXNET3_VERSION_GE_4(adapter)) { 3177 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 3178 NETIF_F_GSO_UDP_TUNNEL_CSUM; 3179 3180 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM | 3181 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3182 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3183 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL | 3184 NETIF_F_GSO_UDP_TUNNEL_CSUM; 3185 } 3186 3187 if (dma64) 3188 netdev->hw_features |= NETIF_F_HIGHDMA; 3189 netdev->vlan_features = netdev->hw_features & 3190 ~(NETIF_F_HW_VLAN_CTAG_TX | 3191 NETIF_F_HW_VLAN_CTAG_RX); 3192 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; 3193} 3194 3195 3196static void 3197vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 3198{ 3199 u32 tmp; 3200 3201 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 3202 *(u32 *)mac = tmp; 3203 3204 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 3205 mac[4] = tmp & 0xff; 3206 mac[5] = (tmp >> 8) & 0xff; 3207} 3208 3209#ifdef CONFIG_PCI_MSI 3210 3211/* 3212 * Enable MSIx vectors. 3213 * Returns : 3214 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 3215 * were enabled. 3216 * number of vectors which were enabled otherwise (this number is greater 3217 * than VMXNET3_LINUX_MIN_MSIX_VECT) 3218 */ 3219 3220static int 3221vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec) 3222{ 3223 int ret = pci_enable_msix_range(adapter->pdev, 3224 adapter->intr.msix_entries, nvec, nvec); 3225 3226 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) { 3227 dev_err(&adapter->netdev->dev, 3228 "Failed to enable %d MSI-X, trying %d\n", 3229 nvec, VMXNET3_LINUX_MIN_MSIX_VECT); 3230 3231 ret = pci_enable_msix_range(adapter->pdev, 3232 adapter->intr.msix_entries, 3233 VMXNET3_LINUX_MIN_MSIX_VECT, 3234 VMXNET3_LINUX_MIN_MSIX_VECT); 3235 } 3236 3237 if (ret < 0) { 3238 dev_err(&adapter->netdev->dev, 3239 "Failed to enable MSI-X, error: %d\n", ret); 3240 } 3241 3242 return ret; 3243} 3244 3245 3246#endif /* CONFIG_PCI_MSI */ 3247 3248static void 3249vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 3250{ 3251 u32 cfg; 3252 unsigned long flags; 3253 3254 /* intr settings */ 3255 spin_lock_irqsave(&adapter->cmd_lock, flags); 3256 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3257 VMXNET3_CMD_GET_CONF_INTR); 3258 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 3259 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3260 adapter->intr.type = cfg & 0x3; 3261 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 3262 3263 if (adapter->intr.type == VMXNET3_IT_AUTO) { 3264 adapter->intr.type = VMXNET3_IT_MSIX; 3265 } 3266 3267#ifdef CONFIG_PCI_MSI 3268 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3269 int i, nvec; 3270 3271 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ? 3272 1 : adapter->num_tx_queues; 3273 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ? 3274 0 : adapter->num_rx_queues; 3275 nvec += 1; /* for link event */ 3276 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ? 3277 nvec : VMXNET3_LINUX_MIN_MSIX_VECT; 3278 3279 for (i = 0; i < nvec; i++) 3280 adapter->intr.msix_entries[i].entry = i; 3281 3282 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec); 3283 if (nvec < 0) 3284 goto msix_err; 3285 3286 /* If we cannot allocate one MSIx vector per queue 3287 * then limit the number of rx queues to 1 3288 */ 3289 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) { 3290 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 3291 || adapter->num_rx_queues != 1) { 3292 adapter->share_intr = VMXNET3_INTR_TXSHARE; 3293 netdev_err(adapter->netdev, 3294 "Number of rx queues : 1\n"); 3295 adapter->num_rx_queues = 1; 3296 } 3297 } 3298 3299 adapter->intr.num_intrs = nvec; 3300 return; 3301 3302msix_err: 3303 /* If we cannot allocate MSIx vectors use only one rx queue */ 3304 dev_info(&adapter->pdev->dev, 3305 "Failed to enable MSI-X, error %d. " 3306 "Limiting #rx queues to 1, try MSI.\n", nvec); 3307 3308 adapter->intr.type = VMXNET3_IT_MSI; 3309 } 3310 3311 if (adapter->intr.type == VMXNET3_IT_MSI) { 3312 if (!pci_enable_msi(adapter->pdev)) { 3313 adapter->num_rx_queues = 1; 3314 adapter->intr.num_intrs = 1; 3315 return; 3316 } 3317 } 3318#endif /* CONFIG_PCI_MSI */ 3319 3320 adapter->num_rx_queues = 1; 3321 dev_info(&adapter->netdev->dev, 3322 "Using INTx interrupt, #Rx queues: 1.\n"); 3323 adapter->intr.type = VMXNET3_IT_INTX; 3324 3325 /* INT-X related setting */ 3326 adapter->intr.num_intrs = 1; 3327} 3328 3329 3330static void 3331vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 3332{ 3333 if (adapter->intr.type == VMXNET3_IT_MSIX) 3334 pci_disable_msix(adapter->pdev); 3335 else if (adapter->intr.type == VMXNET3_IT_MSI) 3336 pci_disable_msi(adapter->pdev); 3337 else 3338 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 3339} 3340 3341 3342static void 3343vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue) 3344{ 3345 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3346 adapter->tx_timeout_count++; 3347 3348 netdev_err(adapter->netdev, "tx hang\n"); 3349 schedule_work(&adapter->work); 3350} 3351 3352 3353static void 3354vmxnet3_reset_work(struct work_struct *data) 3355{ 3356 struct vmxnet3_adapter *adapter; 3357 3358 adapter = container_of(data, struct vmxnet3_adapter, work); 3359 3360 /* if another thread is resetting the device, no need to proceed */ 3361 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3362 return; 3363 3364 /* if the device is closed, we must leave it alone */ 3365 rtnl_lock(); 3366 if (netif_running(adapter->netdev)) { 3367 netdev_notice(adapter->netdev, "resetting\n"); 3368 vmxnet3_quiesce_dev(adapter); 3369 vmxnet3_reset_dev(adapter); 3370 vmxnet3_activate_dev(adapter); 3371 } else { 3372 netdev_info(adapter->netdev, "already closed\n"); 3373 } 3374 rtnl_unlock(); 3375 3376 netif_wake_queue(adapter->netdev); 3377 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3378} 3379 3380 3381static int 3382vmxnet3_probe_device(struct pci_dev *pdev, 3383 const struct pci_device_id *id) 3384{ 3385 static const struct net_device_ops vmxnet3_netdev_ops = { 3386 .ndo_open = vmxnet3_open, 3387 .ndo_stop = vmxnet3_close, 3388 .ndo_start_xmit = vmxnet3_xmit_frame, 3389 .ndo_set_mac_address = vmxnet3_set_mac_addr, 3390 .ndo_change_mtu = vmxnet3_change_mtu, 3391 .ndo_fix_features = vmxnet3_fix_features, 3392 .ndo_set_features = vmxnet3_set_features, 3393 .ndo_features_check = vmxnet3_features_check, 3394 .ndo_get_stats64 = vmxnet3_get_stats64, 3395 .ndo_tx_timeout = vmxnet3_tx_timeout, 3396 .ndo_set_rx_mode = vmxnet3_set_mc, 3397 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 3398 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 3399#ifdef CONFIG_NET_POLL_CONTROLLER 3400 .ndo_poll_controller = vmxnet3_netpoll, 3401#endif 3402 }; 3403 int err; 3404 bool dma64; 3405 u32 ver; 3406 struct net_device *netdev; 3407 struct vmxnet3_adapter *adapter; 3408 u8 mac[ETH_ALEN]; 3409 int size; 3410 int num_tx_queues; 3411 int num_rx_queues; 3412 3413 if (!pci_msi_enabled()) 3414 enable_mq = 0; 3415 3416#ifdef VMXNET3_RSS 3417 if (enable_mq) 3418 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3419 (int)num_online_cpus()); 3420 else 3421#endif 3422 num_rx_queues = 1; 3423 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3424 3425 if (enable_mq) 3426 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 3427 (int)num_online_cpus()); 3428 else 3429 num_tx_queues = 1; 3430 3431 num_tx_queues = rounddown_pow_of_two(num_tx_queues); 3432 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 3433 max(num_tx_queues, num_rx_queues)); 3434 dev_info(&pdev->dev, 3435 "# of Tx queues : %d, # of Rx queues : %d\n", 3436 num_tx_queues, num_rx_queues); 3437 3438 if (!netdev) 3439 return -ENOMEM; 3440 3441 pci_set_drvdata(pdev, netdev); 3442 adapter = netdev_priv(netdev); 3443 adapter->netdev = netdev; 3444 adapter->pdev = pdev; 3445 3446 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE; 3447 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE; 3448 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE; 3449 3450 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 3451 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 3452 dev_err(&pdev->dev, 3453 "pci_set_consistent_dma_mask failed\n"); 3454 err = -EIO; 3455 goto err_set_mask; 3456 } 3457 dma64 = true; 3458 } else { 3459 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 3460 dev_err(&pdev->dev, 3461 "pci_set_dma_mask failed\n"); 3462 err = -EIO; 3463 goto err_set_mask; 3464 } 3465 dma64 = false; 3466 } 3467 3468 spin_lock_init(&adapter->cmd_lock); 3469 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter, 3470 sizeof(struct vmxnet3_adapter), 3471 PCI_DMA_TODEVICE); 3472 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) { 3473 dev_err(&pdev->dev, "Failed to map dma\n"); 3474 err = -EFAULT; 3475 goto err_set_mask; 3476 } 3477 adapter->shared = dma_alloc_coherent( 3478 &adapter->pdev->dev, 3479 sizeof(struct Vmxnet3_DriverShared), 3480 &adapter->shared_pa, GFP_KERNEL); 3481 if (!adapter->shared) { 3482 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3483 err = -ENOMEM; 3484 goto err_alloc_shared; 3485 } 3486 3487 adapter->num_rx_queues = num_rx_queues; 3488 adapter->num_tx_queues = num_tx_queues; 3489 adapter->rx_buf_per_pkt = 1; 3490 3491 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3492 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 3493 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size, 3494 &adapter->queue_desc_pa, 3495 GFP_KERNEL); 3496 3497 if (!adapter->tqd_start) { 3498 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3499 err = -ENOMEM; 3500 goto err_alloc_queue_desc; 3501 } 3502 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 3503 adapter->num_tx_queues); 3504 3505 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev, 3506 sizeof(struct Vmxnet3_PMConf), 3507 &adapter->pm_conf_pa, 3508 GFP_KERNEL); 3509 if (adapter->pm_conf == NULL) { 3510 err = -ENOMEM; 3511 goto err_alloc_pm; 3512 } 3513 3514#ifdef VMXNET3_RSS 3515 3516 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev, 3517 sizeof(struct UPT1_RSSConf), 3518 &adapter->rss_conf_pa, 3519 GFP_KERNEL); 3520 if (adapter->rss_conf == NULL) { 3521 err = -ENOMEM; 3522 goto err_alloc_rss; 3523 } 3524#endif /* VMXNET3_RSS */ 3525 3526 err = vmxnet3_alloc_pci_resources(adapter); 3527 if (err < 0) 3528 goto err_alloc_pci; 3529 3530 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 3531 if (ver & (1 << VMXNET3_REV_4)) { 3532 VMXNET3_WRITE_BAR1_REG(adapter, 3533 VMXNET3_REG_VRRS, 3534 1 << VMXNET3_REV_4); 3535 adapter->version = VMXNET3_REV_4 + 1; 3536 } else if (ver & (1 << VMXNET3_REV_3)) { 3537 VMXNET3_WRITE_BAR1_REG(adapter, 3538 VMXNET3_REG_VRRS, 3539 1 << VMXNET3_REV_3); 3540 adapter->version = VMXNET3_REV_3 + 1; 3541 } else if (ver & (1 << VMXNET3_REV_2)) { 3542 VMXNET3_WRITE_BAR1_REG(adapter, 3543 VMXNET3_REG_VRRS, 3544 1 << VMXNET3_REV_2); 3545 adapter->version = VMXNET3_REV_2 + 1; 3546 } else if (ver & (1 << VMXNET3_REV_1)) { 3547 VMXNET3_WRITE_BAR1_REG(adapter, 3548 VMXNET3_REG_VRRS, 3549 1 << VMXNET3_REV_1); 3550 adapter->version = VMXNET3_REV_1 + 1; 3551 } else { 3552 dev_err(&pdev->dev, 3553 "Incompatible h/w version (0x%x) for adapter\n", ver); 3554 err = -EBUSY; 3555 goto err_ver; 3556 } 3557 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version); 3558 3559 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 3560 if (ver & 1) { 3561 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 3562 } else { 3563 dev_err(&pdev->dev, 3564 "Incompatible upt version (0x%x) for adapter\n", ver); 3565 err = -EBUSY; 3566 goto err_ver; 3567 } 3568 3569 if (VMXNET3_VERSION_GE_3(adapter)) { 3570 adapter->coal_conf = 3571 dma_alloc_coherent(&adapter->pdev->dev, 3572 sizeof(struct Vmxnet3_CoalesceScheme) 3573 , 3574 &adapter->coal_conf_pa, 3575 GFP_KERNEL); 3576 if (!adapter->coal_conf) { 3577 err = -ENOMEM; 3578 goto err_ver; 3579 } 3580 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED; 3581 adapter->default_coal_mode = true; 3582 } 3583 3584 if (VMXNET3_VERSION_GE_4(adapter)) { 3585 adapter->default_rss_fields = true; 3586 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT; 3587 } 3588 3589 SET_NETDEV_DEV(netdev, &pdev->dev); 3590 vmxnet3_declare_features(adapter, dma64); 3591 3592 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ? 3593 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 3594 3595 if (adapter->num_tx_queues == adapter->num_rx_queues) 3596 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE; 3597 else 3598 adapter->share_intr = VMXNET3_INTR_DONTSHARE; 3599 3600 vmxnet3_alloc_intr_resources(adapter); 3601 3602#ifdef VMXNET3_RSS 3603 if (adapter->num_rx_queues > 1 && 3604 adapter->intr.type == VMXNET3_IT_MSIX) { 3605 adapter->rss = true; 3606 netdev->hw_features |= NETIF_F_RXHASH; 3607 netdev->features |= NETIF_F_RXHASH; 3608 dev_dbg(&pdev->dev, "RSS is enabled.\n"); 3609 } else { 3610 adapter->rss = false; 3611 } 3612#endif 3613 3614 vmxnet3_read_mac_addr(adapter, mac); 3615 memcpy(netdev->dev_addr, mac, netdev->addr_len); 3616 3617 netdev->netdev_ops = &vmxnet3_netdev_ops; 3618 vmxnet3_set_ethtool_ops(netdev); 3619 netdev->watchdog_timeo = 5 * HZ; 3620 3621 /* MTU range: 60 - 9000 */ 3622 netdev->min_mtu = VMXNET3_MIN_MTU; 3623 netdev->max_mtu = VMXNET3_MAX_MTU; 3624 3625 INIT_WORK(&adapter->work, vmxnet3_reset_work); 3626 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3627 3628 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3629 int i; 3630 for (i = 0; i < adapter->num_rx_queues; i++) { 3631 netif_napi_add(adapter->netdev, 3632 &adapter->rx_queue[i].napi, 3633 vmxnet3_poll_rx_only, 64); 3634 } 3635 } else { 3636 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 3637 vmxnet3_poll, 64); 3638 } 3639 3640 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 3641 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 3642 3643 netif_carrier_off(netdev); 3644 err = register_netdev(netdev); 3645 3646 if (err) { 3647 dev_err(&pdev->dev, "Failed to register adapter\n"); 3648 goto err_register; 3649 } 3650 3651 vmxnet3_check_link(adapter, false); 3652 return 0; 3653 3654err_register: 3655 if (VMXNET3_VERSION_GE_3(adapter)) { 3656 dma_free_coherent(&adapter->pdev->dev, 3657 sizeof(struct Vmxnet3_CoalesceScheme), 3658 adapter->coal_conf, adapter->coal_conf_pa); 3659 } 3660 vmxnet3_free_intr_resources(adapter); 3661err_ver: 3662 vmxnet3_free_pci_resources(adapter); 3663err_alloc_pci: 3664#ifdef VMXNET3_RSS 3665 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3666 adapter->rss_conf, adapter->rss_conf_pa); 3667err_alloc_rss: 3668#endif 3669 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3670 adapter->pm_conf, adapter->pm_conf_pa); 3671err_alloc_pm: 3672 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3673 adapter->queue_desc_pa); 3674err_alloc_queue_desc: 3675 dma_free_coherent(&adapter->pdev->dev, 3676 sizeof(struct Vmxnet3_DriverShared), 3677 adapter->shared, adapter->shared_pa); 3678err_alloc_shared: 3679 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3680 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3681err_set_mask: 3682 free_netdev(netdev); 3683 return err; 3684} 3685 3686 3687static void 3688vmxnet3_remove_device(struct pci_dev *pdev) 3689{ 3690 struct net_device *netdev = pci_get_drvdata(pdev); 3691 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3692 int size = 0; 3693 int num_rx_queues; 3694 3695#ifdef VMXNET3_RSS 3696 if (enable_mq) 3697 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3698 (int)num_online_cpus()); 3699 else 3700#endif 3701 num_rx_queues = 1; 3702 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3703 3704 cancel_work_sync(&adapter->work); 3705 3706 unregister_netdev(netdev); 3707 3708 vmxnet3_free_intr_resources(adapter); 3709 vmxnet3_free_pci_resources(adapter); 3710 if (VMXNET3_VERSION_GE_3(adapter)) { 3711 dma_free_coherent(&adapter->pdev->dev, 3712 sizeof(struct Vmxnet3_CoalesceScheme), 3713 adapter->coal_conf, adapter->coal_conf_pa); 3714 } 3715#ifdef VMXNET3_RSS 3716 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3717 adapter->rss_conf, adapter->rss_conf_pa); 3718#endif 3719 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3720 adapter->pm_conf, adapter->pm_conf_pa); 3721 3722 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3723 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3724 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3725 adapter->queue_desc_pa); 3726 dma_free_coherent(&adapter->pdev->dev, 3727 sizeof(struct Vmxnet3_DriverShared), 3728 adapter->shared, adapter->shared_pa); 3729 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3730 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3731 free_netdev(netdev); 3732} 3733 3734static void vmxnet3_shutdown_device(struct pci_dev *pdev) 3735{ 3736 struct net_device *netdev = pci_get_drvdata(pdev); 3737 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3738 unsigned long flags; 3739 3740 /* Reset_work may be in the middle of resetting the device, wait for its 3741 * completion. 3742 */ 3743 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3744 usleep_range(1000, 2000); 3745 3746 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, 3747 &adapter->state)) { 3748 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3749 return; 3750 } 3751 spin_lock_irqsave(&adapter->cmd_lock, flags); 3752 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3753 VMXNET3_CMD_QUIESCE_DEV); 3754 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3755 vmxnet3_disable_all_intrs(adapter); 3756 3757 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3758} 3759 3760 3761#ifdef CONFIG_PM 3762 3763static int 3764vmxnet3_suspend(struct device *device) 3765{ 3766 struct pci_dev *pdev = to_pci_dev(device); 3767 struct net_device *netdev = pci_get_drvdata(pdev); 3768 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3769 struct Vmxnet3_PMConf *pmConf; 3770 struct ethhdr *ehdr; 3771 struct arphdr *ahdr; 3772 u8 *arpreq; 3773 struct in_device *in_dev; 3774 struct in_ifaddr *ifa; 3775 unsigned long flags; 3776 int i = 0; 3777 3778 if (!netif_running(netdev)) 3779 return 0; 3780 3781 for (i = 0; i < adapter->num_rx_queues; i++) 3782 napi_disable(&adapter->rx_queue[i].napi); 3783 3784 vmxnet3_disable_all_intrs(adapter); 3785 vmxnet3_free_irqs(adapter); 3786 vmxnet3_free_intr_resources(adapter); 3787 3788 netif_device_detach(netdev); 3789 3790 /* Create wake-up filters. */ 3791 pmConf = adapter->pm_conf; 3792 memset(pmConf, 0, sizeof(*pmConf)); 3793 3794 if (adapter->wol & WAKE_UCAST) { 3795 pmConf->filters[i].patternSize = ETH_ALEN; 3796 pmConf->filters[i].maskSize = 1; 3797 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3798 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3799 3800 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3801 i++; 3802 } 3803 3804 if (adapter->wol & WAKE_ARP) { 3805 rcu_read_lock(); 3806 3807 in_dev = __in_dev_get_rcu(netdev); 3808 if (!in_dev) { 3809 rcu_read_unlock(); 3810 goto skip_arp; 3811 } 3812 3813 ifa = rcu_dereference(in_dev->ifa_list); 3814 if (!ifa) { 3815 rcu_read_unlock(); 3816 goto skip_arp; 3817 } 3818 3819 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3820 sizeof(struct arphdr) + /* ARP header */ 3821 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3822 2 * sizeof(u32); /*2 IPv4 addresses */ 3823 pmConf->filters[i].maskSize = 3824 (pmConf->filters[i].patternSize - 1) / 8 + 1; 3825 3826 /* ETH_P_ARP in Ethernet header. */ 3827 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3828 ehdr->h_proto = htons(ETH_P_ARP); 3829 3830 /* ARPOP_REQUEST in ARP header. */ 3831 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3832 ahdr->ar_op = htons(ARPOP_REQUEST); 3833 arpreq = (u8 *)(ahdr + 1); 3834 3835 /* The Unicast IPv4 address in 'tip' field. */ 3836 arpreq += 2 * ETH_ALEN + sizeof(u32); 3837 *(__be32 *)arpreq = ifa->ifa_address; 3838 3839 rcu_read_unlock(); 3840 3841 /* The mask for the relevant bits. */ 3842 pmConf->filters[i].mask[0] = 0x00; 3843 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3844 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3845 pmConf->filters[i].mask[3] = 0x00; 3846 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3847 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3848 3849 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3850 i++; 3851 } 3852 3853skip_arp: 3854 if (adapter->wol & WAKE_MAGIC) 3855 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3856 3857 pmConf->numFilters = i; 3858 3859 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3860 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3861 *pmConf)); 3862 adapter->shared->devRead.pmConfDesc.confPA = 3863 cpu_to_le64(adapter->pm_conf_pa); 3864 3865 spin_lock_irqsave(&adapter->cmd_lock, flags); 3866 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3867 VMXNET3_CMD_UPDATE_PMCFG); 3868 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3869 3870 pci_save_state(pdev); 3871 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3872 adapter->wol); 3873 pci_disable_device(pdev); 3874 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3875 3876 return 0; 3877} 3878 3879 3880static int 3881vmxnet3_resume(struct device *device) 3882{ 3883 int err; 3884 unsigned long flags; 3885 struct pci_dev *pdev = to_pci_dev(device); 3886 struct net_device *netdev = pci_get_drvdata(pdev); 3887 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3888 3889 if (!netif_running(netdev)) 3890 return 0; 3891 3892 pci_set_power_state(pdev, PCI_D0); 3893 pci_restore_state(pdev); 3894 err = pci_enable_device_mem(pdev); 3895 if (err != 0) 3896 return err; 3897 3898 pci_enable_wake(pdev, PCI_D0, 0); 3899 3900 vmxnet3_alloc_intr_resources(adapter); 3901 3902 /* During hibernate and suspend, device has to be reinitialized as the 3903 * device state need not be preserved. 3904 */ 3905 3906 /* Need not check adapter state as other reset tasks cannot run during 3907 * device resume. 3908 */ 3909 spin_lock_irqsave(&adapter->cmd_lock, flags); 3910 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3911 VMXNET3_CMD_QUIESCE_DEV); 3912 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3913 vmxnet3_tq_cleanup_all(adapter); 3914 vmxnet3_rq_cleanup_all(adapter); 3915 3916 vmxnet3_reset_dev(adapter); 3917 err = vmxnet3_activate_dev(adapter); 3918 if (err != 0) { 3919 netdev_err(netdev, 3920 "failed to re-activate on resume, error: %d", err); 3921 vmxnet3_force_close(adapter); 3922 return err; 3923 } 3924 netif_device_attach(netdev); 3925 3926 return 0; 3927} 3928 3929static const struct dev_pm_ops vmxnet3_pm_ops = { 3930 .suspend = vmxnet3_suspend, 3931 .resume = vmxnet3_resume, 3932 .freeze = vmxnet3_suspend, 3933 .restore = vmxnet3_resume, 3934}; 3935#endif 3936 3937static struct pci_driver vmxnet3_driver = { 3938 .name = vmxnet3_driver_name, 3939 .id_table = vmxnet3_pciid_table, 3940 .probe = vmxnet3_probe_device, 3941 .remove = vmxnet3_remove_device, 3942 .shutdown = vmxnet3_shutdown_device, 3943#ifdef CONFIG_PM 3944 .driver.pm = &vmxnet3_pm_ops, 3945#endif 3946}; 3947 3948 3949static int __init 3950vmxnet3_init_module(void) 3951{ 3952 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC, 3953 VMXNET3_DRIVER_VERSION_REPORT); 3954 return pci_register_driver(&vmxnet3_driver); 3955} 3956 3957module_init(vmxnet3_init_module); 3958 3959 3960static void 3961vmxnet3_exit_module(void) 3962{ 3963 pci_unregister_driver(&vmxnet3_driver); 3964} 3965 3966module_exit(vmxnet3_exit_module); 3967 3968MODULE_AUTHOR("VMware, Inc."); 3969MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3970MODULE_LICENSE("GPL v2"); 3971MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3972