1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ASIX AX8817X based USB 2.0 Ethernet Devices 4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 7 * Copyright (c) 2002-2003 TiVo Inc. 8 */ 9 10#include "asix.h" 11 12#define PHY_MODE_MARVELL 0x0000 13#define MII_MARVELL_LED_CTRL 0x0018 14#define MII_MARVELL_STATUS 0x001b 15#define MII_MARVELL_CTRL 0x0014 16 17#define MARVELL_LED_MANUAL 0x0019 18 19#define MARVELL_STATUS_HWCFG 0x0004 20 21#define MARVELL_CTRL_TXDELAY 0x0002 22#define MARVELL_CTRL_RXDELAY 0x0080 23 24#define PHY_MODE_RTL8211CL 0x000C 25 26#define AX88772A_PHY14H 0x14 27#define AX88772A_PHY14H_DEFAULT 0x442C 28 29#define AX88772A_PHY15H 0x15 30#define AX88772A_PHY15H_DEFAULT 0x03C8 31 32#define AX88772A_PHY16H 0x16 33#define AX88772A_PHY16H_DEFAULT 0x4044 34 35struct ax88172_int_data { 36 __le16 res1; 37 u8 link; 38 __le16 res2; 39 u8 status; 40 __le16 res3; 41} __packed; 42 43static void asix_status(struct usbnet *dev, struct urb *urb) 44{ 45 struct ax88172_int_data *event; 46 int link; 47 48 if (urb->actual_length < 8) 49 return; 50 51 event = urb->transfer_buffer; 52 link = event->link & 0x01; 53 if (netif_carrier_ok(dev->net) != link) { 54 usbnet_link_change(dev, link, 1); 55 netdev_dbg(dev->net, "Link Status is: %d\n", link); 56 } 57} 58 59static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 60{ 61 if (is_valid_ether_addr(addr)) { 62 memcpy(dev->net->dev_addr, addr, ETH_ALEN); 63 } else { 64 netdev_info(dev->net, "invalid hw address, using random\n"); 65 eth_hw_addr_random(dev->net); 66 } 67} 68 69/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 70static u32 asix_get_phyid(struct usbnet *dev) 71{ 72 int phy_reg; 73 u32 phy_id; 74 int i; 75 76 /* Poll for the rare case the FW or phy isn't ready yet. */ 77 for (i = 0; i < 100; i++) { 78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 79 if (phy_reg < 0) 80 return 0; 81 if (phy_reg != 0 && phy_reg != 0xFFFF) 82 break; 83 mdelay(1); 84 } 85 86 if (phy_reg <= 0 || phy_reg == 0xFFFF) 87 return 0; 88 89 phy_id = (phy_reg & 0xffff) << 16; 90 91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 92 if (phy_reg < 0) 93 return 0; 94 95 phy_id |= (phy_reg & 0xffff); 96 97 return phy_id; 98} 99 100static u32 asix_get_link(struct net_device *net) 101{ 102 struct usbnet *dev = netdev_priv(net); 103 104 return mii_link_ok(&dev->mii); 105} 106 107static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) 108{ 109 struct usbnet *dev = netdev_priv(net); 110 111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 112} 113 114/* We need to override some ethtool_ops so we require our 115 own structure so we don't interfere with other usbnet 116 devices that may be connected at the same time. */ 117static const struct ethtool_ops ax88172_ethtool_ops = { 118 .get_drvinfo = asix_get_drvinfo, 119 .get_link = asix_get_link, 120 .get_msglevel = usbnet_get_msglevel, 121 .set_msglevel = usbnet_set_msglevel, 122 .get_wol = asix_get_wol, 123 .set_wol = asix_set_wol, 124 .get_eeprom_len = asix_get_eeprom_len, 125 .get_eeprom = asix_get_eeprom, 126 .set_eeprom = asix_set_eeprom, 127 .nway_reset = usbnet_nway_reset, 128 .get_link_ksettings = usbnet_get_link_ksettings, 129 .set_link_ksettings = usbnet_set_link_ksettings, 130}; 131 132static void ax88172_set_multicast(struct net_device *net) 133{ 134 struct usbnet *dev = netdev_priv(net); 135 struct asix_data *data = (struct asix_data *)&dev->data; 136 u8 rx_ctl = 0x8c; 137 138 if (net->flags & IFF_PROMISC) { 139 rx_ctl |= 0x01; 140 } else if (net->flags & IFF_ALLMULTI || 141 netdev_mc_count(net) > AX_MAX_MCAST) { 142 rx_ctl |= 0x02; 143 } else if (netdev_mc_empty(net)) { 144 /* just broadcast and directed */ 145 } else { 146 /* We use the 20 byte dev->data 147 * for our 8 byte filter buffer 148 * to avoid allocating memory that 149 * is tricky to free later */ 150 struct netdev_hw_addr *ha; 151 u32 crc_bits; 152 153 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 154 155 /* Build the multicast hash filter. */ 156 netdev_for_each_mc_addr(ha, net) { 157 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 158 data->multi_filter[crc_bits >> 3] |= 159 1 << (crc_bits & 7); 160 } 161 162 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 163 AX_MCAST_FILTER_SIZE, data->multi_filter); 164 165 rx_ctl |= 0x10; 166 } 167 168 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 169} 170 171static int ax88172_link_reset(struct usbnet *dev) 172{ 173 u8 mode; 174 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 175 176 mii_check_media(&dev->mii, 1, 1); 177 mii_ethtool_gset(&dev->mii, &ecmd); 178 mode = AX88172_MEDIUM_DEFAULT; 179 180 if (ecmd.duplex != DUPLEX_FULL) 181 mode |= ~AX88172_MEDIUM_FD; 182 183 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 184 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 185 186 asix_write_medium_mode(dev, mode, 0); 187 188 return 0; 189} 190 191static const struct net_device_ops ax88172_netdev_ops = { 192 .ndo_open = usbnet_open, 193 .ndo_stop = usbnet_stop, 194 .ndo_start_xmit = usbnet_start_xmit, 195 .ndo_tx_timeout = usbnet_tx_timeout, 196 .ndo_change_mtu = usbnet_change_mtu, 197 .ndo_get_stats64 = usbnet_get_stats64, 198 .ndo_set_mac_address = eth_mac_addr, 199 .ndo_validate_addr = eth_validate_addr, 200 .ndo_do_ioctl = asix_ioctl, 201 .ndo_set_rx_mode = ax88172_set_multicast, 202}; 203 204static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits) 205{ 206 unsigned int timeout = 5000; 207 208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); 209 210 /* give phy_id a chance to process reset */ 211 udelay(500); 212 213 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */ 214 while (timeout--) { 215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) 216 & BMCR_RESET) 217 udelay(100); 218 else 219 return; 220 } 221 222 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", 223 dev->mii.phy_id); 224} 225 226static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 227{ 228 int ret = 0; 229 u8 buf[ETH_ALEN] = {0}; 230 int i; 231 unsigned long gpio_bits = dev->driver_info->data; 232 233 usbnet_get_endpoints(dev,intf); 234 235 /* Toggle the GPIOs in a manufacturer/model specific way */ 236 for (i = 2; i >= 0; i--) { 237 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 238 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0); 239 if (ret < 0) 240 goto out; 241 msleep(5); 242 } 243 244 ret = asix_write_rx_ctl(dev, 0x80, 0); 245 if (ret < 0) 246 goto out; 247 248 /* Get the MAC address */ 249 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 250 0, 0, ETH_ALEN, buf, 0); 251 if (ret < 0) { 252 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 253 ret); 254 goto out; 255 } 256 257 asix_set_netdev_dev_addr(dev, buf); 258 259 /* Initialize MII structure */ 260 dev->mii.dev = dev->net; 261 dev->mii.mdio_read = asix_mdio_read; 262 dev->mii.mdio_write = asix_mdio_write; 263 dev->mii.phy_id_mask = 0x3f; 264 dev->mii.reg_num_mask = 0x1f; 265 dev->mii.phy_id = asix_get_phy_addr(dev); 266 267 dev->net->netdev_ops = &ax88172_netdev_ops; 268 dev->net->ethtool_ops = &ax88172_ethtool_ops; 269 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 270 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 271 272 asix_phy_reset(dev, BMCR_RESET); 273 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 274 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 275 mii_nway_restart(&dev->mii); 276 277 return 0; 278 279out: 280 return ret; 281} 282 283static const struct ethtool_ops ax88772_ethtool_ops = { 284 .get_drvinfo = asix_get_drvinfo, 285 .get_link = asix_get_link, 286 .get_msglevel = usbnet_get_msglevel, 287 .set_msglevel = usbnet_set_msglevel, 288 .get_wol = asix_get_wol, 289 .set_wol = asix_set_wol, 290 .get_eeprom_len = asix_get_eeprom_len, 291 .get_eeprom = asix_get_eeprom, 292 .set_eeprom = asix_set_eeprom, 293 .nway_reset = usbnet_nway_reset, 294 .get_link_ksettings = usbnet_get_link_ksettings, 295 .set_link_ksettings = usbnet_set_link_ksettings, 296}; 297 298static int ax88772_link_reset(struct usbnet *dev) 299{ 300 u16 mode; 301 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 302 303 mii_check_media(&dev->mii, 1, 1); 304 mii_ethtool_gset(&dev->mii, &ecmd); 305 mode = AX88772_MEDIUM_DEFAULT; 306 307 if (ethtool_cmd_speed(&ecmd) != SPEED_100) 308 mode &= ~AX_MEDIUM_PS; 309 310 if (ecmd.duplex != DUPLEX_FULL) 311 mode &= ~AX_MEDIUM_FD; 312 313 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 314 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 315 316 asix_write_medium_mode(dev, mode, 0); 317 318 return 0; 319} 320 321static int ax88772_reset(struct usbnet *dev) 322{ 323 struct asix_data *data = (struct asix_data *)&dev->data; 324 int ret; 325 326 /* Rewrite MAC address */ 327 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 328 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 329 ETH_ALEN, data->mac_addr, 0); 330 if (ret < 0) 331 goto out; 332 333 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 334 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 335 if (ret < 0) 336 goto out; 337 338 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0); 339 if (ret < 0) 340 goto out; 341 342 return 0; 343 344out: 345 return ret; 346} 347 348static int ax88772_hw_reset(struct usbnet *dev, int in_pm) 349{ 350 struct asix_data *data = (struct asix_data *)&dev->data; 351 int ret, embd_phy; 352 u16 rx_ctl; 353 354 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 355 AX_GPIO_GPO2EN, 5, in_pm); 356 if (ret < 0) 357 goto out; 358 359 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 360 361 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 362 0, 0, NULL, in_pm); 363 if (ret < 0) { 364 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 365 goto out; 366 } 367 368 if (embd_phy) { 369 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm); 370 if (ret < 0) 371 goto out; 372 373 usleep_range(10000, 11000); 374 375 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 376 if (ret < 0) 377 goto out; 378 379 msleep(60); 380 381 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL, 382 in_pm); 383 if (ret < 0) 384 goto out; 385 } else { 386 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL, 387 in_pm); 388 if (ret < 0) 389 goto out; 390 } 391 392 msleep(150); 393 394 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 395 MII_PHYSID1))){ 396 ret = -EIO; 397 goto out; 398 } 399 400 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 401 if (ret < 0) 402 goto out; 403 404 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 405 if (ret < 0) 406 goto out; 407 408 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 409 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 410 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 411 if (ret < 0) { 412 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 413 goto out; 414 } 415 416 /* Rewrite MAC address */ 417 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 418 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 419 ETH_ALEN, data->mac_addr, in_pm); 420 if (ret < 0) 421 goto out; 422 423 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 424 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 425 if (ret < 0) 426 goto out; 427 428 rx_ctl = asix_read_rx_ctl(dev, in_pm); 429 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 430 rx_ctl); 431 432 rx_ctl = asix_read_medium_status(dev, in_pm); 433 netdev_dbg(dev->net, 434 "Medium Status is 0x%04x after all initializations\n", 435 rx_ctl); 436 437 return 0; 438 439out: 440 return ret; 441} 442 443static int ax88772a_hw_reset(struct usbnet *dev, int in_pm) 444{ 445 struct asix_data *data = (struct asix_data *)&dev->data; 446 int ret, embd_phy; 447 u16 rx_ctl, phy14h, phy15h, phy16h; 448 u8 chipcode = 0; 449 450 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm); 451 if (ret < 0) 452 goto out; 453 454 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 455 456 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy | 457 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm); 458 if (ret < 0) { 459 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 460 goto out; 461 } 462 usleep_range(10000, 11000); 463 464 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm); 465 if (ret < 0) 466 goto out; 467 468 usleep_range(10000, 11000); 469 470 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 471 if (ret < 0) 472 goto out; 473 474 msleep(160); 475 476 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 477 if (ret < 0) 478 goto out; 479 480 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 481 if (ret < 0) 482 goto out; 483 484 msleep(200); 485 486 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 487 MII_PHYSID1))) { 488 ret = -1; 489 goto out; 490 } 491 492 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 493 0, 1, &chipcode, in_pm); 494 if (ret < 0) 495 goto out; 496 497 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) { 498 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001, 499 0, NULL, in_pm); 500 if (ret < 0) { 501 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", 502 ret); 503 goto out; 504 } 505 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) { 506 /* Check if the PHY registers have default settings */ 507 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 508 AX88772A_PHY14H); 509 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 510 AX88772A_PHY15H); 511 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 512 AX88772A_PHY16H); 513 514 netdev_dbg(dev->net, 515 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n", 516 phy14h, phy15h, phy16h); 517 518 /* Restore PHY registers default setting if not */ 519 if (phy14h != AX88772A_PHY14H_DEFAULT) 520 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 521 AX88772A_PHY14H, 522 AX88772A_PHY14H_DEFAULT); 523 if (phy15h != AX88772A_PHY15H_DEFAULT) 524 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 525 AX88772A_PHY15H, 526 AX88772A_PHY15H_DEFAULT); 527 if (phy16h != AX88772A_PHY16H_DEFAULT) 528 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 529 AX88772A_PHY16H, 530 AX88772A_PHY16H_DEFAULT); 531 } 532 533 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 534 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 535 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 536 if (ret < 0) { 537 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 538 goto out; 539 } 540 541 /* Rewrite MAC address */ 542 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 543 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 544 data->mac_addr, in_pm); 545 if (ret < 0) 546 goto out; 547 548 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 549 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 550 if (ret < 0) 551 goto out; 552 553 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 554 if (ret < 0) 555 return ret; 556 557 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 558 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 559 if (ret < 0) 560 goto out; 561 562 rx_ctl = asix_read_rx_ctl(dev, in_pm); 563 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 564 rx_ctl); 565 566 rx_ctl = asix_read_medium_status(dev, in_pm); 567 netdev_dbg(dev->net, 568 "Medium Status is 0x%04x after all initializations\n", 569 rx_ctl); 570 571 return 0; 572 573out: 574 return ret; 575} 576 577static const struct net_device_ops ax88772_netdev_ops = { 578 .ndo_open = usbnet_open, 579 .ndo_stop = usbnet_stop, 580 .ndo_start_xmit = usbnet_start_xmit, 581 .ndo_tx_timeout = usbnet_tx_timeout, 582 .ndo_change_mtu = usbnet_change_mtu, 583 .ndo_get_stats64 = usbnet_get_stats64, 584 .ndo_set_mac_address = asix_set_mac_address, 585 .ndo_validate_addr = eth_validate_addr, 586 .ndo_do_ioctl = asix_ioctl, 587 .ndo_set_rx_mode = asix_set_multicast, 588}; 589 590static void ax88772_suspend(struct usbnet *dev) 591{ 592 struct asix_common_private *priv = dev->driver_priv; 593 u16 medium; 594 595 /* Stop MAC operation */ 596 medium = asix_read_medium_status(dev, 1); 597 medium &= ~AX_MEDIUM_RE; 598 asix_write_medium_mode(dev, medium, 1); 599 600 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", 601 asix_read_medium_status(dev, 1)); 602 603 /* Preserve BMCR for restoring */ 604 priv->presvd_phy_bmcr = 605 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR); 606 607 /* Preserve ANAR for restoring */ 608 priv->presvd_phy_advertise = 609 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE); 610} 611 612static int asix_suspend(struct usb_interface *intf, pm_message_t message) 613{ 614 struct usbnet *dev = usb_get_intfdata(intf); 615 struct asix_common_private *priv = dev->driver_priv; 616 617 if (priv && priv->suspend) 618 priv->suspend(dev); 619 620 return usbnet_suspend(intf, message); 621} 622 623static void ax88772_restore_phy(struct usbnet *dev) 624{ 625 struct asix_common_private *priv = dev->driver_priv; 626 627 if (priv->presvd_phy_advertise) { 628 /* Restore Advertisement control reg */ 629 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE, 630 priv->presvd_phy_advertise); 631 632 /* Restore BMCR */ 633 if (priv->presvd_phy_bmcr & BMCR_ANENABLE) 634 priv->presvd_phy_bmcr |= BMCR_ANRESTART; 635 636 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR, 637 priv->presvd_phy_bmcr); 638 639 priv->presvd_phy_advertise = 0; 640 priv->presvd_phy_bmcr = 0; 641 } 642} 643 644static void ax88772_resume(struct usbnet *dev) 645{ 646 int i; 647 648 for (i = 0; i < 3; i++) 649 if (!ax88772_hw_reset(dev, 1)) 650 break; 651 ax88772_restore_phy(dev); 652} 653 654static void ax88772a_resume(struct usbnet *dev) 655{ 656 int i; 657 658 for (i = 0; i < 3; i++) { 659 if (!ax88772a_hw_reset(dev, 1)) 660 break; 661 } 662 663 ax88772_restore_phy(dev); 664} 665 666static int asix_resume(struct usb_interface *intf) 667{ 668 struct usbnet *dev = usb_get_intfdata(intf); 669 struct asix_common_private *priv = dev->driver_priv; 670 671 if (priv && priv->resume) 672 priv->resume(dev); 673 674 return usbnet_resume(intf); 675} 676 677static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 678{ 679 int ret, i; 680 u8 buf[ETH_ALEN] = {0}, chipcode = 0; 681 u32 phyid; 682 struct asix_common_private *priv; 683 684 usbnet_get_endpoints(dev, intf); 685 686 /* Maybe the boot loader passed the MAC address via device tree */ 687 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { 688 netif_dbg(dev, ifup, dev->net, 689 "MAC address read from device tree"); 690 } else { 691 /* Try getting the MAC address from EEPROM */ 692 if (dev->driver_info->data & FLAG_EEPROM_MAC) { 693 for (i = 0; i < (ETH_ALEN >> 1); i++) { 694 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 695 0x04 + i, 0, 2, buf + i * 2, 696 0); 697 if (ret < 0) 698 break; 699 } 700 } else { 701 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 702 0, 0, ETH_ALEN, buf, 0); 703 } 704 705 if (ret < 0) { 706 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", 707 ret); 708 return ret; 709 } 710 } 711 712 asix_set_netdev_dev_addr(dev, buf); 713 714 /* Initialize MII structure */ 715 dev->mii.dev = dev->net; 716 dev->mii.mdio_read = asix_mdio_read; 717 dev->mii.mdio_write = asix_mdio_write; 718 dev->mii.phy_id_mask = 0x1f; 719 dev->mii.reg_num_mask = 0x1f; 720 dev->mii.phy_id = asix_get_phy_addr(dev); 721 722 dev->net->netdev_ops = &ax88772_netdev_ops; 723 dev->net->ethtool_ops = &ax88772_ethtool_ops; 724 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 725 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 726 727 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0); 728 chipcode &= AX_CHIPCODE_MASK; 729 730 ret = (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) : 731 ax88772a_hw_reset(dev, 0); 732 733 if (ret < 0) { 734 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret); 735 return ret; 736 } 737 738 /* Read PHYID register *AFTER* the PHY was reset properly */ 739 phyid = asix_get_phyid(dev); 740 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 741 742 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 743 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 744 /* hard_mtu is still the default - the device does not support 745 jumbo eth frames */ 746 dev->rx_urb_size = 2048; 747 } 748 749 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 750 if (!dev->driver_priv) 751 return -ENOMEM; 752 753 priv = dev->driver_priv; 754 755 priv->presvd_phy_bmcr = 0; 756 priv->presvd_phy_advertise = 0; 757 if (chipcode == AX_AX88772_CHIPCODE) { 758 priv->resume = ax88772_resume; 759 priv->suspend = ax88772_suspend; 760 } else { 761 priv->resume = ax88772a_resume; 762 priv->suspend = ax88772_suspend; 763 } 764 765 return 0; 766} 767 768static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf) 769{ 770 asix_rx_fixup_common_free(dev->driver_priv); 771 kfree(dev->driver_priv); 772} 773 774static const struct ethtool_ops ax88178_ethtool_ops = { 775 .get_drvinfo = asix_get_drvinfo, 776 .get_link = asix_get_link, 777 .get_msglevel = usbnet_get_msglevel, 778 .set_msglevel = usbnet_set_msglevel, 779 .get_wol = asix_get_wol, 780 .set_wol = asix_set_wol, 781 .get_eeprom_len = asix_get_eeprom_len, 782 .get_eeprom = asix_get_eeprom, 783 .set_eeprom = asix_set_eeprom, 784 .nway_reset = usbnet_nway_reset, 785 .get_link_ksettings = usbnet_get_link_ksettings, 786 .set_link_ksettings = usbnet_set_link_ksettings, 787}; 788 789static int marvell_phy_init(struct usbnet *dev) 790{ 791 struct asix_data *data = (struct asix_data *)&dev->data; 792 u16 reg; 793 794 netdev_dbg(dev->net, "marvell_phy_init()\n"); 795 796 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 797 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 798 799 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 800 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 801 802 if (data->ledmode) { 803 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 804 MII_MARVELL_LED_CTRL); 805 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 806 807 reg &= 0xf8ff; 808 reg |= (1 + 0x0100); 809 asix_mdio_write(dev->net, dev->mii.phy_id, 810 MII_MARVELL_LED_CTRL, reg); 811 812 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 813 MII_MARVELL_LED_CTRL); 814 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 815 reg &= 0xfc0f; 816 } 817 818 return 0; 819} 820 821static int rtl8211cl_phy_init(struct usbnet *dev) 822{ 823 struct asix_data *data = (struct asix_data *)&dev->data; 824 825 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 826 827 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 829 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 830 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 831 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 832 833 if (data->ledmode == 12) { 834 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 835 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 836 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 837 } 838 839 return 0; 840} 841 842static int marvell_led_status(struct usbnet *dev, u16 speed) 843{ 844 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 845 846 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 847 848 /* Clear out the center LED bits - 0x03F0 */ 849 reg &= 0xfc0f; 850 851 switch (speed) { 852 case SPEED_1000: 853 reg |= 0x03e0; 854 break; 855 case SPEED_100: 856 reg |= 0x03b0; 857 break; 858 default: 859 reg |= 0x02f0; 860 } 861 862 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 863 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 864 865 return 0; 866} 867 868static int ax88178_reset(struct usbnet *dev) 869{ 870 struct asix_data *data = (struct asix_data *)&dev->data; 871 int ret; 872 __le16 eeprom; 873 u8 status; 874 int gpio0 = 0; 875 u32 phyid; 876 877 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0); 878 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 879 880 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0); 881 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0); 882 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0); 883 884 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 885 886 if (eeprom == cpu_to_le16(0xffff)) { 887 data->phymode = PHY_MODE_MARVELL; 888 data->ledmode = 0; 889 gpio0 = 1; 890 } else { 891 data->phymode = le16_to_cpu(eeprom) & 0x7F; 892 data->ledmode = le16_to_cpu(eeprom) >> 8; 893 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 894 } 895 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 896 897 /* Power up external GigaPHY through AX88178 GPIO pin */ 898 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | 899 AX_GPIO_GPO1EN, 40, 0); 900 if ((le16_to_cpu(eeprom) >> 8) != 1) { 901 asix_write_gpio(dev, 0x003c, 30, 0); 902 asix_write_gpio(dev, 0x001c, 300, 0); 903 asix_write_gpio(dev, 0x003c, 30, 0); 904 } else { 905 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 906 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0); 907 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0); 908 } 909 910 /* Read PHYID register *AFTER* powering up PHY */ 911 phyid = asix_get_phyid(dev); 912 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 913 914 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 915 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0); 916 917 asix_sw_reset(dev, 0, 0); 918 msleep(150); 919 920 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 921 msleep(150); 922 923 asix_write_rx_ctl(dev, 0, 0); 924 925 if (data->phymode == PHY_MODE_MARVELL) { 926 marvell_phy_init(dev); 927 msleep(60); 928 } else if (data->phymode == PHY_MODE_RTL8211CL) 929 rtl8211cl_phy_init(dev); 930 931 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE); 932 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 933 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 934 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 935 ADVERTISE_1000FULL); 936 937 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0); 938 mii_nway_restart(&dev->mii); 939 940 /* Rewrite MAC address */ 941 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 942 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 943 data->mac_addr, 0); 944 if (ret < 0) 945 return ret; 946 947 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 948 if (ret < 0) 949 return ret; 950 951 return 0; 952} 953 954static int ax88178_link_reset(struct usbnet *dev) 955{ 956 u16 mode; 957 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 958 struct asix_data *data = (struct asix_data *)&dev->data; 959 u32 speed; 960 961 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 962 963 mii_check_media(&dev->mii, 1, 1); 964 mii_ethtool_gset(&dev->mii, &ecmd); 965 mode = AX88178_MEDIUM_DEFAULT; 966 speed = ethtool_cmd_speed(&ecmd); 967 968 if (speed == SPEED_1000) 969 mode |= AX_MEDIUM_GM; 970 else if (speed == SPEED_100) 971 mode |= AX_MEDIUM_PS; 972 else 973 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 974 975 mode |= AX_MEDIUM_ENCK; 976 977 if (ecmd.duplex == DUPLEX_FULL) 978 mode |= AX_MEDIUM_FD; 979 else 980 mode &= ~AX_MEDIUM_FD; 981 982 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 983 speed, ecmd.duplex, mode); 984 985 asix_write_medium_mode(dev, mode, 0); 986 987 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 988 marvell_led_status(dev, speed); 989 990 return 0; 991} 992 993static void ax88178_set_mfb(struct usbnet *dev) 994{ 995 u16 mfb = AX_RX_CTL_MFB_16384; 996 u16 rxctl; 997 u16 medium; 998 int old_rx_urb_size = dev->rx_urb_size; 999 1000 if (dev->hard_mtu < 2048) { 1001 dev->rx_urb_size = 2048; 1002 mfb = AX_RX_CTL_MFB_2048; 1003 } else if (dev->hard_mtu < 4096) { 1004 dev->rx_urb_size = 4096; 1005 mfb = AX_RX_CTL_MFB_4096; 1006 } else if (dev->hard_mtu < 8192) { 1007 dev->rx_urb_size = 8192; 1008 mfb = AX_RX_CTL_MFB_8192; 1009 } else if (dev->hard_mtu < 16384) { 1010 dev->rx_urb_size = 16384; 1011 mfb = AX_RX_CTL_MFB_16384; 1012 } 1013 1014 rxctl = asix_read_rx_ctl(dev, 0); 1015 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0); 1016 1017 medium = asix_read_medium_status(dev, 0); 1018 if (dev->net->mtu > 1500) 1019 medium |= AX_MEDIUM_JFE; 1020 else 1021 medium &= ~AX_MEDIUM_JFE; 1022 asix_write_medium_mode(dev, medium, 0); 1023 1024 if (dev->rx_urb_size > old_rx_urb_size) 1025 usbnet_unlink_rx_urbs(dev); 1026} 1027 1028static int ax88178_change_mtu(struct net_device *net, int new_mtu) 1029{ 1030 struct usbnet *dev = netdev_priv(net); 1031 int ll_mtu = new_mtu + net->hard_header_len + 4; 1032 1033 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 1034 1035 if ((ll_mtu % dev->maxpacket) == 0) 1036 return -EDOM; 1037 1038 net->mtu = new_mtu; 1039 dev->hard_mtu = net->mtu + net->hard_header_len; 1040 ax88178_set_mfb(dev); 1041 1042 /* max qlen depend on hard_mtu and rx_urb_size */ 1043 usbnet_update_max_qlen(dev); 1044 1045 return 0; 1046} 1047 1048static const struct net_device_ops ax88178_netdev_ops = { 1049 .ndo_open = usbnet_open, 1050 .ndo_stop = usbnet_stop, 1051 .ndo_start_xmit = usbnet_start_xmit, 1052 .ndo_tx_timeout = usbnet_tx_timeout, 1053 .ndo_get_stats64 = usbnet_get_stats64, 1054 .ndo_set_mac_address = asix_set_mac_address, 1055 .ndo_validate_addr = eth_validate_addr, 1056 .ndo_set_rx_mode = asix_set_multicast, 1057 .ndo_do_ioctl = asix_ioctl, 1058 .ndo_change_mtu = ax88178_change_mtu, 1059}; 1060 1061static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 1062{ 1063 int ret; 1064 u8 buf[ETH_ALEN] = {0}; 1065 1066 usbnet_get_endpoints(dev,intf); 1067 1068 /* Get the MAC address */ 1069 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); 1070 if (ret < 0) { 1071 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 1072 return ret; 1073 } 1074 1075 asix_set_netdev_dev_addr(dev, buf); 1076 1077 /* Initialize MII structure */ 1078 dev->mii.dev = dev->net; 1079 dev->mii.mdio_read = asix_mdio_read; 1080 dev->mii.mdio_write = asix_mdio_write; 1081 dev->mii.phy_id_mask = 0x1f; 1082 dev->mii.reg_num_mask = 0xff; 1083 dev->mii.supports_gmii = 1; 1084 dev->mii.phy_id = asix_get_phy_addr(dev); 1085 1086 dev->net->netdev_ops = &ax88178_netdev_ops; 1087 dev->net->ethtool_ops = &ax88178_ethtool_ops; 1088 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); 1089 1090 /* Blink LEDS so users know driver saw dongle */ 1091 asix_sw_reset(dev, 0, 0); 1092 msleep(150); 1093 1094 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1095 msleep(150); 1096 1097 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 1098 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 1099 /* hard_mtu is still the default - the device does not support 1100 jumbo eth frames */ 1101 dev->rx_urb_size = 2048; 1102 } 1103 1104 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 1105 if (!dev->driver_priv) 1106 return -ENOMEM; 1107 1108 return 0; 1109} 1110 1111static const struct driver_info ax8817x_info = { 1112 .description = "ASIX AX8817x USB 2.0 Ethernet", 1113 .bind = ax88172_bind, 1114 .status = asix_status, 1115 .link_reset = ax88172_link_reset, 1116 .reset = ax88172_link_reset, 1117 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1118 .data = 0x00130103, 1119}; 1120 1121static const struct driver_info dlink_dub_e100_info = { 1122 .description = "DLink DUB-E100 USB Ethernet", 1123 .bind = ax88172_bind, 1124 .status = asix_status, 1125 .link_reset = ax88172_link_reset, 1126 .reset = ax88172_link_reset, 1127 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1128 .data = 0x009f9d9f, 1129}; 1130 1131static const struct driver_info netgear_fa120_info = { 1132 .description = "Netgear FA-120 USB Ethernet", 1133 .bind = ax88172_bind, 1134 .status = asix_status, 1135 .link_reset = ax88172_link_reset, 1136 .reset = ax88172_link_reset, 1137 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1138 .data = 0x00130103, 1139}; 1140 1141static const struct driver_info hawking_uf200_info = { 1142 .description = "Hawking UF200 USB Ethernet", 1143 .bind = ax88172_bind, 1144 .status = asix_status, 1145 .link_reset = ax88172_link_reset, 1146 .reset = ax88172_link_reset, 1147 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1148 .data = 0x001f1d1f, 1149}; 1150 1151static const struct driver_info ax88772_info = { 1152 .description = "ASIX AX88772 USB 2.0 Ethernet", 1153 .bind = ax88772_bind, 1154 .unbind = ax88772_unbind, 1155 .status = asix_status, 1156 .link_reset = ax88772_link_reset, 1157 .reset = ax88772_reset, 1158 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, 1159 .rx_fixup = asix_rx_fixup_common, 1160 .tx_fixup = asix_tx_fixup, 1161}; 1162 1163static const struct driver_info ax88772b_info = { 1164 .description = "ASIX AX88772B USB 2.0 Ethernet", 1165 .bind = ax88772_bind, 1166 .unbind = ax88772_unbind, 1167 .status = asix_status, 1168 .link_reset = ax88772_link_reset, 1169 .reset = ax88772_reset, 1170 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1171 FLAG_MULTI_PACKET, 1172 .rx_fixup = asix_rx_fixup_common, 1173 .tx_fixup = asix_tx_fixup, 1174 .data = FLAG_EEPROM_MAC, 1175}; 1176 1177static const struct driver_info ax88178_info = { 1178 .description = "ASIX AX88178 USB 2.0 Ethernet", 1179 .bind = ax88178_bind, 1180 .unbind = ax88772_unbind, 1181 .status = asix_status, 1182 .link_reset = ax88178_link_reset, 1183 .reset = ax88178_reset, 1184 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1185 FLAG_MULTI_PACKET, 1186 .rx_fixup = asix_rx_fixup_common, 1187 .tx_fixup = asix_tx_fixup, 1188}; 1189 1190/* 1191 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in 1192 * no-name packaging. 1193 * USB device strings are: 1194 * 1: Manufacturer: USBLINK 1195 * 2: Product: HG20F9 USB2.0 1196 * 3: Serial: 000003 1197 * Appears to be compatible with Asix 88772B. 1198 */ 1199static const struct driver_info hg20f9_info = { 1200 .description = "HG20F9 USB 2.0 Ethernet", 1201 .bind = ax88772_bind, 1202 .unbind = ax88772_unbind, 1203 .status = asix_status, 1204 .link_reset = ax88772_link_reset, 1205 .reset = ax88772_reset, 1206 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1207 FLAG_MULTI_PACKET, 1208 .rx_fixup = asix_rx_fixup_common, 1209 .tx_fixup = asix_tx_fixup, 1210 .data = FLAG_EEPROM_MAC, 1211}; 1212 1213static const struct usb_device_id products [] = { 1214{ 1215 // Linksys USB200M 1216 USB_DEVICE (0x077b, 0x2226), 1217 .driver_info = (unsigned long) &ax8817x_info, 1218}, { 1219 // Netgear FA120 1220 USB_DEVICE (0x0846, 0x1040), 1221 .driver_info = (unsigned long) &netgear_fa120_info, 1222}, { 1223 // DLink DUB-E100 1224 USB_DEVICE (0x2001, 0x1a00), 1225 .driver_info = (unsigned long) &dlink_dub_e100_info, 1226}, { 1227 // Intellinet, ST Lab USB Ethernet 1228 USB_DEVICE (0x0b95, 0x1720), 1229 .driver_info = (unsigned long) &ax8817x_info, 1230}, { 1231 // Hawking UF200, TrendNet TU2-ET100 1232 USB_DEVICE (0x07b8, 0x420a), 1233 .driver_info = (unsigned long) &hawking_uf200_info, 1234}, { 1235 // Billionton Systems, USB2AR 1236 USB_DEVICE (0x08dd, 0x90ff), 1237 .driver_info = (unsigned long) &ax8817x_info, 1238}, { 1239 // Billionton Systems, GUSB2AM-1G-B 1240 USB_DEVICE(0x08dd, 0x0114), 1241 .driver_info = (unsigned long) &ax88178_info, 1242}, { 1243 // ATEN UC210T 1244 USB_DEVICE (0x0557, 0x2009), 1245 .driver_info = (unsigned long) &ax8817x_info, 1246}, { 1247 // Buffalo LUA-U2-KTX 1248 USB_DEVICE (0x0411, 0x003d), 1249 .driver_info = (unsigned long) &ax8817x_info, 1250}, { 1251 // Buffalo LUA-U2-GT 10/100/1000 1252 USB_DEVICE (0x0411, 0x006e), 1253 .driver_info = (unsigned long) &ax88178_info, 1254}, { 1255 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 1256 USB_DEVICE (0x6189, 0x182d), 1257 .driver_info = (unsigned long) &ax8817x_info, 1258}, { 1259 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 1260 USB_DEVICE (0x0df6, 0x0056), 1261 .driver_info = (unsigned long) &ax88178_info, 1262}, { 1263 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter" 1264 USB_DEVICE (0x0df6, 0x061c), 1265 .driver_info = (unsigned long) &ax88178_info, 1266}, { 1267 // corega FEther USB2-TX 1268 USB_DEVICE (0x07aa, 0x0017), 1269 .driver_info = (unsigned long) &ax8817x_info, 1270}, { 1271 // Surecom EP-1427X-2 1272 USB_DEVICE (0x1189, 0x0893), 1273 .driver_info = (unsigned long) &ax8817x_info, 1274}, { 1275 // goodway corp usb gwusb2e 1276 USB_DEVICE (0x1631, 0x6200), 1277 .driver_info = (unsigned long) &ax8817x_info, 1278}, { 1279 // JVC MP-PRX1 Port Replicator 1280 USB_DEVICE (0x04f1, 0x3008), 1281 .driver_info = (unsigned long) &ax8817x_info, 1282}, { 1283 // Lenovo U2L100P 10/100 1284 USB_DEVICE (0x17ef, 0x7203), 1285 .driver_info = (unsigned long)&ax88772b_info, 1286}, { 1287 // ASIX AX88772B 10/100 1288 USB_DEVICE (0x0b95, 0x772b), 1289 .driver_info = (unsigned long) &ax88772b_info, 1290}, { 1291 // ASIX AX88772 10/100 1292 USB_DEVICE (0x0b95, 0x7720), 1293 .driver_info = (unsigned long) &ax88772_info, 1294}, { 1295 // ASIX AX88178 10/100/1000 1296 USB_DEVICE (0x0b95, 0x1780), 1297 .driver_info = (unsigned long) &ax88178_info, 1298}, { 1299 // Logitec LAN-GTJ/U2A 1300 USB_DEVICE (0x0789, 0x0160), 1301 .driver_info = (unsigned long) &ax88178_info, 1302}, { 1303 // Linksys USB200M Rev 2 1304 USB_DEVICE (0x13b1, 0x0018), 1305 .driver_info = (unsigned long) &ax88772_info, 1306}, { 1307 // 0Q0 cable ethernet 1308 USB_DEVICE (0x1557, 0x7720), 1309 .driver_info = (unsigned long) &ax88772_info, 1310}, { 1311 // DLink DUB-E100 H/W Ver B1 1312 USB_DEVICE (0x07d1, 0x3c05), 1313 .driver_info = (unsigned long) &ax88772_info, 1314}, { 1315 // DLink DUB-E100 H/W Ver B1 Alternate 1316 USB_DEVICE (0x2001, 0x3c05), 1317 .driver_info = (unsigned long) &ax88772_info, 1318}, { 1319 // DLink DUB-E100 H/W Ver C1 1320 USB_DEVICE (0x2001, 0x1a02), 1321 .driver_info = (unsigned long) &ax88772_info, 1322}, { 1323 // Linksys USB1000 1324 USB_DEVICE (0x1737, 0x0039), 1325 .driver_info = (unsigned long) &ax88178_info, 1326}, { 1327 // IO-DATA ETG-US2 1328 USB_DEVICE (0x04bb, 0x0930), 1329 .driver_info = (unsigned long) &ax88178_info, 1330}, { 1331 // Belkin F5D5055 1332 USB_DEVICE(0x050d, 0x5055), 1333 .driver_info = (unsigned long) &ax88178_info, 1334}, { 1335 // Apple USB Ethernet Adapter 1336 USB_DEVICE(0x05ac, 0x1402), 1337 .driver_info = (unsigned long) &ax88772_info, 1338}, { 1339 // Cables-to-Go USB Ethernet Adapter 1340 USB_DEVICE(0x0b95, 0x772a), 1341 .driver_info = (unsigned long) &ax88772_info, 1342}, { 1343 // ABOCOM for pci 1344 USB_DEVICE(0x14ea, 0xab11), 1345 .driver_info = (unsigned long) &ax88178_info, 1346}, { 1347 // ASIX 88772a 1348 USB_DEVICE(0x0db0, 0xa877), 1349 .driver_info = (unsigned long) &ax88772_info, 1350}, { 1351 // Asus USB Ethernet Adapter 1352 USB_DEVICE (0x0b95, 0x7e2b), 1353 .driver_info = (unsigned long)&ax88772b_info, 1354}, { 1355 /* ASIX 88172a demo board */ 1356 USB_DEVICE(0x0b95, 0x172a), 1357 .driver_info = (unsigned long) &ax88172a_info, 1358}, { 1359 /* 1360 * USBLINK HG20F9 "USB 2.0 LAN" 1361 * Appears to have gazumped Linksys's manufacturer ID but 1362 * doesn't (yet) conflict with any known Linksys product. 1363 */ 1364 USB_DEVICE(0x066b, 0x20f9), 1365 .driver_info = (unsigned long) &hg20f9_info, 1366}, 1367 { }, // END 1368}; 1369MODULE_DEVICE_TABLE(usb, products); 1370 1371static struct usb_driver asix_driver = { 1372 .name = DRIVER_NAME, 1373 .id_table = products, 1374 .probe = usbnet_probe, 1375 .suspend = asix_suspend, 1376 .resume = asix_resume, 1377 .reset_resume = asix_resume, 1378 .disconnect = usbnet_disconnect, 1379 .supports_autosuspend = 1, 1380 .disable_hub_initiated_lpm = 1, 1381}; 1382 1383module_usb_driver(asix_driver); 1384 1385MODULE_AUTHOR("David Hollis"); 1386MODULE_VERSION(DRIVER_VERSION); 1387MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1388MODULE_LICENSE("GPL"); 1389 1390