1// SPDX-License-Identifier: GPL-2.0+ 2/* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10#include <linux/bitops.h> 11#include <linux/phy.h> 12#include <linux/module.h> 13#include <linux/delay.h> 14 15#define RTL821x_PHYSR 0x11 16#define RTL821x_PHYSR_DUPLEX BIT(13) 17#define RTL821x_PHYSR_SPEED GENMASK(15, 14) 18 19#define RTL821x_INER 0x12 20#define RTL8211B_INER_INIT 0x6400 21#define RTL8211E_INER_LINK_STATUS BIT(10) 22#define RTL8211F_INER_LINK_STATUS BIT(4) 23 24#define RTL821x_INSR 0x13 25 26#define RTL821x_EXT_PAGE_SELECT 0x1e 27#define RTL821x_PAGE_SELECT 0x1f 28 29#define RTL8211F_PHYCR1 0x18 30#define RTL8211F_INSR 0x1d 31 32#define RTL8211F_TX_DELAY BIT(8) 33#define RTL8211F_RX_DELAY BIT(3) 34 35#define RTL8211F_ALDPS_PLL_OFF BIT(1) 36#define RTL8211F_ALDPS_ENABLE BIT(2) 37#define RTL8211F_ALDPS_XTAL_OFF BIT(12) 38 39#define RTL8211E_CTRL_DELAY BIT(13) 40#define RTL8211E_TX_DELAY BIT(12) 41#define RTL8211E_RX_DELAY BIT(11) 42 43#define RTL8201F_ISR 0x1e 44#define RTL8201F_IER 0x13 45 46#define RTL8366RB_POWER_SAVE 0x15 47#define RTL8366RB_POWER_SAVE_ON BIT(12) 48 49#define RTL_SUPPORTS_5000FULL BIT(14) 50#define RTL_SUPPORTS_2500FULL BIT(13) 51#define RTL_SUPPORTS_10000FULL BIT(0) 52#define RTL_ADV_2500FULL BIT(7) 53#define RTL_LPADV_10000FULL BIT(11) 54#define RTL_LPADV_5000FULL BIT(6) 55#define RTL_LPADV_2500FULL BIT(5) 56 57#define RTLGEN_SPEED_MASK 0x0630 58 59#define RTL_GENERIC_PHYID 0x001cc800 60 61MODULE_DESCRIPTION("Realtek PHY driver"); 62MODULE_AUTHOR("Johnson Leung"); 63MODULE_LICENSE("GPL"); 64 65static int rtl821x_read_page(struct phy_device *phydev) 66{ 67 return __phy_read(phydev, RTL821x_PAGE_SELECT); 68} 69 70static int rtl821x_write_page(struct phy_device *phydev, int page) 71{ 72 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 73} 74 75static int rtl8201_ack_interrupt(struct phy_device *phydev) 76{ 77 int err; 78 79 err = phy_read(phydev, RTL8201F_ISR); 80 81 return (err < 0) ? err : 0; 82} 83 84static int rtl821x_ack_interrupt(struct phy_device *phydev) 85{ 86 int err; 87 88 err = phy_read(phydev, RTL821x_INSR); 89 90 return (err < 0) ? err : 0; 91} 92 93static int rtl8211f_ack_interrupt(struct phy_device *phydev) 94{ 95 int err; 96 97 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 98 99 return (err < 0) ? err : 0; 100} 101 102static int rtl8201_config_intr(struct phy_device *phydev) 103{ 104 u16 val; 105 106 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 107 val = BIT(13) | BIT(12) | BIT(11); 108 else 109 val = 0; 110 111 return phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 112} 113 114static int rtl8211b_config_intr(struct phy_device *phydev) 115{ 116 int err; 117 118 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 119 err = phy_write(phydev, RTL821x_INER, 120 RTL8211B_INER_INIT); 121 else 122 err = phy_write(phydev, RTL821x_INER, 0); 123 124 return err; 125} 126 127static int rtl8211e_config_intr(struct phy_device *phydev) 128{ 129 int err; 130 131 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 132 err = phy_write(phydev, RTL821x_INER, 133 RTL8211E_INER_LINK_STATUS); 134 else 135 err = phy_write(phydev, RTL821x_INER, 0); 136 137 return err; 138} 139 140static int rtl8211f_config_intr(struct phy_device *phydev) 141{ 142 u16 val; 143 144 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 145 val = RTL8211F_INER_LINK_STATUS; 146 else 147 val = 0; 148 149 return phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 150} 151 152static int rtl8211_config_aneg(struct phy_device *phydev) 153{ 154 int ret; 155 156 ret = genphy_config_aneg(phydev); 157 if (ret < 0) 158 return ret; 159 160 /* Quirk was copied from vendor driver. Unfortunately it includes no 161 * description of the magic numbers. 162 */ 163 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 164 phy_write(phydev, 0x17, 0x2138); 165 phy_write(phydev, 0x0e, 0x0260); 166 } else { 167 phy_write(phydev, 0x17, 0x2108); 168 phy_write(phydev, 0x0e, 0x0000); 169 } 170 171 return 0; 172} 173 174static int rtl8211c_config_init(struct phy_device *phydev) 175{ 176 /* RTL8211C has an issue when operating in Gigabit slave mode */ 177 return phy_set_bits(phydev, MII_CTRL1000, 178 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 179} 180 181static int rtl8211f_config_init(struct phy_device *phydev) 182{ 183 struct device *dev = &phydev->mdio.dev; 184 u16 val_txdly, val_rxdly; 185 u16 val; 186 int ret; 187 188 val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF; 189 phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val); 190 191 switch (phydev->interface) { 192 case PHY_INTERFACE_MODE_RGMII: 193 val_txdly = 0; 194 val_rxdly = 0; 195 break; 196 197 case PHY_INTERFACE_MODE_RGMII_RXID: 198 val_txdly = 0; 199 val_rxdly = RTL8211F_RX_DELAY; 200 break; 201 202 case PHY_INTERFACE_MODE_RGMII_TXID: 203 val_txdly = RTL8211F_TX_DELAY; 204 val_rxdly = 0; 205 break; 206 207 case PHY_INTERFACE_MODE_RGMII_ID: 208 val_txdly = RTL8211F_TX_DELAY; 209 val_rxdly = RTL8211F_RX_DELAY; 210 break; 211 212 default: /* the rest of the modes imply leaving delay as is. */ 213 return 0; 214 } 215 216 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, 217 val_txdly); 218 if (ret < 0) { 219 dev_err(dev, "Failed to update the TX delay register\n"); 220 return ret; 221 } else if (ret) { 222 dev_dbg(dev, 223 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 224 val_txdly ? "Enabling" : "Disabling"); 225 } else { 226 dev_dbg(dev, 227 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 228 val_txdly ? "enabled" : "disabled"); 229 } 230 231 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, 232 val_rxdly); 233 if (ret < 0) { 234 dev_err(dev, "Failed to update the RX delay register\n"); 235 return ret; 236 } else if (ret) { 237 dev_dbg(dev, 238 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 239 val_rxdly ? "Enabling" : "Disabling"); 240 } else { 241 dev_dbg(dev, 242 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 243 val_rxdly ? "enabled" : "disabled"); 244 } 245 246 return 0; 247} 248 249static int rtl821x_resume(struct phy_device *phydev) 250{ 251 int ret; 252 253 ret = genphy_resume(phydev); 254 if (ret < 0) 255 return ret; 256 257 msleep(20); 258 259 return 0; 260} 261 262static int rtl8211e_config_init(struct phy_device *phydev) 263{ 264 int ret = 0, oldpage; 265 u16 val; 266 267 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 268 switch (phydev->interface) { 269 case PHY_INTERFACE_MODE_RGMII: 270 val = RTL8211E_CTRL_DELAY | 0; 271 break; 272 case PHY_INTERFACE_MODE_RGMII_ID: 273 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 274 break; 275 case PHY_INTERFACE_MODE_RGMII_RXID: 276 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 277 break; 278 case PHY_INTERFACE_MODE_RGMII_TXID: 279 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 280 break; 281 default: /* the rest of the modes imply leaving delays as is. */ 282 return 0; 283 } 284 285 /* According to a sample driver there is a 0x1c config register on the 286 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 287 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 288 * The configuration register definition: 289 * 14 = reserved 290 * 13 = Force Tx RX Delay controlled by bit12 bit11, 291 * 12 = RX Delay, 11 = TX Delay 292 * 10:0 = Test && debug settings reserved by realtek 293 */ 294 oldpage = phy_select_page(phydev, 0x7); 295 if (oldpage < 0) 296 goto err_restore_page; 297 298 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); 299 if (ret) 300 goto err_restore_page; 301 302 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY 303 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, 304 val); 305 306err_restore_page: 307 return phy_restore_page(phydev, oldpage, ret); 308} 309 310static int rtl8211b_suspend(struct phy_device *phydev) 311{ 312 phy_write(phydev, MII_MMD_DATA, BIT(9)); 313 314 return genphy_suspend(phydev); 315} 316 317static int rtl8211b_resume(struct phy_device *phydev) 318{ 319 phy_write(phydev, MII_MMD_DATA, 0); 320 321 return genphy_resume(phydev); 322} 323 324static int rtl8366rb_config_init(struct phy_device *phydev) 325{ 326 int ret; 327 328 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 329 RTL8366RB_POWER_SAVE_ON); 330 if (ret) { 331 dev_err(&phydev->mdio.dev, 332 "error enabling power management\n"); 333 } 334 335 return ret; 336} 337 338/* get actual speed to cover the downshift case */ 339static int rtlgen_get_speed(struct phy_device *phydev) 340{ 341 int val; 342 343 if (!phydev->link) 344 return 0; 345 346 val = phy_read_paged(phydev, 0xa43, 0x12); 347 if (val < 0) 348 return val; 349 350 switch (val & RTLGEN_SPEED_MASK) { 351 case 0x0000: 352 phydev->speed = SPEED_10; 353 break; 354 case 0x0010: 355 phydev->speed = SPEED_100; 356 break; 357 case 0x0020: 358 phydev->speed = SPEED_1000; 359 break; 360 case 0x0200: 361 phydev->speed = SPEED_10000; 362 break; 363 case 0x0210: 364 phydev->speed = SPEED_2500; 365 break; 366 case 0x0220: 367 phydev->speed = SPEED_5000; 368 break; 369 default: 370 break; 371 } 372 373 return 0; 374} 375 376static int rtlgen_read_status(struct phy_device *phydev) 377{ 378 int ret; 379 380 ret = genphy_read_status(phydev); 381 if (ret < 0) 382 return ret; 383 384 return rtlgen_get_speed(phydev); 385} 386 387static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 388{ 389 int ret; 390 391 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) { 392 rtl821x_write_page(phydev, 0xa5c); 393 ret = __phy_read(phydev, 0x12); 394 rtl821x_write_page(phydev, 0); 395 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 396 rtl821x_write_page(phydev, 0xa5d); 397 ret = __phy_read(phydev, 0x10); 398 rtl821x_write_page(phydev, 0); 399 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { 400 rtl821x_write_page(phydev, 0xa5d); 401 ret = __phy_read(phydev, 0x11); 402 rtl821x_write_page(phydev, 0); 403 } else { 404 ret = -EOPNOTSUPP; 405 } 406 407 return ret; 408} 409 410static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 411 u16 val) 412{ 413 int ret; 414 415 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 416 rtl821x_write_page(phydev, 0xa5d); 417 ret = __phy_write(phydev, 0x10, val); 418 rtl821x_write_page(phydev, 0); 419 } else { 420 ret = -EOPNOTSUPP; 421 } 422 423 return ret; 424} 425 426static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 427{ 428 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 429 430 if (ret != -EOPNOTSUPP) 431 return ret; 432 433 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) { 434 rtl821x_write_page(phydev, 0xa6e); 435 ret = __phy_read(phydev, 0x16); 436 rtl821x_write_page(phydev, 0); 437 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 438 rtl821x_write_page(phydev, 0xa6d); 439 ret = __phy_read(phydev, 0x12); 440 rtl821x_write_page(phydev, 0); 441 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { 442 rtl821x_write_page(phydev, 0xa6d); 443 ret = __phy_read(phydev, 0x10); 444 rtl821x_write_page(phydev, 0); 445 } 446 447 return ret; 448} 449 450static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 451 u16 val) 452{ 453 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 454 455 if (ret != -EOPNOTSUPP) 456 return ret; 457 458 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 459 rtl821x_write_page(phydev, 0xa6d); 460 ret = __phy_write(phydev, 0x12, val); 461 rtl821x_write_page(phydev, 0); 462 } 463 464 return ret; 465} 466 467static int rtl822x_get_features(struct phy_device *phydev) 468{ 469 int val; 470 471 val = phy_read_paged(phydev, 0xa61, 0x13); 472 if (val < 0) 473 return val; 474 475 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 476 phydev->supported, val & RTL_SUPPORTS_2500FULL); 477 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 478 phydev->supported, val & RTL_SUPPORTS_5000FULL); 479 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 480 phydev->supported, val & RTL_SUPPORTS_10000FULL); 481 482 return genphy_read_abilities(phydev); 483} 484 485static int rtl822x_config_aneg(struct phy_device *phydev) 486{ 487 int ret = 0; 488 489 if (phydev->autoneg == AUTONEG_ENABLE) { 490 u16 adv2500 = 0; 491 492 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 493 phydev->advertising)) 494 adv2500 = RTL_ADV_2500FULL; 495 496 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, 497 RTL_ADV_2500FULL, adv2500); 498 if (ret < 0) 499 return ret; 500 } 501 502 return __genphy_config_aneg(phydev, ret); 503} 504 505static int rtl822x_read_status(struct phy_device *phydev) 506{ 507 int ret; 508 509 if (phydev->autoneg == AUTONEG_ENABLE) { 510 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13); 511 512 if (lpadv < 0) 513 return lpadv; 514 515 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 516 phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL); 517 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 518 phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL); 519 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 520 phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL); 521 } 522 523 ret = genphy_read_status(phydev); 524 if (ret < 0) 525 return ret; 526 527 return rtlgen_get_speed(phydev); 528} 529 530static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 531{ 532 int val; 533 534 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 535 val = phy_read(phydev, 0x13); 536 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 537 538 return val >= 0 && val & RTL_SUPPORTS_2500FULL; 539} 540 541static int rtlgen_match_phy_device(struct phy_device *phydev) 542{ 543 return phydev->phy_id == RTL_GENERIC_PHYID && 544 !rtlgen_supports_2_5gbps(phydev); 545} 546 547static int rtl8226_match_phy_device(struct phy_device *phydev) 548{ 549 return phydev->phy_id == RTL_GENERIC_PHYID && 550 rtlgen_supports_2_5gbps(phydev); 551} 552 553static int rtlgen_resume(struct phy_device *phydev) 554{ 555 int ret = genphy_resume(phydev); 556 557 /* Internal PHY's from RTL8168h up may not be instantly ready */ 558 msleep(20); 559 560 return ret; 561} 562 563static struct phy_driver realtek_drvs[] = { 564 { 565 PHY_ID_MATCH_EXACT(0x00008201), 566 .name = "RTL8201CP Ethernet", 567 .read_page = rtl821x_read_page, 568 .write_page = rtl821x_write_page, 569 }, { 570 PHY_ID_MATCH_EXACT(0x001cc816), 571 .name = "RTL8201F Fast Ethernet", 572 .ack_interrupt = &rtl8201_ack_interrupt, 573 .config_intr = &rtl8201_config_intr, 574 .suspend = genphy_suspend, 575 .resume = genphy_resume, 576 .read_page = rtl821x_read_page, 577 .write_page = rtl821x_write_page, 578 }, { 579 PHY_ID_MATCH_MODEL(0x001cc880), 580 .name = "RTL8208 Fast Ethernet", 581 .read_mmd = genphy_read_mmd_unsupported, 582 .write_mmd = genphy_write_mmd_unsupported, 583 .suspend = genphy_suspend, 584 .resume = genphy_resume, 585 .read_page = rtl821x_read_page, 586 .write_page = rtl821x_write_page, 587 }, { 588 PHY_ID_MATCH_EXACT(0x001cc910), 589 .name = "RTL8211 Gigabit Ethernet", 590 .config_aneg = rtl8211_config_aneg, 591 .read_mmd = &genphy_read_mmd_unsupported, 592 .write_mmd = &genphy_write_mmd_unsupported, 593 .read_page = rtl821x_read_page, 594 .write_page = rtl821x_write_page, 595 }, { 596 PHY_ID_MATCH_EXACT(0x001cc912), 597 .name = "RTL8211B Gigabit Ethernet", 598 .ack_interrupt = &rtl821x_ack_interrupt, 599 .config_intr = &rtl8211b_config_intr, 600 .read_mmd = &genphy_read_mmd_unsupported, 601 .write_mmd = &genphy_write_mmd_unsupported, 602 .suspend = rtl8211b_suspend, 603 .resume = rtl8211b_resume, 604 .read_page = rtl821x_read_page, 605 .write_page = rtl821x_write_page, 606 }, { 607 PHY_ID_MATCH_EXACT(0x001cc913), 608 .name = "RTL8211C Gigabit Ethernet", 609 .config_init = rtl8211c_config_init, 610 .read_mmd = &genphy_read_mmd_unsupported, 611 .write_mmd = &genphy_write_mmd_unsupported, 612 .read_page = rtl821x_read_page, 613 .write_page = rtl821x_write_page, 614 }, { 615 PHY_ID_MATCH_EXACT(0x001cc914), 616 .name = "RTL8211DN Gigabit Ethernet", 617 .ack_interrupt = rtl821x_ack_interrupt, 618 .config_intr = rtl8211e_config_intr, 619 .suspend = genphy_suspend, 620 .resume = genphy_resume, 621 .read_page = rtl821x_read_page, 622 .write_page = rtl821x_write_page, 623 }, { 624 PHY_ID_MATCH_EXACT(0x001cc915), 625 .name = "RTL8211E Gigabit Ethernet", 626 .config_init = &rtl8211e_config_init, 627 .ack_interrupt = &rtl821x_ack_interrupt, 628 .config_intr = &rtl8211e_config_intr, 629 .suspend = genphy_suspend, 630 .resume = genphy_resume, 631 .read_page = rtl821x_read_page, 632 .write_page = rtl821x_write_page, 633 }, { 634 PHY_ID_MATCH_EXACT(0x001cc916), 635 .name = "RTL8211F Gigabit Ethernet", 636 .config_init = &rtl8211f_config_init, 637 .ack_interrupt = &rtl8211f_ack_interrupt, 638 .config_intr = &rtl8211f_config_intr, 639 .suspend = genphy_suspend, 640 .resume = rtl821x_resume, 641 .read_page = rtl821x_read_page, 642 .write_page = rtl821x_write_page, 643 }, { 644 .name = "Generic FE-GE Realtek PHY", 645 .match_phy_device = rtlgen_match_phy_device, 646 .read_status = rtlgen_read_status, 647 .suspend = genphy_suspend, 648 .resume = rtlgen_resume, 649 .read_page = rtl821x_read_page, 650 .write_page = rtl821x_write_page, 651 .read_mmd = rtlgen_read_mmd, 652 .write_mmd = rtlgen_write_mmd, 653 }, { 654 .name = "RTL8226 2.5Gbps PHY", 655 .match_phy_device = rtl8226_match_phy_device, 656 .get_features = rtl822x_get_features, 657 .config_aneg = rtl822x_config_aneg, 658 .read_status = rtl822x_read_status, 659 .suspend = genphy_suspend, 660 .resume = rtlgen_resume, 661 .read_page = rtl821x_read_page, 662 .write_page = rtl821x_write_page, 663 .read_mmd = rtl822x_read_mmd, 664 .write_mmd = rtl822x_write_mmd, 665 }, { 666 PHY_ID_MATCH_EXACT(0x001cc840), 667 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 668 .get_features = rtl822x_get_features, 669 .config_aneg = rtl822x_config_aneg, 670 .read_status = rtl822x_read_status, 671 .suspend = genphy_suspend, 672 .resume = rtlgen_resume, 673 .read_page = rtl821x_read_page, 674 .write_page = rtl821x_write_page, 675 .read_mmd = rtl822x_read_mmd, 676 .write_mmd = rtl822x_write_mmd, 677 }, { 678 PHY_ID_MATCH_EXACT(0x001cc961), 679 .name = "RTL8366RB Gigabit Ethernet", 680 .config_init = &rtl8366rb_config_init, 681 /* These interrupts are handled by the irq controller 682 * embedded inside the RTL8366RB, they get unmasked when the 683 * irq is requested and ACKed by reading the status register, 684 * which is done by the irqchip code. 685 */ 686 .ack_interrupt = genphy_no_ack_interrupt, 687 .config_intr = genphy_no_config_intr, 688 .suspend = genphy_suspend, 689 .resume = genphy_resume, 690 }, 691}; 692 693module_phy_driver(realtek_drvs); 694 695static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 696 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 697 { } 698}; 699 700MODULE_DEVICE_TABLE(mdio, realtek_tbl); 701