1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> 4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de> 5 */ 6 7#include <linux/mdio.h> 8#include <linux/module.h> 9#include <linux/phy.h> 10#include <linux/of.h> 11 12#define XWAY_MDIO_IMASK 0x19 /* interrupt mask */ 13#define XWAY_MDIO_ISTAT 0x1A /* interrupt status */ 14#define XWAY_MDIO_LED 0x1B /* led control */ 15 16/* bit 15:12 are reserved */ 17#define XWAY_MDIO_LED_LED3_EN BIT(11) /* Enable the integrated function of LED3 */ 18#define XWAY_MDIO_LED_LED2_EN BIT(10) /* Enable the integrated function of LED2 */ 19#define XWAY_MDIO_LED_LED1_EN BIT(9) /* Enable the integrated function of LED1 */ 20#define XWAY_MDIO_LED_LED0_EN BIT(8) /* Enable the integrated function of LED0 */ 21/* bit 7:4 are reserved */ 22#define XWAY_MDIO_LED_LED3_DA BIT(3) /* Direct Access to LED3 */ 23#define XWAY_MDIO_LED_LED2_DA BIT(2) /* Direct Access to LED2 */ 24#define XWAY_MDIO_LED_LED1_DA BIT(1) /* Direct Access to LED1 */ 25#define XWAY_MDIO_LED_LED0_DA BIT(0) /* Direct Access to LED0 */ 26 27#define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */ 28#define XWAY_MDIO_INIT_MSRE BIT(14) 29#define XWAY_MDIO_INIT_NPRX BIT(13) 30#define XWAY_MDIO_INIT_NPTX BIT(12) 31#define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */ 32#define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */ 33#define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */ 34#define XWAY_MDIO_INIT_MPIPC BIT(4) 35#define XWAY_MDIO_INIT_MDIXC BIT(3) 36#define XWAY_MDIO_INIT_DXMC BIT(2) /* Duplex mode change */ 37#define XWAY_MDIO_INIT_LSPC BIT(1) /* Link speed change */ 38#define XWAY_MDIO_INIT_LSTC BIT(0) /* Link state change */ 39#define XWAY_MDIO_INIT_MASK (XWAY_MDIO_INIT_LSTC | \ 40 XWAY_MDIO_INIT_ADSC) 41 42#define ADVERTISED_MPD BIT(10) /* Multi-port device */ 43 44/* LED Configuration */ 45#define XWAY_MMD_LEDCH 0x01E0 46/* Inverse of SCAN Function */ 47#define XWAY_MMD_LEDCH_NACS_NONE 0x0000 48#define XWAY_MMD_LEDCH_NACS_LINK 0x0001 49#define XWAY_MMD_LEDCH_NACS_PDOWN 0x0002 50#define XWAY_MMD_LEDCH_NACS_EEE 0x0003 51#define XWAY_MMD_LEDCH_NACS_ANEG 0x0004 52#define XWAY_MMD_LEDCH_NACS_ABIST 0x0005 53#define XWAY_MMD_LEDCH_NACS_CDIAG 0x0006 54#define XWAY_MMD_LEDCH_NACS_TEST 0x0007 55/* Slow Blink Frequency */ 56#define XWAY_MMD_LEDCH_SBF_F02HZ 0x0000 57#define XWAY_MMD_LEDCH_SBF_F04HZ 0x0010 58#define XWAY_MMD_LEDCH_SBF_F08HZ 0x0020 59#define XWAY_MMD_LEDCH_SBF_F16HZ 0x0030 60/* Fast Blink Frequency */ 61#define XWAY_MMD_LEDCH_FBF_F02HZ 0x0000 62#define XWAY_MMD_LEDCH_FBF_F04HZ 0x0040 63#define XWAY_MMD_LEDCH_FBF_F08HZ 0x0080 64#define XWAY_MMD_LEDCH_FBF_F16HZ 0x00C0 65/* LED Configuration */ 66#define XWAY_MMD_LEDCL 0x01E1 67/* Complex Blinking Configuration */ 68#define XWAY_MMD_LEDCH_CBLINK_NONE 0x0000 69#define XWAY_MMD_LEDCH_CBLINK_LINK 0x0001 70#define XWAY_MMD_LEDCH_CBLINK_PDOWN 0x0002 71#define XWAY_MMD_LEDCH_CBLINK_EEE 0x0003 72#define XWAY_MMD_LEDCH_CBLINK_ANEG 0x0004 73#define XWAY_MMD_LEDCH_CBLINK_ABIST 0x0005 74#define XWAY_MMD_LEDCH_CBLINK_CDIAG 0x0006 75#define XWAY_MMD_LEDCH_CBLINK_TEST 0x0007 76/* Complex SCAN Configuration */ 77#define XWAY_MMD_LEDCH_SCAN_NONE 0x0000 78#define XWAY_MMD_LEDCH_SCAN_LINK 0x0010 79#define XWAY_MMD_LEDCH_SCAN_PDOWN 0x0020 80#define XWAY_MMD_LEDCH_SCAN_EEE 0x0030 81#define XWAY_MMD_LEDCH_SCAN_ANEG 0x0040 82#define XWAY_MMD_LEDCH_SCAN_ABIST 0x0050 83#define XWAY_MMD_LEDCH_SCAN_CDIAG 0x0060 84#define XWAY_MMD_LEDCH_SCAN_TEST 0x0070 85/* Configuration for LED Pin x */ 86#define XWAY_MMD_LED0H 0x01E2 87/* Fast Blinking Configuration */ 88#define XWAY_MMD_LEDxH_BLINKF_MASK 0x000F 89#define XWAY_MMD_LEDxH_BLINKF_NONE 0x0000 90#define XWAY_MMD_LEDxH_BLINKF_LINK10 0x0001 91#define XWAY_MMD_LEDxH_BLINKF_LINK100 0x0002 92#define XWAY_MMD_LEDxH_BLINKF_LINK10X 0x0003 93#define XWAY_MMD_LEDxH_BLINKF_LINK1000 0x0004 94#define XWAY_MMD_LEDxH_BLINKF_LINK10_0 0x0005 95#define XWAY_MMD_LEDxH_BLINKF_LINK100X 0x0006 96#define XWAY_MMD_LEDxH_BLINKF_LINK10XX 0x0007 97#define XWAY_MMD_LEDxH_BLINKF_PDOWN 0x0008 98#define XWAY_MMD_LEDxH_BLINKF_EEE 0x0009 99#define XWAY_MMD_LEDxH_BLINKF_ANEG 0x000A 100#define XWAY_MMD_LEDxH_BLINKF_ABIST 0x000B 101#define XWAY_MMD_LEDxH_BLINKF_CDIAG 0x000C 102/* Constant On Configuration */ 103#define XWAY_MMD_LEDxH_CON_MASK 0x00F0 104#define XWAY_MMD_LEDxH_CON_NONE 0x0000 105#define XWAY_MMD_LEDxH_CON_LINK10 0x0010 106#define XWAY_MMD_LEDxH_CON_LINK100 0x0020 107#define XWAY_MMD_LEDxH_CON_LINK10X 0x0030 108#define XWAY_MMD_LEDxH_CON_LINK1000 0x0040 109#define XWAY_MMD_LEDxH_CON_LINK10_0 0x0050 110#define XWAY_MMD_LEDxH_CON_LINK100X 0x0060 111#define XWAY_MMD_LEDxH_CON_LINK10XX 0x0070 112#define XWAY_MMD_LEDxH_CON_PDOWN 0x0080 113#define XWAY_MMD_LEDxH_CON_EEE 0x0090 114#define XWAY_MMD_LEDxH_CON_ANEG 0x00A0 115#define XWAY_MMD_LEDxH_CON_ABIST 0x00B0 116#define XWAY_MMD_LEDxH_CON_CDIAG 0x00C0 117#define XWAY_MMD_LEDxH_CON_COPPER 0x00D0 118#define XWAY_MMD_LEDxH_CON_FIBER 0x00E0 119/* Configuration for LED Pin x */ 120#define XWAY_MMD_LED0L 0x01E3 121/* Pulsing Configuration */ 122#define XWAY_MMD_LEDxL_PULSE_MASK 0x000F 123#define XWAY_MMD_LEDxL_PULSE_NONE 0x0000 124#define XWAY_MMD_LEDxL_PULSE_TXACT 0x0001 125#define XWAY_MMD_LEDxL_PULSE_RXACT 0x0002 126#define XWAY_MMD_LEDxL_PULSE_COL 0x0004 127/* Slow Blinking Configuration */ 128#define XWAY_MMD_LEDxL_BLINKS_MASK 0x00F0 129#define XWAY_MMD_LEDxL_BLINKS_NONE 0x0000 130#define XWAY_MMD_LEDxL_BLINKS_LINK10 0x0010 131#define XWAY_MMD_LEDxL_BLINKS_LINK100 0x0020 132#define XWAY_MMD_LEDxL_BLINKS_LINK10X 0x0030 133#define XWAY_MMD_LEDxL_BLINKS_LINK1000 0x0040 134#define XWAY_MMD_LEDxL_BLINKS_LINK10_0 0x0050 135#define XWAY_MMD_LEDxL_BLINKS_LINK100X 0x0060 136#define XWAY_MMD_LEDxL_BLINKS_LINK10XX 0x0070 137#define XWAY_MMD_LEDxL_BLINKS_PDOWN 0x0080 138#define XWAY_MMD_LEDxL_BLINKS_EEE 0x0090 139#define XWAY_MMD_LEDxL_BLINKS_ANEG 0x00A0 140#define XWAY_MMD_LEDxL_BLINKS_ABIST 0x00B0 141#define XWAY_MMD_LEDxL_BLINKS_CDIAG 0x00C0 142#define XWAY_MMD_LED1H 0x01E4 143#define XWAY_MMD_LED1L 0x01E5 144#define XWAY_MMD_LED2H 0x01E6 145#define XWAY_MMD_LED2L 0x01E7 146#define XWAY_MMD_LED3H 0x01E8 147#define XWAY_MMD_LED3L 0x01E9 148 149#define PHY_ID_PHY11G_1_3 0x030260D1 150#define PHY_ID_PHY22F_1_3 0x030260E1 151#define PHY_ID_PHY11G_1_4 0xD565A400 152#define PHY_ID_PHY22F_1_4 0xD565A410 153#define PHY_ID_PHY11G_1_5 0xD565A401 154#define PHY_ID_PHY22F_1_5 0xD565A411 155#define PHY_ID_PHY11G_VR9_1_1 0xD565A408 156#define PHY_ID_PHY22F_VR9_1_1 0xD565A418 157#define PHY_ID_PHY11G_VR9_1_2 0xD565A409 158#define PHY_ID_PHY22F_VR9_1_2 0xD565A419 159 160static int xway_gphy_config_init(struct phy_device *phydev) 161{ 162 int err; 163 u32 ledxh; 164 u32 ledxl; 165 166 /* Mask all interrupts */ 167 err = phy_write(phydev, XWAY_MDIO_IMASK, 0); 168 if (err) 169 return err; 170 171 /* Clear all pending interrupts */ 172 phy_read(phydev, XWAY_MDIO_ISTAT); 173 174 /* Ensure that integrated led function is enabled for all leds */ 175 err = phy_write(phydev, XWAY_MDIO_LED, 176 XWAY_MDIO_LED_LED0_EN | 177 XWAY_MDIO_LED_LED1_EN | 178 XWAY_MDIO_LED_LED2_EN | 179 XWAY_MDIO_LED_LED3_EN); 180 if (err) 181 return err; 182 183 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, 184 XWAY_MMD_LEDCH_NACS_NONE | 185 XWAY_MMD_LEDCH_SBF_F02HZ | 186 XWAY_MMD_LEDCH_FBF_F16HZ); 187 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, 188 XWAY_MMD_LEDCH_CBLINK_NONE | 189 XWAY_MMD_LEDCH_SCAN_NONE); 190 191 /** 192 * In most cases only one LED is connected to this phy, so 193 * configure them all to constant on and pulse mode. LED3 is 194 * only available in some packages, leave it in its reset 195 * configuration. 196 */ 197 ledxh = XWAY_MMD_LEDxH_BLINKF_NONE | XWAY_MMD_LEDxH_CON_LINK10XX; 198 ledxl = XWAY_MMD_LEDxL_PULSE_TXACT | XWAY_MMD_LEDxL_PULSE_RXACT | 199 XWAY_MMD_LEDxL_BLINKS_NONE; 200 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); 201 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); 202 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); 203 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); 204 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); 205 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); 206 207 return 0; 208} 209 210static int xway_gphy14_config_aneg(struct phy_device *phydev) 211{ 212 int reg, err; 213 214 /* Advertise as multi-port device, see IEEE802.3-2002 40.5.1.1 */ 215 /* This is a workaround for an errata in rev < 1.5 devices */ 216 reg = phy_read(phydev, MII_CTRL1000); 217 reg |= ADVERTISED_MPD; 218 err = phy_write(phydev, MII_CTRL1000, reg); 219 if (err) 220 return err; 221 222 return genphy_config_aneg(phydev); 223} 224 225static int xway_gphy_ack_interrupt(struct phy_device *phydev) 226{ 227 int reg; 228 229 reg = phy_read(phydev, XWAY_MDIO_ISTAT); 230 return (reg < 0) ? reg : 0; 231} 232 233static int xway_gphy_did_interrupt(struct phy_device *phydev) 234{ 235 int reg; 236 237 reg = phy_read(phydev, XWAY_MDIO_ISTAT); 238 return reg & XWAY_MDIO_INIT_MASK; 239} 240 241static int xway_gphy_config_intr(struct phy_device *phydev) 242{ 243 u16 mask = 0; 244 245 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 246 mask = XWAY_MDIO_INIT_MASK; 247 248 return phy_write(phydev, XWAY_MDIO_IMASK, mask); 249} 250 251static struct phy_driver xway_gphy[] = { 252 { 253 .phy_id = PHY_ID_PHY11G_1_3, 254 .phy_id_mask = 0xffffffff, 255 .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3", 256 /* PHY_GBIT_FEATURES */ 257 .config_init = xway_gphy_config_init, 258 .config_aneg = xway_gphy14_config_aneg, 259 .ack_interrupt = xway_gphy_ack_interrupt, 260 .did_interrupt = xway_gphy_did_interrupt, 261 .config_intr = xway_gphy_config_intr, 262 .suspend = genphy_suspend, 263 .resume = genphy_resume, 264 }, { 265 .phy_id = PHY_ID_PHY22F_1_3, 266 .phy_id_mask = 0xffffffff, 267 .name = "Intel XWAY PHY22F (PEF 7061) v1.3", 268 /* PHY_BASIC_FEATURES */ 269 .config_init = xway_gphy_config_init, 270 .config_aneg = xway_gphy14_config_aneg, 271 .ack_interrupt = xway_gphy_ack_interrupt, 272 .did_interrupt = xway_gphy_did_interrupt, 273 .config_intr = xway_gphy_config_intr, 274 .suspend = genphy_suspend, 275 .resume = genphy_resume, 276 }, { 277 .phy_id = PHY_ID_PHY11G_1_4, 278 .phy_id_mask = 0xffffffff, 279 .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4", 280 /* PHY_GBIT_FEATURES */ 281 .config_init = xway_gphy_config_init, 282 .config_aneg = xway_gphy14_config_aneg, 283 .ack_interrupt = xway_gphy_ack_interrupt, 284 .did_interrupt = xway_gphy_did_interrupt, 285 .config_intr = xway_gphy_config_intr, 286 .suspend = genphy_suspend, 287 .resume = genphy_resume, 288 }, { 289 .phy_id = PHY_ID_PHY22F_1_4, 290 .phy_id_mask = 0xffffffff, 291 .name = "Intel XWAY PHY22F (PEF 7061) v1.4", 292 /* PHY_BASIC_FEATURES */ 293 .config_init = xway_gphy_config_init, 294 .config_aneg = xway_gphy14_config_aneg, 295 .ack_interrupt = xway_gphy_ack_interrupt, 296 .did_interrupt = xway_gphy_did_interrupt, 297 .config_intr = xway_gphy_config_intr, 298 .suspend = genphy_suspend, 299 .resume = genphy_resume, 300 }, { 301 .phy_id = PHY_ID_PHY11G_1_5, 302 .phy_id_mask = 0xffffffff, 303 .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6", 304 /* PHY_GBIT_FEATURES */ 305 .config_init = xway_gphy_config_init, 306 .ack_interrupt = xway_gphy_ack_interrupt, 307 .did_interrupt = xway_gphy_did_interrupt, 308 .config_intr = xway_gphy_config_intr, 309 .suspend = genphy_suspend, 310 .resume = genphy_resume, 311 }, { 312 .phy_id = PHY_ID_PHY22F_1_5, 313 .phy_id_mask = 0xffffffff, 314 .name = "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6", 315 /* PHY_BASIC_FEATURES */ 316 .config_init = xway_gphy_config_init, 317 .ack_interrupt = xway_gphy_ack_interrupt, 318 .did_interrupt = xway_gphy_did_interrupt, 319 .config_intr = xway_gphy_config_intr, 320 .suspend = genphy_suspend, 321 .resume = genphy_resume, 322 }, { 323 .phy_id = PHY_ID_PHY11G_VR9_1_1, 324 .phy_id_mask = 0xffffffff, 325 .name = "Intel XWAY PHY11G (xRX v1.1 integrated)", 326 /* PHY_GBIT_FEATURES */ 327 .config_init = xway_gphy_config_init, 328 .ack_interrupt = xway_gphy_ack_interrupt, 329 .did_interrupt = xway_gphy_did_interrupt, 330 .config_intr = xway_gphy_config_intr, 331 .suspend = genphy_suspend, 332 .resume = genphy_resume, 333 }, { 334 .phy_id = PHY_ID_PHY22F_VR9_1_1, 335 .phy_id_mask = 0xffffffff, 336 .name = "Intel XWAY PHY22F (xRX v1.1 integrated)", 337 /* PHY_BASIC_FEATURES */ 338 .config_init = xway_gphy_config_init, 339 .ack_interrupt = xway_gphy_ack_interrupt, 340 .did_interrupt = xway_gphy_did_interrupt, 341 .config_intr = xway_gphy_config_intr, 342 .suspend = genphy_suspend, 343 .resume = genphy_resume, 344 }, { 345 .phy_id = PHY_ID_PHY11G_VR9_1_2, 346 .phy_id_mask = 0xffffffff, 347 .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", 348 /* PHY_GBIT_FEATURES */ 349 .config_init = xway_gphy_config_init, 350 .ack_interrupt = xway_gphy_ack_interrupt, 351 .did_interrupt = xway_gphy_did_interrupt, 352 .config_intr = xway_gphy_config_intr, 353 .suspend = genphy_suspend, 354 .resume = genphy_resume, 355 }, { 356 .phy_id = PHY_ID_PHY22F_VR9_1_2, 357 .phy_id_mask = 0xffffffff, 358 .name = "Intel XWAY PHY22F (xRX v1.2 integrated)", 359 /* PHY_BASIC_FEATURES */ 360 .config_init = xway_gphy_config_init, 361 .ack_interrupt = xway_gphy_ack_interrupt, 362 .did_interrupt = xway_gphy_did_interrupt, 363 .config_intr = xway_gphy_config_intr, 364 .suspend = genphy_suspend, 365 .resume = genphy_resume, 366 }, 367}; 368module_phy_driver(xway_gphy); 369 370static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = { 371 { PHY_ID_PHY11G_1_3, 0xffffffff }, 372 { PHY_ID_PHY22F_1_3, 0xffffffff }, 373 { PHY_ID_PHY11G_1_4, 0xffffffff }, 374 { PHY_ID_PHY22F_1_4, 0xffffffff }, 375 { PHY_ID_PHY11G_1_5, 0xffffffff }, 376 { PHY_ID_PHY22F_1_5, 0xffffffff }, 377 { PHY_ID_PHY11G_VR9_1_1, 0xffffffff }, 378 { PHY_ID_PHY22F_VR9_1_1, 0xffffffff }, 379 { PHY_ID_PHY11G_VR9_1_2, 0xffffffff }, 380 { PHY_ID_PHY22F_VR9_1_2, 0xffffffff }, 381 { } 382}; 383MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl); 384 385MODULE_DESCRIPTION("Intel XWAY PHY driver"); 386MODULE_LICENSE("GPL"); 387