1// SPDX-License-Identifier: GPL-2.0 2/* Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 */ 6 7#include <linux/ethtool.h> 8#include <linux/kernel.h> 9#include <linux/mii.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/phy.h> 13#include <linux/delay.h> 14#include <linux/netdevice.h> 15#include <linux/etherdevice.h> 16#include <linux/bitfield.h> 17 18#include <dt-bindings/net/ti-dp83867.h> 19 20#define DP83867_PHY_ID 0x2000a231 21#define DP83867_DEVADDR 0x1f 22 23#define MII_DP83867_PHYCTRL 0x10 24#define MII_DP83867_PHYSTS 0x11 25#define MII_DP83867_MICR 0x12 26#define MII_DP83867_ISR 0x13 27#define DP83867_CFG2 0x14 28#define DP83867_CFG3 0x1e 29#define DP83867_CTRL 0x1f 30 31/* Extended Registers */ 32#define DP83867_FLD_THR_CFG 0x002e 33#define DP83867_CFG4 0x0031 34#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 35#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 36#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 37#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 38#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 39 40#define DP83867_RGMIICTL 0x0032 41#define DP83867_STRAP_STS1 0x006E 42#define DP83867_STRAP_STS2 0x006f 43#define DP83867_RGMIIDCTL 0x0086 44#define DP83867_DSP_FFE_CFG 0x012c 45#define DP83867_RXFCFG 0x0134 46#define DP83867_RXFPMD1 0x0136 47#define DP83867_RXFPMD2 0x0137 48#define DP83867_RXFPMD3 0x0138 49#define DP83867_RXFSOP1 0x0139 50#define DP83867_RXFSOP2 0x013A 51#define DP83867_RXFSOP3 0x013B 52#define DP83867_IO_MUX_CFG 0x0170 53#define DP83867_SGMIICTL 0x00D3 54#define DP83867_10M_SGMII_CFG 0x016F 55#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 56 57#define DP83867_SW_RESET BIT(15) 58#define DP83867_SW_RESTART BIT(14) 59 60/* MICR Interrupt bits */ 61#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 62#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 63#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 64#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 65#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 66#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 67#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 68#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 69#define MII_DP83867_MICR_WOL_INT_EN BIT(3) 70#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 71#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 72#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 73 74/* RGMIICTL bits */ 75#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 76#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 77 78/* SGMIICTL bits */ 79#define DP83867_SGMII_TYPE BIT(14) 80 81/* RXFCFG bits*/ 82#define DP83867_WOL_MAGIC_EN BIT(0) 83#define DP83867_WOL_BCAST_EN BIT(2) 84#define DP83867_WOL_UCAST_EN BIT(4) 85#define DP83867_WOL_SEC_EN BIT(5) 86#define DP83867_WOL_ENH_MAC BIT(7) 87 88/* STRAP_STS1 bits */ 89#define DP83867_STRAP_STS1_RESERVED BIT(11) 90 91/* STRAP_STS2 bits */ 92#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 93#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 94#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 95#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 96#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 97#define DP83867_STRAP_STS2_STRAP_FLD BIT(10) 98 99/* PHY CTRL bits */ 100#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 101#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 102#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 103#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 104#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 105#define DP83867_PHYCR_RESERVED_MASK BIT(11) 106#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 107 108/* RGMIIDCTL bits */ 109#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 110#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 111#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 112#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 113#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 114#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 115 116/* IO_MUX_CFG bits */ 117#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 118#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 119#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 120#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 121#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 122#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 123 124/* PHY STS bits */ 125#define DP83867_PHYSTS_1000 BIT(15) 126#define DP83867_PHYSTS_100 BIT(14) 127#define DP83867_PHYSTS_DUPLEX BIT(13) 128#define DP83867_PHYSTS_LINK BIT(10) 129 130/* CFG2 bits */ 131#define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) 132#define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 133#define DP83867_DOWNSHIFT_1_COUNT_VAL 0 134#define DP83867_DOWNSHIFT_2_COUNT_VAL 1 135#define DP83867_DOWNSHIFT_4_COUNT_VAL 2 136#define DP83867_DOWNSHIFT_8_COUNT_VAL 3 137#define DP83867_DOWNSHIFT_1_COUNT 1 138#define DP83867_DOWNSHIFT_2_COUNT 2 139#define DP83867_DOWNSHIFT_4_COUNT 4 140#define DP83867_DOWNSHIFT_8_COUNT 8 141#define DP83867_SGMII_AUTONEG_EN BIT(7) 142 143/* CFG3 bits */ 144#define DP83867_CFG3_INT_OE BIT(7) 145#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 146 147/* CFG4 bits */ 148#define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 149 150/* FLD_THR_CFG */ 151#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7 152 153enum { 154 DP83867_PORT_MIRROING_KEEP, 155 DP83867_PORT_MIRROING_EN, 156 DP83867_PORT_MIRROING_DIS, 157}; 158 159struct dp83867_private { 160 u32 rx_id_delay; 161 u32 tx_id_delay; 162 u32 tx_fifo_depth; 163 u32 rx_fifo_depth; 164 int io_impedance; 165 int port_mirroring; 166 bool rxctrl_strap_quirk; 167 bool set_clk_output; 168 u32 clk_output_sel; 169 bool sgmii_ref_clk_en; 170}; 171 172static int dp83867_ack_interrupt(struct phy_device *phydev) 173{ 174 int err = phy_read(phydev, MII_DP83867_ISR); 175 176 if (err < 0) 177 return err; 178 179 return 0; 180} 181 182static int dp83867_set_wol(struct phy_device *phydev, 183 struct ethtool_wolinfo *wol) 184{ 185 struct net_device *ndev = phydev->attached_dev; 186 u16 val_rxcfg, val_micr; 187 u8 *mac; 188 189 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 190 val_micr = phy_read(phydev, MII_DP83867_MICR); 191 192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 193 WAKE_BCAST)) { 194 val_rxcfg |= DP83867_WOL_ENH_MAC; 195 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 196 197 if (wol->wolopts & WAKE_MAGIC) { 198 mac = (u8 *)ndev->dev_addr; 199 200 if (!is_valid_ether_addr(mac)) 201 return -EINVAL; 202 203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 204 (mac[1] << 8 | mac[0])); 205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 206 (mac[3] << 8 | mac[2])); 207 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 208 (mac[5] << 8 | mac[4])); 209 210 val_rxcfg |= DP83867_WOL_MAGIC_EN; 211 } else { 212 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 213 } 214 215 if (wol->wolopts & WAKE_MAGICSECURE) { 216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 217 (wol->sopass[1] << 8) | wol->sopass[0]); 218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, 219 (wol->sopass[3] << 8) | wol->sopass[2]); 220 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, 221 (wol->sopass[5] << 8) | wol->sopass[4]); 222 223 val_rxcfg |= DP83867_WOL_SEC_EN; 224 } else { 225 val_rxcfg &= ~DP83867_WOL_SEC_EN; 226 } 227 228 if (wol->wolopts & WAKE_UCAST) 229 val_rxcfg |= DP83867_WOL_UCAST_EN; 230 else 231 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 232 233 if (wol->wolopts & WAKE_BCAST) 234 val_rxcfg |= DP83867_WOL_BCAST_EN; 235 else 236 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 237 } else { 238 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 239 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 240 } 241 242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 243 phy_write(phydev, MII_DP83867_MICR, val_micr); 244 245 return 0; 246} 247 248static void dp83867_get_wol(struct phy_device *phydev, 249 struct ethtool_wolinfo *wol) 250{ 251 u16 value, sopass_val; 252 253 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 254 WAKE_MAGICSECURE); 255 wol->wolopts = 0; 256 257 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 258 259 if (value & DP83867_WOL_UCAST_EN) 260 wol->wolopts |= WAKE_UCAST; 261 262 if (value & DP83867_WOL_BCAST_EN) 263 wol->wolopts |= WAKE_BCAST; 264 265 if (value & DP83867_WOL_MAGIC_EN) 266 wol->wolopts |= WAKE_MAGIC; 267 268 if (value & DP83867_WOL_SEC_EN) { 269 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 270 DP83867_RXFSOP1); 271 wol->sopass[0] = (sopass_val & 0xff); 272 wol->sopass[1] = (sopass_val >> 8); 273 274 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 275 DP83867_RXFSOP2); 276 wol->sopass[2] = (sopass_val & 0xff); 277 wol->sopass[3] = (sopass_val >> 8); 278 279 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 280 DP83867_RXFSOP3); 281 wol->sopass[4] = (sopass_val & 0xff); 282 wol->sopass[5] = (sopass_val >> 8); 283 284 wol->wolopts |= WAKE_MAGICSECURE; 285 } 286 287 if (!(value & DP83867_WOL_ENH_MAC)) 288 wol->wolopts = 0; 289} 290 291static int dp83867_config_intr(struct phy_device *phydev) 292{ 293 int micr_status; 294 295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 296 micr_status = phy_read(phydev, MII_DP83867_MICR); 297 if (micr_status < 0) 298 return micr_status; 299 300 micr_status |= 301 (MII_DP83867_MICR_AN_ERR_INT_EN | 302 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 303 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 304 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 305 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 306 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 307 308 return phy_write(phydev, MII_DP83867_MICR, micr_status); 309 } 310 311 micr_status = 0x0; 312 return phy_write(phydev, MII_DP83867_MICR, micr_status); 313} 314 315static int dp83867_read_status(struct phy_device *phydev) 316{ 317 int status = phy_read(phydev, MII_DP83867_PHYSTS); 318 int ret; 319 320 ret = genphy_read_status(phydev); 321 if (ret) 322 return ret; 323 324 if (status < 0) 325 return status; 326 327 if (status & DP83867_PHYSTS_DUPLEX) 328 phydev->duplex = DUPLEX_FULL; 329 else 330 phydev->duplex = DUPLEX_HALF; 331 332 if (status & DP83867_PHYSTS_1000) 333 phydev->speed = SPEED_1000; 334 else if (status & DP83867_PHYSTS_100) 335 phydev->speed = SPEED_100; 336 else 337 phydev->speed = SPEED_10; 338 339 return 0; 340} 341 342static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) 343{ 344 int val, cnt, enable, count; 345 346 val = phy_read(phydev, DP83867_CFG2); 347 if (val < 0) 348 return val; 349 350 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val); 351 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val); 352 353 switch (cnt) { 354 case DP83867_DOWNSHIFT_1_COUNT_VAL: 355 count = DP83867_DOWNSHIFT_1_COUNT; 356 break; 357 case DP83867_DOWNSHIFT_2_COUNT_VAL: 358 count = DP83867_DOWNSHIFT_2_COUNT; 359 break; 360 case DP83867_DOWNSHIFT_4_COUNT_VAL: 361 count = DP83867_DOWNSHIFT_4_COUNT; 362 break; 363 case DP83867_DOWNSHIFT_8_COUNT_VAL: 364 count = DP83867_DOWNSHIFT_8_COUNT; 365 break; 366 default: 367 return -EINVAL; 368 } 369 370 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 371 372 return 0; 373} 374 375static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) 376{ 377 int val, count; 378 379 if (cnt > DP83867_DOWNSHIFT_8_COUNT) 380 return -E2BIG; 381 382 if (!cnt) 383 return phy_clear_bits(phydev, DP83867_CFG2, 384 DP83867_DOWNSHIFT_EN); 385 386 switch (cnt) { 387 case DP83867_DOWNSHIFT_1_COUNT: 388 count = DP83867_DOWNSHIFT_1_COUNT_VAL; 389 break; 390 case DP83867_DOWNSHIFT_2_COUNT: 391 count = DP83867_DOWNSHIFT_2_COUNT_VAL; 392 break; 393 case DP83867_DOWNSHIFT_4_COUNT: 394 count = DP83867_DOWNSHIFT_4_COUNT_VAL; 395 break; 396 case DP83867_DOWNSHIFT_8_COUNT: 397 count = DP83867_DOWNSHIFT_8_COUNT_VAL; 398 break; 399 default: 400 phydev_err(phydev, 401 "Downshift count must be 1, 2, 4 or 8\n"); 402 return -EINVAL; 403 } 404 405 val = DP83867_DOWNSHIFT_EN; 406 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count); 407 408 return phy_modify(phydev, DP83867_CFG2, 409 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK, 410 val); 411} 412 413static int dp83867_get_tunable(struct phy_device *phydev, 414 struct ethtool_tunable *tuna, void *data) 415{ 416 switch (tuna->id) { 417 case ETHTOOL_PHY_DOWNSHIFT: 418 return dp83867_get_downshift(phydev, data); 419 default: 420 return -EOPNOTSUPP; 421 } 422} 423 424static int dp83867_set_tunable(struct phy_device *phydev, 425 struct ethtool_tunable *tuna, const void *data) 426{ 427 switch (tuna->id) { 428 case ETHTOOL_PHY_DOWNSHIFT: 429 return dp83867_set_downshift(phydev, *(const u8 *)data); 430 default: 431 return -EOPNOTSUPP; 432 } 433} 434 435static int dp83867_config_port_mirroring(struct phy_device *phydev) 436{ 437 struct dp83867_private *dp83867 = 438 (struct dp83867_private *)phydev->priv; 439 440 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 441 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 442 DP83867_CFG4_PORT_MIRROR_EN); 443 else 444 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 445 DP83867_CFG4_PORT_MIRROR_EN); 446 return 0; 447} 448 449static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 450{ 451 struct dp83867_private *dp83867 = phydev->priv; 452 453 /* Existing behavior was to use default pin strapping delay in rgmii 454 * mode, but rgmii should have meant no delay. Warn existing users. 455 */ 456 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 457 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 458 DP83867_STRAP_STS2); 459 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 460 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 461 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 462 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 463 464 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 465 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 466 phydev_warn(phydev, 467 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 468 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 469 txskew, rxskew); 470 } 471 472 /* RX delay *must* be specified if internal delay of RX is used. */ 473 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 474 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 475 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 476 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 477 return -EINVAL; 478 } 479 480 /* TX delay *must* be specified if internal delay of TX is used. */ 481 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 482 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 483 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 484 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 485 return -EINVAL; 486 } 487 488 return 0; 489} 490 491#if IS_ENABLED(CONFIG_OF_MDIO) 492static int dp83867_of_init(struct phy_device *phydev) 493{ 494 struct dp83867_private *dp83867 = phydev->priv; 495 struct device *dev = &phydev->mdio.dev; 496 struct device_node *of_node = dev->of_node; 497 int ret; 498 499 if (!of_node) 500 return -ENODEV; 501 502 /* Optional configuration */ 503 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 504 &dp83867->clk_output_sel); 505 /* If not set, keep default */ 506 if (!ret) { 507 dp83867->set_clk_output = true; 508 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 509 * DP83867_CLK_O_SEL_OFF. 510 */ 511 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 512 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 513 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 514 dp83867->clk_output_sel); 515 return -EINVAL; 516 } 517 } 518 519 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 520 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 521 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 522 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 523 else 524 dp83867->io_impedance = -1; /* leave at default */ 525 526 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 527 "ti,dp83867-rxctrl-strap-quirk"); 528 529 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 530 "ti,sgmii-ref-clock-output-enable"); 531 532 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 533 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 534 &dp83867->rx_id_delay); 535 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 536 phydev_err(phydev, 537 "ti,rx-internal-delay value of %u out of range\n", 538 dp83867->rx_id_delay); 539 return -EINVAL; 540 } 541 542 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 543 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 544 &dp83867->tx_id_delay); 545 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 546 phydev_err(phydev, 547 "ti,tx-internal-delay value of %u out of range\n", 548 dp83867->tx_id_delay); 549 return -EINVAL; 550 } 551 552 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 553 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 554 555 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 556 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 557 558 ret = of_property_read_u32(of_node, "ti,fifo-depth", 559 &dp83867->tx_fifo_depth); 560 if (ret) { 561 ret = of_property_read_u32(of_node, "tx-fifo-depth", 562 &dp83867->tx_fifo_depth); 563 if (ret) 564 dp83867->tx_fifo_depth = 565 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 566 } 567 568 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 569 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 570 dp83867->tx_fifo_depth); 571 return -EINVAL; 572 } 573 574 ret = of_property_read_u32(of_node, "rx-fifo-depth", 575 &dp83867->rx_fifo_depth); 576 if (ret) 577 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 578 579 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 580 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 581 dp83867->rx_fifo_depth); 582 return -EINVAL; 583 } 584 585 return 0; 586} 587#else 588static int dp83867_of_init(struct phy_device *phydev) 589{ 590 return 0; 591} 592#endif /* CONFIG_OF_MDIO */ 593 594static int dp83867_probe(struct phy_device *phydev) 595{ 596 struct dp83867_private *dp83867; 597 598 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 599 GFP_KERNEL); 600 if (!dp83867) 601 return -ENOMEM; 602 603 phydev->priv = dp83867; 604 605 return dp83867_of_init(phydev); 606} 607 608static int dp83867_config_init(struct phy_device *phydev) 609{ 610 struct dp83867_private *dp83867 = phydev->priv; 611 int ret, val, bs; 612 u16 delay; 613 614 /* Force speed optimization for the PHY even if it strapped */ 615 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, 616 DP83867_DOWNSHIFT_EN); 617 if (ret) 618 return ret; 619 620 ret = dp83867_verify_rgmii_cfg(phydev); 621 if (ret) 622 return ret; 623 624 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 625 if (dp83867->rxctrl_strap_quirk) 626 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 627 BIT(7)); 628 629 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); 630 if (bs & DP83867_STRAP_STS2_STRAP_FLD) { 631 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will 632 * be set to 0x2. This may causes the PHY link to be unstable - 633 * the default value 0x1 need to be restored. 634 */ 635 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 636 DP83867_FLD_THR_CFG, 637 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK, 638 0x1); 639 if (ret) 640 return ret; 641 } 642 643 if (phy_interface_is_rgmii(phydev) || 644 phydev->interface == PHY_INTERFACE_MODE_SGMII) { 645 val = phy_read(phydev, MII_DP83867_PHYCTRL); 646 if (val < 0) 647 return val; 648 649 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 650 val |= (dp83867->tx_fifo_depth << 651 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 652 653 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 654 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 655 val |= (dp83867->rx_fifo_depth << 656 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); 657 } 658 659 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 660 if (ret) 661 return ret; 662 } 663 664 if (phy_interface_is_rgmii(phydev)) { 665 val = phy_read(phydev, MII_DP83867_PHYCTRL); 666 if (val < 0) 667 return val; 668 669 /* The code below checks if "port mirroring" N/A MODE4 has been 670 * enabled during power on bootstrap. 671 * 672 * Such N/A mode enabled by mistake can put PHY IC in some 673 * internal testing mode and disable RGMII transmission. 674 * 675 * In this particular case one needs to check STRAP_STS1 676 * register's bit 11 (marked as RESERVED). 677 */ 678 679 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 680 if (bs & DP83867_STRAP_STS1_RESERVED) 681 val &= ~DP83867_PHYCR_RESERVED_MASK; 682 683 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 684 if (ret) 685 return ret; 686 687 /* If rgmii mode with no internal delay is selected, we do NOT use 688 * aligned mode as one might expect. Instead we use the PHY's default 689 * based on pin strapping. And the "mode 0" default is to *use* 690 * internal delay with a value of 7 (2.00 ns). 691 * 692 * Set up RGMII delays 693 */ 694 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 695 696 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 697 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 698 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 699 700 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 701 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 702 703 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 704 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 705 706 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 707 708 delay = 0; 709 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 710 delay |= dp83867->rx_id_delay; 711 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 712 delay |= dp83867->tx_id_delay << 713 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 714 715 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 716 delay); 717 } 718 719 /* If specified, set io impedance */ 720 if (dp83867->io_impedance >= 0) 721 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 722 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 723 dp83867->io_impedance); 724 725 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 726 /* For support SPEED_10 in SGMII mode 727 * DP83867_10M_SGMII_RATE_ADAPT bit 728 * has to be cleared by software. That 729 * does not affect SPEED_100 and 730 * SPEED_1000. 731 */ 732 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 733 DP83867_10M_SGMII_CFG, 734 DP83867_10M_SGMII_RATE_ADAPT_MASK, 735 0); 736 if (ret) 737 return ret; 738 739 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 740 * are 01). That is not enough to finalize autoneg on some 741 * devices. Increase this timer duration to maximum 16ms. 742 */ 743 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 744 DP83867_CFG4, 745 DP83867_CFG4_SGMII_ANEG_MASK, 746 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 747 748 if (ret) 749 return ret; 750 751 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 752 /* SGMII type is set to 4-wire mode by default. 753 * If we place appropriate property in dts (see above) 754 * switch on 6-wire mode. 755 */ 756 if (dp83867->sgmii_ref_clk_en) 757 val |= DP83867_SGMII_TYPE; 758 else 759 val &= ~DP83867_SGMII_TYPE; 760 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 761 762 /* This is a SW workaround for link instability if RX_CTRL is 763 * not strapped to mode 3 or 4 in HW. This is required for SGMII 764 * in addition to clearing bit 7, handled above. 765 */ 766 if (dp83867->rxctrl_strap_quirk) 767 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 768 BIT(8)); 769 } 770 771 val = phy_read(phydev, DP83867_CFG3); 772 /* Enable Interrupt output INT_OE in CFG3 register */ 773 if (phy_interrupt_is_valid(phydev)) 774 val |= DP83867_CFG3_INT_OE; 775 776 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 777 phy_write(phydev, DP83867_CFG3, val); 778 779 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 780 dp83867_config_port_mirroring(phydev); 781 782 /* Clock output selection if muxing property is set */ 783 if (dp83867->set_clk_output) { 784 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 785 786 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 787 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 788 } else { 789 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 790 val = dp83867->clk_output_sel << 791 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 792 } 793 794 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 795 mask, val); 796 } 797 798 return 0; 799} 800 801static int dp83867_phy_reset(struct phy_device *phydev) 802{ 803 int err; 804 805 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 806 if (err < 0) 807 return err; 808 809 usleep_range(10, 20); 810 811 err = phy_modify(phydev, MII_DP83867_PHYCTRL, 812 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 813 if (err < 0) 814 return err; 815 816 /* Configure the DSP Feedforward Equalizer Configuration register to 817 * improve short cable (< 1 meter) performance. This will not affect 818 * long cable performance. 819 */ 820 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG, 821 0x0e81); 822 if (err < 0) 823 return err; 824 825 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); 826 if (err < 0) 827 return err; 828 829 usleep_range(10, 20); 830 831 return 0; 832} 833 834static void dp83867_link_change_notify(struct phy_device *phydev) 835{ 836 /* There is a limitation in DP83867 PHY device where SGMII AN is 837 * only triggered once after the device is booted up. Even after the 838 * PHY TPI is down and up again, SGMII AN is not triggered and 839 * hence no new in-band message from PHY to MAC side SGMII. 840 * This could cause an issue during power up, when PHY is up prior 841 * to MAC. At this condition, once MAC side SGMII is up, MAC side 842 * SGMII wouldn`t receive new in-band message from TI PHY with 843 * correct link status, speed and duplex info. 844 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg 845 * whenever there is a link change. 846 */ 847 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 848 int val = 0; 849 850 val = phy_clear_bits(phydev, DP83867_CFG2, 851 DP83867_SGMII_AUTONEG_EN); 852 if (val < 0) 853 return; 854 855 phy_set_bits(phydev, DP83867_CFG2, 856 DP83867_SGMII_AUTONEG_EN); 857 } 858} 859 860static struct phy_driver dp83867_driver[] = { 861 { 862 .phy_id = DP83867_PHY_ID, 863 .phy_id_mask = 0xfffffff0, 864 .name = "TI DP83867", 865 /* PHY_GBIT_FEATURES */ 866 867 .probe = dp83867_probe, 868 .config_init = dp83867_config_init, 869 .soft_reset = dp83867_phy_reset, 870 871 .read_status = dp83867_read_status, 872 .get_tunable = dp83867_get_tunable, 873 .set_tunable = dp83867_set_tunable, 874 875 .get_wol = dp83867_get_wol, 876 .set_wol = dp83867_set_wol, 877 878 /* IRQ related */ 879 .ack_interrupt = dp83867_ack_interrupt, 880 .config_intr = dp83867_config_intr, 881 882 .suspend = genphy_suspend, 883 .resume = genphy_resume, 884 885 .link_change_notify = dp83867_link_change_notify, 886 }, 887}; 888module_phy_driver(dp83867_driver); 889 890static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 891 { DP83867_PHY_ID, 0xfffffff0 }, 892 { } 893}; 894 895MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 896 897MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 898MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 899MODULE_LICENSE("GPL v2"); 900