1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/delay.h> 13#include <linux/bitfield.h> 14#include <linux/phy.h> 15 16#include "aquantia.h" 17 18#define PHY_ID_AQ1202 0x03a1b445 19#define PHY_ID_AQ2104 0x03a1b460 20#define PHY_ID_AQR105 0x03a1b4a2 21#define PHY_ID_AQR106 0x03a1b4d0 22#define PHY_ID_AQR107 0x03a1b4e0 23#define PHY_ID_AQCS109 0x03a1b5c2 24#define PHY_ID_AQR405 0x03a1b4b0 25 26#define MDIO_PHYXS_VEND_IF_STATUS 0xe812 27#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 28#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 29#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 30#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 31#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 32#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 33 34#define MDIO_AN_VEND_PROV 0xc400 35#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 36#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 37#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 38#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 39#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 40#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 41#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 42 43#define MDIO_AN_TX_VEND_STATUS1 0xc800 44#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 45#define MDIO_AN_TX_VEND_STATUS1_10BASET 0 46#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 47#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 48#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 49#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 50#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 51#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 52 53#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 54#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 55 56#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 57 58#define MDIO_AN_TX_VEND_INT_MASK2 0xd401 59#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 60 61#define MDIO_AN_RX_LP_STAT1 0xe820 62#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 63#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 64#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 65#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 66#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 67 68#define MDIO_AN_RX_LP_STAT4 0xe823 69#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 70#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 71 72#define MDIO_AN_RX_VEND_STAT3 0xe832 73#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 74 75/* MDIO_MMD_C22EXT */ 76#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 77#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 78#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 79#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 80#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 81#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 82#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 83#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 84#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 85#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 86 87/* Vendor specific 1, MDIO_MMD_VEND1 */ 88#define VEND1_GLOBAL_FW_ID 0x0020 89#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 90#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 91 92#define VEND1_GLOBAL_GEN_STAT2 0xc831 93#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15) 94 95#define VEND1_GLOBAL_RSVD_STAT1 0xc885 96#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 97#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 98 99#define VEND1_GLOBAL_RSVD_STAT9 0xc88d 100#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 101#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 102 103#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 104#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 105 106#define VEND1_GLOBAL_INT_STD_MASK 0xff00 107#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 108#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 109#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 110#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 111#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 112#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 113#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 114#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 115#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 116#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 117#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 118 119#define VEND1_GLOBAL_INT_VEND_MASK 0xff01 120#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 121#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 122#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 123#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 124#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 125#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 126#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 127#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 128 129/* Sleep and timeout for checking if the Processor-Intensive 130 * MDIO operation is finished 131 */ 132#define AQR107_OP_IN_PROG_SLEEP 1000 133#define AQR107_OP_IN_PROG_TIMEOUT 100000 134 135struct aqr107_hw_stat { 136 const char *name; 137 int reg; 138 int size; 139}; 140 141#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 142static const struct aqr107_hw_stat aqr107_hw_stats[] = { 143 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 144 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 145 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 146 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 147 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 148 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 149 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 150 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 151 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 152 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 153}; 154#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 155 156struct aqr107_priv { 157 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 158}; 159 160static int aqr107_get_sset_count(struct phy_device *phydev) 161{ 162 return AQR107_SGMII_STAT_SZ; 163} 164 165static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 166{ 167 int i; 168 169 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 170 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 171 ETH_GSTRING_LEN); 172} 173 174static u64 aqr107_get_stat(struct phy_device *phydev, int index) 175{ 176 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 177 int len_l = min(stat->size, 16); 178 int len_h = stat->size - len_l; 179 u64 ret; 180 int val; 181 182 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 183 if (val < 0) 184 return U64_MAX; 185 186 ret = val & GENMASK(len_l - 1, 0); 187 if (len_h) { 188 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 189 if (val < 0) 190 return U64_MAX; 191 192 ret += (val & GENMASK(len_h - 1, 0)) << 16; 193 } 194 195 return ret; 196} 197 198static void aqr107_get_stats(struct phy_device *phydev, 199 struct ethtool_stats *stats, u64 *data) 200{ 201 struct aqr107_priv *priv = phydev->priv; 202 u64 val; 203 int i; 204 205 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 206 val = aqr107_get_stat(phydev, i); 207 if (val == U64_MAX) 208 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 209 aqr107_hw_stats[i].name); 210 else 211 priv->sgmii_stats[i] += val; 212 213 data[i] = priv->sgmii_stats[i]; 214 } 215} 216 217static int aqr_config_aneg(struct phy_device *phydev) 218{ 219 bool changed = false; 220 u16 reg; 221 int ret; 222 223 if (phydev->autoneg == AUTONEG_DISABLE) 224 return genphy_c45_pma_setup_forced(phydev); 225 226 ret = genphy_c45_an_config_aneg(phydev); 227 if (ret < 0) 228 return ret; 229 if (ret > 0) 230 changed = true; 231 232 /* Clause 45 has no standardized support for 1000BaseT, therefore 233 * use vendor registers for this mode. 234 */ 235 reg = 0; 236 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 237 phydev->advertising)) 238 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 239 240 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 241 phydev->advertising)) 242 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 243 244 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 245 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 246 phydev->advertising)) 247 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 248 249 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 250 phydev->advertising)) 251 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 252 253 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 254 MDIO_AN_VEND_PROV_1000BASET_HALF | 255 MDIO_AN_VEND_PROV_1000BASET_FULL | 256 MDIO_AN_VEND_PROV_2500BASET_FULL | 257 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 258 if (ret < 0) 259 return ret; 260 if (ret > 0) 261 changed = true; 262 263 return genphy_c45_check_and_restart_aneg(phydev, changed); 264} 265 266static int aqr_config_intr(struct phy_device *phydev) 267{ 268 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 269 int err; 270 271 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 272 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 273 if (err < 0) 274 return err; 275 276 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 277 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 278 if (err < 0) 279 return err; 280 281 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 282 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 283 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 284} 285 286static int aqr_ack_interrupt(struct phy_device *phydev) 287{ 288 int reg; 289 290 reg = phy_read_mmd(phydev, MDIO_MMD_AN, 291 MDIO_AN_TX_VEND_INT_STATUS2); 292 return (reg < 0) ? reg : 0; 293} 294 295static int aqr_read_status(struct phy_device *phydev) 296{ 297 int val; 298 299 if (phydev->autoneg == AUTONEG_ENABLE) { 300 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 301 if (val < 0) 302 return val; 303 304 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 305 phydev->lp_advertising, 306 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 307 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 308 phydev->lp_advertising, 309 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 310 } 311 312 return genphy_c45_read_status(phydev); 313} 314 315static int aqr107_read_rate(struct phy_device *phydev) 316{ 317 int val; 318 319 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 320 if (val < 0) 321 return val; 322 323 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 324 case MDIO_AN_TX_VEND_STATUS1_10BASET: 325 phydev->speed = SPEED_10; 326 break; 327 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 328 phydev->speed = SPEED_100; 329 break; 330 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 331 phydev->speed = SPEED_1000; 332 break; 333 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 334 phydev->speed = SPEED_2500; 335 break; 336 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 337 phydev->speed = SPEED_5000; 338 break; 339 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 340 phydev->speed = SPEED_10000; 341 break; 342 default: 343 phydev->speed = SPEED_UNKNOWN; 344 break; 345 } 346 347 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 348 phydev->duplex = DUPLEX_FULL; 349 else 350 phydev->duplex = DUPLEX_HALF; 351 352 return 0; 353} 354 355static int aqr107_read_status(struct phy_device *phydev) 356{ 357 int val, ret; 358 359 ret = aqr_read_status(phydev); 360 if (ret) 361 return ret; 362 363 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 364 return 0; 365 366 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 367 if (val < 0) 368 return val; 369 370 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 371 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 372 phydev->interface = PHY_INTERFACE_MODE_10GKR; 373 break; 374 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 375 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 376 break; 377 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 378 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 379 break; 380 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 381 phydev->interface = PHY_INTERFACE_MODE_SGMII; 382 break; 383 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 384 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 385 break; 386 default: 387 phydev->interface = PHY_INTERFACE_MODE_NA; 388 break; 389 } 390 391 /* Read possibly downshifted rate from vendor register */ 392 return aqr107_read_rate(phydev); 393} 394 395static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 396{ 397 int val, cnt, enable; 398 399 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 400 if (val < 0) 401 return val; 402 403 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 404 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 405 406 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 407 408 return 0; 409} 410 411static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 412{ 413 int val = 0; 414 415 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 416 return -E2BIG; 417 418 if (cnt != DOWNSHIFT_DEV_DISABLE) { 419 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 420 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 421 } 422 423 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 424 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 425 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 426} 427 428static int aqr107_get_tunable(struct phy_device *phydev, 429 struct ethtool_tunable *tuna, void *data) 430{ 431 switch (tuna->id) { 432 case ETHTOOL_PHY_DOWNSHIFT: 433 return aqr107_get_downshift(phydev, data); 434 default: 435 return -EOPNOTSUPP; 436 } 437} 438 439static int aqr107_set_tunable(struct phy_device *phydev, 440 struct ethtool_tunable *tuna, const void *data) 441{ 442 switch (tuna->id) { 443 case ETHTOOL_PHY_DOWNSHIFT: 444 return aqr107_set_downshift(phydev, *(const u8 *)data); 445 default: 446 return -EOPNOTSUPP; 447 } 448} 449 450/* If we configure settings whilst firmware is still initializing the chip, 451 * then these settings may be overwritten. Therefore make sure chip 452 * initialization has completed. Use presence of the firmware ID as 453 * indicator for initialization having completed. 454 * The chip also provides a "reset completed" bit, but it's cleared after 455 * read. Therefore function would time out if called again. 456 */ 457static int aqr107_wait_reset_complete(struct phy_device *phydev) 458{ 459 int val; 460 461 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 462 VEND1_GLOBAL_FW_ID, val, val != 0, 463 20000, 2000000, false); 464} 465 466static void aqr107_chip_info(struct phy_device *phydev) 467{ 468 u8 fw_major, fw_minor, build_id, prov_id; 469 int val; 470 471 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 472 if (val < 0) 473 return; 474 475 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 476 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 477 478 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 479 if (val < 0) 480 return; 481 482 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 483 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 484 485 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 486 fw_major, fw_minor, build_id, prov_id); 487} 488 489static int aqr107_config_init(struct phy_device *phydev) 490{ 491 int ret; 492 493 /* Check that the PHY interface type is compatible */ 494 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 495 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 496 phydev->interface != PHY_INTERFACE_MODE_XGMII && 497 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 498 phydev->interface != PHY_INTERFACE_MODE_10GKR && 499 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 500 return -ENODEV; 501 502 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 503 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 504 505 ret = aqr107_wait_reset_complete(phydev); 506 if (!ret) 507 aqr107_chip_info(phydev); 508 509 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 510} 511 512static int aqcs109_config_init(struct phy_device *phydev) 513{ 514 int ret; 515 516 /* Check that the PHY interface type is compatible */ 517 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 518 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 519 return -ENODEV; 520 521 ret = aqr107_wait_reset_complete(phydev); 522 if (!ret) 523 aqr107_chip_info(phydev); 524 525 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 526 * PMA speed ability bits are the same for all members of the family, 527 * AQCS109 however supports speeds up to 2.5G only. 528 */ 529 ret = phy_set_max_speed(phydev, SPEED_2500); 530 if (ret) 531 return ret; 532 533 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 534} 535 536static void aqr107_link_change_notify(struct phy_device *phydev) 537{ 538 u8 fw_major, fw_minor; 539 bool downshift, short_reach, afr; 540 int mode, val; 541 542 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 543 return; 544 545 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 546 /* call failed or link partner is no Aquantia PHY */ 547 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 548 return; 549 550 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 551 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 552 553 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 554 if (val < 0) 555 return; 556 557 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 558 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 559 560 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 561 if (val < 0) 562 return; 563 564 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 565 566 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 567 fw_major, fw_minor, 568 short_reach ? ", short reach mode" : "", 569 downshift ? ", fast-retrain downshift advertised" : "", 570 afr ? ", fast reframe advertised" : ""); 571 572 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 573 if (val < 0) 574 return; 575 576 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 577 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 578 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 579} 580 581static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 582{ 583 int val, err; 584 585 /* The datasheet notes to wait at least 1ms after issuing a 586 * processor intensive operation before checking. 587 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 588 * because that just determines the maximum time slept, not the minimum. 589 */ 590 usleep_range(1000, 5000); 591 592 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 593 VEND1_GLOBAL_GEN_STAT2, val, 594 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 595 AQR107_OP_IN_PROG_SLEEP, 596 AQR107_OP_IN_PROG_TIMEOUT, false); 597 if (err) { 598 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 599 return err; 600 } 601 602 return 0; 603} 604 605static int aqr107_suspend(struct phy_device *phydev) 606{ 607 int err; 608 609 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 610 MDIO_CTRL1_LPOWER); 611 if (err) 612 return err; 613 614 return aqr107_wait_processor_intensive_op(phydev); 615} 616 617static int aqr107_resume(struct phy_device *phydev) 618{ 619 int err; 620 621 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 622 MDIO_CTRL1_LPOWER); 623 if (err) 624 return err; 625 626 return aqr107_wait_processor_intensive_op(phydev); 627} 628 629static int aqr107_probe(struct phy_device *phydev) 630{ 631 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 632 sizeof(struct aqr107_priv), GFP_KERNEL); 633 if (!phydev->priv) 634 return -ENOMEM; 635 636 return aqr_hwmon_probe(phydev); 637} 638 639static struct phy_driver aqr_driver[] = { 640{ 641 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 642 .name = "Aquantia AQ1202", 643 .config_aneg = aqr_config_aneg, 644 .config_intr = aqr_config_intr, 645 .ack_interrupt = aqr_ack_interrupt, 646 .read_status = aqr_read_status, 647}, 648{ 649 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 650 .name = "Aquantia AQ2104", 651 .config_aneg = aqr_config_aneg, 652 .config_intr = aqr_config_intr, 653 .ack_interrupt = aqr_ack_interrupt, 654 .read_status = aqr_read_status, 655}, 656{ 657 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 658 .name = "Aquantia AQR105", 659 .config_aneg = aqr_config_aneg, 660 .config_intr = aqr_config_intr, 661 .ack_interrupt = aqr_ack_interrupt, 662 .read_status = aqr_read_status, 663 .suspend = aqr107_suspend, 664 .resume = aqr107_resume, 665}, 666{ 667 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 668 .name = "Aquantia AQR106", 669 .config_aneg = aqr_config_aneg, 670 .config_intr = aqr_config_intr, 671 .ack_interrupt = aqr_ack_interrupt, 672 .read_status = aqr_read_status, 673}, 674{ 675 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 676 .name = "Aquantia AQR107", 677 .probe = aqr107_probe, 678 .config_init = aqr107_config_init, 679 .config_aneg = aqr_config_aneg, 680 .config_intr = aqr_config_intr, 681 .ack_interrupt = aqr_ack_interrupt, 682 .read_status = aqr107_read_status, 683 .get_tunable = aqr107_get_tunable, 684 .set_tunable = aqr107_set_tunable, 685 .suspend = aqr107_suspend, 686 .resume = aqr107_resume, 687 .get_sset_count = aqr107_get_sset_count, 688 .get_strings = aqr107_get_strings, 689 .get_stats = aqr107_get_stats, 690 .link_change_notify = aqr107_link_change_notify, 691}, 692{ 693 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 694 .name = "Aquantia AQCS109", 695 .probe = aqr107_probe, 696 .config_init = aqcs109_config_init, 697 .config_aneg = aqr_config_aneg, 698 .config_intr = aqr_config_intr, 699 .ack_interrupt = aqr_ack_interrupt, 700 .read_status = aqr107_read_status, 701 .get_tunable = aqr107_get_tunable, 702 .set_tunable = aqr107_set_tunable, 703 .suspend = aqr107_suspend, 704 .resume = aqr107_resume, 705 .get_sset_count = aqr107_get_sset_count, 706 .get_strings = aqr107_get_strings, 707 .get_stats = aqr107_get_stats, 708 .link_change_notify = aqr107_link_change_notify, 709}, 710{ 711 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 712 .name = "Aquantia AQR405", 713 .config_aneg = aqr_config_aneg, 714 .config_intr = aqr_config_intr, 715 .ack_interrupt = aqr_ack_interrupt, 716 .read_status = aqr_read_status, 717}, 718}; 719 720module_phy_driver(aqr_driver); 721 722static struct mdio_device_id __maybe_unused aqr_tbl[] = { 723 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 724 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 725 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 726 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 727 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 728 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 729 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 730 { } 731}; 732 733MODULE_DEVICE_TABLE(mdio, aqr_tbl); 734 735MODULE_DESCRIPTION("Aquantia PHY driver"); 736MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 737MODULE_LICENSE("GPL v2"); 738