1// SPDX-License-Identifier: GPL-2.0 2 3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2019-2021 Linaro Ltd. 5 */ 6 7#include <linux/types.h> 8#include <linux/device.h> 9#include <linux/slab.h> 10#include <linux/bitfield.h> 11#include <linux/dma-direction.h> 12 13#include "gsi.h" 14#include "gsi_trans.h" 15#include "ipa.h" 16#include "ipa_endpoint.h" 17#include "ipa_table.h" 18#include "ipa_cmd.h" 19#include "ipa_mem.h" 20 21/** 22 * DOC: IPA Immediate Commands 23 * 24 * The AP command TX endpoint is used to issue immediate commands to the IPA. 25 * An immediate command is generally used to request the IPA do something 26 * other than data transfer to another endpoint. 27 * 28 * Immediate commands are represented by GSI transactions just like other 29 * transfer requests, represented by a single GSI TRE. Each immediate 30 * command has a well-defined format, having a payload of a known length. 31 * This allows the transfer element's length field to be used to hold an 32 * immediate command's opcode. The payload for a command resides in DRAM 33 * and is described by a single scatterlist entry in its transaction. 34 * Commands do not require a transaction completion callback. To commit 35 * an immediate command transaction, either gsi_trans_commit_wait() or 36 * gsi_trans_commit_wait_timeout() is used. 37 */ 38 39/* Some commands can wait until indicated pipeline stages are clear */ 40enum pipeline_clear_options { 41 pipeline_clear_hps = 0, 42 pipeline_clear_src_grp = 1, 43 pipeline_clear_full = 2, 44}; 45 46/* IPA_CMD_IP_V{4,6}_{FILTER,ROUTING}_INIT */ 47 48struct ipa_cmd_hw_ip_fltrt_init { 49 __le64 hash_rules_addr; 50 __le64 flags; 51 __le64 nhash_rules_addr; 52}; 53 54/* Field masks for ipa_cmd_hw_ip_fltrt_init structure fields */ 55#define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0) 56#define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12) 57#define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28) 58#define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40) 59 60/* IPA_CMD_HDR_INIT_LOCAL */ 61 62struct ipa_cmd_hw_hdr_init_local { 63 __le64 hdr_table_addr; 64 __le32 flags; 65 __le32 reserved; 66}; 67 68/* Field masks for ipa_cmd_hw_hdr_init_local structure fields */ 69#define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0) 70#define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12) 71 72/* IPA_CMD_REGISTER_WRITE */ 73 74/* For IPA v4.0+, this opcode gets modified with pipeline clear options */ 75 76#define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) 77#define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) 78 79struct ipa_cmd_register_write { 80 __le16 flags; /* Unused/reserved for IPA v3.5.1 */ 81 __le16 offset; 82 __le32 value; 83 __le32 value_mask; 84 __le32 clear_options; /* Unused/reserved for IPA v4.0+ */ 85}; 86 87/* Field masks for ipa_cmd_register_write structure fields */ 88/* The next field is present for IPA v4.0 and above */ 89#define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11) 90/* The next field is present for IPA v3.5.1 only */ 91#define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15) 92 93/* The next field and its values are present for IPA v3.5.1 only */ 94#define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0) 95 96/* IPA_CMD_IP_PACKET_INIT */ 97 98struct ipa_cmd_ip_packet_init { 99 u8 dest_endpoint; 100 u8 reserved[7]; 101}; 102 103/* Field masks for ipa_cmd_ip_packet_init dest_endpoint field */ 104#define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0) 105 106/* IPA_CMD_DMA_SHARED_MEM */ 107 108/* For IPA v4.0+, this opcode gets modified with pipeline clear options */ 109 110#define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) 111#define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) 112 113struct ipa_cmd_hw_dma_mem_mem { 114 __le16 clear_after_read; /* 0 or DMA_SHARED_MEM_CLEAR_AFTER_READ */ 115 __le16 size; 116 __le16 local_addr; 117 __le16 flags; 118 __le64 system_addr; 119}; 120 121/* Flag allowing atomic clear of target region after reading data (v4.0+)*/ 122#define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15) 123 124/* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */ 125#define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0) 126/* The next two fields are present for IPA v3.5.1 only. */ 127#define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1) 128#define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2) 129 130/* IPA_CMD_IP_PACKET_TAG_STATUS */ 131 132struct ipa_cmd_ip_packet_tag_status { 133 __le64 tag; 134}; 135 136#define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16) 137 138/* Immediate command payload */ 139union ipa_cmd_payload { 140 struct ipa_cmd_hw_ip_fltrt_init table_init; 141 struct ipa_cmd_hw_hdr_init_local hdr_init_local; 142 struct ipa_cmd_register_write register_write; 143 struct ipa_cmd_ip_packet_init ip_packet_init; 144 struct ipa_cmd_hw_dma_mem_mem dma_shared_mem; 145 struct ipa_cmd_ip_packet_tag_status ip_packet_tag_status; 146}; 147 148static void ipa_cmd_validate_build(void) 149{ 150 /* The sizes of a filter and route tables need to fit into fields 151 * in the ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables 152 * might not be used, non-hashed and hashed tables have the same 153 * maximum size. IPv4 and IPv6 filter tables have the same number 154 * of entries, as and IPv4 and IPv6 route tables have the same number 155 * of entries. 156 */ 157#define TABLE_SIZE (TABLE_COUNT_MAX * sizeof(__le64)) 158#define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX) 159 BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK)); 160 BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK)); 161#undef TABLE_COUNT_MAX 162#undef TABLE_SIZE 163} 164 165#ifdef IPA_VALIDATE 166 167/* Validate a memory region holding a table */ 168bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, 169 bool route, bool ipv6, bool hashed) 170{ 171 struct device *dev = &ipa->pdev->dev; 172 u32 offset_max; 173 174 offset_max = hashed ? field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) 175 : field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); 176 if (mem->offset > offset_max || 177 ipa->mem_offset > offset_max - mem->offset) { 178 dev_err(dev, "IPv%c %s%s table region offset too large\n", 179 ipv6 ? '6' : '4', hashed ? "hashed " : "", 180 route ? "route" : "filter"); 181 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 182 ipa->mem_offset, mem->offset, offset_max); 183 184 return false; 185 } 186 187 if (mem->offset > ipa->mem_size || 188 mem->size > ipa->mem_size - mem->offset) { 189 dev_err(dev, "IPv%c %s%s table region out of range\n", 190 ipv6 ? '6' : '4', hashed ? "hashed " : "", 191 route ? "route" : "filter"); 192 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 193 mem->offset, mem->size, ipa->mem_size); 194 195 return false; 196 } 197 198 return true; 199} 200 201/* Validate the memory region that holds headers */ 202static bool ipa_cmd_header_valid(struct ipa *ipa) 203{ 204 const struct ipa_mem *mem = &ipa->mem[IPA_MEM_MODEM_HEADER]; 205 struct device *dev = &ipa->pdev->dev; 206 u32 offset_max; 207 u32 size_max; 208 u32 size; 209 210 /* In ipa_cmd_hdr_init_local_add() we record the offset and size 211 * of the header table memory area. Make sure the offset and size 212 * fit in the fields that need to hold them, and that the entire 213 * range is within the overall IPA memory range. 214 */ 215 offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK); 216 if (mem->offset > offset_max || 217 ipa->mem_offset > offset_max - mem->offset) { 218 dev_err(dev, "header table region offset too large\n"); 219 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 220 ipa->mem_offset, mem->offset, offset_max); 221 222 return false; 223 } 224 225 size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK); 226 size = ipa->mem[IPA_MEM_MODEM_HEADER].size; 227 size += ipa->mem[IPA_MEM_AP_HEADER].size; 228 229 if (size > size_max) { 230 dev_err(dev, "header table region size too large\n"); 231 dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max); 232 233 return false; 234 } 235 if (size > ipa->mem_size || mem->offset > ipa->mem_size - size) { 236 dev_err(dev, "header table region out of range\n"); 237 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 238 mem->offset, size, ipa->mem_size); 239 240 return false; 241 } 242 243 return true; 244} 245 246/* Indicate whether an offset can be used with a register_write command */ 247static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa, 248 const char *name, u32 offset) 249{ 250 struct ipa_cmd_register_write *payload; 251 struct device *dev = &ipa->pdev->dev; 252 u32 offset_max; 253 u32 bit_count; 254 255 /* The maximum offset in a register_write immediate command depends 256 * on the version of IPA. IPA v3.5.1 supports a 16 bit offset, but 257 * newer versions allow some additional high-order bits. 258 */ 259 bit_count = BITS_PER_BYTE * sizeof(payload->offset); 260 if (ipa->version != IPA_VERSION_3_5_1) 261 bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); 262 BUILD_BUG_ON(bit_count > 32); 263 offset_max = ~0U >> (32 - bit_count); 264 265 /* Make sure the offset can be represented by the field(s) 266 * that holds it. Also make sure the offset is not outside 267 * the overall IPA memory range. 268 */ 269 if (offset > offset_max || ipa->mem_offset > offset_max - offset) { 270 dev_err(dev, "%s offset too large 0x%04x + 0x%04x > 0x%04x)\n", 271 name, ipa->mem_offset, offset, offset_max); 272 return false; 273 } 274 275 return true; 276} 277 278/* Check whether offsets passed to register_write are valid */ 279static bool ipa_cmd_register_write_valid(struct ipa *ipa) 280{ 281 const char *name; 282 u32 offset; 283 284 /* If hashed tables are supported, ensure the hash flush register 285 * offset will fit in a register write IPA immediate command. 286 */ 287 if (ipa->version != IPA_VERSION_4_2) { 288 offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version); 289 name = "filter/route hash flush"; 290 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) 291 return false; 292 } 293 294 /* Each endpoint can have a status endpoint associated with it, 295 * and this is recorded in an endpoint register. If the modem 296 * crashes, we reset the status endpoint for all modem endpoints 297 * using a register write IPA immediate command. Make sure the 298 * worst case (highest endpoint number) offset of that endpoint 299 * fits in the register write command field(s) that must hold it. 300 */ 301 offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1); 302 name = "maximal endpoint status"; 303 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) 304 return false; 305 306 return true; 307} 308 309bool ipa_cmd_data_valid(struct ipa *ipa) 310{ 311 if (!ipa_cmd_header_valid(ipa)) 312 return false; 313 314 if (!ipa_cmd_register_write_valid(ipa)) 315 return false; 316 317 return true; 318} 319 320#endif /* IPA_VALIDATE */ 321 322int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max) 323{ 324 struct gsi_trans_info *trans_info = &channel->trans_info; 325 struct device *dev = channel->gsi->dev; 326 int ret; 327 328 /* This is as good a place as any to validate build constants */ 329 ipa_cmd_validate_build(); 330 331 /* Even though command payloads are allocated one at a time, 332 * a single transaction can require up to tlv_count of them, 333 * so we treat them as if that many can be allocated at once. 334 */ 335 ret = gsi_trans_pool_init_dma(dev, &trans_info->cmd_pool, 336 sizeof(union ipa_cmd_payload), 337 tre_max, channel->tlv_count); 338 if (ret) 339 return ret; 340 341 /* Each TRE needs a command info structure */ 342 ret = gsi_trans_pool_init(&trans_info->info_pool, 343 sizeof(struct ipa_cmd_info), 344 tre_max, channel->tlv_count); 345 if (ret) 346 gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool); 347 348 return ret; 349} 350 351void ipa_cmd_pool_exit(struct gsi_channel *channel) 352{ 353 struct gsi_trans_info *trans_info = &channel->trans_info; 354 struct device *dev = channel->gsi->dev; 355 356 gsi_trans_pool_exit(&trans_info->info_pool); 357 gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool); 358} 359 360static union ipa_cmd_payload * 361ipa_cmd_payload_alloc(struct ipa *ipa, dma_addr_t *addr) 362{ 363 struct gsi_trans_info *trans_info; 364 struct ipa_endpoint *endpoint; 365 366 endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 367 trans_info = &ipa->gsi.channel[endpoint->channel_id].trans_info; 368 369 return gsi_trans_pool_alloc_dma(&trans_info->cmd_pool, addr); 370} 371 372/* If hash_size is 0, hash_offset and hash_addr ignored. */ 373void ipa_cmd_table_init_add(struct gsi_trans *trans, 374 enum ipa_cmd_opcode opcode, u16 size, u32 offset, 375 dma_addr_t addr, u16 hash_size, u32 hash_offset, 376 dma_addr_t hash_addr) 377{ 378 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 379 enum dma_data_direction direction = DMA_TO_DEVICE; 380 struct ipa_cmd_hw_ip_fltrt_init *payload; 381 union ipa_cmd_payload *cmd_payload; 382 dma_addr_t payload_addr; 383 u64 val; 384 385 /* Record the non-hash table offset and size */ 386 offset += ipa->mem_offset; 387 val = u64_encode_bits(offset, IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); 388 val |= u64_encode_bits(size, IP_FLTRT_FLAGS_NHASH_SIZE_FMASK); 389 390 /* The hash table offset and address are zero if its size is 0 */ 391 if (hash_size) { 392 /* Record the hash table offset and size */ 393 hash_offset += ipa->mem_offset; 394 val |= u64_encode_bits(hash_offset, 395 IP_FLTRT_FLAGS_HASH_ADDR_FMASK); 396 val |= u64_encode_bits(hash_size, 397 IP_FLTRT_FLAGS_HASH_SIZE_FMASK); 398 } 399 400 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 401 payload = &cmd_payload->table_init; 402 403 /* Fill in all offsets and sizes and the non-hash table address */ 404 if (hash_size) 405 payload->hash_rules_addr = cpu_to_le64(hash_addr); 406 payload->flags = cpu_to_le64(val); 407 payload->nhash_rules_addr = cpu_to_le64(addr); 408 409 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 410 direction, opcode); 411} 412 413/* Initialize header space in IPA-local memory */ 414void ipa_cmd_hdr_init_local_add(struct gsi_trans *trans, u32 offset, u16 size, 415 dma_addr_t addr) 416{ 417 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 418 enum ipa_cmd_opcode opcode = IPA_CMD_HDR_INIT_LOCAL; 419 enum dma_data_direction direction = DMA_TO_DEVICE; 420 struct ipa_cmd_hw_hdr_init_local *payload; 421 union ipa_cmd_payload *cmd_payload; 422 dma_addr_t payload_addr; 423 u32 flags; 424 425 offset += ipa->mem_offset; 426 427 /* With this command we tell the IPA where in its local memory the 428 * header tables reside. The content of the buffer provided is 429 * also written via DMA into that space. The IPA hardware owns 430 * the table, but the AP must initialize it. 431 */ 432 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 433 payload = &cmd_payload->hdr_init_local; 434 435 payload->hdr_table_addr = cpu_to_le64(addr); 436 flags = u32_encode_bits(size, HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK); 437 flags |= u32_encode_bits(offset, HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK); 438 payload->flags = cpu_to_le32(flags); 439 440 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 441 direction, opcode); 442} 443 444void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value, 445 u32 mask, bool clear_full) 446{ 447 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 448 struct ipa_cmd_register_write *payload; 449 union ipa_cmd_payload *cmd_payload; 450 u32 opcode = IPA_CMD_REGISTER_WRITE; 451 dma_addr_t payload_addr; 452 u32 clear_option; 453 u32 options; 454 u16 flags; 455 456 /* pipeline_clear_src_grp is not used */ 457 clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps; 458 459 if (ipa->version != IPA_VERSION_3_5_1) { 460 u16 offset_high; 461 u32 val; 462 463 /* Opcode encodes pipeline clear options */ 464 /* SKIP_CLEAR is always 0 (don't skip pipeline clear) */ 465 val = u16_encode_bits(clear_option, 466 REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK); 467 opcode |= val; 468 469 /* Extract the high 4 bits from the offset */ 470 offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16)); 471 offset &= (1 << 16) - 1; 472 473 /* Extract the top 4 bits and encode it into the flags field */ 474 flags = u16_encode_bits(offset_high, 475 REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); 476 options = 0; /* reserved */ 477 478 } else { 479 flags = 0; /* SKIP_CLEAR flag is always 0 */ 480 options = u16_encode_bits(clear_option, 481 REGISTER_WRITE_CLEAR_OPTIONS_FMASK); 482 } 483 484 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 485 payload = &cmd_payload->register_write; 486 487 payload->flags = cpu_to_le16(flags); 488 payload->offset = cpu_to_le16((u16)offset); 489 payload->value = cpu_to_le32(value); 490 payload->value_mask = cpu_to_le32(mask); 491 payload->clear_options = cpu_to_le32(options); 492 493 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 494 DMA_NONE, opcode); 495} 496 497/* Skip IP packet processing on the next data transfer on a TX channel */ 498static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id) 499{ 500 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 501 enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_INIT; 502 enum dma_data_direction direction = DMA_TO_DEVICE; 503 struct ipa_cmd_ip_packet_init *payload; 504 union ipa_cmd_payload *cmd_payload; 505 dma_addr_t payload_addr; 506 507 /* assert(endpoint_id < 508 field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK)); */ 509 510 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 511 payload = &cmd_payload->ip_packet_init; 512 513 payload->dest_endpoint = u8_encode_bits(endpoint_id, 514 IPA_PACKET_INIT_DEST_ENDPOINT_FMASK); 515 516 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 517 direction, opcode); 518} 519 520/* Use a DMA command to read or write a block of IPA-resident memory */ 521void ipa_cmd_dma_shared_mem_add(struct gsi_trans *trans, u32 offset, u16 size, 522 dma_addr_t addr, bool toward_ipa) 523{ 524 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 525 enum ipa_cmd_opcode opcode = IPA_CMD_DMA_SHARED_MEM; 526 struct ipa_cmd_hw_dma_mem_mem *payload; 527 union ipa_cmd_payload *cmd_payload; 528 enum dma_data_direction direction; 529 dma_addr_t payload_addr; 530 u16 flags; 531 532 /* size and offset must fit in 16 bit fields */ 533 /* assert(size > 0 && size <= U16_MAX); */ 534 /* assert(offset <= U16_MAX && ipa->mem_offset <= U16_MAX - offset); */ 535 536 offset += ipa->mem_offset; 537 538 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 539 payload = &cmd_payload->dma_shared_mem; 540 541 /* payload->clear_after_read was reserved prior to IPA v4.0. It's 542 * never needed for current code, so it's 0 regardless of version. 543 */ 544 payload->size = cpu_to_le16(size); 545 payload->local_addr = cpu_to_le16(offset); 546 /* payload->flags: 547 * direction: 0 = write to IPA, 1 read from IPA 548 * Starting at v4.0 these are reserved; either way, all zero: 549 * pipeline clear: 0 = wait for pipeline clear (don't skip) 550 * clear_options: 0 = pipeline_clear_hps 551 * Instead, for v4.0+ these are encoded in the opcode. But again 552 * since both values are 0 we won't bother OR'ing them in. 553 */ 554 flags = toward_ipa ? 0 : DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK; 555 payload->flags = cpu_to_le16(flags); 556 payload->system_addr = cpu_to_le64(addr); 557 558 direction = toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 559 560 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 561 direction, opcode); 562} 563 564static void ipa_cmd_ip_tag_status_add(struct gsi_trans *trans, u64 tag) 565{ 566 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 567 enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_TAG_STATUS; 568 enum dma_data_direction direction = DMA_TO_DEVICE; 569 struct ipa_cmd_ip_packet_tag_status *payload; 570 union ipa_cmd_payload *cmd_payload; 571 dma_addr_t payload_addr; 572 573 /* assert(tag <= field_max(IP_PACKET_TAG_STATUS_TAG_FMASK)); */ 574 575 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 576 payload = &cmd_payload->ip_packet_tag_status; 577 578 payload->tag = u64_encode_bits(tag, IP_PACKET_TAG_STATUS_TAG_FMASK); 579 580 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 581 direction, opcode); 582} 583 584/* Issue a small command TX data transfer */ 585static void ipa_cmd_transfer_add(struct gsi_trans *trans, u16 size) 586{ 587 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 588 enum dma_data_direction direction = DMA_TO_DEVICE; 589 enum ipa_cmd_opcode opcode = IPA_CMD_NONE; 590 union ipa_cmd_payload *payload; 591 dma_addr_t payload_addr; 592 593 /* assert(size <= sizeof(*payload)); */ 594 595 /* Just transfer a zero-filled payload structure */ 596 payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 597 598 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 599 direction, opcode); 600} 601 602void ipa_cmd_tag_process_add(struct gsi_trans *trans) 603{ 604 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 605 struct ipa_endpoint *endpoint; 606 607 endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; 608 609 ipa_cmd_register_write_add(trans, 0, 0, 0, true); 610 ipa_cmd_ip_packet_init_add(trans, endpoint->endpoint_id); 611 ipa_cmd_ip_tag_status_add(trans, 0xcba987654321); 612 ipa_cmd_transfer_add(trans, 4); 613} 614 615/* Returns the number of commands required for the tag process */ 616u32 ipa_cmd_tag_process_count(void) 617{ 618 return 4; 619} 620 621void ipa_cmd_tag_process(struct ipa *ipa) 622{ 623 u32 count = ipa_cmd_tag_process_count(); 624 struct gsi_trans *trans; 625 626 trans = ipa_cmd_trans_alloc(ipa, count); 627 if (trans) { 628 ipa_cmd_tag_process_add(trans); 629 gsi_trans_commit_wait(trans); 630 } else { 631 dev_err(&ipa->pdev->dev, 632 "error allocating %u entry tag transaction\n", count); 633 } 634} 635 636static struct ipa_cmd_info * 637ipa_cmd_info_alloc(struct ipa_endpoint *endpoint, u32 tre_count) 638{ 639 struct gsi_channel *channel; 640 641 channel = &endpoint->ipa->gsi.channel[endpoint->channel_id]; 642 643 return gsi_trans_pool_alloc(&channel->trans_info.info_pool, tre_count); 644} 645 646/* Allocate a transaction for the command TX endpoint */ 647struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count) 648{ 649 struct ipa_endpoint *endpoint; 650 struct gsi_trans *trans; 651 652 endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 653 654 trans = gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id, 655 tre_count, DMA_NONE); 656 if (trans) 657 trans->info = ipa_cmd_info_alloc(endpoint, tre_count); 658 659 return trans; 660} 661