1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * DaVinci Ethernet Medium Access Controller 4 * 5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine 6 * 7 * Copyright (C) 2009 Texas Instruments. 8 * 9 * --------------------------------------------------------------------------- 10 * History: 11 * 0-5 A number of folks worked on this driver in bits and pieces but the major 12 * contribution came from Suraj Iyer and Anant Gole 13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions 14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features, 15 * PHY layer usage 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/sched.h> 21#include <linux/string.h> 22#include <linux/timer.h> 23#include <linux/errno.h> 24#include <linux/in.h> 25#include <linux/ioport.h> 26#include <linux/slab.h> 27#include <linux/mm.h> 28#include <linux/interrupt.h> 29#include <linux/init.h> 30#include <linux/netdevice.h> 31#include <linux/etherdevice.h> 32#include <linux/skbuff.h> 33#include <linux/ethtool.h> 34#include <linux/highmem.h> 35#include <linux/proc_fs.h> 36#include <linux/ctype.h> 37#include <linux/spinlock.h> 38#include <linux/dma-mapping.h> 39#include <linux/clk.h> 40#include <linux/platform_device.h> 41#include <linux/regmap.h> 42#include <linux/semaphore.h> 43#include <linux/phy.h> 44#include <linux/bitops.h> 45#include <linux/io.h> 46#include <linux/uaccess.h> 47#include <linux/pm_runtime.h> 48#include <linux/davinci_emac.h> 49#include <linux/of.h> 50#include <linux/of_address.h> 51#include <linux/of_device.h> 52#include <linux/of_mdio.h> 53#include <linux/of_irq.h> 54#include <linux/of_net.h> 55#include <linux/mfd/syscon.h> 56 57#include <asm/irq.h> 58#include <asm/page.h> 59 60#include "cpsw.h" 61#include "davinci_cpdma.h" 62 63static int debug_level; 64module_param(debug_level, int, 0); 65MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 66 67/* Netif debug messages possible */ 68#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ 69 NETIF_MSG_PROBE | \ 70 NETIF_MSG_LINK | \ 71 NETIF_MSG_TIMER | \ 72 NETIF_MSG_IFDOWN | \ 73 NETIF_MSG_IFUP | \ 74 NETIF_MSG_RX_ERR | \ 75 NETIF_MSG_TX_ERR | \ 76 NETIF_MSG_TX_QUEUED | \ 77 NETIF_MSG_INTR | \ 78 NETIF_MSG_TX_DONE | \ 79 NETIF_MSG_RX_STATUS | \ 80 NETIF_MSG_PKTDATA | \ 81 NETIF_MSG_HW | \ 82 NETIF_MSG_WOL) 83 84/* version info */ 85#define EMAC_MAJOR_VERSION 6 86#define EMAC_MINOR_VERSION 1 87#define EMAC_MODULE_VERSION "6.1" 88MODULE_VERSION(EMAC_MODULE_VERSION); 89static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 90 91/* Configuration items */ 92#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ 93#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 94#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 95#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 96#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 97#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 98#define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ 99#define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ 100#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 101#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 102#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 103#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 104 105#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 106#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 107 108#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 109#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 110#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 111#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 112#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 113#define EMAC_DEF_RX_NUM_DESC (128) 114#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 115#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 116#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 117 118/* Buffer descriptor parameters */ 119#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 120#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 121 122/* EMAC register related defines */ 123#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 124#define EMAC_NUM_MULTICAST_BITS (64) 125#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 126#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 127#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 128#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 129#define EMAC_INT_MASK_CLEAR (0xFF) 130 131/* RX MBP register bit positions */ 132#define EMAC_RXMBP_PASSCRC_MASK BIT(30) 133#define EMAC_RXMBP_QOSEN_MASK BIT(29) 134#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 135#define EMAC_RXMBP_CMFEN_MASK BIT(24) 136#define EMAC_RXMBP_CSFEN_MASK BIT(23) 137#define EMAC_RXMBP_CEFEN_MASK BIT(22) 138#define EMAC_RXMBP_CAFEN_MASK BIT(21) 139#define EMAC_RXMBP_PROMCH_SHIFT (16) 140#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 141#define EMAC_RXMBP_BROADEN_MASK BIT(13) 142#define EMAC_RXMBP_BROADCH_SHIFT (8) 143#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 144#define EMAC_RXMBP_MULTIEN_MASK BIT(5) 145#define EMAC_RXMBP_MULTICH_SHIFT (0) 146#define EMAC_RXMBP_MULTICH_MASK (0x7) 147#define EMAC_RXMBP_CHMASK (0x7) 148 149/* EMAC register definitions/bit maps used */ 150# define EMAC_MBP_RXPROMISC (0x00200000) 151# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 152# define EMAC_MBP_RXBCAST (0x00002000) 153# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 154# define EMAC_MBP_RXMCAST (0x00000020) 155# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 156 157/* EMAC mac_control register */ 158#define EMAC_MACCONTROL_TXPTYPE BIT(9) 159#define EMAC_MACCONTROL_TXPACEEN BIT(6) 160#define EMAC_MACCONTROL_GMIIEN BIT(5) 161#define EMAC_MACCONTROL_GIGABITEN BIT(7) 162#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 163#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 164 165/* GIGABIT MODE related bits */ 166#define EMAC_DM646X_MACCONTORL_GIG BIT(7) 167#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 168 169/* EMAC mac_status register */ 170#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 171#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 172#define EMAC_MACSTATUS_TXERRCH_MASK (0x70000) 173#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 174#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 175#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 176#define EMAC_MACSTATUS_RXERRCH_MASK (0x700) 177#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 178 179/* EMAC RX register masks */ 180#define EMAC_RX_MAX_LEN_MASK (0xFFFF) 181#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 182 183/* MAC_IN_VECTOR (0x180) register bit fields */ 184#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 185#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 186#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 187#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 188 189/** NOTE:: For DM646x the IN_VECTOR has changed */ 190#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 191#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 192#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 193#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 194 195/* CPPI bit positions */ 196#define EMAC_CPPI_SOP_BIT BIT(31) 197#define EMAC_CPPI_EOP_BIT BIT(30) 198#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 199#define EMAC_CPPI_EOQ_BIT BIT(28) 200#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 201#define EMAC_CPPI_PASS_CRC_BIT BIT(26) 202#define EMAC_RX_BD_BUF_SIZE (0xFFFF) 203#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 204#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 205 206/* Max hardware defines */ 207#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 208#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 209 210/* EMAC Peripheral Device Register Memory Layout structure */ 211#define EMAC_MACINVECTOR 0x90 212 213#define EMAC_DM646X_MACEOIVECTOR 0x94 214 215#define EMAC_MACINTSTATRAW 0xB0 216#define EMAC_MACINTSTATMASKED 0xB4 217#define EMAC_MACINTMASKSET 0xB8 218#define EMAC_MACINTMASKCLEAR 0xBC 219 220#define EMAC_RXMBPENABLE 0x100 221#define EMAC_RXUNICASTSET 0x104 222#define EMAC_RXUNICASTCLEAR 0x108 223#define EMAC_RXMAXLEN 0x10C 224#define EMAC_RXBUFFEROFFSET 0x110 225#define EMAC_RXFILTERLOWTHRESH 0x114 226 227#define EMAC_MACCONTROL 0x160 228#define EMAC_MACSTATUS 0x164 229#define EMAC_EMCONTROL 0x168 230#define EMAC_FIFOCONTROL 0x16C 231#define EMAC_MACCONFIG 0x170 232#define EMAC_SOFTRESET 0x174 233#define EMAC_MACSRCADDRLO 0x1D0 234#define EMAC_MACSRCADDRHI 0x1D4 235#define EMAC_MACHASH1 0x1D8 236#define EMAC_MACHASH2 0x1DC 237#define EMAC_MACADDRLO 0x500 238#define EMAC_MACADDRHI 0x504 239#define EMAC_MACINDEX 0x508 240 241/* EMAC statistics registers */ 242#define EMAC_RXGOODFRAMES 0x200 243#define EMAC_RXBCASTFRAMES 0x204 244#define EMAC_RXMCASTFRAMES 0x208 245#define EMAC_RXPAUSEFRAMES 0x20C 246#define EMAC_RXCRCERRORS 0x210 247#define EMAC_RXALIGNCODEERRORS 0x214 248#define EMAC_RXOVERSIZED 0x218 249#define EMAC_RXJABBER 0x21C 250#define EMAC_RXUNDERSIZED 0x220 251#define EMAC_RXFRAGMENTS 0x224 252#define EMAC_RXFILTERED 0x228 253#define EMAC_RXQOSFILTERED 0x22C 254#define EMAC_RXOCTETS 0x230 255#define EMAC_TXGOODFRAMES 0x234 256#define EMAC_TXBCASTFRAMES 0x238 257#define EMAC_TXMCASTFRAMES 0x23C 258#define EMAC_TXPAUSEFRAMES 0x240 259#define EMAC_TXDEFERRED 0x244 260#define EMAC_TXCOLLISION 0x248 261#define EMAC_TXSINGLECOLL 0x24C 262#define EMAC_TXMULTICOLL 0x250 263#define EMAC_TXEXCESSIVECOLL 0x254 264#define EMAC_TXLATECOLL 0x258 265#define EMAC_TXUNDERRUN 0x25C 266#define EMAC_TXCARRIERSENSE 0x260 267#define EMAC_TXOCTETS 0x264 268#define EMAC_NETOCTETS 0x280 269#define EMAC_RXSOFOVERRUNS 0x284 270#define EMAC_RXMOFOVERRUNS 0x288 271#define EMAC_RXDMAOVERRUNS 0x28C 272 273/* EMAC DM644x control registers */ 274#define EMAC_CTRL_EWCTL (0x4) 275#define EMAC_CTRL_EWINTTCNT (0x8) 276 277/* EMAC DM644x control module masks */ 278#define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF 279#define EMAC_DM644X_INTMIN_INTVL 0x1 280#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 281 282/* EMAC DM646X control module registers */ 283#define EMAC_DM646X_CMINTCTRL 0x0C 284#define EMAC_DM646X_CMRXINTEN 0x14 285#define EMAC_DM646X_CMTXINTEN 0x18 286#define EMAC_DM646X_CMRXINTMAX 0x70 287#define EMAC_DM646X_CMTXINTMAX 0x74 288 289/* EMAC DM646X control module masks */ 290#define EMAC_DM646X_INTPACEEN (0x3 << 16) 291#define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) 292#define EMAC_DM646X_CMINTMAX_CNT 63 293#define EMAC_DM646X_CMINTMIN_CNT 2 294#define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) 295#define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) 296 297 298/* EMAC EOI codes for C0 */ 299#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 300#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 301 302/* EMAC Stats Clear Mask */ 303#define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 304 305/* emac_priv: EMAC private data structure 306 * 307 * EMAC adapter private data structure 308 */ 309struct emac_priv { 310 u32 msg_enable; 311 struct net_device *ndev; 312 struct platform_device *pdev; 313 struct napi_struct napi; 314 char mac_addr[6]; 315 void __iomem *remap_addr; 316 u32 emac_base_phys; 317 void __iomem *emac_base; 318 void __iomem *ctrl_base; 319 struct cpdma_ctlr *dma; 320 struct cpdma_chan *txchan; 321 struct cpdma_chan *rxchan; 322 u32 link; /* 1=link on, 0=link off */ 323 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 324 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 325 u32 rx_buf_size; 326 u32 isr_count; 327 u32 coal_intvl; 328 u32 bus_freq_mhz; 329 u8 rmii_en; 330 u8 version; 331 u32 mac_hash1; 332 u32 mac_hash2; 333 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 334 u32 rx_addr_type; 335 const char *phy_id; 336 struct device_node *phy_node; 337 spinlock_t lock; 338 /*platform specific members*/ 339 void (*int_enable) (void); 340 void (*int_disable) (void); 341}; 342 343/* EMAC TX Host Error description strings */ 344static char *emac_txhost_errcodes[16] = { 345 "No error", "SOP error", "Ownership bit not set in SOP buffer", 346 "Zero Next Buffer Descriptor Pointer Without EOP", 347 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", 348 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 349 "Reserved", "Reserved", "Reserved", "Reserved" 350}; 351 352/* EMAC RX Host Error description strings */ 353static char *emac_rxhost_errcodes[16] = { 354 "No error", "Reserved", "Ownership bit not set in input buffer", 355 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", 356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 357 "Reserved", "Reserved", "Reserved", "Reserved" 358}; 359 360/* Helper macros */ 361#define emac_read(reg) ioread32(priv->emac_base + (reg)) 362#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) 363 364#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 365#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 366 367/** 368 * emac_get_drvinfo - Get EMAC driver information 369 * @ndev: The DaVinci EMAC network adapter 370 * @info: ethtool info structure containing name and version 371 * 372 * Returns EMAC driver information (name and version) 373 * 374 */ 375static void emac_get_drvinfo(struct net_device *ndev, 376 struct ethtool_drvinfo *info) 377{ 378 strlcpy(info->driver, emac_version_string, sizeof(info->driver)); 379 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version)); 380} 381 382/** 383 * emac_get_coalesce - Get interrupt coalesce settings for this device 384 * @ndev : The DaVinci EMAC network adapter 385 * @coal : ethtool coalesce settings structure 386 * 387 * Fetch the current interrupt coalesce settings 388 * 389 */ 390static int emac_get_coalesce(struct net_device *ndev, 391 struct ethtool_coalesce *coal) 392{ 393 struct emac_priv *priv = netdev_priv(ndev); 394 395 coal->rx_coalesce_usecs = priv->coal_intvl; 396 return 0; 397 398} 399 400/** 401 * emac_set_coalesce - Set interrupt coalesce settings for this device 402 * @ndev : The DaVinci EMAC network adapter 403 * @coal : ethtool coalesce settings structure 404 * 405 * Set interrupt coalesce parameters 406 * 407 */ 408static int emac_set_coalesce(struct net_device *ndev, 409 struct ethtool_coalesce *coal) 410{ 411 struct emac_priv *priv = netdev_priv(ndev); 412 u32 int_ctrl, num_interrupts = 0; 413 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; 414 415 if (!coal->rx_coalesce_usecs) { 416 priv->coal_intvl = 0; 417 418 switch (priv->version) { 419 case EMAC_VERSION_2: 420 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0); 421 break; 422 default: 423 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0); 424 break; 425 } 426 427 return 0; 428 } 429 430 coal_intvl = coal->rx_coalesce_usecs; 431 432 switch (priv->version) { 433 case EMAC_VERSION_2: 434 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); 435 prescale = priv->bus_freq_mhz * 4; 436 437 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) 438 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; 439 440 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { 441 /* 442 * Interrupt pacer works with 4us Pulse, we can 443 * throttle further by dilating the 4us pulse. 444 */ 445 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; 446 447 if (addnl_dvdr > 1) { 448 prescale *= addnl_dvdr; 449 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL 450 * addnl_dvdr)) 451 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL 452 * addnl_dvdr); 453 } else { 454 addnl_dvdr = 1; 455 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; 456 } 457 } 458 459 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 460 461 int_ctrl |= EMAC_DM646X_INTPACEEN; 462 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); 463 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); 464 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); 465 466 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); 467 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); 468 469 break; 470 default: 471 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); 472 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); 473 prescale = coal_intvl * priv->bus_freq_mhz; 474 if (prescale > EMAC_DM644X_EWINTCNT_MASK) { 475 prescale = EMAC_DM644X_EWINTCNT_MASK; 476 coal_intvl = prescale / priv->bus_freq_mhz; 477 } 478 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); 479 480 break; 481 } 482 483 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); 484 priv->coal_intvl = coal_intvl; 485 486 return 0; 487 488} 489 490 491/* ethtool_ops: DaVinci EMAC Ethtool structure 492 * 493 * Ethtool support for EMAC adapter 494 */ 495static const struct ethtool_ops ethtool_ops = { 496 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, 497 .get_drvinfo = emac_get_drvinfo, 498 .get_link = ethtool_op_get_link, 499 .get_coalesce = emac_get_coalesce, 500 .set_coalesce = emac_set_coalesce, 501 .get_ts_info = ethtool_op_get_ts_info, 502 .get_link_ksettings = phy_ethtool_get_link_ksettings, 503 .set_link_ksettings = phy_ethtool_set_link_ksettings, 504}; 505 506/** 507 * emac_update_phystatus - Update Phy status 508 * @priv: The DaVinci EMAC private adapter structure 509 * 510 * Updates phy status and takes action for network queue if required 511 * based upon link status 512 * 513 */ 514static void emac_update_phystatus(struct emac_priv *priv) 515{ 516 u32 mac_control; 517 u32 new_duplex; 518 u32 cur_duplex; 519 struct net_device *ndev = priv->ndev; 520 521 mac_control = emac_read(EMAC_MACCONTROL); 522 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 523 DUPLEX_FULL : DUPLEX_HALF; 524 if (ndev->phydev) 525 new_duplex = ndev->phydev->duplex; 526 else 527 new_duplex = DUPLEX_FULL; 528 529 /* We get called only if link has changed (speed/duplex/status) */ 530 if ((priv->link) && (new_duplex != cur_duplex)) { 531 priv->duplex = new_duplex; 532 if (DUPLEX_FULL == priv->duplex) 533 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); 534 else 535 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); 536 } 537 538 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { 539 mac_control = emac_read(EMAC_MACCONTROL); 540 mac_control |= (EMAC_DM646X_MACCONTORL_GIG | 541 EMAC_DM646X_MACCONTORL_GIGFORCE); 542 } else { 543 /* Clear the GIG bit and GIGFORCE bit */ 544 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | 545 EMAC_DM646X_MACCONTORL_GIG); 546 547 if (priv->rmii_en && (priv->speed == SPEED_100)) 548 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; 549 else 550 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; 551 } 552 553 /* Update mac_control if changed */ 554 emac_write(EMAC_MACCONTROL, mac_control); 555 556 if (priv->link) { 557 /* link ON */ 558 if (!netif_carrier_ok(ndev)) 559 netif_carrier_on(ndev); 560 /* reactivate the transmit queue if it is stopped */ 561 if (netif_running(ndev) && netif_queue_stopped(ndev)) 562 netif_wake_queue(ndev); 563 } else { 564 /* link OFF */ 565 if (netif_carrier_ok(ndev)) 566 netif_carrier_off(ndev); 567 if (!netif_queue_stopped(ndev)) 568 netif_stop_queue(ndev); 569 } 570} 571 572/** 573 * hash_get - Calculate hash value from mac address 574 * @addr: mac address to delete from hash table 575 * 576 * Calculates hash value from mac address 577 * 578 */ 579static u32 hash_get(u8 *addr) 580{ 581 u32 hash; 582 u8 tmpval; 583 int cnt; 584 hash = 0; 585 586 for (cnt = 0; cnt < 2; cnt++) { 587 tmpval = *addr++; 588 hash ^= (tmpval >> 2) ^ (tmpval << 4); 589 tmpval = *addr++; 590 hash ^= (tmpval >> 4) ^ (tmpval << 2); 591 tmpval = *addr++; 592 hash ^= (tmpval >> 6) ^ (tmpval); 593 } 594 595 return hash & 0x3F; 596} 597 598/** 599 * emac_hash_add - Hash function to add mac addr from hash table 600 * @priv: The DaVinci EMAC private adapter structure 601 * @mac_addr: mac address to delete from hash table 602 * 603 * Adds mac address to the internal hash table 604 * 605 */ 606static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr) 607{ 608 struct device *emac_dev = &priv->ndev->dev; 609 u32 rc = 0; 610 u32 hash_bit; 611 u32 hash_value = hash_get(mac_addr); 612 613 if (hash_value >= EMAC_NUM_MULTICAST_BITS) { 614 if (netif_msg_drv(priv)) { 615 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\ 616 "Hash %08x, should not be greater than %08x", 617 hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); 618 } 619 return -1; 620 } 621 622 /* set the hash bit only if not previously set */ 623 if (priv->multicast_hash_cnt[hash_value] == 0) { 624 rc = 1; /* hash value changed */ 625 if (hash_value < 32) { 626 hash_bit = BIT(hash_value); 627 priv->mac_hash1 |= hash_bit; 628 } else { 629 hash_bit = BIT((hash_value - 32)); 630 priv->mac_hash2 |= hash_bit; 631 } 632 } 633 634 /* incr counter for num of mcast addr's mapped to "this" hash bit */ 635 ++priv->multicast_hash_cnt[hash_value]; 636 637 return rc; 638} 639 640/** 641 * emac_hash_del - Hash function to delete mac addr from hash table 642 * @priv: The DaVinci EMAC private adapter structure 643 * @mac_addr: mac address to delete from hash table 644 * 645 * Removes mac address from the internal hash table 646 * 647 */ 648static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr) 649{ 650 u32 hash_value; 651 u32 hash_bit; 652 653 hash_value = hash_get(mac_addr); 654 if (priv->multicast_hash_cnt[hash_value] > 0) { 655 /* dec cntr for num of mcast addr's mapped to this hash bit */ 656 --priv->multicast_hash_cnt[hash_value]; 657 } 658 659 /* if counter still > 0, at least one multicast address refers 660 * to this hash bit. so return 0 */ 661 if (priv->multicast_hash_cnt[hash_value] > 0) 662 return 0; 663 664 if (hash_value < 32) { 665 hash_bit = BIT(hash_value); 666 priv->mac_hash1 &= ~hash_bit; 667 } else { 668 hash_bit = BIT((hash_value - 32)); 669 priv->mac_hash2 &= ~hash_bit; 670 } 671 672 /* return 1 to indicate change in mac_hash registers reqd */ 673 return 1; 674} 675 676/* EMAC multicast operation */ 677#define EMAC_MULTICAST_ADD 0 678#define EMAC_MULTICAST_DEL 1 679#define EMAC_ALL_MULTI_SET 2 680#define EMAC_ALL_MULTI_CLR 3 681 682/** 683 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) 684 * @priv: The DaVinci EMAC private adapter structure 685 * @action: multicast operation to perform 686 * @mac_addr: mac address to set 687 * 688 * Set multicast addresses in EMAC adapter - internal function 689 * 690 */ 691static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) 692{ 693 struct device *emac_dev = &priv->ndev->dev; 694 int update = -1; 695 696 switch (action) { 697 case EMAC_MULTICAST_ADD: 698 update = emac_hash_add(priv, mac_addr); 699 break; 700 case EMAC_MULTICAST_DEL: 701 update = emac_hash_del(priv, mac_addr); 702 break; 703 case EMAC_ALL_MULTI_SET: 704 update = 1; 705 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; 706 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; 707 break; 708 case EMAC_ALL_MULTI_CLR: 709 update = 1; 710 priv->mac_hash1 = 0; 711 priv->mac_hash2 = 0; 712 memset(&(priv->multicast_hash_cnt[0]), 0, 713 sizeof(priv->multicast_hash_cnt[0]) * 714 EMAC_NUM_MULTICAST_BITS); 715 break; 716 default: 717 if (netif_msg_drv(priv)) 718 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ 719 ": bad operation %d", action); 720 break; 721 } 722 723 /* write to the hardware only if the register status chances */ 724 if (update > 0) { 725 emac_write(EMAC_MACHASH1, priv->mac_hash1); 726 emac_write(EMAC_MACHASH2, priv->mac_hash2); 727 } 728} 729 730/** 731 * emac_dev_mcast_set - Set multicast address in the EMAC adapter 732 * @ndev: The DaVinci EMAC network adapter 733 * 734 * Set multicast addresses in EMAC adapter 735 * 736 */ 737static void emac_dev_mcast_set(struct net_device *ndev) 738{ 739 u32 mbp_enable; 740 struct emac_priv *priv = netdev_priv(ndev); 741 742 mbp_enable = emac_read(EMAC_RXMBPENABLE); 743 if (ndev->flags & IFF_PROMISC) { 744 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); 745 mbp_enable |= (EMAC_MBP_RXPROMISC); 746 } else { 747 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 748 if ((ndev->flags & IFF_ALLMULTI) || 749 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { 750 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 751 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 752 } else if (!netdev_mc_empty(ndev)) { 753 struct netdev_hw_addr *ha; 754 755 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 756 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 757 /* program multicast address list into EMAC hardware */ 758 netdev_for_each_mc_addr(ha, ndev) { 759 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 760 (u8 *) ha->addr); 761 } 762 } else { 763 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 764 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 765 } 766 } 767 /* Set mbp config register */ 768 emac_write(EMAC_RXMBPENABLE, mbp_enable); 769} 770 771/************************************************************************* 772 * EMAC Hardware manipulation 773 *************************************************************************/ 774 775/** 776 * emac_int_disable - Disable EMAC module interrupt (from adapter) 777 * @priv: The DaVinci EMAC private adapter structure 778 * 779 * Disable EMAC interrupt on the adapter 780 * 781 */ 782static void emac_int_disable(struct emac_priv *priv) 783{ 784 if (priv->version == EMAC_VERSION_2) { 785 unsigned long flags; 786 787 local_irq_save(flags); 788 789 /* Program C0_Int_En to zero to turn off 790 * interrupts to the CPU */ 791 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 792 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 793 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 794 if (priv->int_disable) 795 priv->int_disable(); 796 797 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 798 799 /* ack rxen only then a new pulse will be generated */ 800 emac_write(EMAC_DM646X_MACEOIVECTOR, 801 EMAC_DM646X_MAC_EOI_C0_RXEN); 802 803 /* ack txen- only then a new pulse will be generated */ 804 emac_write(EMAC_DM646X_MACEOIVECTOR, 805 EMAC_DM646X_MAC_EOI_C0_TXEN); 806 807 local_irq_restore(flags); 808 809 } else { 810 /* Set DM644x control registers for interrupt control */ 811 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); 812 } 813} 814 815/** 816 * emac_int_enable - Enable EMAC module interrupt (from adapter) 817 * @priv: The DaVinci EMAC private adapter structure 818 * 819 * Enable EMAC interrupt on the adapter 820 * 821 */ 822static void emac_int_enable(struct emac_priv *priv) 823{ 824 if (priv->version == EMAC_VERSION_2) { 825 if (priv->int_enable) 826 priv->int_enable(); 827 828 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 829 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 830 831 /* In addition to turning on interrupt Enable, we need 832 * ack by writing appropriate values to the EOI 833 * register */ 834 835 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 836 } else { 837 /* Set DM644x control registers for interrupt control */ 838 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); 839 } 840} 841 842/** 843 * emac_irq - EMAC interrupt handler 844 * @irq: interrupt number 845 * @dev_id: EMAC network adapter data structure ptr 846 * 847 * EMAC Interrupt handler - we only schedule NAPI and not process any packets 848 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function 849 * 850 * Returns interrupt handled condition 851 */ 852static irqreturn_t emac_irq(int irq, void *dev_id) 853{ 854 struct net_device *ndev = (struct net_device *)dev_id; 855 struct emac_priv *priv = netdev_priv(ndev); 856 857 ++priv->isr_count; 858 if (likely(netif_running(priv->ndev))) { 859 emac_int_disable(priv); 860 napi_schedule(&priv->napi); 861 } else { 862 /* we are closing down, so dont process anything */ 863 } 864 return IRQ_HANDLED; 865} 866 867static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) 868{ 869 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); 870 if (WARN_ON(!skb)) 871 return NULL; 872 skb_reserve(skb, NET_IP_ALIGN); 873 return skb; 874} 875 876static void emac_rx_handler(void *token, int len, int status) 877{ 878 struct sk_buff *skb = token; 879 struct net_device *ndev = skb->dev; 880 struct emac_priv *priv = netdev_priv(ndev); 881 struct device *emac_dev = &ndev->dev; 882 int ret; 883 884 /* free and bail if we are shutting down */ 885 if (unlikely(!netif_running(ndev))) { 886 dev_kfree_skb_any(skb); 887 return; 888 } 889 890 /* recycle on receive error */ 891 if (status < 0) { 892 ndev->stats.rx_errors++; 893 goto recycle; 894 } 895 896 /* feed received packet up the stack */ 897 skb_put(skb, len); 898 skb->protocol = eth_type_trans(skb, ndev); 899 netif_receive_skb(skb); 900 ndev->stats.rx_bytes += len; 901 ndev->stats.rx_packets++; 902 903 /* alloc a new packet for receive */ 904 skb = emac_rx_alloc(priv); 905 if (!skb) { 906 if (netif_msg_rx_err(priv) && net_ratelimit()) 907 dev_err(emac_dev, "failed rx buffer alloc\n"); 908 return; 909 } 910 911recycle: 912 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 913 skb_tailroom(skb), 0); 914 915 WARN_ON(ret == -ENOMEM); 916 if (unlikely(ret < 0)) 917 dev_kfree_skb_any(skb); 918} 919 920static void emac_tx_handler(void *token, int len, int status) 921{ 922 struct sk_buff *skb = token; 923 struct net_device *ndev = skb->dev; 924 925 /* Check whether the queue is stopped due to stalled tx dma, if the 926 * queue is stopped then start the queue as we have free desc for tx 927 */ 928 if (unlikely(netif_queue_stopped(ndev))) 929 netif_wake_queue(ndev); 930 ndev->stats.tx_packets++; 931 ndev->stats.tx_bytes += len; 932 dev_kfree_skb_any(skb); 933} 934 935/** 936 * emac_dev_xmit - EMAC Transmit function 937 * @skb: SKB pointer 938 * @ndev: The DaVinci EMAC network adapter 939 * 940 * Called by the system to transmit a packet - we queue the packet in 941 * EMAC hardware transmit queue 942 * 943 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) 944 */ 945static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) 946{ 947 struct device *emac_dev = &ndev->dev; 948 int ret_code; 949 struct emac_priv *priv = netdev_priv(ndev); 950 951 /* If no link, return */ 952 if (unlikely(!priv->link)) { 953 if (netif_msg_tx_err(priv) && net_ratelimit()) 954 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 955 goto fail_tx; 956 } 957 958 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); 959 if (unlikely(ret_code < 0)) { 960 if (netif_msg_tx_err(priv) && net_ratelimit()) 961 dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); 962 goto fail_tx; 963 } 964 965 skb_tx_timestamp(skb); 966 967 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, 968 0); 969 if (unlikely(ret_code != 0)) { 970 if (netif_msg_tx_err(priv) && net_ratelimit()) 971 dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); 972 goto fail_tx; 973 } 974 975 /* If there is no more tx desc left free then we need to 976 * tell the kernel to stop sending us tx frames. 977 */ 978 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan))) 979 netif_stop_queue(ndev); 980 981 return NETDEV_TX_OK; 982 983fail_tx: 984 ndev->stats.tx_dropped++; 985 netif_stop_queue(ndev); 986 return NETDEV_TX_BUSY; 987} 988 989/** 990 * emac_dev_tx_timeout - EMAC Transmit timeout function 991 * @ndev: The DaVinci EMAC network adapter 992 * @txqueue: the index of the hung transmit queue 993 * 994 * Called when system detects that a skb timeout period has expired 995 * potentially due to a fault in the adapter in not being able to send 996 * it out on the wire. We teardown the TX channel assuming a hardware 997 * error and re-initialize the TX channel for hardware operation 998 * 999 */ 1000static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1001{ 1002 struct emac_priv *priv = netdev_priv(ndev); 1003 struct device *emac_dev = &ndev->dev; 1004 1005 if (netif_msg_tx_err(priv)) 1006 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1007 1008 ndev->stats.tx_errors++; 1009 emac_int_disable(priv); 1010 cpdma_chan_stop(priv->txchan); 1011 cpdma_chan_start(priv->txchan); 1012 emac_int_enable(priv); 1013} 1014 1015/** 1016 * emac_set_type0addr - Set EMAC Type0 mac address 1017 * @priv: The DaVinci EMAC private adapter structure 1018 * @ch: RX channel number 1019 * @mac_addr: MAC address to set in device 1020 * 1021 * Called internally to set Type0 mac address of the adapter (Device) 1022 * 1023 * Returns success (0) or appropriate error code (none as of now) 1024 */ 1025static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1026{ 1027 u32 val; 1028 val = ((mac_addr[5] << 8) | (mac_addr[4])); 1029 emac_write(EMAC_MACSRCADDRLO, val); 1030 1031 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1032 (mac_addr[1] << 8) | (mac_addr[0])); 1033 emac_write(EMAC_MACSRCADDRHI, val); 1034 val = emac_read(EMAC_RXUNICASTSET); 1035 val |= BIT(ch); 1036 emac_write(EMAC_RXUNICASTSET, val); 1037 val = emac_read(EMAC_RXUNICASTCLEAR); 1038 val &= ~BIT(ch); 1039 emac_write(EMAC_RXUNICASTCLEAR, val); 1040} 1041 1042/** 1043 * emac_set_type1addr - Set EMAC Type1 mac address 1044 * @priv: The DaVinci EMAC private adapter structure 1045 * @ch: RX channel number 1046 * @mac_addr: MAC address to set in device 1047 * 1048 * Called internally to set Type1 mac address of the adapter (Device) 1049 * 1050 * Returns success (0) or appropriate error code (none as of now) 1051 */ 1052static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1053{ 1054 u32 val; 1055 emac_write(EMAC_MACINDEX, ch); 1056 val = ((mac_addr[5] << 8) | mac_addr[4]); 1057 emac_write(EMAC_MACADDRLO, val); 1058 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1059 (mac_addr[1] << 8) | (mac_addr[0])); 1060 emac_write(EMAC_MACADDRHI, val); 1061 emac_set_type0addr(priv, ch, mac_addr); 1062} 1063 1064/** 1065 * emac_set_type2addr - Set EMAC Type2 mac address 1066 * @priv: The DaVinci EMAC private adapter structure 1067 * @ch: RX channel number 1068 * @mac_addr: MAC address to set in device 1069 * @index: index into RX address entries 1070 * @match: match parameter for RX address matching logic 1071 * 1072 * Called internally to set Type2 mac address of the adapter (Device) 1073 * 1074 * Returns success (0) or appropriate error code (none as of now) 1075 */ 1076static void emac_set_type2addr(struct emac_priv *priv, u32 ch, 1077 char *mac_addr, int index, int match) 1078{ 1079 u32 val; 1080 emac_write(EMAC_MACINDEX, index); 1081 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1082 (mac_addr[1] << 8) | (mac_addr[0])); 1083 emac_write(EMAC_MACADDRHI, val); 1084 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ 1085 (match << 19) | BIT(20)); 1086 emac_write(EMAC_MACADDRLO, val); 1087 emac_set_type0addr(priv, ch, mac_addr); 1088} 1089 1090/** 1091 * emac_setmac - Set mac address in the adapter (internal function) 1092 * @priv: The DaVinci EMAC private adapter structure 1093 * @ch: RX channel number 1094 * @mac_addr: MAC address to set in device 1095 * 1096 * Called internally to set the mac address of the adapter (Device) 1097 * 1098 * Returns success (0) or appropriate error code (none as of now) 1099 */ 1100static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) 1101{ 1102 struct device *emac_dev = &priv->ndev->dev; 1103 1104 if (priv->rx_addr_type == 0) { 1105 emac_set_type0addr(priv, ch, mac_addr); 1106 } else if (priv->rx_addr_type == 1) { 1107 u32 cnt; 1108 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) 1109 emac_set_type1addr(priv, ch, mac_addr); 1110 } else if (priv->rx_addr_type == 2) { 1111 emac_set_type2addr(priv, ch, mac_addr, ch, 1); 1112 emac_set_type0addr(priv, ch, mac_addr); 1113 } else { 1114 if (netif_msg_drv(priv)) 1115 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); 1116 } 1117} 1118 1119/** 1120 * emac_dev_setmac_addr - Set mac address in the adapter 1121 * @ndev: The DaVinci EMAC network adapter 1122 * @addr: MAC address to set in device 1123 * 1124 * Called by the system to set the mac address of the adapter (Device) 1125 * 1126 * Returns success (0) or appropriate error code (none as of now) 1127 */ 1128static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1129{ 1130 struct emac_priv *priv = netdev_priv(ndev); 1131 struct device *emac_dev = &priv->ndev->dev; 1132 struct sockaddr *sa = addr; 1133 1134 if (!is_valid_ether_addr(sa->sa_data)) 1135 return -EADDRNOTAVAIL; 1136 1137 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1138 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1139 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); 1140 1141 /* MAC address is configured only after the interface is enabled. */ 1142 if (netif_running(ndev)) { 1143 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1144 } 1145 1146 if (netif_msg_drv(priv)) 1147 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1148 priv->mac_addr); 1149 1150 return 0; 1151} 1152 1153/** 1154 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception 1155 * @priv: The DaVinci EMAC private adapter structure 1156 * 1157 * Enables EMAC hardware for packet processing - enables PHY, enables RX 1158 * for packet reception and enables device interrupts and then NAPI 1159 * 1160 * Returns success (0) or appropriate error code (none right now) 1161 */ 1162static int emac_hw_enable(struct emac_priv *priv) 1163{ 1164 u32 val, mbp_enable, mac_control; 1165 1166 /* Soft reset */ 1167 emac_write(EMAC_SOFTRESET, 1); 1168 while (emac_read(EMAC_SOFTRESET)) 1169 cpu_relax(); 1170 1171 /* Disable interrupt & Set pacing for more interrupts initially */ 1172 emac_int_disable(priv); 1173 1174 /* Full duplex enable bit set when auto negotiation happens */ 1175 mac_control = 1176 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | 1177 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | 1178 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | 1179 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); 1180 emac_write(EMAC_MACCONTROL, mac_control); 1181 1182 mbp_enable = 1183 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | 1184 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | 1185 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | 1186 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | 1187 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | 1188 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | 1189 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | 1190 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ 1191 EMAC_RXMBP_PROMCH_SHIFT) | 1192 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | 1193 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ 1194 EMAC_RXMBP_BROADCH_SHIFT) | 1195 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | 1196 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ 1197 EMAC_RXMBP_MULTICH_SHIFT)); 1198 emac_write(EMAC_RXMBPENABLE, mbp_enable); 1199 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & 1200 EMAC_RX_MAX_LEN_MASK)); 1201 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & 1202 EMAC_RX_BUFFER_OFFSET_MASK)); 1203 emac_write(EMAC_RXFILTERLOWTHRESH, 0); 1204 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1205 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1206 1207 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1208 1209 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1210 1211 /* Enable MII */ 1212 val = emac_read(EMAC_MACCONTROL); 1213 val |= (EMAC_MACCONTROL_GMIIEN); 1214 emac_write(EMAC_MACCONTROL, val); 1215 1216 /* Enable NAPI and interrupts */ 1217 napi_enable(&priv->napi); 1218 emac_int_enable(priv); 1219 return 0; 1220 1221} 1222 1223/** 1224 * emac_poll - EMAC NAPI Poll function 1225 * @napi: pointer to the napi_struct containing The DaVinci EMAC network adapter 1226 * @budget: Number of receive packets to process (as told by NAPI layer) 1227 * 1228 * NAPI Poll function implemented to process packets as per budget. We check 1229 * the type of interrupt on the device and accordingly call the TX or RX 1230 * packet processing functions. We follow the budget for RX processing and 1231 * also put a cap on number of TX pkts processed through config param. The 1232 * NAPI schedule function is called if more packets pending. 1233 * 1234 * Returns number of packets received (in most cases; else TX pkts - rarely) 1235 */ 1236static int emac_poll(struct napi_struct *napi, int budget) 1237{ 1238 unsigned int mask; 1239 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 1240 struct net_device *ndev = priv->ndev; 1241 struct device *emac_dev = &ndev->dev; 1242 u32 status = 0; 1243 u32 num_rx_pkts = 0; 1244 1245 /* Check interrupt vectors and call packet processing */ 1246 status = emac_read(EMAC_MACINVECTOR); 1247 1248 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; 1249 1250 if (priv->version == EMAC_VERSION_2) 1251 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1252 1253 if (status & mask) { 1254 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE); 1255 } /* TX processing */ 1256 1257 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1258 1259 if (priv->version == EMAC_VERSION_2) 1260 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1261 1262 if (status & mask) { 1263 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); 1264 } /* RX processing */ 1265 1266 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1267 if (priv->version == EMAC_VERSION_2) 1268 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; 1269 1270 if (unlikely(status & mask)) { 1271 u32 ch, cause; 1272 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); 1273 netif_stop_queue(ndev); 1274 napi_disable(&priv->napi); 1275 1276 status = emac_read(EMAC_MACSTATUS); 1277 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> 1278 EMAC_MACSTATUS_TXERRCODE_SHIFT); 1279 if (cause) { 1280 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> 1281 EMAC_MACSTATUS_TXERRCH_SHIFT); 1282 if (net_ratelimit()) { 1283 dev_err(emac_dev, "TX Host error %s on ch=%d\n", 1284 &emac_txhost_errcodes[cause][0], ch); 1285 } 1286 } 1287 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> 1288 EMAC_MACSTATUS_RXERRCODE_SHIFT); 1289 if (cause) { 1290 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> 1291 EMAC_MACSTATUS_RXERRCH_SHIFT); 1292 if (netif_msg_hw(priv) && net_ratelimit()) 1293 dev_err(emac_dev, "RX Host error %s on ch=%d\n", 1294 &emac_rxhost_errcodes[cause][0], ch); 1295 } 1296 } else if (num_rx_pkts < budget) { 1297 napi_complete_done(napi, num_rx_pkts); 1298 emac_int_enable(priv); 1299 } 1300 1301 return num_rx_pkts; 1302} 1303 1304#ifdef CONFIG_NET_POLL_CONTROLLER 1305/** 1306 * emac_poll_controller - EMAC Poll controller function 1307 * @ndev: The DaVinci EMAC network adapter 1308 * 1309 * Polled functionality used by netconsole and others in non interrupt mode 1310 * 1311 */ 1312static void emac_poll_controller(struct net_device *ndev) 1313{ 1314 struct emac_priv *priv = netdev_priv(ndev); 1315 1316 emac_int_disable(priv); 1317 emac_irq(ndev->irq, ndev); 1318 emac_int_enable(priv); 1319} 1320#endif 1321 1322static void emac_adjust_link(struct net_device *ndev) 1323{ 1324 struct emac_priv *priv = netdev_priv(ndev); 1325 struct phy_device *phydev = ndev->phydev; 1326 unsigned long flags; 1327 int new_state = 0; 1328 1329 spin_lock_irqsave(&priv->lock, flags); 1330 1331 if (phydev->link) { 1332 /* check the mode of operation - full/half duplex */ 1333 if (phydev->duplex != priv->duplex) { 1334 new_state = 1; 1335 priv->duplex = phydev->duplex; 1336 } 1337 if (phydev->speed != priv->speed) { 1338 new_state = 1; 1339 priv->speed = phydev->speed; 1340 } 1341 if (!priv->link) { 1342 new_state = 1; 1343 priv->link = 1; 1344 } 1345 1346 } else if (priv->link) { 1347 new_state = 1; 1348 priv->link = 0; 1349 priv->speed = 0; 1350 priv->duplex = ~0; 1351 } 1352 if (new_state) { 1353 emac_update_phystatus(priv); 1354 phy_print_status(ndev->phydev); 1355 } 1356 1357 spin_unlock_irqrestore(&priv->lock, flags); 1358} 1359 1360/************************************************************************* 1361 * Linux Driver Model 1362 *************************************************************************/ 1363 1364/** 1365 * emac_devioctl - EMAC adapter ioctl 1366 * @ndev: The DaVinci EMAC network adapter 1367 * @ifrq: request parameter 1368 * @cmd: command parameter 1369 * 1370 * EMAC driver ioctl function 1371 * 1372 * Returns success(0) or appropriate error code 1373 */ 1374static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) 1375{ 1376 if (!(netif_running(ndev))) 1377 return -EINVAL; 1378 1379 /* TODO: Add phy read and write and private statistics get feature */ 1380 1381 if (ndev->phydev) 1382 return phy_mii_ioctl(ndev->phydev, ifrq, cmd); 1383 else 1384 return -EOPNOTSUPP; 1385} 1386 1387static int match_first_device(struct device *dev, const void *data) 1388{ 1389 if (dev->parent && dev->parent->of_node) 1390 return of_device_is_compatible(dev->parent->of_node, 1391 "ti,davinci_mdio"); 1392 1393 return !strncmp(dev_name(dev), "davinci_mdio", 12); 1394} 1395 1396/** 1397 * emac_dev_open - EMAC device open 1398 * @ndev: The DaVinci EMAC network adapter 1399 * 1400 * Called when system wants to start the interface. We init TX/RX channels 1401 * and enable the hardware for packet reception/transmission and start the 1402 * network queue. 1403 * 1404 * Returns 0 for a successful open, or appropriate error code 1405 */ 1406static int emac_dev_open(struct net_device *ndev) 1407{ 1408 struct device *emac_dev = &ndev->dev; 1409 u32 cnt; 1410 struct resource *res; 1411 int q, m, ret; 1412 int res_num = 0, irq_num = 0; 1413 int i = 0; 1414 struct emac_priv *priv = netdev_priv(ndev); 1415 struct phy_device *phydev = NULL; 1416 struct device *phy = NULL; 1417 1418 ret = pm_runtime_get_sync(&priv->pdev->dev); 1419 if (ret < 0) { 1420 pm_runtime_put_noidle(&priv->pdev->dev); 1421 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1422 __func__, ret); 1423 return ret; 1424 } 1425 1426 netif_carrier_off(ndev); 1427 for (cnt = 0; cnt < ETH_ALEN; cnt++) 1428 ndev->dev_addr[cnt] = priv->mac_addr[cnt]; 1429 1430 /* Configuration items */ 1431 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1432 1433 priv->mac_hash1 = 0; 1434 priv->mac_hash2 = 0; 1435 emac_write(EMAC_MACHASH1, 0); 1436 emac_write(EMAC_MACHASH2, 0); 1437 1438 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { 1439 struct sk_buff *skb = emac_rx_alloc(priv); 1440 1441 if (!skb) 1442 break; 1443 1444 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data, 1445 skb_tailroom(skb), 0); 1446 if (WARN_ON(ret < 0)) 1447 break; 1448 } 1449 1450 /* Request IRQ */ 1451 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, 1452 res_num))) { 1453 for (irq_num = res->start; irq_num <= res->end; irq_num++) { 1454 if (request_irq(irq_num, emac_irq, 0, ndev->name, 1455 ndev)) { 1456 dev_err(emac_dev, 1457 "DaVinci EMAC: request_irq() failed\n"); 1458 ret = -EBUSY; 1459 1460 goto rollback; 1461 } 1462 } 1463 res_num++; 1464 } 1465 /* prepare counters for rollback in case of an error */ 1466 res_num--; 1467 irq_num--; 1468 1469 /* Start/Enable EMAC hardware */ 1470 emac_hw_enable(priv); 1471 1472 /* Enable Interrupt pacing if configured */ 1473 if (priv->coal_intvl != 0) { 1474 struct ethtool_coalesce coal; 1475 1476 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1477 emac_set_coalesce(ndev, &coal); 1478 } 1479 1480 cpdma_ctlr_start(priv->dma); 1481 1482 if (priv->phy_node) { 1483 phydev = of_phy_connect(ndev, priv->phy_node, 1484 &emac_adjust_link, 0, 0); 1485 if (!phydev) { 1486 dev_err(emac_dev, "could not connect to phy %pOF\n", 1487 priv->phy_node); 1488 ret = -ENODEV; 1489 goto err; 1490 } 1491 } 1492 1493 /* use the first phy on the bus if pdata did not give us a phy id */ 1494 if (!phydev && !priv->phy_id) { 1495 /* NOTE: we can't use bus_find_device_by_name() here because 1496 * the device name is not guaranteed to be 'davinci_mdio'. On 1497 * some systems it can be 'davinci_mdio.0' so we need to use 1498 * strncmp() against the first part of the string to correctly 1499 * match it. 1500 */ 1501 phy = bus_find_device(&mdio_bus_type, NULL, NULL, 1502 match_first_device); 1503 if (phy) { 1504 priv->phy_id = dev_name(phy); 1505 if (!priv->phy_id || !*priv->phy_id) 1506 put_device(phy); 1507 } 1508 } 1509 1510 if (!phydev && priv->phy_id && *priv->phy_id) { 1511 phydev = phy_connect(ndev, priv->phy_id, 1512 &emac_adjust_link, 1513 PHY_INTERFACE_MODE_MII); 1514 put_device(phy); /* reference taken by bus_find_device */ 1515 if (IS_ERR(phydev)) { 1516 dev_err(emac_dev, "could not connect to phy %s\n", 1517 priv->phy_id); 1518 ret = PTR_ERR(phydev); 1519 goto err; 1520 } 1521 1522 priv->link = 0; 1523 priv->speed = 0; 1524 priv->duplex = ~0; 1525 1526 phy_attached_info(phydev); 1527 } 1528 1529 if (!phydev) { 1530 /* No PHY , fix the link, speed and duplex settings */ 1531 dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); 1532 priv->link = 1; 1533 priv->speed = SPEED_100; 1534 priv->duplex = DUPLEX_FULL; 1535 emac_update_phystatus(priv); 1536 } 1537 1538 if (netif_msg_drv(priv)) 1539 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1540 1541 if (phydev) 1542 phy_start(phydev); 1543 1544 return 0; 1545 1546err: 1547 emac_int_disable(priv); 1548 napi_disable(&priv->napi); 1549 1550rollback: 1551 for (q = res_num; q >= 0; q--) { 1552 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q); 1553 /* at the first iteration, irq_num is already set to the 1554 * right value 1555 */ 1556 if (q != res_num) 1557 irq_num = res->end; 1558 1559 for (m = irq_num; m >= res->start; m--) 1560 free_irq(m, ndev); 1561 } 1562 cpdma_ctlr_stop(priv->dma); 1563 pm_runtime_put(&priv->pdev->dev); 1564 return ret; 1565} 1566 1567/** 1568 * emac_dev_stop - EMAC device stop 1569 * @ndev: The DaVinci EMAC network adapter 1570 * 1571 * Called when system wants to stop or down the interface. We stop the network 1572 * queue, disable interrupts and cleanup TX/RX channels. 1573 * 1574 * We return the statistics in net_device_stats structure pulled from emac 1575 */ 1576static int emac_dev_stop(struct net_device *ndev) 1577{ 1578 struct resource *res; 1579 int i = 0; 1580 int irq_num; 1581 struct emac_priv *priv = netdev_priv(ndev); 1582 struct device *emac_dev = &ndev->dev; 1583 1584 /* inform the upper layers. */ 1585 netif_stop_queue(ndev); 1586 napi_disable(&priv->napi); 1587 1588 netif_carrier_off(ndev); 1589 emac_int_disable(priv); 1590 cpdma_ctlr_stop(priv->dma); 1591 emac_write(EMAC_SOFTRESET, 1); 1592 1593 if (ndev->phydev) 1594 phy_disconnect(ndev->phydev); 1595 1596 /* Free IRQ */ 1597 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { 1598 for (irq_num = res->start; irq_num <= res->end; irq_num++) 1599 free_irq(irq_num, priv->ndev); 1600 i++; 1601 } 1602 1603 if (netif_msg_drv(priv)) 1604 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); 1605 1606 pm_runtime_put(&priv->pdev->dev); 1607 return 0; 1608} 1609 1610/** 1611 * emac_dev_getnetstats - EMAC get statistics function 1612 * @ndev: The DaVinci EMAC network adapter 1613 * 1614 * Called when system wants to get statistics from the device. 1615 * 1616 * We return the statistics in net_device_stats structure pulled from emac 1617 */ 1618static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 1619{ 1620 struct emac_priv *priv = netdev_priv(ndev); 1621 u32 mac_control; 1622 u32 stats_clear_mask; 1623 int err; 1624 1625 err = pm_runtime_get_sync(&priv->pdev->dev); 1626 if (err < 0) { 1627 pm_runtime_put_noidle(&priv->pdev->dev); 1628 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1629 __func__, err); 1630 return &ndev->stats; 1631 } 1632 1633 /* update emac hardware stats and reset the registers*/ 1634 1635 mac_control = emac_read(EMAC_MACCONTROL); 1636 1637 if (mac_control & EMAC_MACCONTROL_GMIIEN) 1638 stats_clear_mask = EMAC_STATS_CLR_MASK; 1639 else 1640 stats_clear_mask = 0; 1641 1642 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 1643 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); 1644 1645 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + 1646 emac_read(EMAC_TXSINGLECOLL) + 1647 emac_read(EMAC_TXMULTICOLL)); 1648 emac_write(EMAC_TXCOLLISION, stats_clear_mask); 1649 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); 1650 emac_write(EMAC_TXMULTICOLL, stats_clear_mask); 1651 1652 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 1653 emac_read(EMAC_RXJABBER) + 1654 emac_read(EMAC_RXUNDERSIZED)); 1655 emac_write(EMAC_RXOVERSIZED, stats_clear_mask); 1656 emac_write(EMAC_RXJABBER, stats_clear_mask); 1657 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); 1658 1659 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 1660 emac_read(EMAC_RXMOFOVERRUNS)); 1661 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); 1662 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); 1663 1664 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 1665 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); 1666 1667 ndev->stats.tx_carrier_errors += 1668 emac_read(EMAC_TXCARRIERSENSE); 1669 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1670 1671 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); 1672 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1673 1674 pm_runtime_put(&priv->pdev->dev); 1675 1676 return &ndev->stats; 1677} 1678 1679static const struct net_device_ops emac_netdev_ops = { 1680 .ndo_open = emac_dev_open, 1681 .ndo_stop = emac_dev_stop, 1682 .ndo_start_xmit = emac_dev_xmit, 1683 .ndo_set_rx_mode = emac_dev_mcast_set, 1684 .ndo_set_mac_address = emac_dev_setmac_addr, 1685 .ndo_do_ioctl = emac_devioctl, 1686 .ndo_tx_timeout = emac_dev_tx_timeout, 1687 .ndo_get_stats = emac_dev_getnetstats, 1688#ifdef CONFIG_NET_POLL_CONTROLLER 1689 .ndo_poll_controller = emac_poll_controller, 1690#endif 1691}; 1692 1693static const struct of_device_id davinci_emac_of_match[]; 1694 1695static struct emac_platform_data * 1696davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) 1697{ 1698 struct device_node *np; 1699 const struct of_device_id *match; 1700 const struct emac_platform_data *auxdata; 1701 struct emac_platform_data *pdata = NULL; 1702 const u8 *mac_addr; 1703 1704 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 1705 return dev_get_platdata(&pdev->dev); 1706 1707 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1708 if (!pdata) 1709 return NULL; 1710 1711 np = pdev->dev.of_node; 1712 pdata->version = EMAC_VERSION_2; 1713 1714 if (!is_valid_ether_addr(pdata->mac_addr)) { 1715 mac_addr = of_get_mac_address(np); 1716 if (!IS_ERR(mac_addr)) 1717 ether_addr_copy(pdata->mac_addr, mac_addr); 1718 } 1719 1720 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", 1721 &pdata->ctrl_reg_offset); 1722 1723 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", 1724 &pdata->ctrl_mod_reg_offset); 1725 1726 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", 1727 &pdata->ctrl_ram_offset); 1728 1729 of_property_read_u32(np, "ti,davinci-ctrl-ram-size", 1730 &pdata->ctrl_ram_size); 1731 1732 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en); 1733 1734 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram"); 1735 1736 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 1737 if (!priv->phy_node) { 1738 if (!of_phy_is_fixed_link(np)) 1739 pdata->phy_id = NULL; 1740 else if (of_phy_register_fixed_link(np) >= 0) 1741 priv->phy_node = of_node_get(np); 1742 } 1743 1744 auxdata = pdev->dev.platform_data; 1745 if (auxdata) { 1746 pdata->interrupt_enable = auxdata->interrupt_enable; 1747 pdata->interrupt_disable = auxdata->interrupt_disable; 1748 } 1749 1750 match = of_match_device(davinci_emac_of_match, &pdev->dev); 1751 if (match && match->data) { 1752 auxdata = match->data; 1753 pdata->version = auxdata->version; 1754 pdata->hw_ram_addr = auxdata->hw_ram_addr; 1755 } 1756 1757 return pdata; 1758} 1759 1760static int davinci_emac_try_get_mac(struct platform_device *pdev, 1761 int instance, u8 *mac_addr) 1762{ 1763 if (!pdev->dev.of_node) 1764 return -EINVAL; 1765 1766 return ti_cm_get_macid(&pdev->dev, instance, mac_addr); 1767} 1768 1769/** 1770 * davinci_emac_probe - EMAC device probe 1771 * @pdev: The DaVinci EMAC device that we are removing 1772 * 1773 * Called when probing for emac devicesr. We get details of instances and 1774 * resource information from platform init and register a network device 1775 * and allocate resources necessary for driver to perform 1776 */ 1777static int davinci_emac_probe(struct platform_device *pdev) 1778{ 1779 struct device_node *np = pdev->dev.of_node; 1780 int rc = 0; 1781 struct resource *res, *res_ctrl; 1782 struct net_device *ndev; 1783 struct emac_priv *priv; 1784 unsigned long hw_ram_addr; 1785 struct emac_platform_data *pdata; 1786 struct cpdma_params dma_params; 1787 struct clk *emac_clk; 1788 unsigned long emac_bus_frequency; 1789 1790 1791 /* obtain emac clock from kernel */ 1792 emac_clk = devm_clk_get(&pdev->dev, NULL); 1793 if (IS_ERR(emac_clk)) { 1794 dev_err(&pdev->dev, "failed to get EMAC clock\n"); 1795 return -EBUSY; 1796 } 1797 emac_bus_frequency = clk_get_rate(emac_clk); 1798 devm_clk_put(&pdev->dev, emac_clk); 1799 1800 /* TODO: Probe PHY here if possible */ 1801 1802 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1803 if (!ndev) 1804 return -ENOMEM; 1805 1806 platform_set_drvdata(pdev, ndev); 1807 priv = netdev_priv(ndev); 1808 priv->pdev = pdev; 1809 priv->ndev = ndev; 1810 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1811 1812 spin_lock_init(&priv->lock); 1813 1814 pdata = davinci_emac_of_get_pdata(pdev, priv); 1815 if (!pdata) { 1816 dev_err(&pdev->dev, "no platform data\n"); 1817 rc = -ENODEV; 1818 goto err_free_netdev; 1819 } 1820 1821 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1822 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN); 1823 priv->phy_id = pdata->phy_id; 1824 priv->rmii_en = pdata->rmii_en; 1825 priv->version = pdata->version; 1826 priv->int_enable = pdata->interrupt_enable; 1827 priv->int_disable = pdata->interrupt_disable; 1828 1829 priv->coal_intvl = 0; 1830 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); 1831 1832 /* Get EMAC platform data */ 1833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1834 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1835 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res); 1836 if (IS_ERR(priv->remap_addr)) { 1837 rc = PTR_ERR(priv->remap_addr); 1838 goto no_pdata; 1839 } 1840 1841 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1842 if (res_ctrl) { 1843 priv->ctrl_base = 1844 devm_ioremap_resource(&pdev->dev, res_ctrl); 1845 if (IS_ERR(priv->ctrl_base)) { 1846 rc = PTR_ERR(priv->ctrl_base); 1847 goto no_pdata; 1848 } 1849 } else { 1850 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1851 } 1852 1853 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; 1854 ndev->base_addr = (unsigned long)priv->remap_addr; 1855 1856 hw_ram_addr = pdata->hw_ram_addr; 1857 if (!hw_ram_addr) 1858 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; 1859 1860 memset(&dma_params, 0, sizeof(dma_params)); 1861 dma_params.dev = &pdev->dev; 1862 dma_params.dmaregs = priv->emac_base; 1863 dma_params.rxthresh = priv->emac_base + 0x120; 1864 dma_params.rxfree = priv->emac_base + 0x140; 1865 dma_params.txhdp = priv->emac_base + 0x600; 1866 dma_params.rxhdp = priv->emac_base + 0x620; 1867 dma_params.txcp = priv->emac_base + 0x640; 1868 dma_params.rxcp = priv->emac_base + 0x660; 1869 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; 1870 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; 1871 dma_params.desc_hw_addr = hw_ram_addr; 1872 dma_params.desc_mem_size = pdata->ctrl_ram_size; 1873 dma_params.desc_align = 16; 1874 1875 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : 1876 (u32 __force)res->start + pdata->ctrl_ram_offset; 1877 1878 priv->dma = cpdma_ctlr_create(&dma_params); 1879 if (!priv->dma) { 1880 dev_err(&pdev->dev, "error initializing DMA\n"); 1881 rc = -ENOMEM; 1882 goto no_pdata; 1883 } 1884 1885 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH, 1886 emac_tx_handler, 0); 1887 if (IS_ERR(priv->txchan)) { 1888 dev_err(&pdev->dev, "error initializing tx dma channel\n"); 1889 rc = PTR_ERR(priv->txchan); 1890 goto err_free_dma; 1891 } 1892 1893 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH, 1894 emac_rx_handler, 1); 1895 if (IS_ERR(priv->rxchan)) { 1896 dev_err(&pdev->dev, "error initializing rx dma channel\n"); 1897 rc = PTR_ERR(priv->rxchan); 1898 goto err_free_txchan; 1899 } 1900 1901 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1902 if (!res) { 1903 dev_err(&pdev->dev, "error getting irq res\n"); 1904 rc = -ENOENT; 1905 goto err_free_rxchan; 1906 } 1907 ndev->irq = res->start; 1908 1909 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr); 1910 if (!rc) 1911 ether_addr_copy(ndev->dev_addr, priv->mac_addr); 1912 1913 if (!is_valid_ether_addr(priv->mac_addr)) { 1914 /* Use random MAC if still none obtained. */ 1915 eth_hw_addr_random(ndev); 1916 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); 1917 dev_warn(&pdev->dev, "using random MAC addr: %pM\n", 1918 priv->mac_addr); 1919 } 1920 1921 ndev->netdev_ops = &emac_netdev_ops; 1922 ndev->ethtool_ops = ðtool_ops; 1923 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); 1924 1925 pm_runtime_enable(&pdev->dev); 1926 rc = pm_runtime_get_sync(&pdev->dev); 1927 if (rc < 0) { 1928 pm_runtime_put_noidle(&pdev->dev); 1929 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n", 1930 __func__, rc); 1931 goto err_napi_del; 1932 } 1933 1934 /* register the network device */ 1935 SET_NETDEV_DEV(ndev, &pdev->dev); 1936 rc = register_netdev(ndev); 1937 if (rc) { 1938 dev_err(&pdev->dev, "error in register_netdev\n"); 1939 rc = -ENODEV; 1940 pm_runtime_put(&pdev->dev); 1941 goto err_napi_del; 1942 } 1943 1944 1945 if (netif_msg_probe(priv)) { 1946 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device " 1947 "(regs: %pa, irq: %d)\n", 1948 &priv->emac_base_phys, ndev->irq); 1949 } 1950 pm_runtime_put(&pdev->dev); 1951 1952 return 0; 1953 1954err_napi_del: 1955 netif_napi_del(&priv->napi); 1956err_free_rxchan: 1957 cpdma_chan_destroy(priv->rxchan); 1958err_free_txchan: 1959 cpdma_chan_destroy(priv->txchan); 1960err_free_dma: 1961 cpdma_ctlr_destroy(priv->dma); 1962no_pdata: 1963 if (of_phy_is_fixed_link(np)) 1964 of_phy_deregister_fixed_link(np); 1965 of_node_put(priv->phy_node); 1966err_free_netdev: 1967 free_netdev(ndev); 1968 return rc; 1969} 1970 1971/** 1972 * davinci_emac_remove - EMAC device remove 1973 * @pdev: The DaVinci EMAC device that we are removing 1974 * 1975 * Called when removing the device driver. We disable clock usage and release 1976 * the resources taken up by the driver and unregister network device 1977 */ 1978static int davinci_emac_remove(struct platform_device *pdev) 1979{ 1980 struct net_device *ndev = platform_get_drvdata(pdev); 1981 struct emac_priv *priv = netdev_priv(ndev); 1982 struct device_node *np = pdev->dev.of_node; 1983 1984 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); 1985 1986 if (priv->txchan) 1987 cpdma_chan_destroy(priv->txchan); 1988 if (priv->rxchan) 1989 cpdma_chan_destroy(priv->rxchan); 1990 cpdma_ctlr_destroy(priv->dma); 1991 1992 unregister_netdev(ndev); 1993 of_node_put(priv->phy_node); 1994 pm_runtime_disable(&pdev->dev); 1995 if (of_phy_is_fixed_link(np)) 1996 of_phy_deregister_fixed_link(np); 1997 free_netdev(ndev); 1998 1999 return 0; 2000} 2001 2002static int davinci_emac_suspend(struct device *dev) 2003{ 2004 struct net_device *ndev = dev_get_drvdata(dev); 2005 2006 if (netif_running(ndev)) 2007 emac_dev_stop(ndev); 2008 2009 return 0; 2010} 2011 2012static int davinci_emac_resume(struct device *dev) 2013{ 2014 struct net_device *ndev = dev_get_drvdata(dev); 2015 2016 if (netif_running(ndev)) 2017 emac_dev_open(ndev); 2018 2019 return 0; 2020} 2021 2022static const struct dev_pm_ops davinci_emac_pm_ops = { 2023 .suspend = davinci_emac_suspend, 2024 .resume = davinci_emac_resume, 2025}; 2026 2027static const struct emac_platform_data am3517_emac_data = { 2028 .version = EMAC_VERSION_2, 2029 .hw_ram_addr = 0x01e20000, 2030}; 2031 2032static const struct emac_platform_data dm816_emac_data = { 2033 .version = EMAC_VERSION_2, 2034}; 2035 2036static const struct of_device_id davinci_emac_of_match[] = { 2037 {.compatible = "ti,davinci-dm6467-emac", }, 2038 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, }, 2039 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, }, 2040 {}, 2041}; 2042MODULE_DEVICE_TABLE(of, davinci_emac_of_match); 2043 2044/* davinci_emac_driver: EMAC platform driver structure */ 2045static struct platform_driver davinci_emac_driver = { 2046 .driver = { 2047 .name = "davinci_emac", 2048 .pm = &davinci_emac_pm_ops, 2049 .of_match_table = davinci_emac_of_match, 2050 }, 2051 .probe = davinci_emac_probe, 2052 .remove = davinci_emac_remove, 2053}; 2054 2055/** 2056 * davinci_emac_init - EMAC driver module init 2057 * 2058 * Called when initializing the driver. We register the driver with 2059 * the platform. 2060 */ 2061static int __init davinci_emac_init(void) 2062{ 2063 return platform_driver_register(&davinci_emac_driver); 2064} 2065late_initcall(davinci_emac_init); 2066 2067/** 2068 * davinci_emac_exit - EMAC driver module exit 2069 * 2070 * Called when exiting the driver completely. We unregister the driver with 2071 * the platform and exit 2072 */ 2073static void __exit davinci_emac_exit(void) 2074{ 2075 platform_driver_unregister(&davinci_emac_driver); 2076} 2077module_exit(davinci_emac_exit); 2078 2079MODULE_LICENSE("GPL"); 2080MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); 2081MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); 2082MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); 2083