1// SPDX-License-Identifier: GPL-2.0-only 2/******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9*******************************************************************************/ 10 11#include <linux/etherdevice.h> 12#include <linux/ethtool.h> 13#include <linux/interrupt.h> 14#include <linux/mii.h> 15#include <linux/phylink.h> 16#include <linux/net_tstamp.h> 17#include <asm/io.h> 18 19#include "stmmac.h" 20#include "dwmac_dma.h" 21#include "dwxgmac2.h" 22 23#define REG_SPACE_SIZE 0x1060 24#define GMAC4_REG_SPACE_SIZE 0x116C 25#define MAC100_ETHTOOL_NAME "st_mac100" 26#define GMAC_ETHTOOL_NAME "st_gmac" 27#define XGMAC_ETHTOOL_NAME "st_xgmac" 28 29/* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 30 * 31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 32 * same time due to the conflicting macro names. 33 */ 34#define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 35 36#define ETHTOOL_DMA_OFFSET 55 37 38struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42}; 43 44#define STMMAC_STAT(m) \ 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 STMMAC_STAT(rx_split_hdr_pkt_n), 79 /* Tx/Rx IRQ error info */ 80 STMMAC_STAT(tx_undeflow_irq), 81 STMMAC_STAT(tx_process_stopped_irq), 82 STMMAC_STAT(tx_jabber_irq), 83 STMMAC_STAT(rx_overflow_irq), 84 STMMAC_STAT(rx_buf_unav_irq), 85 STMMAC_STAT(rx_process_stopped_irq), 86 STMMAC_STAT(rx_watchdog_irq), 87 STMMAC_STAT(tx_early_irq), 88 STMMAC_STAT(fatal_bus_error_irq), 89 /* Tx/Rx IRQ Events */ 90 STMMAC_STAT(rx_early_irq), 91 STMMAC_STAT(threshold), 92 STMMAC_STAT(tx_pkt_n), 93 STMMAC_STAT(rx_pkt_n), 94 STMMAC_STAT(normal_irq_n), 95 STMMAC_STAT(rx_normal_irq_n), 96 STMMAC_STAT(napi_poll), 97 STMMAC_STAT(tx_normal_irq_n), 98 STMMAC_STAT(tx_clean), 99 STMMAC_STAT(tx_set_ic_bit), 100 STMMAC_STAT(irq_receive_pmt_irq_n), 101 /* MMC info */ 102 STMMAC_STAT(mmc_tx_irq_n), 103 STMMAC_STAT(mmc_rx_irq_n), 104 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 105 /* EEE */ 106 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 107 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 108 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 109 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 110 STMMAC_STAT(phy_eee_wakeup_error_n), 111 /* Extended RDES status */ 112 STMMAC_STAT(ip_hdr_err), 113 STMMAC_STAT(ip_payload_err), 114 STMMAC_STAT(ip_csum_bypassed), 115 STMMAC_STAT(ipv4_pkt_rcvd), 116 STMMAC_STAT(ipv6_pkt_rcvd), 117 STMMAC_STAT(no_ptp_rx_msg_type_ext), 118 STMMAC_STAT(ptp_rx_msg_type_sync), 119 STMMAC_STAT(ptp_rx_msg_type_follow_up), 120 STMMAC_STAT(ptp_rx_msg_type_delay_req), 121 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 122 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 123 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 124 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 125 STMMAC_STAT(ptp_rx_msg_type_announce), 126 STMMAC_STAT(ptp_rx_msg_type_management), 127 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 128 STMMAC_STAT(ptp_frame_type), 129 STMMAC_STAT(ptp_ver), 130 STMMAC_STAT(timestamp_dropped), 131 STMMAC_STAT(av_pkt_rcvd), 132 STMMAC_STAT(av_tagged_pkt_rcvd), 133 STMMAC_STAT(vlan_tag_priority_val), 134 STMMAC_STAT(l3_filter_match), 135 STMMAC_STAT(l4_filter_match), 136 STMMAC_STAT(l3_l4_filter_no_match), 137 /* PCS */ 138 STMMAC_STAT(irq_pcs_ane_n), 139 STMMAC_STAT(irq_pcs_link_n), 140 STMMAC_STAT(irq_rgmii_n), 141 /* DEBUG */ 142 STMMAC_STAT(mtl_tx_status_fifo_full), 143 STMMAC_STAT(mtl_tx_fifo_not_empty), 144 STMMAC_STAT(mmtl_fifo_ctrl), 145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 147 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 148 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 149 STMMAC_STAT(mac_tx_in_pause), 150 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 151 STMMAC_STAT(mac_tx_frame_ctrl_idle), 152 STMMAC_STAT(mac_tx_frame_ctrl_wait), 153 STMMAC_STAT(mac_tx_frame_ctrl_pause), 154 STMMAC_STAT(mac_gmii_tx_proto_engine), 155 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 156 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 157 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 158 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 161 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 162 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 163 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 164 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 165 STMMAC_STAT(mac_gmii_rx_proto_engine), 166 /* TSO */ 167 STMMAC_STAT(tx_tso_frames), 168 STMMAC_STAT(tx_tso_nfrags), 169}; 170#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 171 172/* HW MAC Management counters (if supported) */ 173#define STMMAC_MMC_STAT(m) \ 174 { #m, sizeof_field(struct stmmac_counters, m), \ 175 offsetof(struct stmmac_priv, mmc.m)} 176 177static const struct stmmac_stats stmmac_mmc[] = { 178 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 179 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 180 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 181 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 182 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 183 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 184 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 185 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 186 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 187 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 188 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 189 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 190 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 191 STMMAC_MMC_STAT(mmc_tx_underflow_error), 192 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 193 STMMAC_MMC_STAT(mmc_tx_multicol_g), 194 STMMAC_MMC_STAT(mmc_tx_deferred), 195 STMMAC_MMC_STAT(mmc_tx_latecol), 196 STMMAC_MMC_STAT(mmc_tx_exesscol), 197 STMMAC_MMC_STAT(mmc_tx_carrier_error), 198 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 199 STMMAC_MMC_STAT(mmc_tx_framecount_g), 200 STMMAC_MMC_STAT(mmc_tx_excessdef), 201 STMMAC_MMC_STAT(mmc_tx_pause_frame), 202 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 203 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 204 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 205 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 206 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 207 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 208 STMMAC_MMC_STAT(mmc_rx_crc_error), 209 STMMAC_MMC_STAT(mmc_rx_align_error), 210 STMMAC_MMC_STAT(mmc_rx_run_error), 211 STMMAC_MMC_STAT(mmc_rx_jabber_error), 212 STMMAC_MMC_STAT(mmc_rx_undersize_g), 213 STMMAC_MMC_STAT(mmc_rx_oversize_g), 214 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 215 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 216 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 217 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 218 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 219 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 220 STMMAC_MMC_STAT(mmc_rx_unicast_g), 221 STMMAC_MMC_STAT(mmc_rx_length_error), 222 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 223 STMMAC_MMC_STAT(mmc_rx_pause_frames), 224 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 225 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 226 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 227 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 228 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 229 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 230 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 231 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 232 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 233 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 234 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 235 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 236 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 237 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 238 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 239 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 240 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 241 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 242 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 243 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 244 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 245 STMMAC_MMC_STAT(mmc_rx_udp_gd), 246 STMMAC_MMC_STAT(mmc_rx_udp_err), 247 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 248 STMMAC_MMC_STAT(mmc_rx_tcp_err), 249 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 250 STMMAC_MMC_STAT(mmc_rx_icmp_err), 251 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 252 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 253 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 254 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 255 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 256 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 257 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 258 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 259 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 260 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 261 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 262 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 263}; 264#define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 265 266static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 267 struct ethtool_drvinfo *info) 268{ 269 struct stmmac_priv *priv = netdev_priv(dev); 270 271 if (priv->plat->has_gmac || priv->plat->has_gmac4) 272 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 273 else if (priv->plat->has_xgmac) 274 strlcpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 275 else 276 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 277 sizeof(info->driver)); 278 279 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 280} 281 282static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 283 struct ethtool_link_ksettings *cmd) 284{ 285 struct stmmac_priv *priv = netdev_priv(dev); 286 287 if (priv->hw->pcs & STMMAC_PCS_RGMII || 288 priv->hw->pcs & STMMAC_PCS_SGMII) { 289 struct rgmii_adv adv; 290 u32 supported, advertising, lp_advertising; 291 292 if (!priv->xstats.pcs_link) { 293 cmd->base.speed = SPEED_UNKNOWN; 294 cmd->base.duplex = DUPLEX_UNKNOWN; 295 return 0; 296 } 297 cmd->base.duplex = priv->xstats.pcs_duplex; 298 299 cmd->base.speed = priv->xstats.pcs_speed; 300 301 /* Get and convert ADV/LP_ADV from the HW AN registers */ 302 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 303 return -EOPNOTSUPP; /* should never happen indeed */ 304 305 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 306 307 ethtool_convert_link_mode_to_legacy_u32( 308 &supported, cmd->link_modes.supported); 309 ethtool_convert_link_mode_to_legacy_u32( 310 &advertising, cmd->link_modes.advertising); 311 ethtool_convert_link_mode_to_legacy_u32( 312 &lp_advertising, cmd->link_modes.lp_advertising); 313 314 if (adv.pause & STMMAC_PCS_PAUSE) 315 advertising |= ADVERTISED_Pause; 316 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 317 advertising |= ADVERTISED_Asym_Pause; 318 if (adv.lp_pause & STMMAC_PCS_PAUSE) 319 lp_advertising |= ADVERTISED_Pause; 320 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 321 lp_advertising |= ADVERTISED_Asym_Pause; 322 323 /* Reg49[3] always set because ANE is always supported */ 324 cmd->base.autoneg = ADVERTISED_Autoneg; 325 supported |= SUPPORTED_Autoneg; 326 advertising |= ADVERTISED_Autoneg; 327 lp_advertising |= ADVERTISED_Autoneg; 328 329 if (adv.duplex) { 330 supported |= (SUPPORTED_1000baseT_Full | 331 SUPPORTED_100baseT_Full | 332 SUPPORTED_10baseT_Full); 333 advertising |= (ADVERTISED_1000baseT_Full | 334 ADVERTISED_100baseT_Full | 335 ADVERTISED_10baseT_Full); 336 } else { 337 supported |= (SUPPORTED_1000baseT_Half | 338 SUPPORTED_100baseT_Half | 339 SUPPORTED_10baseT_Half); 340 advertising |= (ADVERTISED_1000baseT_Half | 341 ADVERTISED_100baseT_Half | 342 ADVERTISED_10baseT_Half); 343 } 344 if (adv.lp_duplex) 345 lp_advertising |= (ADVERTISED_1000baseT_Full | 346 ADVERTISED_100baseT_Full | 347 ADVERTISED_10baseT_Full); 348 else 349 lp_advertising |= (ADVERTISED_1000baseT_Half | 350 ADVERTISED_100baseT_Half | 351 ADVERTISED_10baseT_Half); 352 cmd->base.port = PORT_OTHER; 353 354 ethtool_convert_legacy_u32_to_link_mode( 355 cmd->link_modes.supported, supported); 356 ethtool_convert_legacy_u32_to_link_mode( 357 cmd->link_modes.advertising, advertising); 358 ethtool_convert_legacy_u32_to_link_mode( 359 cmd->link_modes.lp_advertising, lp_advertising); 360 361 return 0; 362 } 363 364 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 365} 366 367static int 368stmmac_ethtool_set_link_ksettings(struct net_device *dev, 369 const struct ethtool_link_ksettings *cmd) 370{ 371 struct stmmac_priv *priv = netdev_priv(dev); 372 373 if (priv->hw->pcs & STMMAC_PCS_RGMII || 374 priv->hw->pcs & STMMAC_PCS_SGMII) { 375 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 376 377 /* Only support ANE */ 378 if (cmd->base.autoneg != AUTONEG_ENABLE) 379 return -EINVAL; 380 381 mask &= (ADVERTISED_1000baseT_Half | 382 ADVERTISED_1000baseT_Full | 383 ADVERTISED_100baseT_Half | 384 ADVERTISED_100baseT_Full | 385 ADVERTISED_10baseT_Half | 386 ADVERTISED_10baseT_Full); 387 388 mutex_lock(&priv->lock); 389 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 390 mutex_unlock(&priv->lock); 391 392 return 0; 393 } 394 395 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 396} 397 398static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 399{ 400 struct stmmac_priv *priv = netdev_priv(dev); 401 return priv->msg_enable; 402} 403 404static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 405{ 406 struct stmmac_priv *priv = netdev_priv(dev); 407 priv->msg_enable = level; 408 409} 410 411static int stmmac_check_if_running(struct net_device *dev) 412{ 413 if (!netif_running(dev)) 414 return -EBUSY; 415 return 0; 416} 417 418static int stmmac_ethtool_get_regs_len(struct net_device *dev) 419{ 420 struct stmmac_priv *priv = netdev_priv(dev); 421 422 if (priv->plat->has_xgmac) 423 return XGMAC_REGSIZE * 4; 424 else if (priv->plat->has_gmac4) 425 return GMAC4_REG_SPACE_SIZE; 426 return REG_SPACE_SIZE; 427} 428 429static void stmmac_ethtool_gregs(struct net_device *dev, 430 struct ethtool_regs *regs, void *space) 431{ 432 struct stmmac_priv *priv = netdev_priv(dev); 433 u32 *reg_space = (u32 *) space; 434 435 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 436 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 437 438 /* Copy DMA registers to where ethtool expects them */ 439 if (priv->plat->has_gmac4) { 440 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 441 memcpy(®_space[ETHTOOL_DMA_OFFSET], 442 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 443 NUM_DWMAC4_DMA_REGS * 4); 444 } else if (!priv->plat->has_xgmac) { 445 memcpy(®_space[ETHTOOL_DMA_OFFSET], 446 ®_space[DMA_BUS_MODE / 4], 447 NUM_DWMAC1000_DMA_REGS * 4); 448 } 449} 450 451static int stmmac_nway_reset(struct net_device *dev) 452{ 453 struct stmmac_priv *priv = netdev_priv(dev); 454 455 return phylink_ethtool_nway_reset(priv->phylink); 456} 457 458static void stmmac_get_ringparam(struct net_device *netdev, 459 struct ethtool_ringparam *ring) 460{ 461 struct stmmac_priv *priv = netdev_priv(netdev); 462 463 ring->rx_max_pending = DMA_MAX_RX_SIZE; 464 ring->tx_max_pending = DMA_MAX_TX_SIZE; 465 ring->rx_pending = priv->dma_rx_size; 466 ring->tx_pending = priv->dma_tx_size; 467} 468 469static int stmmac_set_ringparam(struct net_device *netdev, 470 struct ethtool_ringparam *ring) 471{ 472 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 473 ring->rx_pending < DMA_MIN_RX_SIZE || 474 ring->rx_pending > DMA_MAX_RX_SIZE || 475 !is_power_of_2(ring->rx_pending) || 476 ring->tx_pending < DMA_MIN_TX_SIZE || 477 ring->tx_pending > DMA_MAX_TX_SIZE || 478 !is_power_of_2(ring->tx_pending)) 479 return -EINVAL; 480 481 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 482 ring->tx_pending); 483} 484 485static void 486stmmac_get_pauseparam(struct net_device *netdev, 487 struct ethtool_pauseparam *pause) 488{ 489 struct stmmac_priv *priv = netdev_priv(netdev); 490 struct rgmii_adv adv_lp; 491 492 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 493 pause->autoneg = 1; 494 if (!adv_lp.pause) 495 return; 496 } else { 497 phylink_ethtool_get_pauseparam(priv->phylink, pause); 498 } 499} 500 501static int 502stmmac_set_pauseparam(struct net_device *netdev, 503 struct ethtool_pauseparam *pause) 504{ 505 struct stmmac_priv *priv = netdev_priv(netdev); 506 struct rgmii_adv adv_lp; 507 508 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 509 pause->autoneg = 1; 510 if (!adv_lp.pause) 511 return -EOPNOTSUPP; 512 return 0; 513 } else { 514 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 515 } 516} 517 518static void stmmac_get_ethtool_stats(struct net_device *dev, 519 struct ethtool_stats *dummy, u64 *data) 520{ 521 struct stmmac_priv *priv = netdev_priv(dev); 522 u32 rx_queues_count = priv->plat->rx_queues_to_use; 523 u32 tx_queues_count = priv->plat->tx_queues_to_use; 524 unsigned long count; 525 int i, j = 0, ret; 526 527 if (priv->dma_cap.asp) { 528 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 529 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 530 &count, NULL)) 531 data[j++] = count; 532 } 533 } 534 535 /* Update the DMA HW counters for dwmac10/100 */ 536 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 537 priv->ioaddr); 538 if (ret) { 539 /* If supported, for new GMAC chips expose the MMC counters */ 540 if (priv->dma_cap.rmon) { 541 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 542 543 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 544 char *p; 545 p = (char *)priv + stmmac_mmc[i].stat_offset; 546 547 data[j++] = (stmmac_mmc[i].sizeof_stat == 548 sizeof(u64)) ? (*(u64 *)p) : 549 (*(u32 *)p); 550 } 551 } 552 if (priv->eee_enabled) { 553 int val = phylink_get_eee_err(priv->phylink); 554 if (val) 555 priv->xstats.phy_eee_wakeup_error_n = val; 556 } 557 558 if (priv->synopsys_id >= DWMAC_CORE_3_50) 559 stmmac_mac_debug(priv, priv->ioaddr, 560 (void *)&priv->xstats, 561 rx_queues_count, tx_queues_count); 562 } 563 for (i = 0; i < STMMAC_STATS_LEN; i++) { 564 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 565 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 566 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 567 } 568} 569 570static int stmmac_get_sset_count(struct net_device *netdev, int sset) 571{ 572 struct stmmac_priv *priv = netdev_priv(netdev); 573 int i, len, safety_len = 0; 574 575 switch (sset) { 576 case ETH_SS_STATS: 577 len = STMMAC_STATS_LEN; 578 579 if (priv->dma_cap.rmon) 580 len += STMMAC_MMC_STATS_LEN; 581 if (priv->dma_cap.asp) { 582 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 583 if (!stmmac_safety_feat_dump(priv, 584 &priv->sstats, i, 585 NULL, NULL)) 586 safety_len++; 587 } 588 589 len += safety_len; 590 } 591 592 return len; 593 case ETH_SS_TEST: 594 return stmmac_selftest_get_count(priv); 595 default: 596 return -EOPNOTSUPP; 597 } 598} 599 600static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 601{ 602 int i; 603 u8 *p = data; 604 struct stmmac_priv *priv = netdev_priv(dev); 605 606 switch (stringset) { 607 case ETH_SS_STATS: 608 if (priv->dma_cap.asp) { 609 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 610 const char *desc; 611 if (!stmmac_safety_feat_dump(priv, 612 &priv->sstats, i, 613 NULL, &desc)) { 614 memcpy(p, desc, ETH_GSTRING_LEN); 615 p += ETH_GSTRING_LEN; 616 } 617 } 618 } 619 if (priv->dma_cap.rmon) 620 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 621 memcpy(p, stmmac_mmc[i].stat_string, 622 ETH_GSTRING_LEN); 623 p += ETH_GSTRING_LEN; 624 } 625 for (i = 0; i < STMMAC_STATS_LEN; i++) { 626 memcpy(p, stmmac_gstrings_stats[i].stat_string, 627 ETH_GSTRING_LEN); 628 p += ETH_GSTRING_LEN; 629 } 630 break; 631 case ETH_SS_TEST: 632 stmmac_selftest_get_strings(priv, p); 633 break; 634 default: 635 WARN_ON(1); 636 break; 637 } 638} 639 640/* Currently only support WOL through Magic packet. */ 641static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 642{ 643 struct stmmac_priv *priv = netdev_priv(dev); 644 645 if (!priv->plat->pmt) 646 return phylink_ethtool_get_wol(priv->phylink, wol); 647 648 mutex_lock(&priv->lock); 649 if (device_can_wakeup(priv->device)) { 650 wol->supported = WAKE_MAGIC | WAKE_UCAST; 651 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 652 wol->supported &= ~WAKE_MAGIC; 653 wol->wolopts = priv->wolopts; 654 } 655 mutex_unlock(&priv->lock); 656} 657 658static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 659{ 660 struct stmmac_priv *priv = netdev_priv(dev); 661 u32 support = WAKE_MAGIC | WAKE_UCAST; 662 663 if (!device_can_wakeup(priv->device)) 664 return -EOPNOTSUPP; 665 666 if (!priv->plat->pmt) { 667 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 668 669 if (!ret) 670 device_set_wakeup_enable(priv->device, !!wol->wolopts); 671 return ret; 672 } 673 674 /* By default almost all GMAC devices support the WoL via 675 * magic frame but we can disable it if the HW capability 676 * register shows no support for pmt_magic_frame. */ 677 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 678 wol->wolopts &= ~WAKE_MAGIC; 679 680 if (wol->wolopts & ~support) 681 return -EINVAL; 682 683 if (wol->wolopts) { 684 pr_info("stmmac: wakeup enable\n"); 685 device_set_wakeup_enable(priv->device, 1); 686 enable_irq_wake(priv->wol_irq); 687 } else { 688 device_set_wakeup_enable(priv->device, 0); 689 disable_irq_wake(priv->wol_irq); 690 } 691 692 mutex_lock(&priv->lock); 693 priv->wolopts = wol->wolopts; 694 mutex_unlock(&priv->lock); 695 696 return 0; 697} 698 699static int stmmac_ethtool_op_get_eee(struct net_device *dev, 700 struct ethtool_eee *edata) 701{ 702 struct stmmac_priv *priv = netdev_priv(dev); 703 704 if (!priv->dma_cap.eee) 705 return -EOPNOTSUPP; 706 707 edata->eee_enabled = priv->eee_enabled; 708 edata->eee_active = priv->eee_active; 709 edata->tx_lpi_timer = priv->tx_lpi_timer; 710 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 711 712 return phylink_ethtool_get_eee(priv->phylink, edata); 713} 714 715static int stmmac_ethtool_op_set_eee(struct net_device *dev, 716 struct ethtool_eee *edata) 717{ 718 struct stmmac_priv *priv = netdev_priv(dev); 719 int ret; 720 721 if (!priv->dma_cap.eee) 722 return -EOPNOTSUPP; 723 724 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 725 netdev_warn(priv->dev, 726 "Setting EEE tx-lpi is not supported\n"); 727 728 if (!edata->eee_enabled) 729 stmmac_disable_eee_mode(priv); 730 731 ret = phylink_ethtool_set_eee(priv->phylink, edata); 732 if (ret) 733 return ret; 734 735 if (edata->eee_enabled && 736 priv->tx_lpi_timer != edata->tx_lpi_timer) { 737 priv->tx_lpi_timer = edata->tx_lpi_timer; 738 stmmac_eee_init(priv); 739 } 740 741 return 0; 742} 743 744static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 745{ 746 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 747 748 if (!clk) { 749 clk = priv->plat->clk_ref_rate; 750 if (!clk) 751 return 0; 752 } 753 754 return (usec * (clk / 1000000)) / 256; 755} 756 757static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 758{ 759 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 760 761 if (!clk) { 762 clk = priv->plat->clk_ref_rate; 763 if (!clk) 764 return 0; 765 } 766 767 return (riwt * 256) / (clk / 1000000); 768} 769 770static int stmmac_get_coalesce(struct net_device *dev, 771 struct ethtool_coalesce *ec) 772{ 773 struct stmmac_priv *priv = netdev_priv(dev); 774 775 ec->tx_coalesce_usecs = priv->tx_coal_timer; 776 ec->tx_max_coalesced_frames = priv->tx_coal_frames; 777 778 if (priv->use_riwt) { 779 ec->rx_max_coalesced_frames = priv->rx_coal_frames; 780 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv); 781 } 782 783 return 0; 784} 785 786static int stmmac_set_coalesce(struct net_device *dev, 787 struct ethtool_coalesce *ec) 788{ 789 struct stmmac_priv *priv = netdev_priv(dev); 790 u32 rx_cnt = priv->plat->rx_queues_to_use; 791 unsigned int rx_riwt; 792 793 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 794 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 795 796 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 797 return -EINVAL; 798 799 priv->rx_riwt = rx_riwt; 800 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 801 } 802 803 if ((ec->tx_coalesce_usecs == 0) && 804 (ec->tx_max_coalesced_frames == 0)) 805 return -EINVAL; 806 807 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 808 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 809 return -EINVAL; 810 811 /* Only copy relevant parameters, ignore all others. */ 812 priv->tx_coal_frames = ec->tx_max_coalesced_frames; 813 priv->tx_coal_timer = ec->tx_coalesce_usecs; 814 priv->rx_coal_frames = ec->rx_max_coalesced_frames; 815 return 0; 816} 817 818static int stmmac_get_rxnfc(struct net_device *dev, 819 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 820{ 821 struct stmmac_priv *priv = netdev_priv(dev); 822 823 switch (rxnfc->cmd) { 824 case ETHTOOL_GRXRINGS: 825 rxnfc->data = priv->plat->rx_queues_to_use; 826 break; 827 default: 828 return -EOPNOTSUPP; 829 } 830 831 return 0; 832} 833 834static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 835{ 836 struct stmmac_priv *priv = netdev_priv(dev); 837 838 return sizeof(priv->rss.key); 839} 840 841static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 842{ 843 struct stmmac_priv *priv = netdev_priv(dev); 844 845 return ARRAY_SIZE(priv->rss.table); 846} 847 848static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 849 u8 *hfunc) 850{ 851 struct stmmac_priv *priv = netdev_priv(dev); 852 int i; 853 854 if (indir) { 855 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 856 indir[i] = priv->rss.table[i]; 857 } 858 859 if (key) 860 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 861 if (hfunc) 862 *hfunc = ETH_RSS_HASH_TOP; 863 864 return 0; 865} 866 867static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 868 const u8 *key, const u8 hfunc) 869{ 870 struct stmmac_priv *priv = netdev_priv(dev); 871 int i; 872 873 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 874 return -EOPNOTSUPP; 875 876 if (indir) { 877 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 878 priv->rss.table[i] = indir[i]; 879 } 880 881 if (key) 882 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 883 884 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 885 priv->plat->rx_queues_to_use); 886} 887 888static void stmmac_get_channels(struct net_device *dev, 889 struct ethtool_channels *chan) 890{ 891 struct stmmac_priv *priv = netdev_priv(dev); 892 893 chan->rx_count = priv->plat->rx_queues_to_use; 894 chan->tx_count = priv->plat->tx_queues_to_use; 895 chan->max_rx = priv->dma_cap.number_rx_queues; 896 chan->max_tx = priv->dma_cap.number_tx_queues; 897} 898 899static int stmmac_set_channels(struct net_device *dev, 900 struct ethtool_channels *chan) 901{ 902 struct stmmac_priv *priv = netdev_priv(dev); 903 904 if (chan->rx_count > priv->dma_cap.number_rx_queues || 905 chan->tx_count > priv->dma_cap.number_tx_queues || 906 !chan->rx_count || !chan->tx_count) 907 return -EINVAL; 908 909 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 910} 911 912static int stmmac_get_ts_info(struct net_device *dev, 913 struct ethtool_ts_info *info) 914{ 915 struct stmmac_priv *priv = netdev_priv(dev); 916 917 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 918 919 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 920 SOF_TIMESTAMPING_TX_HARDWARE | 921 SOF_TIMESTAMPING_RX_SOFTWARE | 922 SOF_TIMESTAMPING_RX_HARDWARE | 923 SOF_TIMESTAMPING_SOFTWARE | 924 SOF_TIMESTAMPING_RAW_HARDWARE; 925 926 if (priv->ptp_clock) 927 info->phc_index = ptp_clock_index(priv->ptp_clock); 928 929 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 930 931 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 932 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 933 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 934 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 935 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 936 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 937 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 938 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 939 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 940 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 941 (1 << HWTSTAMP_FILTER_ALL)); 942 return 0; 943 } else 944 return ethtool_op_get_ts_info(dev, info); 945} 946 947static int stmmac_get_tunable(struct net_device *dev, 948 const struct ethtool_tunable *tuna, void *data) 949{ 950 struct stmmac_priv *priv = netdev_priv(dev); 951 int ret = 0; 952 953 switch (tuna->id) { 954 case ETHTOOL_RX_COPYBREAK: 955 *(u32 *)data = priv->rx_copybreak; 956 break; 957 default: 958 ret = -EINVAL; 959 break; 960 } 961 962 return ret; 963} 964 965static int stmmac_set_tunable(struct net_device *dev, 966 const struct ethtool_tunable *tuna, 967 const void *data) 968{ 969 struct stmmac_priv *priv = netdev_priv(dev); 970 int ret = 0; 971 972 switch (tuna->id) { 973 case ETHTOOL_RX_COPYBREAK: 974 priv->rx_copybreak = *(u32 *)data; 975 break; 976 default: 977 ret = -EINVAL; 978 break; 979 } 980 981 return ret; 982} 983 984static const struct ethtool_ops stmmac_ethtool_ops = { 985 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 986 ETHTOOL_COALESCE_MAX_FRAMES, 987 .begin = stmmac_check_if_running, 988 .get_drvinfo = stmmac_ethtool_getdrvinfo, 989 .get_msglevel = stmmac_ethtool_getmsglevel, 990 .set_msglevel = stmmac_ethtool_setmsglevel, 991 .get_regs = stmmac_ethtool_gregs, 992 .get_regs_len = stmmac_ethtool_get_regs_len, 993 .get_link = ethtool_op_get_link, 994 .nway_reset = stmmac_nway_reset, 995 .get_ringparam = stmmac_get_ringparam, 996 .set_ringparam = stmmac_set_ringparam, 997 .get_pauseparam = stmmac_get_pauseparam, 998 .set_pauseparam = stmmac_set_pauseparam, 999 .self_test = stmmac_selftest_run, 1000 .get_ethtool_stats = stmmac_get_ethtool_stats, 1001 .get_strings = stmmac_get_strings, 1002 .get_wol = stmmac_get_wol, 1003 .set_wol = stmmac_set_wol, 1004 .get_eee = stmmac_ethtool_op_get_eee, 1005 .set_eee = stmmac_ethtool_op_set_eee, 1006 .get_sset_count = stmmac_get_sset_count, 1007 .get_rxnfc = stmmac_get_rxnfc, 1008 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1009 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1010 .get_rxfh = stmmac_get_rxfh, 1011 .set_rxfh = stmmac_set_rxfh, 1012 .get_ts_info = stmmac_get_ts_info, 1013 .get_coalesce = stmmac_get_coalesce, 1014 .set_coalesce = stmmac_set_coalesce, 1015 .get_channels = stmmac_get_channels, 1016 .set_channels = stmmac_set_channels, 1017 .get_tunable = stmmac_get_tunable, 1018 .set_tunable = stmmac_set_tunable, 1019 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1020 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1021}; 1022 1023void stmmac_set_ethtool_ops(struct net_device *netdev) 1024{ 1025 netdev->ethtool_ops = &stmmac_ethtool_ops; 1026} 1027