1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 4 * DWC Ether MAC version 4.xx has been used for developing this code. 5 * 6 * This contains the functions to handle the dma. 7 * 8 * Copyright (C) 2015 STMicroelectronics Ltd 9 * 10 * Author: Alexandre Torgue <alexandre.torgue@st.com> 11 */ 12 13#include <linux/io.h> 14#include "dwmac4.h" 15#include "dwmac4_dma.h" 16 17static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 18{ 19 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 20 int i; 21 22 pr_info("dwmac4: Master AXI performs %s burst length\n", 23 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 24 25 if (axi->axi_lpi_en) 26 value |= DMA_AXI_EN_LPI; 27 if (axi->axi_xit_frm) 28 value |= DMA_AXI_LPI_XIT_FRM; 29 30 value &= ~DMA_AXI_WR_OSR_LMT; 31 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 32 DMA_AXI_WR_OSR_LMT_SHIFT; 33 34 value &= ~DMA_AXI_RD_OSR_LMT; 35 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 36 DMA_AXI_RD_OSR_LMT_SHIFT; 37 38 /* Depending on the UNDEF bit the Master AXI will perform any burst 39 * length according to the BLEN programmed (by default all BLEN are 40 * set). 41 */ 42 for (i = 0; i < AXI_BLEN; i++) { 43 switch (axi->axi_blen[i]) { 44 case 256: 45 value |= DMA_AXI_BLEN256; 46 break; 47 case 128: 48 value |= DMA_AXI_BLEN128; 49 break; 50 case 64: 51 value |= DMA_AXI_BLEN64; 52 break; 53 case 32: 54 value |= DMA_AXI_BLEN32; 55 break; 56 case 16: 57 value |= DMA_AXI_BLEN16; 58 break; 59 case 8: 60 value |= DMA_AXI_BLEN8; 61 break; 62 case 4: 63 value |= DMA_AXI_BLEN4; 64 break; 65 } 66 } 67 68 writel(value, ioaddr + DMA_SYS_BUS_MODE); 69} 70 71static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 72 struct stmmac_dma_cfg *dma_cfg, 73 dma_addr_t dma_rx_phy, u32 chan) 74{ 75 u32 value; 76 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 77 78 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 79 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 80 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 81 82 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 83 writel(upper_32_bits(dma_rx_phy), 84 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); 85 86 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); 87} 88 89static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 90 struct stmmac_dma_cfg *dma_cfg, 91 dma_addr_t dma_tx_phy, u32 chan) 92{ 93 u32 value; 94 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 95 96 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 97 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 98 99 /* Enable OSP to get best performance */ 100 value |= DMA_CONTROL_OSP; 101 102 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 103 104 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 105 writel(upper_32_bits(dma_tx_phy), 106 ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan)); 107 108 writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); 109} 110 111static void dwmac4_dma_init_channel(void __iomem *ioaddr, 112 struct stmmac_dma_cfg *dma_cfg, u32 chan) 113{ 114 u32 value; 115 116 /* common channel control register config */ 117 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 118 if (dma_cfg->pblx8) 119 value = value | DMA_BUS_MODE_PBL; 120 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 121 122 /* Mask interrupts by writing to CSR7 */ 123 writel(DMA_CHAN_INTR_DEFAULT_MASK, 124 ioaddr + DMA_CHAN_INTR_ENA(chan)); 125} 126 127static void dwmac410_dma_init_channel(void __iomem *ioaddr, 128 struct stmmac_dma_cfg *dma_cfg, u32 chan) 129{ 130 u32 value; 131 132 /* common channel control register config */ 133 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 134 if (dma_cfg->pblx8) 135 value = value | DMA_BUS_MODE_PBL; 136 137 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 138 139 /* Mask interrupts by writing to CSR7 */ 140 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10, 141 ioaddr + DMA_CHAN_INTR_ENA(chan)); 142} 143 144static void dwmac4_dma_init(void __iomem *ioaddr, 145 struct stmmac_dma_cfg *dma_cfg, int atds) 146{ 147 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 148 149 /* Set the Fixed burst mode */ 150 if (dma_cfg->fixed_burst) 151 value |= DMA_SYS_BUS_FB; 152 153 /* Mixed Burst has no effect when fb is set */ 154 if (dma_cfg->mixed_burst) 155 value |= DMA_SYS_BUS_MB; 156 157 if (dma_cfg->aal) 158 value |= DMA_SYS_BUS_AAL; 159 160 if (dma_cfg->eame) 161 value |= DMA_SYS_BUS_EAME; 162 163 writel(value, ioaddr + DMA_SYS_BUS_MODE); 164} 165 166static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 167 u32 *reg_space) 168{ 169 reg_space[DMA_CHAN_CONTROL(channel) / 4] = 170 readl(ioaddr + DMA_CHAN_CONTROL(channel)); 171 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 172 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 173 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 174 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 175 reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 176 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 177 reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 178 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 179 reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 180 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 181 reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 182 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 183 reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 184 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 185 reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 186 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 187 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 188 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 189 reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 190 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 191 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 192 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 193 reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 194 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 195 reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 196 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 197 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 198 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 199 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 200 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 201 reg_space[DMA_CHAN_STATUS(channel) / 4] = 202 readl(ioaddr + DMA_CHAN_STATUS(channel)); 203} 204 205static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 206{ 207 int i; 208 209 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 210 _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 211} 212 213static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) 214{ 215 u32 chan; 216 217 for (chan = 0; chan < number_chan; chan++) 218 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan)); 219} 220 221static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 222 u32 channel, int fifosz, u8 qmode) 223{ 224 unsigned int rqs = fifosz / 256 - 1; 225 u32 mtl_rx_op; 226 227 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 228 229 if (mode == SF_DMA_MODE) { 230 pr_debug("GMAC: enable RX store and forward mode\n"); 231 mtl_rx_op |= MTL_OP_MODE_RSF; 232 } else { 233 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 234 mtl_rx_op &= ~MTL_OP_MODE_RSF; 235 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 236 if (mode <= 32) 237 mtl_rx_op |= MTL_OP_MODE_RTC_32; 238 else if (mode <= 64) 239 mtl_rx_op |= MTL_OP_MODE_RTC_64; 240 else if (mode <= 96) 241 mtl_rx_op |= MTL_OP_MODE_RTC_96; 242 else 243 mtl_rx_op |= MTL_OP_MODE_RTC_128; 244 } 245 246 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 247 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 248 249 /* Enable flow control only if each channel gets 4 KiB or more FIFO and 250 * only if channel is not an AVB channel. 251 */ 252 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 253 unsigned int rfd, rfa; 254 255 mtl_rx_op |= MTL_OP_MODE_EHFC; 256 257 /* Set Threshold for Activating Flow Control to min 2 frames, 258 * i.e. 1500 * 2 = 3000 bytes. 259 * 260 * Set Threshold for Deactivating Flow Control to min 1 frame, 261 * i.e. 1500 bytes. 262 */ 263 switch (fifosz) { 264 case 4096: 265 /* This violates the above formula because of FIFO size 266 * limit therefore overflow may occur in spite of this. 267 */ 268 rfd = 0x03; /* Full-2.5K */ 269 rfa = 0x01; /* Full-1.5K */ 270 break; 271 272 default: 273 rfd = 0x07; /* Full-4.5K */ 274 rfa = 0x04; /* Full-3K */ 275 break; 276 } 277 278 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 279 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 280 281 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 282 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 283 } 284 285 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 286} 287 288static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 289 u32 channel, int fifosz, u8 qmode) 290{ 291 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 292 unsigned int tqs = fifosz / 256 - 1; 293 294 if (mode == SF_DMA_MODE) { 295 pr_debug("GMAC: enable TX store and forward mode\n"); 296 /* Transmit COE type 2 cannot be done in cut-through mode. */ 297 mtl_tx_op |= MTL_OP_MODE_TSF; 298 } else { 299 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 300 mtl_tx_op &= ~MTL_OP_MODE_TSF; 301 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 302 /* Set the transmit threshold */ 303 if (mode <= 32) 304 mtl_tx_op |= MTL_OP_MODE_TTC_32; 305 else if (mode <= 64) 306 mtl_tx_op |= MTL_OP_MODE_TTC_64; 307 else if (mode <= 96) 308 mtl_tx_op |= MTL_OP_MODE_TTC_96; 309 else if (mode <= 128) 310 mtl_tx_op |= MTL_OP_MODE_TTC_128; 311 else if (mode <= 192) 312 mtl_tx_op |= MTL_OP_MODE_TTC_192; 313 else if (mode <= 256) 314 mtl_tx_op |= MTL_OP_MODE_TTC_256; 315 else if (mode <= 384) 316 mtl_tx_op |= MTL_OP_MODE_TTC_384; 317 else 318 mtl_tx_op |= MTL_OP_MODE_TTC_512; 319 } 320 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 321 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 322 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 323 * with reset values: TXQEN off, TQS 256 bytes. 324 * 325 * TXQEN must be written for multi-channel operation and TQS must 326 * reflect the available fifo size per queue (total fifo size / number 327 * of enabled queues). 328 */ 329 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 330 if (qmode != MTL_QUEUE_AVB) 331 mtl_tx_op |= MTL_OP_MODE_TXQEN; 332 else 333 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 334 mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 335 mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 336 337 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 338} 339 340static int dwmac4_get_hw_feature(void __iomem *ioaddr, 341 struct dma_features *dma_cap) 342{ 343 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 344 345 /* MAC HW feature0 */ 346 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 347 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 348 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 349 dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 350 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 351 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 352 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 353 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 354 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 355 /* MMC */ 356 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 357 /* IEEE 1588-2008 */ 358 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 359 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 360 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 361 /* TX and RX csum */ 362 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 363 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 364 dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27; 365 dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9; 366 367 /* MAC HW feature1 */ 368 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 369 dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27; 370 dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; 371 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 372 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 373 dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17; 374 375 dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; 376 switch (dma_cap->addr64) { 377 case 0: 378 dma_cap->addr64 = 32; 379 break; 380 case 1: 381 dma_cap->addr64 = 40; 382 break; 383 case 2: 384 dma_cap->addr64 = 48; 385 break; 386 default: 387 dma_cap->addr64 = 32; 388 break; 389 } 390 391 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 392 * shifting and store the sizes in bytes. 393 */ 394 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 395 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 396 /* MAC HW feature2 */ 397 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 398 /* TX and RX number of channels */ 399 dma_cap->number_rx_channel = 400 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 401 dma_cap->number_tx_channel = 402 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 403 /* TX and RX number of queues */ 404 dma_cap->number_rx_queues = 405 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 406 dma_cap->number_tx_queues = 407 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 408 /* PPS output */ 409 dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 410 411 /* IEEE 1588-2002 */ 412 dma_cap->time_stamp = 0; 413 414 /* MAC HW feature3 */ 415 hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 416 417 /* 5.10 Features */ 418 dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 419 dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27; 420 dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26; 421 dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20; 422 dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17; 423 dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16; 424 dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 425 dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 426 dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 427 dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5; 428 429 return 0; 430} 431 432/* Enable/disable TSO feature and set MSS */ 433static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 434{ 435 u32 value; 436 437 if (en) { 438 /* enable TSO */ 439 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 440 writel(value | DMA_CONTROL_TSE, 441 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 442 } else { 443 /* enable TSO */ 444 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 445 writel(value & ~DMA_CONTROL_TSE, 446 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 447 } 448} 449 450static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 451{ 452 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 453 454 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 455 if (qmode != MTL_QUEUE_AVB) 456 mtl_tx_op |= MTL_OP_MODE_TXQEN; 457 else 458 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 459 460 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 461} 462 463static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 464{ 465 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 466 467 value &= ~DMA_RBSZ_MASK; 468 value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; 469 470 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 471} 472 473static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan) 474{ 475 u32 value = readl(ioaddr + GMAC_EXT_CONFIG); 476 477 value &= ~GMAC_CONFIG_HDSMS; 478 value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ 479 writel(value, ioaddr + GMAC_EXT_CONFIG); 480 481 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 482 if (en) 483 value |= DMA_CONTROL_SPH; 484 else 485 value &= ~DMA_CONTROL_SPH; 486 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 487} 488 489static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) 490{ 491 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 492 493 if (en) 494 value |= DMA_CONTROL_EDSE; 495 else 496 value &= ~DMA_CONTROL_EDSE; 497 498 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 499 500 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE; 501 if (en && !value) 502 return -EIO; 503 504 writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL); 505 return 0; 506} 507 508const struct stmmac_dma_ops dwmac4_dma_ops = { 509 .reset = dwmac4_dma_reset, 510 .init = dwmac4_dma_init, 511 .init_chan = dwmac4_dma_init_channel, 512 .init_rx_chan = dwmac4_dma_init_rx_chan, 513 .init_tx_chan = dwmac4_dma_init_tx_chan, 514 .axi = dwmac4_dma_axi, 515 .dump_regs = dwmac4_dump_dma_regs, 516 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 517 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 518 .enable_dma_irq = dwmac4_enable_dma_irq, 519 .disable_dma_irq = dwmac4_disable_dma_irq, 520 .start_tx = dwmac4_dma_start_tx, 521 .stop_tx = dwmac4_dma_stop_tx, 522 .start_rx = dwmac4_dma_start_rx, 523 .stop_rx = dwmac4_dma_stop_rx, 524 .dma_interrupt = dwmac4_dma_interrupt, 525 .get_hw_feature = dwmac4_get_hw_feature, 526 .rx_watchdog = dwmac4_rx_watchdog, 527 .set_rx_ring_len = dwmac4_set_rx_ring_len, 528 .set_tx_ring_len = dwmac4_set_tx_ring_len, 529 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 530 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 531 .enable_tso = dwmac4_enable_tso, 532 .qmode = dwmac4_qmode, 533 .set_bfsize = dwmac4_set_bfsize, 534 .enable_sph = dwmac4_enable_sph, 535}; 536 537const struct stmmac_dma_ops dwmac410_dma_ops = { 538 .reset = dwmac4_dma_reset, 539 .init = dwmac4_dma_init, 540 .init_chan = dwmac410_dma_init_channel, 541 .init_rx_chan = dwmac4_dma_init_rx_chan, 542 .init_tx_chan = dwmac4_dma_init_tx_chan, 543 .axi = dwmac4_dma_axi, 544 .dump_regs = dwmac4_dump_dma_regs, 545 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 546 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 547 .enable_dma_irq = dwmac410_enable_dma_irq, 548 .disable_dma_irq = dwmac4_disable_dma_irq, 549 .start_tx = dwmac4_dma_start_tx, 550 .stop_tx = dwmac4_dma_stop_tx, 551 .start_rx = dwmac4_dma_start_rx, 552 .stop_rx = dwmac4_dma_stop_rx, 553 .dma_interrupt = dwmac4_dma_interrupt, 554 .get_hw_feature = dwmac4_get_hw_feature, 555 .rx_watchdog = dwmac4_rx_watchdog, 556 .set_rx_ring_len = dwmac4_set_rx_ring_len, 557 .set_tx_ring_len = dwmac4_set_tx_ring_len, 558 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 559 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 560 .enable_tso = dwmac4_enable_tso, 561 .qmode = dwmac4_qmode, 562 .set_bfsize = dwmac4_set_bfsize, 563 .enable_sph = dwmac4_enable_sph, 564 .enable_tbs = dwmac4_enable_tbs, 565}; 566