1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * DWMAC4 Header file. 4 * 5 * Copyright (C) 2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10#ifndef __DWMAC4_H__ 11#define __DWMAC4_H__ 12 13#include "common.h" 14 15/* MAC registers */ 16#define GMAC_CONFIG 0x00000000 17#define GMAC_EXT_CONFIG 0x00000004 18#define GMAC_PACKET_FILTER 0x00000008 19#define GMAC_HASH_TAB(x) (0x10 + (x) * 4) 20#define GMAC_VLAN_TAG 0x00000050 21#define GMAC_VLAN_TAG_DATA 0x00000054 22#define GMAC_VLAN_HASH_TABLE 0x00000058 23#define GMAC_RX_FLOW_CTRL 0x00000090 24#define GMAC_VLAN_INCL 0x00000060 25#define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 26#define GMAC_TXQ_PRTY_MAP0 0x98 27#define GMAC_TXQ_PRTY_MAP1 0x9C 28#define GMAC_RXQ_CTRL0 0x000000a0 29#define GMAC_RXQ_CTRL1 0x000000a4 30#define GMAC_RXQ_CTRL2 0x000000a8 31#define GMAC_RXQ_CTRL3 0x000000ac 32#define GMAC_INT_STATUS 0x000000b0 33#define GMAC_INT_EN 0x000000b4 34#define GMAC_1US_TIC_COUNTER 0x000000dc 35#define GMAC_PCS_BASE 0x000000e0 36#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 37#define GMAC_PMT 0x000000c0 38#define GMAC_DEBUG 0x00000114 39#define GMAC_HW_FEATURE0 0x0000011c 40#define GMAC_HW_FEATURE1 0x00000120 41#define GMAC_HW_FEATURE2 0x00000124 42#define GMAC_HW_FEATURE3 0x00000128 43#define GMAC_MDIO_ADDR 0x00000200 44#define GMAC_MDIO_DATA 0x00000204 45#define GMAC_ARP_ADDR 0x00000210 46#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 47#define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 48#define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30) 49#define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30) 50#define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30) 51#define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30) 52 53/* RX Queues Routing */ 54#define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 55#define GMAC_RXQCTRL_AVCPQ_SHIFT 0 56#define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 57#define GMAC_RXQCTRL_PTPQ_SHIFT 4 58#define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 59#define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 60#define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 61#define GMAC_RXQCTRL_UPQ_SHIFT 12 62#define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 63#define GMAC_RXQCTRL_MCBCQ_SHIFT 16 64#define GMAC_RXQCTRL_MCBCQEN BIT(20) 65#define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 66#define GMAC_RXQCTRL_TACPQE BIT(21) 67#define GMAC_RXQCTRL_TACPQE_SHIFT 21 68#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24) 69#define GMAC_RXQCTRL_FPRQ_SHIFT 24 70 71/* MAC Packet Filtering */ 72#define GMAC_PACKET_FILTER_PR BIT(0) 73#define GMAC_PACKET_FILTER_HMC BIT(2) 74#define GMAC_PACKET_FILTER_PM BIT(4) 75#define GMAC_PACKET_FILTER_PCF BIT(7) 76#define GMAC_PACKET_FILTER_HPF BIT(10) 77#define GMAC_PACKET_FILTER_VTFE BIT(16) 78#define GMAC_PACKET_FILTER_IPFE BIT(20) 79#define GMAC_PACKET_FILTER_RA BIT(31) 80 81#define GMAC_MAX_PERFECT_ADDRESSES 128 82 83/* MAC VLAN */ 84#define GMAC_VLAN_EDVLP BIT(26) 85#define GMAC_VLAN_VTHM BIT(25) 86#define GMAC_VLAN_DOVLTC BIT(20) 87#define GMAC_VLAN_ESVL BIT(18) 88#define GMAC_VLAN_ETV BIT(16) 89#define GMAC_VLAN_VID GENMASK(15, 0) 90#define GMAC_VLAN_VLTI BIT(20) 91#define GMAC_VLAN_CSVL BIT(19) 92#define GMAC_VLAN_VLC GENMASK(17, 16) 93#define GMAC_VLAN_VLC_SHIFT 16 94#define GMAC_VLAN_VLHT GENMASK(15, 0) 95 96/* MAC VLAN Tag */ 97#define GMAC_VLAN_TAG_VID GENMASK(15, 0) 98#define GMAC_VLAN_TAG_ETV BIT(16) 99 100/* MAC VLAN Tag Control */ 101#define GMAC_VLAN_TAG_CTRL_OB BIT(0) 102#define GMAC_VLAN_TAG_CTRL_CT BIT(1) 103#define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2) 104#define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2 105#define GMAC_VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21) 106#define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT 21 107#define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24) 108 109#define GMAC_VLAN_TAG_STRIP_NONE (0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 110#define GMAC_VLAN_TAG_STRIP_PASS (0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 111#define GMAC_VLAN_TAG_STRIP_FAIL (0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 112#define GMAC_VLAN_TAG_STRIP_ALL (0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 113 114/* MAC VLAN Tag Data/Filter */ 115#define GMAC_VLAN_TAG_DATA_VID GENMASK(15, 0) 116#define GMAC_VLAN_TAG_DATA_VEN BIT(16) 117#define GMAC_VLAN_TAG_DATA_ETV BIT(17) 118 119/* MAC RX Queue Enable */ 120#define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 121#define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 122#define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 123 124/* MAC Flow Control RX */ 125#define GMAC_RX_FLOW_CTRL_RFE BIT(0) 126 127/* RX Queues Priorities */ 128#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 129#define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 130 131/* TX Queues Priorities */ 132#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 133#define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 134 135/* MAC Flow Control TX */ 136#define GMAC_TX_FLOW_CTRL_TFE BIT(1) 137#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 138 139/* MAC Interrupt bitmap*/ 140#define GMAC_INT_RGSMIIS BIT(0) 141#define GMAC_INT_PCS_LINK BIT(1) 142#define GMAC_INT_PCS_ANE BIT(2) 143#define GMAC_INT_PCS_PHYIS BIT(3) 144#define GMAC_INT_PMT_EN BIT(4) 145#define GMAC_INT_LPI_EN BIT(5) 146 147#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 148 GMAC_INT_PCS_ANE) 149 150#define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN) 151 152enum dwmac4_irq_status { 153 time_stamp_irq = 0x00001000, 154 mmc_rx_csum_offload_irq = 0x00000800, 155 mmc_tx_irq = 0x00000400, 156 mmc_rx_irq = 0x00000200, 157 mmc_irq = 0x00000100, 158 lpi_irq = 0x00000020, 159 pmt_irq = 0x00000010, 160}; 161 162/* MAC PMT bitmap */ 163enum power_event { 164 pointer_reset = 0x80000000, 165 global_unicast = 0x00000200, 166 wake_up_rx_frame = 0x00000040, 167 magic_frame = 0x00000020, 168 wake_up_frame_en = 0x00000004, 169 magic_pkt_en = 0x00000002, 170 power_down = 0x00000001, 171}; 172 173/* Energy Efficient Ethernet (EEE) for GMAC4 174 * 175 * LPI status, timer and control register offset 176 */ 177#define GMAC4_LPI_CTRL_STATUS 0xd0 178#define GMAC4_LPI_TIMER_CTRL 0xd4 179 180/* LPI control and status defines */ 181#define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */ 182#define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 183#define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 184#define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 185#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 186#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 187#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 188#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 189 190/* MAC Debug bitmap */ 191#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 192#define GMAC_DEBUG_TFCSTS_SHIFT 17 193#define GMAC_DEBUG_TFCSTS_IDLE 0 194#define GMAC_DEBUG_TFCSTS_WAIT 1 195#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 196#define GMAC_DEBUG_TFCSTS_XFER 3 197#define GMAC_DEBUG_TPESTS BIT(16) 198#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 199#define GMAC_DEBUG_RFCFCSTS_SHIFT 1 200#define GMAC_DEBUG_RPESTS BIT(0) 201 202/* MAC config */ 203#define GMAC_CONFIG_ARPEN BIT(31) 204#define GMAC_CONFIG_SARC GENMASK(30, 28) 205#define GMAC_CONFIG_SARC_SHIFT 28 206#define GMAC_CONFIG_IPC BIT(27) 207#define GMAC_CONFIG_IPG GENMASK(26, 24) 208#define GMAC_CONFIG_IPG_SHIFT 24 209#define GMAC_CONFIG_2K BIT(22) 210#define GMAC_CONFIG_ACS BIT(20) 211#define GMAC_CONFIG_BE BIT(18) 212#define GMAC_CONFIG_JD BIT(17) 213#define GMAC_CONFIG_JE BIT(16) 214#define GMAC_CONFIG_PS BIT(15) 215#define GMAC_CONFIG_FES BIT(14) 216#define GMAC_CONFIG_FES_SHIFT 14 217#define GMAC_CONFIG_DM BIT(13) 218#define GMAC_CONFIG_LM BIT(12) 219#define GMAC_CONFIG_DCRS BIT(9) 220#define GMAC_CONFIG_TE BIT(1) 221#define GMAC_CONFIG_RE BIT(0) 222 223/* MAC extended config */ 224#define GMAC_CONFIG_EIPG GENMASK(29, 25) 225#define GMAC_CONFIG_EIPG_SHIFT 25 226#define GMAC_CONFIG_EIPG_EN BIT(24) 227#define GMAC_CONFIG_HDSMS GENMASK(22, 20) 228#define GMAC_CONFIG_HDSMS_SHIFT 20 229#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT) 230 231/* MAC HW features0 bitmap */ 232#define GMAC_HW_FEAT_SAVLANINS BIT(27) 233#define GMAC_HW_FEAT_ADDMAC BIT(18) 234#define GMAC_HW_FEAT_RXCOESEL BIT(16) 235#define GMAC_HW_FEAT_TXCOSEL BIT(14) 236#define GMAC_HW_FEAT_EEESEL BIT(13) 237#define GMAC_HW_FEAT_TSSEL BIT(12) 238#define GMAC_HW_FEAT_ARPOFFSEL BIT(9) 239#define GMAC_HW_FEAT_MMCSEL BIT(8) 240#define GMAC_HW_FEAT_MGKSEL BIT(7) 241#define GMAC_HW_FEAT_RWKSEL BIT(6) 242#define GMAC_HW_FEAT_SMASEL BIT(5) 243#define GMAC_HW_FEAT_VLHASH BIT(4) 244#define GMAC_HW_FEAT_PCSSEL BIT(3) 245#define GMAC_HW_FEAT_HDSEL BIT(2) 246#define GMAC_HW_FEAT_GMIISEL BIT(1) 247#define GMAC_HW_FEAT_MIISEL BIT(0) 248 249/* MAC HW features1 bitmap */ 250#define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27) 251#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) 252#define GMAC_HW_FEAT_AVSEL BIT(20) 253#define GMAC_HW_TSOEN BIT(18) 254#define GMAC_HW_FEAT_SPHEN BIT(17) 255#define GMAC_HW_ADDR64 GENMASK(15, 14) 256#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 257#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 258 259/* MAC HW features2 bitmap */ 260#define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24) 261#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 262#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 263#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 264#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 265 266/* MAC HW features3 bitmap */ 267#define GMAC_HW_FEAT_ASP GENMASK(29, 28) 268#define GMAC_HW_FEAT_TBSSEL BIT(27) 269#define GMAC_HW_FEAT_FPESEL BIT(26) 270#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20) 271#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17) 272#define GMAC_HW_FEAT_ESTSEL BIT(16) 273#define GMAC_HW_FEAT_FRPES GENMASK(14, 13) 274#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11) 275#define GMAC_HW_FEAT_FRPSEL BIT(10) 276#define GMAC_HW_FEAT_DVLAN BIT(5) 277#define GMAC_HW_FEAT_NRVF GENMASK(2, 0) 278 279/* MAC HW ADDR regs */ 280#define GMAC_HI_DCS GENMASK(18, 16) 281#define GMAC_HI_DCS_SHIFT 16 282#define GMAC_HI_REG_AE BIT(31) 283 284/* L3/L4 Filters regs */ 285#define GMAC_L4DPIM0 BIT(21) 286#define GMAC_L4DPM0 BIT(20) 287#define GMAC_L4SPIM0 BIT(19) 288#define GMAC_L4SPM0 BIT(18) 289#define GMAC_L4PEN0 BIT(16) 290#define GMAC_L3DAIM0 BIT(5) 291#define GMAC_L3DAM0 BIT(4) 292#define GMAC_L3SAIM0 BIT(3) 293#define GMAC_L3SAM0 BIT(2) 294#define GMAC_L3PEN0 BIT(0) 295#define GMAC_L4DP0 GENMASK(31, 16) 296#define GMAC_L4DP0_SHIFT 16 297#define GMAC_L4SP0 GENMASK(15, 0) 298 299/* MTL registers */ 300#define MTL_OPERATION_MODE 0x00000c00 301#define MTL_FRPE BIT(15) 302#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 303#define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 304#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 305#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 306#define MTL_OPERATION_SCHALG_SP (0x3 << 5) 307#define MTL_OPERATION_RAA BIT(2) 308#define MTL_OPERATION_RAA_SP (0x0 << 2) 309#define MTL_OPERATION_RAA_WSP (0x1 << 2) 310 311#define MTL_INT_STATUS 0x00000c20 312#define MTL_INT_QX(x) BIT(x) 313 314#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 315#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 316#define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0) 317#define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0) 318#define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x)) 319#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 320 321#define MTL_CHAN_BASE_ADDR 0x00000d00 322#define MTL_CHAN_BASE_OFFSET 0x40 323#define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 324 (x * MTL_CHAN_BASE_OFFSET)) 325 326#define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 327#define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 328#define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 329#define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 330#define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 331 332#define MTL_OP_MODE_RSF BIT(5) 333#define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 334#define MTL_OP_MODE_TXQEN_AV BIT(2) 335#define MTL_OP_MODE_TXQEN BIT(3) 336#define MTL_OP_MODE_TSF BIT(1) 337 338#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 339#define MTL_OP_MODE_TQS_SHIFT 16 340 341#define MTL_OP_MODE_TTC_MASK 0x70 342#define MTL_OP_MODE_TTC_SHIFT 4 343 344#define MTL_OP_MODE_TTC_32 0 345#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 346#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 347#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 348#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 349#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 350#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 351#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 352 353#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 354#define MTL_OP_MODE_RQS_SHIFT 20 355 356#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 357#define MTL_OP_MODE_RFD_SHIFT 14 358 359#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 360#define MTL_OP_MODE_RFA_SHIFT 8 361 362#define MTL_OP_MODE_EHFC BIT(7) 363 364#define MTL_OP_MODE_RTC_MASK 0x18 365#define MTL_OP_MODE_RTC_SHIFT 3 366 367#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 368#define MTL_OP_MODE_RTC_64 0 369#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 370#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 371 372/* MTL ETS Control register */ 373#define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 374#define MTL_ETS_CTRL_BASE_OFFSET 0x40 375#define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \ 376 ((x) * MTL_ETS_CTRL_BASE_OFFSET)) 377 378#define MTL_ETS_CTRL_CC BIT(3) 379#define MTL_ETS_CTRL_AVALG BIT(2) 380 381/* MTL Queue Quantum Weight */ 382#define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 383#define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 384#define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \ 385 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET)) 386#define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 387 388/* MTL sendSlopeCredit register */ 389#define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 390#define MTL_SEND_SLP_CRED_OFFSET 0x40 391#define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \ 392 ((x) * MTL_SEND_SLP_CRED_OFFSET)) 393 394#define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 395 396/* MTL hiCredit register */ 397#define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 398#define MTL_HIGH_CRED_OFFSET 0x40 399#define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \ 400 ((x) * MTL_HIGH_CRED_OFFSET)) 401 402#define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 403 404/* MTL loCredit register */ 405#define MTL_LOW_CRED_BASE_ADDR 0x00000d24 406#define MTL_LOW_CRED_OFFSET 0x40 407#define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \ 408 ((x) * MTL_LOW_CRED_OFFSET)) 409 410#define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 411 412/* MTL debug */ 413#define MTL_DEBUG_TXSTSFSTS BIT(5) 414#define MTL_DEBUG_TXFSTS BIT(4) 415#define MTL_DEBUG_TWCSTS BIT(3) 416 417/* MTL debug: Tx FIFO Read Controller Status */ 418#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 419#define MTL_DEBUG_TRCSTS_SHIFT 1 420#define MTL_DEBUG_TRCSTS_IDLE 0 421#define MTL_DEBUG_TRCSTS_READ 1 422#define MTL_DEBUG_TRCSTS_TXW 2 423#define MTL_DEBUG_TRCSTS_WRITE 3 424#define MTL_DEBUG_TXPAUSED BIT(0) 425 426/* MAC debug: GMII or MII Transmit Protocol Engine Status */ 427#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 428#define MTL_DEBUG_RXFSTS_SHIFT 4 429#define MTL_DEBUG_RXFSTS_EMPTY 0 430#define MTL_DEBUG_RXFSTS_BT 1 431#define MTL_DEBUG_RXFSTS_AT 2 432#define MTL_DEBUG_RXFSTS_FULL 3 433#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 434#define MTL_DEBUG_RRCSTS_SHIFT 1 435#define MTL_DEBUG_RRCSTS_IDLE 0 436#define MTL_DEBUG_RRCSTS_RDATA 1 437#define MTL_DEBUG_RRCSTS_RSTAT 2 438#define MTL_DEBUG_RRCSTS_FLUSH 3 439#define MTL_DEBUG_RWCSTS BIT(0) 440 441/* MTL interrupt */ 442#define MTL_RX_OVERFLOW_INT_EN BIT(24) 443#define MTL_RX_OVERFLOW_INT BIT(16) 444 445/* Default operating mode of the MAC */ 446#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 447 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \ 448 GMAC_CONFIG_JE) 449 450/* To dump the core regs excluding the Address Registers */ 451#define GMAC_REG_NUM 132 452 453/* MTL debug */ 454#define MTL_DEBUG_TXSTSFSTS BIT(5) 455#define MTL_DEBUG_TXFSTS BIT(4) 456#define MTL_DEBUG_TWCSTS BIT(3) 457 458/* MTL debug: Tx FIFO Read Controller Status */ 459#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 460#define MTL_DEBUG_TRCSTS_SHIFT 1 461#define MTL_DEBUG_TRCSTS_IDLE 0 462#define MTL_DEBUG_TRCSTS_READ 1 463#define MTL_DEBUG_TRCSTS_TXW 2 464#define MTL_DEBUG_TRCSTS_WRITE 3 465#define MTL_DEBUG_TXPAUSED BIT(0) 466 467/* MAC debug: GMII or MII Transmit Protocol Engine Status */ 468#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 469#define MTL_DEBUG_RXFSTS_SHIFT 4 470#define MTL_DEBUG_RXFSTS_EMPTY 0 471#define MTL_DEBUG_RXFSTS_BT 1 472#define MTL_DEBUG_RXFSTS_AT 2 473#define MTL_DEBUG_RXFSTS_FULL 3 474#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 475#define MTL_DEBUG_RRCSTS_SHIFT 1 476#define MTL_DEBUG_RRCSTS_IDLE 0 477#define MTL_DEBUG_RRCSTS_RDATA 1 478#define MTL_DEBUG_RRCSTS_RSTAT 2 479#define MTL_DEBUG_RRCSTS_FLUSH 3 480#define MTL_DEBUG_RWCSTS BIT(0) 481 482/* SGMII/RGMII status register */ 483#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 484#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 485#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 486#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 487#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 488#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 489#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 490#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 491#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 492/* LNKMOD */ 493#define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 494/* LNKSPEED */ 495#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 496#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 497#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 498 499extern const struct stmmac_dma_ops dwmac4_dma_ops; 500extern const struct stmmac_dma_ops dwmac410_dma_ops; 501#endif /* __DWMAC4_H__ */ 502