1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8#include <linux/clk.h> 9#include <linux/io.h> 10#include <linux/iopoll.h> 11#include <linux/mdio-mux.h> 12#include <linux/mfd/syscon.h> 13#include <linux/module.h> 14#include <linux/of_device.h> 15#include <linux/of_mdio.h> 16#include <linux/of_net.h> 17#include <linux/phy.h> 18#include <linux/platform_device.h> 19#include <linux/regulator/consumer.h> 20#include <linux/regmap.h> 21#include <linux/stmmac.h> 22 23#include "stmmac.h" 24#include "stmmac_platform.h" 25 26/* General notes on dwmac-sun8i: 27 * Locking: no locking is necessary in this file because all necessary locking 28 * is done in the "stmmac files" 29 */ 30 31/* struct emac_variant - Describe dwmac-sun8i hardware variant 32 * @default_syscon_value: The default value of the EMAC register in syscon 33 * This value is used for disabling properly EMAC 34 * and used as a good starting value in case of the 35 * boot process(uboot) leave some stuff. 36 * @syscon_field reg_field for the syscon's gmac register 37 * @soc_has_internal_phy: Does the MAC embed an internal PHY 38 * @support_mii: Does the MAC handle MII 39 * @support_rmii: Does the MAC handle RMII 40 * @support_rgmii: Does the MAC handle RGMII 41 * 42 * @rx_delay_max: Maximum raw value for RX delay chain 43 * @tx_delay_max: Maximum raw value for TX delay chain 44 * These two also indicate the bitmask for 45 * the RX and TX delay chain registers. A 46 * value of zero indicates this is not supported. 47 */ 48struct emac_variant { 49 u32 default_syscon_value; 50 const struct reg_field *syscon_field; 51 bool soc_has_internal_phy; 52 bool support_mii; 53 bool support_rmii; 54 bool support_rgmii; 55 u8 rx_delay_max; 56 u8 tx_delay_max; 57}; 58 59/* struct sunxi_priv_data - hold all sunxi private data 60 * @tx_clk: reference to MAC TX clock 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @use_internal_phy: Is the internal PHY selected for use 68 * @mux_handle: Internal pointer used by mdio-mux lib 69 */ 70struct sunxi_priv_data { 71 struct clk *tx_clk; 72 struct clk *ephy_clk; 73 struct regulator *regulator; 74 struct reset_control *rst_ephy; 75 const struct emac_variant *variant; 76 struct regmap_field *regmap_field; 77 bool internal_phy_powered; 78 bool use_internal_phy; 79 void *mux_handle; 80}; 81 82/* EMAC clock register @ 0x30 in the "system control" address range */ 83static const struct reg_field sun8i_syscon_reg_field = { 84 .reg = 0x30, 85 .lsb = 0, 86 .msb = 31, 87}; 88 89/* EMAC clock register @ 0x164 in the CCU address range */ 90static const struct reg_field sun8i_ccu_reg_field = { 91 .reg = 0x164, 92 .lsb = 0, 93 .msb = 31, 94}; 95 96static const struct emac_variant emac_variant_h3 = { 97 .default_syscon_value = 0x58000, 98 .syscon_field = &sun8i_syscon_reg_field, 99 .soc_has_internal_phy = true, 100 .support_mii = true, 101 .support_rmii = true, 102 .support_rgmii = true, 103 .rx_delay_max = 31, 104 .tx_delay_max = 7, 105}; 106 107static const struct emac_variant emac_variant_v3s = { 108 .default_syscon_value = 0x38000, 109 .syscon_field = &sun8i_syscon_reg_field, 110 .soc_has_internal_phy = true, 111 .support_mii = true 112}; 113 114static const struct emac_variant emac_variant_a83t = { 115 .default_syscon_value = 0, 116 .syscon_field = &sun8i_syscon_reg_field, 117 .soc_has_internal_phy = false, 118 .support_mii = true, 119 .support_rgmii = true, 120 .rx_delay_max = 31, 121 .tx_delay_max = 7, 122}; 123 124static const struct emac_variant emac_variant_r40 = { 125 .default_syscon_value = 0, 126 .syscon_field = &sun8i_ccu_reg_field, 127 .support_mii = true, 128 .support_rgmii = true, 129 .rx_delay_max = 7, 130}; 131 132static const struct emac_variant emac_variant_a64 = { 133 .default_syscon_value = 0, 134 .syscon_field = &sun8i_syscon_reg_field, 135 .soc_has_internal_phy = false, 136 .support_mii = true, 137 .support_rmii = true, 138 .support_rgmii = true, 139 .rx_delay_max = 31, 140 .tx_delay_max = 7, 141}; 142 143static const struct emac_variant emac_variant_h6 = { 144 .default_syscon_value = 0x50000, 145 .syscon_field = &sun8i_syscon_reg_field, 146 /* The "Internal PHY" of H6 is not on the die. It's on the 147 * co-packaged AC200 chip instead. 148 */ 149 .soc_has_internal_phy = false, 150 .support_mii = true, 151 .support_rmii = true, 152 .support_rgmii = true, 153 .rx_delay_max = 31, 154 .tx_delay_max = 7, 155}; 156 157#define EMAC_BASIC_CTL0 0x00 158#define EMAC_BASIC_CTL1 0x04 159#define EMAC_INT_STA 0x08 160#define EMAC_INT_EN 0x0C 161#define EMAC_TX_CTL0 0x10 162#define EMAC_TX_CTL1 0x14 163#define EMAC_TX_FLOW_CTL 0x1C 164#define EMAC_TX_DESC_LIST 0x20 165#define EMAC_RX_CTL0 0x24 166#define EMAC_RX_CTL1 0x28 167#define EMAC_RX_DESC_LIST 0x34 168#define EMAC_RX_FRM_FLT 0x38 169#define EMAC_MDIO_CMD 0x48 170#define EMAC_MDIO_DATA 0x4C 171#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 172#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 173#define EMAC_TX_DMA_STA 0xB0 174#define EMAC_TX_CUR_DESC 0xB4 175#define EMAC_TX_CUR_BUF 0xB8 176#define EMAC_RX_DMA_STA 0xC0 177#define EMAC_RX_CUR_DESC 0xC4 178#define EMAC_RX_CUR_BUF 0xC8 179 180/* Use in EMAC_BASIC_CTL0 */ 181#define EMAC_DUPLEX_FULL BIT(0) 182#define EMAC_LOOPBACK BIT(1) 183#define EMAC_SPEED_1000 0 184#define EMAC_SPEED_100 (0x03 << 2) 185#define EMAC_SPEED_10 (0x02 << 2) 186 187/* Use in EMAC_BASIC_CTL1 */ 188#define EMAC_BURSTLEN_SHIFT 24 189 190/* Used in EMAC_RX_FRM_FLT */ 191#define EMAC_FRM_FLT_RXALL BIT(0) 192#define EMAC_FRM_FLT_CTL BIT(13) 193#define EMAC_FRM_FLT_MULTICAST BIT(16) 194 195/* Used in RX_CTL1*/ 196#define EMAC_RX_MD BIT(1) 197#define EMAC_RX_TH_MASK GENMASK(5, 4) 198#define EMAC_RX_TH_32 0 199#define EMAC_RX_TH_64 (0x1 << 4) 200#define EMAC_RX_TH_96 (0x2 << 4) 201#define EMAC_RX_TH_128 (0x3 << 4) 202#define EMAC_RX_DMA_EN BIT(30) 203#define EMAC_RX_DMA_START BIT(31) 204 205/* Used in TX_CTL1*/ 206#define EMAC_TX_MD BIT(1) 207#define EMAC_TX_NEXT_FRM BIT(2) 208#define EMAC_TX_TH_MASK GENMASK(10, 8) 209#define EMAC_TX_TH_64 0 210#define EMAC_TX_TH_128 (0x1 << 8) 211#define EMAC_TX_TH_192 (0x2 << 8) 212#define EMAC_TX_TH_256 (0x3 << 8) 213#define EMAC_TX_DMA_EN BIT(30) 214#define EMAC_TX_DMA_START BIT(31) 215 216/* Used in RX_CTL0 */ 217#define EMAC_RX_RECEIVER_EN BIT(31) 218#define EMAC_RX_DO_CRC BIT(27) 219#define EMAC_RX_FLOW_CTL_EN BIT(16) 220 221/* Used in TX_CTL0 */ 222#define EMAC_TX_TRANSMITTER_EN BIT(31) 223 224/* Used in EMAC_TX_FLOW_CTL */ 225#define EMAC_TX_FLOW_CTL_EN BIT(0) 226 227/* Used in EMAC_INT_STA */ 228#define EMAC_TX_INT BIT(0) 229#define EMAC_TX_DMA_STOP_INT BIT(1) 230#define EMAC_TX_BUF_UA_INT BIT(2) 231#define EMAC_TX_TIMEOUT_INT BIT(3) 232#define EMAC_TX_UNDERFLOW_INT BIT(4) 233#define EMAC_TX_EARLY_INT BIT(5) 234#define EMAC_RX_INT BIT(8) 235#define EMAC_RX_BUF_UA_INT BIT(9) 236#define EMAC_RX_DMA_STOP_INT BIT(10) 237#define EMAC_RX_TIMEOUT_INT BIT(11) 238#define EMAC_RX_OVERFLOW_INT BIT(12) 239#define EMAC_RX_EARLY_INT BIT(13) 240#define EMAC_RGMII_STA_INT BIT(16) 241 242#define MAC_ADDR_TYPE_DST BIT(31) 243 244/* H3 specific bits for EPHY */ 245#define H3_EPHY_ADDR_SHIFT 20 246#define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 247#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 248#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 249#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 250#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 251#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 252#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 253 254/* H3/A64 specific bits */ 255#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 256 257/* Generic system control EMAC_CLK bits */ 258#define SYSCON_ETXDC_SHIFT 10 259#define SYSCON_ERXDC_SHIFT 5 260/* EMAC PHY Interface Type */ 261#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 262#define SYSCON_ETCS_MASK GENMASK(1, 0) 263#define SYSCON_ETCS_MII 0x0 264#define SYSCON_ETCS_EXT_GMII 0x1 265#define SYSCON_ETCS_INT_GMII 0x2 266 267/* sun8i_dwmac_dma_reset() - reset the EMAC 268 * Called from stmmac via stmmac_dma_ops->reset 269 */ 270static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 271{ 272 writel(0, ioaddr + EMAC_RX_CTL1); 273 writel(0, ioaddr + EMAC_TX_CTL1); 274 writel(0, ioaddr + EMAC_RX_FRM_FLT); 275 writel(0, ioaddr + EMAC_RX_DESC_LIST); 276 writel(0, ioaddr + EMAC_TX_DESC_LIST); 277 writel(0, ioaddr + EMAC_INT_EN); 278 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 279 return 0; 280} 281 282/* sun8i_dwmac_dma_init() - initialize the EMAC 283 * Called from stmmac via stmmac_dma_ops->init 284 */ 285static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 286 struct stmmac_dma_cfg *dma_cfg, int atds) 287{ 288 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 289 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 290} 291 292static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 293 struct stmmac_dma_cfg *dma_cfg, 294 dma_addr_t dma_rx_phy, u32 chan) 295{ 296 /* Write RX descriptors address */ 297 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 298} 299 300static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 301 struct stmmac_dma_cfg *dma_cfg, 302 dma_addr_t dma_tx_phy, u32 chan) 303{ 304 /* Write TX descriptors address */ 305 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 306} 307 308/* sun8i_dwmac_dump_regs() - Dump EMAC address space 309 * Called from stmmac_dma_ops->dump_regs 310 * Used for ethtool 311 */ 312static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 313{ 314 int i; 315 316 for (i = 0; i < 0xC8; i += 4) { 317 if (i == 0x32 || i == 0x3C) 318 continue; 319 reg_space[i / 4] = readl(ioaddr + i); 320 } 321} 322 323/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 324 * Called from stmmac_ops->dump_regs 325 * Used for ethtool 326 */ 327static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 328 u32 *reg_space) 329{ 330 int i; 331 void __iomem *ioaddr = hw->pcsr; 332 333 for (i = 0; i < 0xC8; i += 4) { 334 if (i == 0x32 || i == 0x3C) 335 continue; 336 reg_space[i / 4] = readl(ioaddr + i); 337 } 338} 339 340static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, 341 bool rx, bool tx) 342{ 343 u32 value = readl(ioaddr + EMAC_INT_EN); 344 345 if (rx) 346 value |= EMAC_RX_INT; 347 if (tx) 348 value |= EMAC_TX_INT; 349 350 writel(value, ioaddr + EMAC_INT_EN); 351} 352 353static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, 354 bool rx, bool tx) 355{ 356 u32 value = readl(ioaddr + EMAC_INT_EN); 357 358 if (rx) 359 value &= ~EMAC_RX_INT; 360 if (tx) 361 value &= ~EMAC_TX_INT; 362 363 writel(value, ioaddr + EMAC_INT_EN); 364} 365 366static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 367{ 368 u32 v; 369 370 v = readl(ioaddr + EMAC_TX_CTL1); 371 v |= EMAC_TX_DMA_START; 372 v |= EMAC_TX_DMA_EN; 373 writel(v, ioaddr + EMAC_TX_CTL1); 374} 375 376static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 377{ 378 u32 v; 379 380 v = readl(ioaddr + EMAC_TX_CTL1); 381 v |= EMAC_TX_DMA_START; 382 v |= EMAC_TX_DMA_EN; 383 writel(v, ioaddr + EMAC_TX_CTL1); 384} 385 386static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 387{ 388 u32 v; 389 390 v = readl(ioaddr + EMAC_TX_CTL1); 391 v &= ~EMAC_TX_DMA_EN; 392 writel(v, ioaddr + EMAC_TX_CTL1); 393} 394 395static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 396{ 397 u32 v; 398 399 v = readl(ioaddr + EMAC_RX_CTL1); 400 v |= EMAC_RX_DMA_START; 401 v |= EMAC_RX_DMA_EN; 402 writel(v, ioaddr + EMAC_RX_CTL1); 403} 404 405static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 406{ 407 u32 v; 408 409 v = readl(ioaddr + EMAC_RX_CTL1); 410 v &= ~EMAC_RX_DMA_EN; 411 writel(v, ioaddr + EMAC_RX_CTL1); 412} 413 414static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 415 struct stmmac_extra_stats *x, u32 chan) 416{ 417 u32 v; 418 int ret = 0; 419 420 v = readl(ioaddr + EMAC_INT_STA); 421 422 if (v & EMAC_TX_INT) { 423 ret |= handle_tx; 424 x->tx_normal_irq_n++; 425 } 426 427 if (v & EMAC_TX_DMA_STOP_INT) 428 x->tx_process_stopped_irq++; 429 430 if (v & EMAC_TX_BUF_UA_INT) 431 x->tx_process_stopped_irq++; 432 433 if (v & EMAC_TX_TIMEOUT_INT) 434 ret |= tx_hard_error; 435 436 if (v & EMAC_TX_UNDERFLOW_INT) { 437 ret |= tx_hard_error; 438 x->tx_undeflow_irq++; 439 } 440 441 if (v & EMAC_TX_EARLY_INT) 442 x->tx_early_irq++; 443 444 if (v & EMAC_RX_INT) { 445 ret |= handle_rx; 446 x->rx_normal_irq_n++; 447 } 448 449 if (v & EMAC_RX_BUF_UA_INT) 450 x->rx_buf_unav_irq++; 451 452 if (v & EMAC_RX_DMA_STOP_INT) 453 x->rx_process_stopped_irq++; 454 455 if (v & EMAC_RX_TIMEOUT_INT) 456 ret |= tx_hard_error; 457 458 if (v & EMAC_RX_OVERFLOW_INT) { 459 ret |= tx_hard_error; 460 x->rx_overflow_irq++; 461 } 462 463 if (v & EMAC_RX_EARLY_INT) 464 x->rx_early_irq++; 465 466 if (v & EMAC_RGMII_STA_INT) 467 x->irq_rgmii_n++; 468 469 writel(v, ioaddr + EMAC_INT_STA); 470 471 return ret; 472} 473 474static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 475 u32 channel, int fifosz, u8 qmode) 476{ 477 u32 v; 478 479 v = readl(ioaddr + EMAC_RX_CTL1); 480 if (mode == SF_DMA_MODE) { 481 v |= EMAC_RX_MD; 482 } else { 483 v &= ~EMAC_RX_MD; 484 v &= ~EMAC_RX_TH_MASK; 485 if (mode < 32) 486 v |= EMAC_RX_TH_32; 487 else if (mode < 64) 488 v |= EMAC_RX_TH_64; 489 else if (mode < 96) 490 v |= EMAC_RX_TH_96; 491 else if (mode < 128) 492 v |= EMAC_RX_TH_128; 493 } 494 writel(v, ioaddr + EMAC_RX_CTL1); 495} 496 497static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 498 u32 channel, int fifosz, u8 qmode) 499{ 500 u32 v; 501 502 v = readl(ioaddr + EMAC_TX_CTL1); 503 if (mode == SF_DMA_MODE) { 504 v |= EMAC_TX_MD; 505 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 506 * comment is 507 * "Operating on second frame increase the performance 508 * especially when transmit store-and-forward is used." 509 */ 510 v |= EMAC_TX_NEXT_FRM; 511 } else { 512 v &= ~EMAC_TX_MD; 513 v &= ~EMAC_TX_TH_MASK; 514 if (mode < 64) 515 v |= EMAC_TX_TH_64; 516 else if (mode < 128) 517 v |= EMAC_TX_TH_128; 518 else if (mode < 192) 519 v |= EMAC_TX_TH_192; 520 else if (mode < 256) 521 v |= EMAC_TX_TH_256; 522 } 523 writel(v, ioaddr + EMAC_TX_CTL1); 524} 525 526static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 527 .reset = sun8i_dwmac_dma_reset, 528 .init = sun8i_dwmac_dma_init, 529 .init_rx_chan = sun8i_dwmac_dma_init_rx, 530 .init_tx_chan = sun8i_dwmac_dma_init_tx, 531 .dump_regs = sun8i_dwmac_dump_regs, 532 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 533 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 534 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 535 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 536 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 537 .start_tx = sun8i_dwmac_dma_start_tx, 538 .stop_tx = sun8i_dwmac_dma_stop_tx, 539 .start_rx = sun8i_dwmac_dma_start_rx, 540 .stop_rx = sun8i_dwmac_dma_stop_rx, 541 .dma_interrupt = sun8i_dwmac_dma_interrupt, 542}; 543 544static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); 545 546static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 547{ 548 struct net_device *ndev = platform_get_drvdata(pdev); 549 struct sunxi_priv_data *gmac = priv; 550 int ret; 551 552 if (gmac->regulator) { 553 ret = regulator_enable(gmac->regulator); 554 if (ret) { 555 dev_err(&pdev->dev, "Fail to enable regulator\n"); 556 return ret; 557 } 558 } 559 560 ret = clk_prepare_enable(gmac->tx_clk); 561 if (ret) { 562 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 563 goto err_disable_regulator; 564 } 565 566 if (gmac->use_internal_phy) { 567 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); 568 if (ret) 569 goto err_disable_clk; 570 } 571 572 return 0; 573 574err_disable_clk: 575 clk_disable_unprepare(gmac->tx_clk); 576err_disable_regulator: 577 if (gmac->regulator) 578 regulator_disable(gmac->regulator); 579 580 return ret; 581} 582 583static void sun8i_dwmac_core_init(struct mac_device_info *hw, 584 struct net_device *dev) 585{ 586 void __iomem *ioaddr = hw->pcsr; 587 u32 v; 588 589 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 590 writel(v, ioaddr + EMAC_BASIC_CTL1); 591} 592 593static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 594{ 595 u32 t, r; 596 597 t = readl(ioaddr + EMAC_TX_CTL0); 598 r = readl(ioaddr + EMAC_RX_CTL0); 599 if (enable) { 600 t |= EMAC_TX_TRANSMITTER_EN; 601 r |= EMAC_RX_RECEIVER_EN; 602 } else { 603 t &= ~EMAC_TX_TRANSMITTER_EN; 604 r &= ~EMAC_RX_RECEIVER_EN; 605 } 606 writel(t, ioaddr + EMAC_TX_CTL0); 607 writel(r, ioaddr + EMAC_RX_CTL0); 608} 609 610/* Set MAC address at slot reg_n 611 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 612 * If addr is NULL, clear the slot 613 */ 614static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 615 unsigned char *addr, 616 unsigned int reg_n) 617{ 618 void __iomem *ioaddr = hw->pcsr; 619 u32 v; 620 621 if (!addr) { 622 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 623 return; 624 } 625 626 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 627 EMAC_MACADDR_LO(reg_n)); 628 if (reg_n > 0) { 629 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 630 v |= MAC_ADDR_TYPE_DST; 631 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 632 } 633} 634 635static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 636 unsigned char *addr, 637 unsigned int reg_n) 638{ 639 void __iomem *ioaddr = hw->pcsr; 640 641 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 642 EMAC_MACADDR_LO(reg_n)); 643} 644 645/* caution this function must return non 0 to work */ 646static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 647{ 648 void __iomem *ioaddr = hw->pcsr; 649 u32 v; 650 651 v = readl(ioaddr + EMAC_RX_CTL0); 652 v |= EMAC_RX_DO_CRC; 653 writel(v, ioaddr + EMAC_RX_CTL0); 654 655 return 1; 656} 657 658static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 659 struct net_device *dev) 660{ 661 void __iomem *ioaddr = hw->pcsr; 662 u32 v; 663 int i = 1; 664 struct netdev_hw_addr *ha; 665 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 666 667 v = EMAC_FRM_FLT_CTL; 668 669 if (dev->flags & IFF_PROMISC) { 670 v = EMAC_FRM_FLT_RXALL; 671 } else if (dev->flags & IFF_ALLMULTI) { 672 v |= EMAC_FRM_FLT_MULTICAST; 673 } else if (macaddrs <= hw->unicast_filter_entries) { 674 if (!netdev_mc_empty(dev)) { 675 netdev_for_each_mc_addr(ha, dev) { 676 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 677 i++; 678 } 679 } 680 if (!netdev_uc_empty(dev)) { 681 netdev_for_each_uc_addr(ha, dev) { 682 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 683 i++; 684 } 685 } 686 } else { 687 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 688 netdev_info(dev, "Too many address, switching to promiscuous\n"); 689 v = EMAC_FRM_FLT_RXALL; 690 } 691 692 /* Disable unused address filter slots */ 693 while (i < hw->unicast_filter_entries) 694 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 695 696 writel(v, ioaddr + EMAC_RX_FRM_FLT); 697} 698 699static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 700 unsigned int duplex, unsigned int fc, 701 unsigned int pause_time, u32 tx_cnt) 702{ 703 void __iomem *ioaddr = hw->pcsr; 704 u32 v; 705 706 v = readl(ioaddr + EMAC_RX_CTL0); 707 if (fc == FLOW_AUTO) 708 v |= EMAC_RX_FLOW_CTL_EN; 709 else 710 v &= ~EMAC_RX_FLOW_CTL_EN; 711 writel(v, ioaddr + EMAC_RX_CTL0); 712 713 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 714 if (fc == FLOW_AUTO) 715 v |= EMAC_TX_FLOW_CTL_EN; 716 else 717 v &= ~EMAC_TX_FLOW_CTL_EN; 718 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 719} 720 721static int sun8i_dwmac_reset(struct stmmac_priv *priv) 722{ 723 u32 v; 724 int err; 725 726 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 727 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 728 729 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 730 * need more if no cable plugged. 100ms seems OK 731 */ 732 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 733 !(v & 0x01), 100, 100000); 734 735 if (err) { 736 dev_err(priv->device, "EMAC reset timeout\n"); 737 return err; 738 } 739 return 0; 740} 741 742/* Search in mdio-mux node for internal PHY node and get its clk/reset */ 743static int get_ephy_nodes(struct stmmac_priv *priv) 744{ 745 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 746 struct device_node *mdio_mux, *iphynode; 747 struct device_node *mdio_internal; 748 int ret; 749 750 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 751 if (!mdio_mux) { 752 dev_err(priv->device, "Cannot get mdio-mux node\n"); 753 return -ENODEV; 754 } 755 756 mdio_internal = of_get_compatible_child(mdio_mux, 757 "allwinner,sun8i-h3-mdio-internal"); 758 of_node_put(mdio_mux); 759 if (!mdio_internal) { 760 dev_err(priv->device, "Cannot get internal_mdio node\n"); 761 return -ENODEV; 762 } 763 764 /* Seek for internal PHY */ 765 for_each_child_of_node(mdio_internal, iphynode) { 766 gmac->ephy_clk = of_clk_get(iphynode, 0); 767 if (IS_ERR(gmac->ephy_clk)) 768 continue; 769 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 770 if (IS_ERR(gmac->rst_ephy)) { 771 ret = PTR_ERR(gmac->rst_ephy); 772 if (ret == -EPROBE_DEFER) { 773 of_node_put(iphynode); 774 of_node_put(mdio_internal); 775 return ret; 776 } 777 continue; 778 } 779 dev_info(priv->device, "Found internal PHY node\n"); 780 of_node_put(iphynode); 781 of_node_put(mdio_internal); 782 return 0; 783 } 784 785 of_node_put(mdio_internal); 786 return -ENODEV; 787} 788 789static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 790{ 791 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 792 int ret; 793 794 if (gmac->internal_phy_powered) { 795 dev_warn(priv->device, "Internal PHY already powered\n"); 796 return 0; 797 } 798 799 dev_info(priv->device, "Powering internal PHY\n"); 800 ret = clk_prepare_enable(gmac->ephy_clk); 801 if (ret) { 802 dev_err(priv->device, "Cannot enable internal PHY\n"); 803 return ret; 804 } 805 806 /* Make sure the EPHY is properly reseted, as U-Boot may leave 807 * it at deasserted state, and thus it may fail to reset EMAC. 808 */ 809 reset_control_assert(gmac->rst_ephy); 810 811 ret = reset_control_deassert(gmac->rst_ephy); 812 if (ret) { 813 dev_err(priv->device, "Cannot deassert internal phy\n"); 814 clk_disable_unprepare(gmac->ephy_clk); 815 return ret; 816 } 817 818 gmac->internal_phy_powered = true; 819 820 return 0; 821} 822 823static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 824{ 825 if (!gmac->internal_phy_powered) 826 return 0; 827 828 clk_disable_unprepare(gmac->ephy_clk); 829 reset_control_assert(gmac->rst_ephy); 830 gmac->internal_phy_powered = false; 831 return 0; 832} 833 834/* MDIO multiplexing switch function 835 * This function is called by the mdio-mux layer when it thinks the mdio bus 836 * multiplexer needs to switch. 837 * 'current_child' is the current value of the mux register 838 * 'desired_child' is the value of the 'reg' property of the target child MDIO 839 * node. 840 * The first time this function is called, current_child == -1. 841 * If current_child == desired_child, then the mux is already set to the 842 * correct bus. 843 */ 844static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 845 void *data) 846{ 847 struct stmmac_priv *priv = data; 848 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 849 u32 reg, val; 850 int ret = 0; 851 852 if (current_child ^ desired_child) { 853 regmap_field_read(gmac->regmap_field, ®); 854 switch (desired_child) { 855 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 856 dev_info(priv->device, "Switch mux to internal PHY"); 857 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 858 gmac->use_internal_phy = true; 859 break; 860 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 861 dev_info(priv->device, "Switch mux to external PHY"); 862 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 863 gmac->use_internal_phy = false; 864 break; 865 default: 866 dev_err(priv->device, "Invalid child ID %x\n", 867 desired_child); 868 return -EINVAL; 869 } 870 regmap_field_write(gmac->regmap_field, val); 871 if (gmac->use_internal_phy) { 872 ret = sun8i_dwmac_power_internal_phy(priv); 873 if (ret) 874 return ret; 875 } else { 876 sun8i_dwmac_unpower_internal_phy(gmac); 877 } 878 /* After changing syscon value, the MAC need reset or it will 879 * use the last value (and so the last PHY set). 880 */ 881 ret = sun8i_dwmac_reset(priv); 882 } 883 return ret; 884} 885 886static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 887{ 888 int ret; 889 struct device_node *mdio_mux; 890 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 891 892 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 893 if (!mdio_mux) 894 return -ENODEV; 895 896 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 897 &gmac->mux_handle, priv, priv->mii); 898 of_node_put(mdio_mux); 899 return ret; 900} 901 902static int sun8i_dwmac_set_syscon(struct device *dev, 903 struct plat_stmmacenet_data *plat) 904{ 905 struct sunxi_priv_data *gmac = plat->bsp_priv; 906 struct device_node *node = dev->of_node; 907 int ret; 908 u32 reg, val; 909 910 ret = regmap_field_read(gmac->regmap_field, &val); 911 if (ret) { 912 dev_err(dev, "Fail to read from regmap field.\n"); 913 return ret; 914 } 915 916 reg = gmac->variant->default_syscon_value; 917 if (reg != val) 918 dev_warn(dev, 919 "Current syscon value is not the default %x (expect %x)\n", 920 val, reg); 921 922 if (gmac->variant->soc_has_internal_phy) { 923 if (of_property_read_bool(node, "allwinner,leds-active-low")) 924 reg |= H3_EPHY_LED_POL; 925 else 926 reg &= ~H3_EPHY_LED_POL; 927 928 /* Force EPHY xtal frequency to 24MHz. */ 929 reg |= H3_EPHY_CLK_SEL; 930 931 ret = of_mdio_parse_addr(dev, plat->phy_node); 932 if (ret < 0) { 933 dev_err(dev, "Could not parse MDIO addr\n"); 934 return ret; 935 } 936 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 937 * address. No need to mask it again. 938 */ 939 reg |= 1 << H3_EPHY_ADDR_SHIFT; 940 } else { 941 /* For SoCs without internal PHY the PHY selection bit should be 942 * set to 0 (external PHY). 943 */ 944 reg &= ~H3_EPHY_SELECT; 945 } 946 947 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 948 if (val % 100) { 949 dev_err(dev, "tx-delay must be a multiple of 100\n"); 950 return -EINVAL; 951 } 952 val /= 100; 953 dev_dbg(dev, "set tx-delay to %x\n", val); 954 if (val <= gmac->variant->tx_delay_max) { 955 reg &= ~(gmac->variant->tx_delay_max << 956 SYSCON_ETXDC_SHIFT); 957 reg |= (val << SYSCON_ETXDC_SHIFT); 958 } else { 959 dev_err(dev, "Invalid TX clock delay: %d\n", 960 val); 961 return -EINVAL; 962 } 963 } 964 965 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 966 if (val % 100) { 967 dev_err(dev, "rx-delay must be a multiple of 100\n"); 968 return -EINVAL; 969 } 970 val /= 100; 971 dev_dbg(dev, "set rx-delay to %x\n", val); 972 if (val <= gmac->variant->rx_delay_max) { 973 reg &= ~(gmac->variant->rx_delay_max << 974 SYSCON_ERXDC_SHIFT); 975 reg |= (val << SYSCON_ERXDC_SHIFT); 976 } else { 977 dev_err(dev, "Invalid RX clock delay: %d\n", 978 val); 979 return -EINVAL; 980 } 981 } 982 983 /* Clear interface mode bits */ 984 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 985 if (gmac->variant->support_rmii) 986 reg &= ~SYSCON_RMII_EN; 987 988 switch (plat->interface) { 989 case PHY_INTERFACE_MODE_MII: 990 /* default */ 991 break; 992 case PHY_INTERFACE_MODE_RGMII: 993 case PHY_INTERFACE_MODE_RGMII_ID: 994 case PHY_INTERFACE_MODE_RGMII_RXID: 995 case PHY_INTERFACE_MODE_RGMII_TXID: 996 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 997 break; 998 case PHY_INTERFACE_MODE_RMII: 999 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 1000 break; 1001 default: 1002 dev_err(dev, "Unsupported interface mode: %s", 1003 phy_modes(plat->interface)); 1004 return -EINVAL; 1005 } 1006 1007 regmap_field_write(gmac->regmap_field, reg); 1008 1009 return 0; 1010} 1011 1012static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 1013{ 1014 u32 reg = gmac->variant->default_syscon_value; 1015 1016 regmap_field_write(gmac->regmap_field, reg); 1017} 1018 1019static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 1020{ 1021 struct sunxi_priv_data *gmac = priv; 1022 1023 if (gmac->variant->soc_has_internal_phy) { 1024 if (gmac->internal_phy_powered) 1025 sun8i_dwmac_unpower_internal_phy(gmac); 1026 } 1027 1028 clk_disable_unprepare(gmac->tx_clk); 1029 1030 if (gmac->regulator) 1031 regulator_disable(gmac->regulator); 1032} 1033 1034static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1035{ 1036 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1037 1038 if (enable) 1039 value |= EMAC_LOOPBACK; 1040 else 1041 value &= ~EMAC_LOOPBACK; 1042 1043 writel(value, ioaddr + EMAC_BASIC_CTL0); 1044} 1045 1046static const struct stmmac_ops sun8i_dwmac_ops = { 1047 .core_init = sun8i_dwmac_core_init, 1048 .set_mac = sun8i_dwmac_set_mac, 1049 .dump_regs = sun8i_dwmac_dump_mac_regs, 1050 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1051 .set_filter = sun8i_dwmac_set_filter, 1052 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1053 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1054 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1055 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1056}; 1057 1058static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1059{ 1060 struct mac_device_info *mac; 1061 struct stmmac_priv *priv = ppriv; 1062 1063 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1064 if (!mac) 1065 return NULL; 1066 1067 mac->pcsr = priv->ioaddr; 1068 mac->mac = &sun8i_dwmac_ops; 1069 mac->dma = &sun8i_dwmac_dma_ops; 1070 1071 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1072 1073 /* The loopback bit seems to be re-set when link change 1074 * Simply mask it each time 1075 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1076 */ 1077 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1078 mac->link.speed10 = EMAC_SPEED_10; 1079 mac->link.speed100 = EMAC_SPEED_100; 1080 mac->link.speed1000 = EMAC_SPEED_1000; 1081 mac->link.duplex = EMAC_DUPLEX_FULL; 1082 mac->mii.addr = EMAC_MDIO_CMD; 1083 mac->mii.data = EMAC_MDIO_DATA; 1084 mac->mii.reg_shift = 4; 1085 mac->mii.reg_mask = GENMASK(8, 4); 1086 mac->mii.addr_shift = 12; 1087 mac->mii.addr_mask = GENMASK(16, 12); 1088 mac->mii.clk_csr_shift = 20; 1089 mac->mii.clk_csr_mask = GENMASK(22, 20); 1090 mac->unicast_filter_entries = 8; 1091 1092 /* Synopsys Id is not available */ 1093 priv->synopsys_id = 0; 1094 1095 return mac; 1096} 1097 1098static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1099{ 1100 struct device_node *syscon_node; 1101 struct platform_device *syscon_pdev; 1102 struct regmap *regmap = NULL; 1103 1104 syscon_node = of_parse_phandle(node, "syscon", 0); 1105 if (!syscon_node) 1106 return ERR_PTR(-ENODEV); 1107 1108 syscon_pdev = of_find_device_by_node(syscon_node); 1109 if (!syscon_pdev) { 1110 /* platform device might not be probed yet */ 1111 regmap = ERR_PTR(-EPROBE_DEFER); 1112 goto out_put_node; 1113 } 1114 1115 /* If no regmap is found then the other device driver is at fault */ 1116 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1117 if (!regmap) 1118 regmap = ERR_PTR(-EINVAL); 1119 1120 platform_device_put(syscon_pdev); 1121out_put_node: 1122 of_node_put(syscon_node); 1123 return regmap; 1124} 1125 1126static int sun8i_dwmac_probe(struct platform_device *pdev) 1127{ 1128 struct plat_stmmacenet_data *plat_dat; 1129 struct stmmac_resources stmmac_res; 1130 struct sunxi_priv_data *gmac; 1131 struct device *dev = &pdev->dev; 1132 phy_interface_t interface; 1133 int ret; 1134 struct stmmac_priv *priv; 1135 struct net_device *ndev; 1136 struct regmap *regmap; 1137 1138 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1139 if (ret) 1140 return ret; 1141 1142 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1143 if (!gmac) 1144 return -ENOMEM; 1145 1146 gmac->variant = of_device_get_match_data(&pdev->dev); 1147 if (!gmac->variant) { 1148 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1149 return -EINVAL; 1150 } 1151 1152 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1153 if (IS_ERR(gmac->tx_clk)) { 1154 dev_err(dev, "Could not get TX clock\n"); 1155 return PTR_ERR(gmac->tx_clk); 1156 } 1157 1158 /* Optional regulator for PHY */ 1159 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1160 if (IS_ERR(gmac->regulator)) { 1161 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1162 return -EPROBE_DEFER; 1163 dev_info(dev, "No regulator found\n"); 1164 gmac->regulator = NULL; 1165 } 1166 1167 /* The "GMAC clock control" register might be located in the 1168 * CCU address range (on the R40), or the system control address 1169 * range (on most other sun8i and later SoCs). 1170 * 1171 * The former controls most if not all clocks in the SoC. The 1172 * latter has an SoC identification register, and on some SoCs, 1173 * controls to map device specific SRAM to either the intended 1174 * peripheral, or the CPU address space. 1175 * 1176 * In either case, there should be a coordinated and restricted 1177 * method of accessing the register needed here. This is done by 1178 * having the device export a custom regmap, instead of a generic 1179 * syscon, which grants all access to all registers. 1180 * 1181 * To support old device trees, we fall back to using the syscon 1182 * interface if possible. 1183 */ 1184 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1185 if (IS_ERR(regmap)) 1186 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1187 "syscon"); 1188 if (IS_ERR(regmap)) { 1189 ret = PTR_ERR(regmap); 1190 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1191 return ret; 1192 } 1193 1194 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1195 *gmac->variant->syscon_field); 1196 if (IS_ERR(gmac->regmap_field)) { 1197 ret = PTR_ERR(gmac->regmap_field); 1198 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1199 return ret; 1200 } 1201 1202 ret = of_get_phy_mode(dev->of_node, &interface); 1203 if (ret) 1204 return -EINVAL; 1205 1206 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1207 if (IS_ERR(plat_dat)) 1208 return PTR_ERR(plat_dat); 1209 1210 /* platform data specifying hardware features and callbacks. 1211 * hardware features were copied from Allwinner drivers. 1212 */ 1213 plat_dat->interface = interface; 1214 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1215 plat_dat->tx_coe = 1; 1216 plat_dat->has_sun8i = true; 1217 plat_dat->bsp_priv = gmac; 1218 plat_dat->init = sun8i_dwmac_init; 1219 plat_dat->exit = sun8i_dwmac_exit; 1220 plat_dat->setup = sun8i_dwmac_setup; 1221 plat_dat->tx_fifo_size = 4096; 1222 plat_dat->rx_fifo_size = 16384; 1223 1224 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); 1225 if (ret) 1226 goto dwmac_deconfig; 1227 1228 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1229 if (ret) 1230 goto dwmac_syscon; 1231 1232 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1233 if (ret) 1234 goto dwmac_exit; 1235 1236 ndev = dev_get_drvdata(&pdev->dev); 1237 priv = netdev_priv(ndev); 1238 /* The mux must be registered after parent MDIO 1239 * so after stmmac_dvr_probe() 1240 */ 1241 if (gmac->variant->soc_has_internal_phy) { 1242 ret = get_ephy_nodes(priv); 1243 if (ret) 1244 goto dwmac_remove; 1245 ret = sun8i_dwmac_register_mdio_mux(priv); 1246 if (ret) { 1247 dev_err(&pdev->dev, "Failed to register mux\n"); 1248 goto dwmac_mux; 1249 } 1250 } else { 1251 ret = sun8i_dwmac_reset(priv); 1252 if (ret) 1253 goto dwmac_remove; 1254 } 1255 1256 return ret; 1257dwmac_mux: 1258 reset_control_put(gmac->rst_ephy); 1259 clk_put(gmac->ephy_clk); 1260dwmac_remove: 1261 stmmac_dvr_remove(&pdev->dev); 1262dwmac_exit: 1263 sun8i_dwmac_exit(pdev, gmac); 1264dwmac_syscon: 1265 sun8i_dwmac_unset_syscon(gmac); 1266dwmac_deconfig: 1267 stmmac_remove_config_dt(pdev, plat_dat); 1268 1269 return ret; 1270} 1271 1272static int sun8i_dwmac_remove(struct platform_device *pdev) 1273{ 1274 struct net_device *ndev = platform_get_drvdata(pdev); 1275 struct stmmac_priv *priv = netdev_priv(ndev); 1276 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1277 1278 if (gmac->variant->soc_has_internal_phy) { 1279 mdio_mux_uninit(gmac->mux_handle); 1280 sun8i_dwmac_unpower_internal_phy(gmac); 1281 reset_control_put(gmac->rst_ephy); 1282 clk_put(gmac->ephy_clk); 1283 } 1284 1285 stmmac_pltfr_remove(pdev); 1286 sun8i_dwmac_unset_syscon(gmac); 1287 1288 return 0; 1289} 1290 1291static const struct of_device_id sun8i_dwmac_match[] = { 1292 { .compatible = "allwinner,sun8i-h3-emac", 1293 .data = &emac_variant_h3 }, 1294 { .compatible = "allwinner,sun8i-v3s-emac", 1295 .data = &emac_variant_v3s }, 1296 { .compatible = "allwinner,sun8i-a83t-emac", 1297 .data = &emac_variant_a83t }, 1298 { .compatible = "allwinner,sun8i-r40-gmac", 1299 .data = &emac_variant_r40 }, 1300 { .compatible = "allwinner,sun50i-a64-emac", 1301 .data = &emac_variant_a64 }, 1302 { .compatible = "allwinner,sun50i-h6-emac", 1303 .data = &emac_variant_h6 }, 1304 { } 1305}; 1306MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1307 1308static struct platform_driver sun8i_dwmac_driver = { 1309 .probe = sun8i_dwmac_probe, 1310 .remove = sun8i_dwmac_remove, 1311 .driver = { 1312 .name = "dwmac-sun8i", 1313 .pm = &stmmac_pltfr_pm_ops, 1314 .of_match_table = sun8i_dwmac_match, 1315 }, 1316}; 1317module_platform_driver(sun8i_dwmac_driver); 1318 1319MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1320MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1321MODULE_LICENSE("GPL"); 1322