1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
4 *
5 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/device.h>
12#include <linux/ethtool.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/platform_device.h>
20#include <linux/stmmac.h>
21
22#include "stmmac_platform.h"
23
24#define PRG_ETH0			0x0
25
26#define PRG_ETH0_RGMII_MODE		BIT(0)
27
28#define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
29#define PRG_ETH0_EXT_RGMII_MODE		1
30#define PRG_ETH0_EXT_RMII_MODE		4
31
32/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
33#define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
34
35/* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
36 * cycle of the 125MHz RGMII TX clock):
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
38 */
39#define PRG_ETH0_TXDLY_MASK		GENMASK(6, 5)
40
41/* divider for the result of m250_sel */
42#define PRG_ETH0_CLK_M250_DIV_SHIFT	7
43#define PRG_ETH0_CLK_M250_DIV_WIDTH	3
44
45#define PRG_ETH0_RGMII_TX_CLK_EN	10
46
47#define PRG_ETH0_INVERTED_RMII_CLK	BIT(11)
48#define PRG_ETH0_TX_AND_PHY_REF_CLK	BIT(12)
49
50/* Bypass (= 0, the signal from the GPIO input directly connects to the
51 * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
52 * timing tuning.
53 */
54#define PRG_ETH0_ADJ_ENABLE		BIT(13)
55/* Controls whether the RXEN and RXD[3:0] signals should be aligned with the
56 * input RX rising/falling edge and sent to the Ethernet internals. This sets
57 * the automatically delay and skew automatically (internally).
58 */
59#define PRG_ETH0_ADJ_SETUP		BIT(14)
60/* An internal counter based on the "timing-adjustment" clock. The counter is
61 * cleared on both, the falling and rising edge of the RX_CLK. This selects the
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
63 */
64#define PRG_ETH0_ADJ_DELAY		GENMASK(19, 15)
65/* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
68 */
69#define PRG_ETH0_ADJ_SKEW		GENMASK(24, 20)
70
71struct meson8b_dwmac;
72
73struct meson8b_dwmac_data {
74	int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
75};
76
77struct meson8b_dwmac {
78	struct device			*dev;
79	void __iomem			*regs;
80
81	const struct meson8b_dwmac_data	*data;
82	phy_interface_t			phy_mode;
83	struct clk			*rgmii_tx_clk;
84	u32				tx_delay_ns;
85	u32				rx_delay_ns;
86	struct clk			*timing_adj_clk;
87};
88
89struct meson8b_dwmac_clk_configs {
90	struct clk_mux		m250_mux;
91	struct clk_divider	m250_div;
92	struct clk_fixed_factor	fixed_div2;
93	struct clk_gate		rgmii_tx_en;
94};
95
96static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
97				    u32 mask, u32 value)
98{
99	u32 data;
100
101	data = readl(dwmac->regs + reg);
102	data &= ~mask;
103	data |= (value & mask);
104
105	writel(data, dwmac->regs + reg);
106}
107
108static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
109					      const char *name_suffix,
110					      const struct clk_parent_data *parents,
111					      int num_parents,
112					      const struct clk_ops *ops,
113					      struct clk_hw *hw)
114{
115	struct clk_init_data init = { };
116	char clk_name[32];
117
118	snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
119		 name_suffix);
120
121	init.name = clk_name;
122	init.ops = ops;
123	init.flags = CLK_SET_RATE_PARENT;
124	init.parent_data = parents;
125	init.num_parents = num_parents;
126
127	hw->init = &init;
128
129	return devm_clk_register(dwmac->dev, hw);
130}
131
132static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
133{
134	struct clk *clk;
135	struct device *dev = dwmac->dev;
136	static const struct clk_parent_data mux_parents[] = {
137		{ .fw_name = "clkin0", },
138		{ .index = -1, },
139	};
140	static const struct clk_div_table div_table[] = {
141		{ .div = 2, .val = 2, },
142		{ .div = 3, .val = 3, },
143		{ .div = 4, .val = 4, },
144		{ .div = 5, .val = 5, },
145		{ .div = 6, .val = 6, },
146		{ .div = 7, .val = 7, },
147		{ /* end of array */ }
148	};
149	struct meson8b_dwmac_clk_configs *clk_configs;
150	struct clk_parent_data parent_data = { };
151
152	clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL);
153	if (!clk_configs)
154		return -ENOMEM;
155
156	clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
157	clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);
158	clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>
159				     clk_configs->m250_mux.shift;
160	clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
161					 ARRAY_SIZE(mux_parents), &clk_mux_ops,
162					 &clk_configs->m250_mux.hw);
163	if (WARN_ON(IS_ERR(clk)))
164		return PTR_ERR(clk);
165
166	parent_data.hw = &clk_configs->m250_mux.hw;
167	clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
168	clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
169	clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
170	clk_configs->m250_div.table = div_table;
171	clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO |
172				      CLK_DIVIDER_ROUND_CLOSEST;
173	clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_data, 1,
174					 &clk_divider_ops,
175					 &clk_configs->m250_div.hw);
176	if (WARN_ON(IS_ERR(clk)))
177		return PTR_ERR(clk);
178
179	parent_data.hw = &clk_configs->m250_div.hw;
180	clk_configs->fixed_div2.mult = 1;
181	clk_configs->fixed_div2.div = 2;
182	clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_data, 1,
183					 &clk_fixed_factor_ops,
184					 &clk_configs->fixed_div2.hw);
185	if (WARN_ON(IS_ERR(clk)))
186		return PTR_ERR(clk);
187
188	parent_data.hw = &clk_configs->fixed_div2.hw;
189	clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
190	clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
191	clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_data, 1,
192					 &clk_gate_ops,
193					 &clk_configs->rgmii_tx_en.hw);
194	if (WARN_ON(IS_ERR(clk)))
195		return PTR_ERR(clk);
196
197	dwmac->rgmii_tx_clk = clk;
198
199	return 0;
200}
201
202static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
203{
204	switch (dwmac->phy_mode) {
205	case PHY_INTERFACE_MODE_RGMII:
206	case PHY_INTERFACE_MODE_RGMII_RXID:
207	case PHY_INTERFACE_MODE_RGMII_ID:
208	case PHY_INTERFACE_MODE_RGMII_TXID:
209		/* enable RGMII mode */
210		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
211					PRG_ETH0_RGMII_MODE,
212					PRG_ETH0_RGMII_MODE);
213		break;
214	case PHY_INTERFACE_MODE_RMII:
215		/* disable RGMII mode -> enables RMII mode */
216		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
217					PRG_ETH0_RGMII_MODE, 0);
218		break;
219	default:
220		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
221			phy_modes(dwmac->phy_mode));
222		return -EINVAL;
223	}
224
225	return 0;
226}
227
228static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
229{
230	switch (dwmac->phy_mode) {
231	case PHY_INTERFACE_MODE_RGMII:
232	case PHY_INTERFACE_MODE_RGMII_RXID:
233	case PHY_INTERFACE_MODE_RGMII_ID:
234	case PHY_INTERFACE_MODE_RGMII_TXID:
235		/* enable RGMII mode */
236		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
237					PRG_ETH0_EXT_PHY_MODE_MASK,
238					PRG_ETH0_EXT_RGMII_MODE);
239		break;
240	case PHY_INTERFACE_MODE_RMII:
241		/* disable RGMII mode -> enables RMII mode */
242		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
243					PRG_ETH0_EXT_PHY_MODE_MASK,
244					PRG_ETH0_EXT_RMII_MODE);
245		break;
246	default:
247		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
248			phy_modes(dwmac->phy_mode));
249		return -EINVAL;
250	}
251
252	return 0;
253}
254
255static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,
256					   struct clk *clk)
257{
258	int ret;
259
260	ret = clk_prepare_enable(clk);
261	if (ret)
262		return ret;
263
264	return devm_add_action_or_reset(dwmac->dev,
265					(void(*)(void *))clk_disable_unprepare,
266					clk);
267}
268
269static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
270{
271	u32 tx_dly_config, rx_dly_config, delay_config;
272	int ret;
273
274	tx_dly_config = FIELD_PREP(PRG_ETH0_TXDLY_MASK,
275				   dwmac->tx_delay_ns >> 1);
276
277	if (dwmac->rx_delay_ns == 2)
278		rx_dly_config = PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP;
279	else
280		rx_dly_config = 0;
281
282	switch (dwmac->phy_mode) {
283	case PHY_INTERFACE_MODE_RGMII:
284		delay_config = tx_dly_config | rx_dly_config;
285		break;
286	case PHY_INTERFACE_MODE_RGMII_RXID:
287		delay_config = tx_dly_config;
288		break;
289	case PHY_INTERFACE_MODE_RGMII_TXID:
290		delay_config = rx_dly_config;
291		break;
292	case PHY_INTERFACE_MODE_RGMII_ID:
293	case PHY_INTERFACE_MODE_RMII:
294		delay_config = 0;
295		break;
296	default:
297		dev_err(dwmac->dev, "unsupported phy-mode %s\n",
298			phy_modes(dwmac->phy_mode));
299		return -EINVAL;
300	};
301
302	if (delay_config & PRG_ETH0_ADJ_ENABLE) {
303		if (!dwmac->timing_adj_clk) {
304			dev_err(dwmac->dev,
305				"The timing-adjustment clock is mandatory for the RX delay re-timing\n");
306			return -EINVAL;
307		}
308
309		/* The timing adjustment logic is driven by a separate clock */
310		ret = meson8b_devm_clk_prepare_enable(dwmac,
311						      dwmac->timing_adj_clk);
312		if (ret) {
313			dev_err(dwmac->dev,
314				"Failed to enable the timing-adjustment clock\n");
315			return ret;
316		}
317	}
318
319	meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK |
320				PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP |
321				PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW,
322				delay_config);
323
324	if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) {
325		/* only relevant for RMII mode -> disable in RGMII mode */
326		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
327					PRG_ETH0_INVERTED_RMII_CLK, 0);
328
329		/* Configure the 125MHz RGMII TX clock, the IP block changes
330		 * the output automatically (= without us having to configure
331		 * a register) based on the line-speed (125MHz for Gbit speeds,
332		 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s).
333		 */
334		ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
335		if (ret) {
336			dev_err(dwmac->dev,
337				"failed to set RGMII TX clock\n");
338			return ret;
339		}
340
341		ret = meson8b_devm_clk_prepare_enable(dwmac,
342						      dwmac->rgmii_tx_clk);
343		if (ret) {
344			dev_err(dwmac->dev,
345				"failed to enable the RGMII TX clock\n");
346			return ret;
347		}
348	} else {
349		/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
350		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
351					PRG_ETH0_INVERTED_RMII_CLK,
352					PRG_ETH0_INVERTED_RMII_CLK);
353	}
354
355	/* enable TX_CLK and PHY_REF_CLK generator */
356	meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
357				PRG_ETH0_TX_AND_PHY_REF_CLK);
358
359	return 0;
360}
361
362static int meson8b_dwmac_probe(struct platform_device *pdev)
363{
364	struct plat_stmmacenet_data *plat_dat;
365	struct stmmac_resources stmmac_res;
366	struct meson8b_dwmac *dwmac;
367	int ret;
368
369	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
370	if (ret)
371		return ret;
372
373	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
374	if (IS_ERR(plat_dat))
375		return PTR_ERR(plat_dat);
376
377	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
378	if (!dwmac) {
379		ret = -ENOMEM;
380		goto err_remove_config_dt;
381	}
382
383	dwmac->data = (const struct meson8b_dwmac_data *)
384		of_device_get_match_data(&pdev->dev);
385	if (!dwmac->data) {
386		ret = -EINVAL;
387		goto err_remove_config_dt;
388	}
389	dwmac->regs = devm_platform_ioremap_resource(pdev, 1);
390	if (IS_ERR(dwmac->regs)) {
391		ret = PTR_ERR(dwmac->regs);
392		goto err_remove_config_dt;
393	}
394
395	dwmac->dev = &pdev->dev;
396	ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode);
397	if (ret) {
398		dev_err(&pdev->dev, "missing phy-mode property\n");
399		goto err_remove_config_dt;
400	}
401
402	/* use 2ns as fallback since this value was previously hardcoded */
403	if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
404				 &dwmac->tx_delay_ns))
405		dwmac->tx_delay_ns = 2;
406
407	/* use 0ns as fallback since this is what most boards actually use */
408	if (of_property_read_u32(pdev->dev.of_node, "amlogic,rx-delay-ns",
409				 &dwmac->rx_delay_ns))
410		dwmac->rx_delay_ns = 0;
411
412	if (dwmac->rx_delay_ns != 0 && dwmac->rx_delay_ns != 2) {
413		dev_err(&pdev->dev,
414			"The only allowed RX delays values are: 0ns, 2ns");
415		ret = -EINVAL;
416		goto err_remove_config_dt;
417	}
418
419	dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,
420						      "timing-adjustment");
421	if (IS_ERR(dwmac->timing_adj_clk)) {
422		ret = PTR_ERR(dwmac->timing_adj_clk);
423		goto err_remove_config_dt;
424	}
425
426	ret = meson8b_init_rgmii_tx_clk(dwmac);
427	if (ret)
428		goto err_remove_config_dt;
429
430	ret = dwmac->data->set_phy_mode(dwmac);
431	if (ret)
432		goto err_remove_config_dt;
433
434	ret = meson8b_init_prg_eth(dwmac);
435	if (ret)
436		goto err_remove_config_dt;
437
438	plat_dat->bsp_priv = dwmac;
439
440	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
441	if (ret)
442		goto err_remove_config_dt;
443
444	return 0;
445
446err_remove_config_dt:
447	stmmac_remove_config_dt(pdev, plat_dat);
448
449	return ret;
450}
451
452static const struct meson8b_dwmac_data meson8b_dwmac_data = {
453	.set_phy_mode = meson8b_set_phy_mode,
454};
455
456static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
457	.set_phy_mode = meson_axg_set_phy_mode,
458};
459
460static const struct of_device_id meson8b_dwmac_match[] = {
461	{
462		.compatible = "amlogic,meson8b-dwmac",
463		.data = &meson8b_dwmac_data,
464	},
465	{
466		.compatible = "amlogic,meson8m2-dwmac",
467		.data = &meson8b_dwmac_data,
468	},
469	{
470		.compatible = "amlogic,meson-gxbb-dwmac",
471		.data = &meson8b_dwmac_data,
472	},
473	{
474		.compatible = "amlogic,meson-axg-dwmac",
475		.data = &meson_axg_dwmac_data,
476	},
477	{
478		.compatible = "amlogic,meson-g12a-dwmac",
479		.data = &meson_axg_dwmac_data,
480	},
481	{ }
482};
483MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
484
485static struct platform_driver meson8b_dwmac_driver = {
486	.probe  = meson8b_dwmac_probe,
487	.remove = stmmac_pltfr_remove,
488	.driver = {
489		.name           = "meson8b-dwmac",
490		.pm		= &stmmac_pltfr_pm_ops,
491		.of_match_table = meson8b_dwmac_match,
492	},
493};
494module_platform_driver(meson8b_dwmac_driver);
495
496MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
497MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer");
498MODULE_LICENSE("GPL v2");
499