1// SPDX-License-Identifier: GPL-2.0+ 2 3#include <linux/types.h> 4#include <linux/clk.h> 5#include <linux/platform_device.h> 6#include <linux/pm_runtime.h> 7#include <linux/acpi.h> 8#include <linux/of_mdio.h> 9#include <linux/of_net.h> 10#include <linux/etherdevice.h> 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/netlink.h> 14#include <linux/bpf.h> 15#include <linux/bpf_trace.h> 16 17#include <net/tcp.h> 18#include <net/page_pool.h> 19#include <net/ip6_checksum.h> 20 21#define NETSEC_REG_SOFT_RST 0x104 22#define NETSEC_REG_COM_INIT 0x120 23 24#define NETSEC_REG_TOP_STATUS 0x200 25#define NETSEC_IRQ_RX BIT(1) 26#define NETSEC_IRQ_TX BIT(0) 27 28#define NETSEC_REG_TOP_INTEN 0x204 29#define NETSEC_REG_INTEN_SET 0x234 30#define NETSEC_REG_INTEN_CLR 0x238 31 32#define NETSEC_REG_NRM_TX_STATUS 0x400 33#define NETSEC_REG_NRM_TX_INTEN 0x404 34#define NETSEC_REG_NRM_TX_INTEN_SET 0x428 35#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 36#define NRM_TX_ST_NTOWNR BIT(17) 37#define NRM_TX_ST_TR_ERR BIT(16) 38#define NRM_TX_ST_TXDONE BIT(15) 39#define NRM_TX_ST_TMREXP BIT(14) 40 41#define NETSEC_REG_NRM_RX_STATUS 0x440 42#define NETSEC_REG_NRM_RX_INTEN 0x444 43#define NETSEC_REG_NRM_RX_INTEN_SET 0x468 44#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 45#define NRM_RX_ST_RC_ERR BIT(16) 46#define NRM_RX_ST_PKTCNT BIT(15) 47#define NRM_RX_ST_TMREXP BIT(14) 48 49#define NETSEC_REG_PKT_CMD_BUF 0xd0 50 51#define NETSEC_REG_CLK_EN 0x100 52 53#define NETSEC_REG_PKT_CTRL 0x140 54 55#define NETSEC_REG_DMA_TMR_CTRL 0x20c 56#define NETSEC_REG_F_TAIKI_MC_VER 0x22c 57#define NETSEC_REG_F_TAIKI_VER 0x230 58#define NETSEC_REG_DMA_HM_CTRL 0x214 59#define NETSEC_REG_DMA_MH_CTRL 0x220 60#define NETSEC_REG_ADDR_DIS_CORE 0x218 61#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 62#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 63 64#define NETSEC_REG_NRM_TX_PKTCNT 0x410 65 66#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 67#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 68 69#define NETSEC_REG_NRM_TX_TMR 0x41c 70 71#define NETSEC_REG_NRM_RX_PKTCNT 0x454 72#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 73#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 74#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 75 76#define NETSEC_REG_NRM_RX_TMR 0x45c 77 78#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 79#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 80#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 81#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 82 83#define NETSEC_REG_NRM_TX_CONFIG 0x430 84#define NETSEC_REG_NRM_RX_CONFIG 0x470 85 86#define MAC_REG_STATUS 0x1024 87#define MAC_REG_DATA 0x11c0 88#define MAC_REG_CMD 0x11c4 89#define MAC_REG_FLOW_TH 0x11cc 90#define MAC_REG_INTF_SEL 0x11d4 91#define MAC_REG_DESC_INIT 0x11fc 92#define MAC_REG_DESC_SOFT_RST 0x1204 93#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 94 95#define GMAC_REG_MCR 0x0000 96#define GMAC_REG_MFFR 0x0004 97#define GMAC_REG_GAR 0x0010 98#define GMAC_REG_GDR 0x0014 99#define GMAC_REG_FCR 0x0018 100#define GMAC_REG_BMR 0x1000 101#define GMAC_REG_RDLAR 0x100c 102#define GMAC_REG_TDLAR 0x1010 103#define GMAC_REG_OMR 0x1018 104 105#define MHZ(n) ((n) * 1000 * 1000) 106 107#define NETSEC_TX_SHIFT_OWN_FIELD 31 108#define NETSEC_TX_SHIFT_LD_FIELD 30 109#define NETSEC_TX_SHIFT_DRID_FIELD 24 110#define NETSEC_TX_SHIFT_PT_FIELD 21 111#define NETSEC_TX_SHIFT_TDRID_FIELD 16 112#define NETSEC_TX_SHIFT_CC_FIELD 15 113#define NETSEC_TX_SHIFT_FS_FIELD 9 114#define NETSEC_TX_LAST 8 115#define NETSEC_TX_SHIFT_CO 7 116#define NETSEC_TX_SHIFT_SO 6 117#define NETSEC_TX_SHIFT_TRS_FIELD 4 118 119#define NETSEC_RX_PKT_OWN_FIELD 31 120#define NETSEC_RX_PKT_LD_FIELD 30 121#define NETSEC_RX_PKT_SDRID_FIELD 24 122#define NETSEC_RX_PKT_FR_FIELD 23 123#define NETSEC_RX_PKT_ER_FIELD 21 124#define NETSEC_RX_PKT_ERR_FIELD 16 125#define NETSEC_RX_PKT_TDRID_FIELD 12 126#define NETSEC_RX_PKT_FS_FIELD 9 127#define NETSEC_RX_PKT_LS_FIELD 8 128#define NETSEC_RX_PKT_CO_FIELD 6 129 130#define NETSEC_RX_PKT_ERR_MASK 3 131 132#define NETSEC_MAX_TX_PKT_LEN 1518 133#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 134 135#define NETSEC_RING_GMAC 15 136#define NETSEC_RING_MAX 2 137 138#define NETSEC_TCP_SEG_LEN_MAX 1460 139#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 140 141#define NETSEC_RX_CKSUM_NOTAVAIL 0 142#define NETSEC_RX_CKSUM_OK 1 143#define NETSEC_RX_CKSUM_NG 2 144 145#define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 146#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 147 148#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 149#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 150 151#define NETSEC_INT_PKTCNT_MAX 2047 152 153#define NETSEC_FLOW_START_TH_MAX 95 154#define NETSEC_FLOW_STOP_TH_MAX 95 155#define NETSEC_FLOW_PAUSE_TIME_MIN 5 156 157#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 158 159#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 160#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 161#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 162#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 163#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 164#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 165 166#define NETSEC_CLK_EN_REG_DOM_G BIT(5) 167#define NETSEC_CLK_EN_REG_DOM_C BIT(1) 168#define NETSEC_CLK_EN_REG_DOM_D BIT(0) 169 170#define NETSEC_COM_INIT_REG_DB BIT(2) 171#define NETSEC_COM_INIT_REG_CLS BIT(1) 172#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 173 NETSEC_COM_INIT_REG_DB) 174 175#define NETSEC_SOFT_RST_REG_RESET 0 176#define NETSEC_SOFT_RST_REG_RUN BIT(31) 177 178#define NETSEC_DMA_CTRL_REG_STOP 1 179#define MH_CTRL__MODE_TRANS BIT(20) 180 181#define NETSEC_GMAC_CMD_ST_READ 0 182#define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 183#define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 184 185#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 186#define NETSEC_GMAC_BMR_REG_RESET 0x00020181 187#define NETSEC_GMAC_BMR_REG_SWR 0x00000001 188 189#define NETSEC_GMAC_OMR_REG_ST BIT(13) 190#define NETSEC_GMAC_OMR_REG_SR BIT(1) 191 192#define NETSEC_GMAC_MCR_REG_IBN BIT(30) 193#define NETSEC_GMAC_MCR_REG_CST BIT(25) 194#define NETSEC_GMAC_MCR_REG_JE BIT(20) 195#define NETSEC_MCR_PS BIT(15) 196#define NETSEC_GMAC_MCR_REG_FES BIT(14) 197#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 198#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 199 200#define NETSEC_FCR_RFE BIT(2) 201#define NETSEC_FCR_TFE BIT(1) 202 203#define NETSEC_GMAC_GAR_REG_GW BIT(1) 204#define NETSEC_GMAC_GAR_REG_GB BIT(0) 205 206#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 207#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 208#define GMAC_REG_SHIFT_CR_GAR 2 209 210#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 211#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 212#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 213#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 214#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 215#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 216 217#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 218#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 219 220#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 221 222#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 223#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 224#define NETSEC_REG_DESC_TMR_MODE 4 225#define NETSEC_REG_DESC_ENDIAN 0 226 227#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 228#define NETSEC_MAC_DESC_INIT_REG_INIT 1 229 230#define NETSEC_EEPROM_MAC_ADDRESS 0x00 231#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 232#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 233#define NETSEC_EEPROM_HM_ME_SIZE 0x10 234#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 235#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 236#define NETSEC_EEPROM_MH_ME_SIZE 0x1C 237#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 238#define NETSEC_EEPROM_PKT_ME_SIZE 0x24 239 240#define DESC_NUM 256 241 242#define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 243#define NETSEC_RXBUF_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ 244 NET_IP_ALIGN) 245#define NETSEC_RX_BUF_NON_DATA (NETSEC_RXBUF_HEADROOM + \ 246 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 247#define NETSEC_RX_BUF_SIZE (PAGE_SIZE - NETSEC_RX_BUF_NON_DATA) 248 249#define DESC_SZ sizeof(struct netsec_de) 250 251#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 252 253#define NETSEC_XDP_PASS 0 254#define NETSEC_XDP_CONSUMED BIT(0) 255#define NETSEC_XDP_TX BIT(1) 256#define NETSEC_XDP_REDIR BIT(2) 257 258enum ring_id { 259 NETSEC_RING_TX = 0, 260 NETSEC_RING_RX 261}; 262 263enum buf_type { 264 TYPE_NETSEC_SKB = 0, 265 TYPE_NETSEC_XDP_TX, 266 TYPE_NETSEC_XDP_NDO, 267}; 268 269struct netsec_desc { 270 union { 271 struct sk_buff *skb; 272 struct xdp_frame *xdpf; 273 }; 274 dma_addr_t dma_addr; 275 void *addr; 276 u16 len; 277 u8 buf_type; 278}; 279 280struct netsec_desc_ring { 281 dma_addr_t desc_dma; 282 struct netsec_desc *desc; 283 void *vaddr; 284 u16 head, tail; 285 u16 xdp_xmit; /* netsec_xdp_xmit packets */ 286 struct page_pool *page_pool; 287 struct xdp_rxq_info xdp_rxq; 288 spinlock_t lock; /* XDP tx queue locking */ 289}; 290 291struct netsec_priv { 292 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 293 struct ethtool_coalesce et_coalesce; 294 struct bpf_prog *xdp_prog; 295 spinlock_t reglock; /* protect reg access */ 296 struct napi_struct napi; 297 phy_interface_t phy_interface; 298 struct net_device *ndev; 299 struct device_node *phy_np; 300 struct phy_device *phydev; 301 struct mii_bus *mii_bus; 302 void __iomem *ioaddr; 303 void __iomem *eeprom_base; 304 struct device *dev; 305 struct clk *clk; 306 u32 msg_enable; 307 u32 freq; 308 u32 phy_addr; 309 bool rx_cksum_offload_flag; 310}; 311 312struct netsec_de { /* Netsec Descriptor layout */ 313 u32 attr; 314 u32 data_buf_addr_up; 315 u32 data_buf_addr_lw; 316 u32 buf_len_info; 317}; 318 319struct netsec_tx_pkt_ctrl { 320 u16 tcp_seg_len; 321 bool tcp_seg_offload_flag; 322 bool cksum_offload_flag; 323}; 324 325struct netsec_rx_pkt_info { 326 int rx_cksum_result; 327 int err_code; 328 bool err_flag; 329}; 330 331static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 332{ 333 writel(val, priv->ioaddr + reg_addr); 334} 335 336static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 337{ 338 return readl(priv->ioaddr + reg_addr); 339} 340 341/************* MDIO BUS OPS FOLLOW *************/ 342 343#define TIMEOUT_SPINS_MAC 1000 344#define TIMEOUT_SECONDARY_MS_MAC 100 345 346static u32 netsec_clk_type(u32 freq) 347{ 348 if (freq < MHZ(35)) 349 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 350 if (freq < MHZ(60)) 351 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 352 if (freq < MHZ(100)) 353 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 354 if (freq < MHZ(150)) 355 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 356 if (freq < MHZ(250)) 357 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 358 359 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 360} 361 362static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 363{ 364 u32 timeout = TIMEOUT_SPINS_MAC; 365 366 while (--timeout && netsec_read(priv, addr) & mask) 367 cpu_relax(); 368 if (timeout) 369 return 0; 370 371 timeout = TIMEOUT_SECONDARY_MS_MAC; 372 while (--timeout && netsec_read(priv, addr) & mask) 373 usleep_range(1000, 2000); 374 375 if (timeout) 376 return 0; 377 378 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 379 380 return -ETIMEDOUT; 381} 382 383static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 384{ 385 netsec_write(priv, MAC_REG_DATA, value); 386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 387 return netsec_wait_while_busy(priv, 388 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 389} 390 391static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 392{ 393 int ret; 394 395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 396 ret = netsec_wait_while_busy(priv, 397 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 398 if (ret) 399 return ret; 400 401 *read = netsec_read(priv, MAC_REG_DATA); 402 403 return 0; 404} 405 406static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 407 u32 addr, u32 mask) 408{ 409 u32 timeout = TIMEOUT_SPINS_MAC; 410 int ret, data; 411 412 do { 413 ret = netsec_mac_read(priv, addr, &data); 414 if (ret) 415 break; 416 cpu_relax(); 417 } while (--timeout && (data & mask)); 418 419 if (timeout) 420 return 0; 421 422 timeout = TIMEOUT_SECONDARY_MS_MAC; 423 do { 424 usleep_range(1000, 2000); 425 426 ret = netsec_mac_read(priv, addr, &data); 427 if (ret) 428 break; 429 cpu_relax(); 430 } while (--timeout && (data & mask)); 431 432 if (timeout && !ret) 433 return 0; 434 435 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 436 437 return -ETIMEDOUT; 438} 439 440static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 441{ 442 struct phy_device *phydev = priv->ndev->phydev; 443 u32 value = 0; 444 445 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 446 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 447 448 if (phydev->speed != SPEED_1000) 449 value |= NETSEC_MCR_PS; 450 451 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 452 phydev->speed == SPEED_100) 453 value |= NETSEC_GMAC_MCR_REG_FES; 454 455 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 456 457 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 458 value |= NETSEC_GMAC_MCR_REG_IBN; 459 460 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 461 return -ETIMEDOUT; 462 463 return 0; 464} 465 466static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); 467 468static int netsec_phy_write(struct mii_bus *bus, 469 int phy_addr, int reg, u16 val) 470{ 471 int status; 472 struct netsec_priv *priv = bus->priv; 473 474 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 475 return -ETIMEDOUT; 476 if (netsec_mac_write(priv, GMAC_REG_GAR, 477 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 478 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 479 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 480 (netsec_clk_type(priv->freq) << 481 GMAC_REG_SHIFT_CR_GAR))) 482 return -ETIMEDOUT; 483 484 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 485 NETSEC_GMAC_GAR_REG_GB); 486 487 /* Developerbox implements RTL8211E PHY and there is 488 * a compatibility problem with F_GMAC4. 489 * RTL8211E expects MDC clock must be kept toggling for several 490 * clock cycle with MDIO high before entering the IDLE state. 491 * To meet this requirement, netsec driver needs to issue dummy 492 * read(e.g. read PHYID1(offset 0x2) register) right after write. 493 */ 494 netsec_phy_read(bus, phy_addr, MII_PHYSID1); 495 496 return status; 497} 498 499static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 500{ 501 struct netsec_priv *priv = bus->priv; 502 u32 data; 503 int ret; 504 505 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 506 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 507 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 508 (netsec_clk_type(priv->freq) << 509 GMAC_REG_SHIFT_CR_GAR))) 510 return -ETIMEDOUT; 511 512 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 513 NETSEC_GMAC_GAR_REG_GB); 514 if (ret) 515 return ret; 516 517 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 518 if (ret) 519 return ret; 520 521 return data; 522} 523 524/************* ETHTOOL_OPS FOLLOW *************/ 525 526static void netsec_et_get_drvinfo(struct net_device *net_device, 527 struct ethtool_drvinfo *info) 528{ 529 strlcpy(info->driver, "netsec", sizeof(info->driver)); 530 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 531 sizeof(info->bus_info)); 532} 533 534static int netsec_et_get_coalesce(struct net_device *net_device, 535 struct ethtool_coalesce *et_coalesce) 536{ 537 struct netsec_priv *priv = netdev_priv(net_device); 538 539 *et_coalesce = priv->et_coalesce; 540 541 return 0; 542} 543 544static int netsec_et_set_coalesce(struct net_device *net_device, 545 struct ethtool_coalesce *et_coalesce) 546{ 547 struct netsec_priv *priv = netdev_priv(net_device); 548 549 priv->et_coalesce = *et_coalesce; 550 551 if (priv->et_coalesce.tx_coalesce_usecs < 50) 552 priv->et_coalesce.tx_coalesce_usecs = 50; 553 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 554 priv->et_coalesce.tx_max_coalesced_frames = 1; 555 556 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 557 priv->et_coalesce.tx_max_coalesced_frames); 558 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 559 priv->et_coalesce.tx_coalesce_usecs); 560 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 561 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 562 563 if (priv->et_coalesce.rx_coalesce_usecs < 50) 564 priv->et_coalesce.rx_coalesce_usecs = 50; 565 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 566 priv->et_coalesce.rx_max_coalesced_frames = 1; 567 568 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 569 priv->et_coalesce.rx_max_coalesced_frames); 570 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 571 priv->et_coalesce.rx_coalesce_usecs); 572 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 573 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 574 575 return 0; 576} 577 578static u32 netsec_et_get_msglevel(struct net_device *dev) 579{ 580 struct netsec_priv *priv = netdev_priv(dev); 581 582 return priv->msg_enable; 583} 584 585static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 586{ 587 struct netsec_priv *priv = netdev_priv(dev); 588 589 priv->msg_enable = datum; 590} 591 592static const struct ethtool_ops netsec_ethtool_ops = { 593 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 594 ETHTOOL_COALESCE_MAX_FRAMES, 595 .get_drvinfo = netsec_et_get_drvinfo, 596 .get_link_ksettings = phy_ethtool_get_link_ksettings, 597 .set_link_ksettings = phy_ethtool_set_link_ksettings, 598 .get_link = ethtool_op_get_link, 599 .get_coalesce = netsec_et_get_coalesce, 600 .set_coalesce = netsec_et_set_coalesce, 601 .get_msglevel = netsec_et_get_msglevel, 602 .set_msglevel = netsec_et_set_msglevel, 603}; 604 605/************* NETDEV_OPS FOLLOW *************/ 606 607 608static void netsec_set_rx_de(struct netsec_priv *priv, 609 struct netsec_desc_ring *dring, u16 idx, 610 const struct netsec_desc *desc) 611{ 612 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 613 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 614 (1 << NETSEC_RX_PKT_FS_FIELD) | 615 (1 << NETSEC_RX_PKT_LS_FIELD); 616 617 if (idx == DESC_NUM - 1) 618 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 619 620 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 621 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 622 de->buf_len_info = desc->len; 623 de->attr = attr; 624 dma_wmb(); 625 626 dring->desc[idx].dma_addr = desc->dma_addr; 627 dring->desc[idx].addr = desc->addr; 628 dring->desc[idx].len = desc->len; 629} 630 631static bool netsec_clean_tx_dring(struct netsec_priv *priv) 632{ 633 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 634 struct netsec_de *entry; 635 int tail = dring->tail; 636 unsigned int bytes; 637 int cnt = 0; 638 639 spin_lock(&dring->lock); 640 641 bytes = 0; 642 entry = dring->vaddr + DESC_SZ * tail; 643 644 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) && 645 cnt < DESC_NUM) { 646 struct netsec_desc *desc; 647 int eop; 648 649 desc = &dring->desc[tail]; 650 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 651 dma_rmb(); 652 653 /* if buf_type is either TYPE_NETSEC_SKB or 654 * TYPE_NETSEC_XDP_NDO we mapped it 655 */ 656 if (desc->buf_type != TYPE_NETSEC_XDP_TX) 657 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 658 DMA_TO_DEVICE); 659 660 if (!eop) 661 goto next; 662 663 if (desc->buf_type == TYPE_NETSEC_SKB) { 664 bytes += desc->skb->len; 665 dev_kfree_skb(desc->skb); 666 } else { 667 bytes += desc->xdpf->len; 668 xdp_return_frame(desc->xdpf); 669 } 670next: 671 /* clean up so netsec_uninit_pkt_dring() won't free the skb 672 * again 673 */ 674 *desc = (struct netsec_desc){}; 675 676 /* entry->attr is not going to be accessed by the NIC until 677 * netsec_set_tx_de() is called. No need for a dma_wmb() here 678 */ 679 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 680 /* move tail ahead */ 681 dring->tail = (tail + 1) % DESC_NUM; 682 683 tail = dring->tail; 684 entry = dring->vaddr + DESC_SZ * tail; 685 cnt++; 686 } 687 688 spin_unlock(&dring->lock); 689 690 if (!cnt) 691 return false; 692 693 /* reading the register clears the irq */ 694 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 695 696 priv->ndev->stats.tx_packets += cnt; 697 priv->ndev->stats.tx_bytes += bytes; 698 699 netdev_completed_queue(priv->ndev, cnt, bytes); 700 701 return true; 702} 703 704static void netsec_process_tx(struct netsec_priv *priv) 705{ 706 struct net_device *ndev = priv->ndev; 707 bool cleaned; 708 709 cleaned = netsec_clean_tx_dring(priv); 710 711 if (cleaned && netif_queue_stopped(ndev)) { 712 /* Make sure we update the value, anyone stopping the queue 713 * after this will read the proper consumer idx 714 */ 715 smp_wmb(); 716 netif_wake_queue(ndev); 717 } 718} 719 720static void *netsec_alloc_rx_data(struct netsec_priv *priv, 721 dma_addr_t *dma_handle, u16 *desc_len) 722 723{ 724 725 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 726 struct page *page; 727 728 page = page_pool_dev_alloc_pages(dring->page_pool); 729 if (!page) 730 return NULL; 731 732 /* We allocate the same buffer length for XDP and non-XDP cases. 733 * page_pool API will map the whole page, skip what's needed for 734 * network payloads and/or XDP 735 */ 736 *dma_handle = page_pool_get_dma_addr(page) + NETSEC_RXBUF_HEADROOM; 737 /* Make sure the incoming payload fits in the page for XDP and non-XDP 738 * cases and reserve enough space for headroom + skb_shared_info 739 */ 740 *desc_len = NETSEC_RX_BUF_SIZE; 741 742 return page_address(page); 743} 744 745static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num) 746{ 747 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 748 u16 idx = from; 749 750 while (num) { 751 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]); 752 idx++; 753 if (idx >= DESC_NUM) 754 idx = 0; 755 num--; 756 } 757} 758 759static void netsec_xdp_ring_tx_db(struct netsec_priv *priv, u16 pkts) 760{ 761 if (likely(pkts)) 762 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts); 763} 764 765static void netsec_finalize_xdp_rx(struct netsec_priv *priv, u32 xdp_res, 766 u16 pkts) 767{ 768 if (xdp_res & NETSEC_XDP_REDIR) 769 xdp_do_flush_map(); 770 771 if (xdp_res & NETSEC_XDP_TX) 772 netsec_xdp_ring_tx_db(priv, pkts); 773} 774 775static void netsec_set_tx_de(struct netsec_priv *priv, 776 struct netsec_desc_ring *dring, 777 const struct netsec_tx_pkt_ctrl *tx_ctrl, 778 const struct netsec_desc *desc, void *buf) 779{ 780 int idx = dring->head; 781 struct netsec_de *de; 782 u32 attr; 783 784 de = dring->vaddr + (DESC_SZ * idx); 785 786 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 787 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 788 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 789 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 790 (1 << NETSEC_TX_LAST) | 791 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 792 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 793 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 794 if (idx == DESC_NUM - 1) 795 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 796 797 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 798 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 799 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 800 de->attr = attr; 801 802 dring->desc[idx] = *desc; 803 if (desc->buf_type == TYPE_NETSEC_SKB) 804 dring->desc[idx].skb = buf; 805 else if (desc->buf_type == TYPE_NETSEC_XDP_TX || 806 desc->buf_type == TYPE_NETSEC_XDP_NDO) 807 dring->desc[idx].xdpf = buf; 808 809 /* move head ahead */ 810 dring->head = (dring->head + 1) % DESC_NUM; 811} 812 813/* The current driver only supports 1 Txq, this should run under spin_lock() */ 814static u32 netsec_xdp_queue_one(struct netsec_priv *priv, 815 struct xdp_frame *xdpf, bool is_ndo) 816 817{ 818 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 819 struct page *page = virt_to_page(xdpf->data); 820 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 821 struct netsec_desc tx_desc; 822 dma_addr_t dma_handle; 823 u16 filled; 824 825 if (tx_ring->head >= tx_ring->tail) 826 filled = tx_ring->head - tx_ring->tail; 827 else 828 filled = tx_ring->head + DESC_NUM - tx_ring->tail; 829 830 if (DESC_NUM - filled <= 1) 831 return NETSEC_XDP_CONSUMED; 832 833 if (is_ndo) { 834 /* this is for ndo_xdp_xmit, the buffer needs mapping before 835 * sending 836 */ 837 dma_handle = dma_map_single(priv->dev, xdpf->data, xdpf->len, 838 DMA_TO_DEVICE); 839 if (dma_mapping_error(priv->dev, dma_handle)) 840 return NETSEC_XDP_CONSUMED; 841 tx_desc.buf_type = TYPE_NETSEC_XDP_NDO; 842 } else { 843 /* This is the device Rx buffer from page_pool. No need to remap 844 * just sync and send it 845 */ 846 struct netsec_desc_ring *rx_ring = 847 &priv->desc_ring[NETSEC_RING_RX]; 848 enum dma_data_direction dma_dir = 849 page_pool_get_dma_dir(rx_ring->page_pool); 850 851 dma_handle = page_pool_get_dma_addr(page) + xdpf->headroom + 852 sizeof(*xdpf); 853 dma_sync_single_for_device(priv->dev, dma_handle, xdpf->len, 854 dma_dir); 855 tx_desc.buf_type = TYPE_NETSEC_XDP_TX; 856 } 857 858 tx_desc.dma_addr = dma_handle; 859 tx_desc.addr = xdpf->data; 860 tx_desc.len = xdpf->len; 861 862 netdev_sent_queue(priv->ndev, xdpf->len); 863 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf); 864 865 return NETSEC_XDP_TX; 866} 867 868static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp) 869{ 870 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 871 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 872 u32 ret; 873 874 if (unlikely(!xdpf)) 875 return NETSEC_XDP_CONSUMED; 876 877 spin_lock(&tx_ring->lock); 878 ret = netsec_xdp_queue_one(priv, xdpf, false); 879 spin_unlock(&tx_ring->lock); 880 881 return ret; 882} 883 884static u32 netsec_run_xdp(struct netsec_priv *priv, struct bpf_prog *prog, 885 struct xdp_buff *xdp) 886{ 887 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 888 unsigned int sync, len = xdp->data_end - xdp->data; 889 u32 ret = NETSEC_XDP_PASS; 890 struct page *page; 891 int err; 892 u32 act; 893 894 act = bpf_prog_run_xdp(prog, xdp); 895 896 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 897 sync = xdp->data_end - xdp->data_hard_start - NETSEC_RXBUF_HEADROOM; 898 sync = max(sync, len); 899 900 switch (act) { 901 case XDP_PASS: 902 ret = NETSEC_XDP_PASS; 903 break; 904 case XDP_TX: 905 ret = netsec_xdp_xmit_back(priv, xdp); 906 if (ret != NETSEC_XDP_TX) { 907 page = virt_to_head_page(xdp->data); 908 page_pool_put_page(dring->page_pool, page, sync, true); 909 } 910 break; 911 case XDP_REDIRECT: 912 err = xdp_do_redirect(priv->ndev, xdp, prog); 913 if (!err) { 914 ret = NETSEC_XDP_REDIR; 915 } else { 916 ret = NETSEC_XDP_CONSUMED; 917 page = virt_to_head_page(xdp->data); 918 page_pool_put_page(dring->page_pool, page, sync, true); 919 } 920 break; 921 default: 922 bpf_warn_invalid_xdp_action(act); 923 fallthrough; 924 case XDP_ABORTED: 925 trace_xdp_exception(priv->ndev, prog, act); 926 fallthrough; /* handle aborts by dropping packet */ 927 case XDP_DROP: 928 ret = NETSEC_XDP_CONSUMED; 929 page = virt_to_head_page(xdp->data); 930 page_pool_put_page(dring->page_pool, page, sync, true); 931 break; 932 } 933 934 return ret; 935} 936 937static int netsec_process_rx(struct netsec_priv *priv, int budget) 938{ 939 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 940 struct net_device *ndev = priv->ndev; 941 struct netsec_rx_pkt_info rx_info; 942 enum dma_data_direction dma_dir; 943 struct bpf_prog *xdp_prog; 944 struct xdp_buff xdp; 945 u16 xdp_xmit = 0; 946 u32 xdp_act = 0; 947 int done = 0; 948 949 xdp.rxq = &dring->xdp_rxq; 950 xdp.frame_sz = PAGE_SIZE; 951 952 rcu_read_lock(); 953 xdp_prog = READ_ONCE(priv->xdp_prog); 954 dma_dir = page_pool_get_dma_dir(dring->page_pool); 955 956 while (done < budget) { 957 u16 idx = dring->tail; 958 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 959 struct netsec_desc *desc = &dring->desc[idx]; 960 struct page *page = virt_to_page(desc->addr); 961 u32 xdp_result = NETSEC_XDP_PASS; 962 struct sk_buff *skb = NULL; 963 u16 pkt_len, desc_len; 964 dma_addr_t dma_handle; 965 void *buf_addr; 966 967 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 968 /* reading the register clears the irq */ 969 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 970 break; 971 } 972 973 /* This barrier is needed to keep us from reading 974 * any other fields out of the netsec_de until we have 975 * verified the descriptor has been written back 976 */ 977 dma_rmb(); 978 done++; 979 980 pkt_len = de->buf_len_info >> 16; 981 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) & 982 NETSEC_RX_PKT_ERR_MASK; 983 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 984 if (rx_info.err_flag) { 985 netif_err(priv, drv, priv->ndev, 986 "%s: rx fail err(%d)\n", __func__, 987 rx_info.err_code); 988 ndev->stats.rx_dropped++; 989 dring->tail = (dring->tail + 1) % DESC_NUM; 990 /* reuse buffer page frag */ 991 netsec_rx_fill(priv, idx, 1); 992 continue; 993 } 994 rx_info.rx_cksum_result = 995 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 996 997 /* allocate a fresh buffer and map it to the hardware. 998 * This will eventually replace the old buffer in the hardware 999 */ 1000 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len); 1001 1002 if (unlikely(!buf_addr)) 1003 break; 1004 1005 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len, 1006 dma_dir); 1007 prefetch(desc->addr); 1008 1009 xdp.data_hard_start = desc->addr; 1010 xdp.data = desc->addr + NETSEC_RXBUF_HEADROOM; 1011 xdp_set_data_meta_invalid(&xdp); 1012 xdp.data_end = xdp.data + pkt_len; 1013 1014 if (xdp_prog) { 1015 xdp_result = netsec_run_xdp(priv, xdp_prog, &xdp); 1016 if (xdp_result != NETSEC_XDP_PASS) { 1017 xdp_act |= xdp_result; 1018 if (xdp_result == NETSEC_XDP_TX) 1019 xdp_xmit++; 1020 goto next; 1021 } 1022 } 1023 skb = build_skb(desc->addr, desc->len + NETSEC_RX_BUF_NON_DATA); 1024 1025 if (unlikely(!skb)) { 1026 /* If skb fails recycle_direct will either unmap and 1027 * free the page or refill the cache depending on the 1028 * cache state. Since we paid the allocation cost if 1029 * building an skb fails try to put the page into cache 1030 */ 1031 page_pool_put_page(dring->page_pool, page, pkt_len, 1032 true); 1033 netif_err(priv, drv, priv->ndev, 1034 "rx failed to build skb\n"); 1035 break; 1036 } 1037 page_pool_release_page(dring->page_pool, page); 1038 1039 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1040 skb_put(skb, xdp.data_end - xdp.data); 1041 skb->protocol = eth_type_trans(skb, priv->ndev); 1042 1043 if (priv->rx_cksum_offload_flag && 1044 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 1045 skb->ip_summed = CHECKSUM_UNNECESSARY; 1046 1047next: 1048 if (skb) 1049 napi_gro_receive(&priv->napi, skb); 1050 if (skb || xdp_result) { 1051 ndev->stats.rx_packets++; 1052 ndev->stats.rx_bytes += xdp.data_end - xdp.data; 1053 } 1054 1055 /* Update the descriptor with fresh buffers */ 1056 desc->len = desc_len; 1057 desc->dma_addr = dma_handle; 1058 desc->addr = buf_addr; 1059 1060 netsec_rx_fill(priv, idx, 1); 1061 dring->tail = (dring->tail + 1) % DESC_NUM; 1062 } 1063 netsec_finalize_xdp_rx(priv, xdp_act, xdp_xmit); 1064 1065 rcu_read_unlock(); 1066 1067 return done; 1068} 1069 1070static int netsec_napi_poll(struct napi_struct *napi, int budget) 1071{ 1072 struct netsec_priv *priv; 1073 int done; 1074 1075 priv = container_of(napi, struct netsec_priv, napi); 1076 1077 netsec_process_tx(priv); 1078 done = netsec_process_rx(priv, budget); 1079 1080 if (done < budget && napi_complete_done(napi, done)) { 1081 unsigned long flags; 1082 1083 spin_lock_irqsave(&priv->reglock, flags); 1084 netsec_write(priv, NETSEC_REG_INTEN_SET, 1085 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1086 spin_unlock_irqrestore(&priv->reglock, flags); 1087 } 1088 1089 return done; 1090} 1091 1092 1093static int netsec_desc_used(struct netsec_desc_ring *dring) 1094{ 1095 int used; 1096 1097 if (dring->head >= dring->tail) 1098 used = dring->head - dring->tail; 1099 else 1100 used = dring->head + DESC_NUM - dring->tail; 1101 1102 return used; 1103} 1104 1105static int netsec_check_stop_tx(struct netsec_priv *priv, int used) 1106{ 1107 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1108 1109 /* keep tail from touching the queue */ 1110 if (DESC_NUM - used < 2) { 1111 netif_stop_queue(priv->ndev); 1112 1113 /* Make sure we read the updated value in case 1114 * descriptors got freed 1115 */ 1116 smp_rmb(); 1117 1118 used = netsec_desc_used(dring); 1119 if (DESC_NUM - used < 2) 1120 return NETDEV_TX_BUSY; 1121 1122 netif_wake_queue(priv->ndev); 1123 } 1124 1125 return 0; 1126} 1127 1128static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 1129 struct net_device *ndev) 1130{ 1131 struct netsec_priv *priv = netdev_priv(ndev); 1132 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1133 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 1134 struct netsec_desc tx_desc; 1135 u16 tso_seg_len = 0; 1136 int filled; 1137 1138 spin_lock_bh(&dring->lock); 1139 filled = netsec_desc_used(dring); 1140 if (netsec_check_stop_tx(priv, filled)) { 1141 spin_unlock_bh(&dring->lock); 1142 net_warn_ratelimited("%s %s Tx queue full\n", 1143 dev_name(priv->dev), ndev->name); 1144 return NETDEV_TX_BUSY; 1145 } 1146 1147 if (skb->ip_summed == CHECKSUM_PARTIAL) 1148 tx_ctrl.cksum_offload_flag = true; 1149 1150 if (skb_is_gso(skb)) 1151 tso_seg_len = skb_shinfo(skb)->gso_size; 1152 1153 if (tso_seg_len > 0) { 1154 if (skb->protocol == htons(ETH_P_IP)) { 1155 ip_hdr(skb)->tot_len = 0; 1156 tcp_hdr(skb)->check = 1157 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 1158 ip_hdr(skb)->daddr, 0); 1159 } else { 1160 tcp_v6_gso_csum_prep(skb); 1161 } 1162 1163 tx_ctrl.tcp_seg_offload_flag = true; 1164 tx_ctrl.tcp_seg_len = tso_seg_len; 1165 } 1166 1167 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 1168 skb_headlen(skb), DMA_TO_DEVICE); 1169 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 1170 spin_unlock_bh(&dring->lock); 1171 netif_err(priv, drv, priv->ndev, 1172 "%s: DMA mapping failed\n", __func__); 1173 ndev->stats.tx_dropped++; 1174 dev_kfree_skb_any(skb); 1175 return NETDEV_TX_OK; 1176 } 1177 tx_desc.addr = skb->data; 1178 tx_desc.len = skb_headlen(skb); 1179 tx_desc.buf_type = TYPE_NETSEC_SKB; 1180 1181 skb_tx_timestamp(skb); 1182 netdev_sent_queue(priv->ndev, skb->len); 1183 1184 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 1185 spin_unlock_bh(&dring->lock); 1186 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 1187 1188 return NETDEV_TX_OK; 1189} 1190 1191static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 1192{ 1193 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1194 struct netsec_desc *desc; 1195 u16 idx; 1196 1197 if (!dring->vaddr || !dring->desc) 1198 return; 1199 for (idx = 0; idx < DESC_NUM; idx++) { 1200 desc = &dring->desc[idx]; 1201 if (!desc->addr) 1202 continue; 1203 1204 if (id == NETSEC_RING_RX) { 1205 struct page *page = virt_to_page(desc->addr); 1206 1207 page_pool_put_full_page(dring->page_pool, page, false); 1208 } else if (id == NETSEC_RING_TX) { 1209 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 1210 DMA_TO_DEVICE); 1211 dev_kfree_skb(desc->skb); 1212 } 1213 } 1214 1215 /* Rx is currently using page_pool */ 1216 if (id == NETSEC_RING_RX) { 1217 if (xdp_rxq_info_is_reg(&dring->xdp_rxq)) 1218 xdp_rxq_info_unreg(&dring->xdp_rxq); 1219 page_pool_destroy(dring->page_pool); 1220 } 1221 1222 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 1223 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 1224 1225 dring->head = 0; 1226 dring->tail = 0; 1227 1228 if (id == NETSEC_RING_TX) 1229 netdev_reset_queue(priv->ndev); 1230} 1231 1232static void netsec_free_dring(struct netsec_priv *priv, int id) 1233{ 1234 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1235 1236 if (dring->vaddr) { 1237 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 1238 dring->vaddr, dring->desc_dma); 1239 dring->vaddr = NULL; 1240 } 1241 1242 kfree(dring->desc); 1243 dring->desc = NULL; 1244} 1245 1246static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 1247{ 1248 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1249 1250 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 1251 &dring->desc_dma, GFP_KERNEL); 1252 if (!dring->vaddr) 1253 goto err; 1254 1255 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 1256 if (!dring->desc) 1257 goto err; 1258 1259 return 0; 1260err: 1261 netsec_free_dring(priv, id); 1262 1263 return -ENOMEM; 1264} 1265 1266static void netsec_setup_tx_dring(struct netsec_priv *priv) 1267{ 1268 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1269 int i; 1270 1271 for (i = 0; i < DESC_NUM; i++) { 1272 struct netsec_de *de; 1273 1274 de = dring->vaddr + (DESC_SZ * i); 1275 /* de->attr is not going to be accessed by the NIC 1276 * until netsec_set_tx_de() is called. 1277 * No need for a dma_wmb() here 1278 */ 1279 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 1280 } 1281} 1282 1283static int netsec_setup_rx_dring(struct netsec_priv *priv) 1284{ 1285 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 1286 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog); 1287 struct page_pool_params pp_params = { 1288 .order = 0, 1289 /* internal DMA mapping in page_pool */ 1290 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1291 .pool_size = DESC_NUM, 1292 .nid = NUMA_NO_NODE, 1293 .dev = priv->dev, 1294 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 1295 .offset = NETSEC_RXBUF_HEADROOM, 1296 .max_len = NETSEC_RX_BUF_SIZE, 1297 }; 1298 int i, err; 1299 1300 dring->page_pool = page_pool_create(&pp_params); 1301 if (IS_ERR(dring->page_pool)) { 1302 err = PTR_ERR(dring->page_pool); 1303 dring->page_pool = NULL; 1304 goto err_out; 1305 } 1306 1307 err = xdp_rxq_info_reg(&dring->xdp_rxq, priv->ndev, 0); 1308 if (err) 1309 goto err_out; 1310 1311 err = xdp_rxq_info_reg_mem_model(&dring->xdp_rxq, MEM_TYPE_PAGE_POOL, 1312 dring->page_pool); 1313 if (err) 1314 goto err_out; 1315 1316 for (i = 0; i < DESC_NUM; i++) { 1317 struct netsec_desc *desc = &dring->desc[i]; 1318 dma_addr_t dma_handle; 1319 void *buf; 1320 u16 len; 1321 1322 buf = netsec_alloc_rx_data(priv, &dma_handle, &len); 1323 1324 if (!buf) { 1325 err = -ENOMEM; 1326 goto err_out; 1327 } 1328 desc->dma_addr = dma_handle; 1329 desc->addr = buf; 1330 desc->len = len; 1331 } 1332 1333 netsec_rx_fill(priv, 0, DESC_NUM); 1334 1335 return 0; 1336 1337err_out: 1338 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1339 return err; 1340} 1341 1342static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1343 u32 addr_h, u32 addr_l, u32 size) 1344{ 1345 u64 base = (u64)addr_h << 32 | addr_l; 1346 void __iomem *ucode; 1347 u32 i; 1348 1349 ucode = ioremap(base, size * sizeof(u32)); 1350 if (!ucode) 1351 return -ENOMEM; 1352 1353 for (i = 0; i < size; i++) 1354 netsec_write(priv, reg, readl(ucode + i * 4)); 1355 1356 iounmap(ucode); 1357 return 0; 1358} 1359 1360static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1361{ 1362 u32 addr_h, addr_l, size; 1363 int err; 1364 1365 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1366 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1367 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1368 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1369 addr_h, addr_l, size); 1370 if (err) 1371 return err; 1372 1373 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1374 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1375 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1376 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1377 addr_h, addr_l, size); 1378 if (err) 1379 return err; 1380 1381 addr_h = 0; 1382 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1383 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1384 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1385 addr_h, addr_l, size); 1386 if (err) 1387 return err; 1388 1389 return 0; 1390} 1391 1392static int netsec_reset_hardware(struct netsec_priv *priv, 1393 bool load_ucode) 1394{ 1395 u32 value; 1396 int err; 1397 1398 /* stop DMA engines */ 1399 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1400 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1401 NETSEC_DMA_CTRL_REG_STOP); 1402 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1403 NETSEC_DMA_CTRL_REG_STOP); 1404 1405 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1406 NETSEC_DMA_CTRL_REG_STOP) 1407 cpu_relax(); 1408 1409 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1410 NETSEC_DMA_CTRL_REG_STOP) 1411 cpu_relax(); 1412 } 1413 1414 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1415 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1416 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1417 1418 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1419 cpu_relax(); 1420 1421 /* set desc_start addr */ 1422 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1423 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1424 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1425 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1426 1427 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1428 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1429 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1430 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1431 1432 /* set normal tx dring ring config */ 1433 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1434 1 << NETSEC_REG_DESC_ENDIAN); 1435 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1436 1 << NETSEC_REG_DESC_ENDIAN); 1437 1438 if (load_ucode) { 1439 err = netsec_netdev_load_microcode(priv); 1440 if (err) { 1441 netif_err(priv, probe, priv->ndev, 1442 "%s: failed to load microcode (%d)\n", 1443 __func__, err); 1444 return err; 1445 } 1446 } 1447 1448 /* start DMA engines */ 1449 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1450 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1451 1452 usleep_range(1000, 2000); 1453 1454 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1455 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1456 netif_err(priv, probe, priv->ndev, 1457 "microengine start failed\n"); 1458 return -ENXIO; 1459 } 1460 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1461 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1462 1463 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1464 if (priv->ndev->mtu > ETH_DATA_LEN) 1465 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1466 1467 /* change to normal mode */ 1468 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1469 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1470 1471 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1472 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1473 cpu_relax(); 1474 1475 /* clear any pending EMPTY/ERR irq status */ 1476 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1477 1478 /* Disable TX & RX intr */ 1479 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1480 1481 return 0; 1482} 1483 1484static int netsec_start_gmac(struct netsec_priv *priv) 1485{ 1486 struct phy_device *phydev = priv->ndev->phydev; 1487 u32 value = 0; 1488 int ret; 1489 1490 if (phydev->speed != SPEED_1000) 1491 value = (NETSEC_GMAC_MCR_REG_CST | 1492 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1493 1494 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1495 return -ETIMEDOUT; 1496 if (netsec_mac_write(priv, GMAC_REG_BMR, 1497 NETSEC_GMAC_BMR_REG_RESET)) 1498 return -ETIMEDOUT; 1499 1500 /* Wait soft reset */ 1501 usleep_range(1000, 5000); 1502 1503 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1504 if (ret) 1505 return ret; 1506 if (value & NETSEC_GMAC_BMR_REG_SWR) 1507 return -EAGAIN; 1508 1509 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1510 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1511 return -ETIMEDOUT; 1512 1513 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1514 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1515 return -ETIMEDOUT; 1516 1517 if (netsec_mac_write(priv, GMAC_REG_BMR, 1518 NETSEC_GMAC_BMR_REG_COMMON)) 1519 return -ETIMEDOUT; 1520 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1521 NETSEC_GMAC_RDLAR_REG_COMMON)) 1522 return -ETIMEDOUT; 1523 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1524 NETSEC_GMAC_TDLAR_REG_COMMON)) 1525 return -ETIMEDOUT; 1526 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1527 return -ETIMEDOUT; 1528 1529 ret = netsec_mac_update_to_phy_state(priv); 1530 if (ret) 1531 return ret; 1532 1533 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1534 if (ret) 1535 return ret; 1536 1537 value |= NETSEC_GMAC_OMR_REG_SR; 1538 value |= NETSEC_GMAC_OMR_REG_ST; 1539 1540 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1541 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1542 1543 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1544 1545 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1546 return -ETIMEDOUT; 1547 1548 return 0; 1549} 1550 1551static int netsec_stop_gmac(struct netsec_priv *priv) 1552{ 1553 u32 value; 1554 int ret; 1555 1556 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1557 if (ret) 1558 return ret; 1559 value &= ~NETSEC_GMAC_OMR_REG_SR; 1560 value &= ~NETSEC_GMAC_OMR_REG_ST; 1561 1562 /* disable all interrupts */ 1563 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1564 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1565 1566 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1567} 1568 1569static void netsec_phy_adjust_link(struct net_device *ndev) 1570{ 1571 struct netsec_priv *priv = netdev_priv(ndev); 1572 1573 if (ndev->phydev->link) 1574 netsec_start_gmac(priv); 1575 else 1576 netsec_stop_gmac(priv); 1577 1578 phy_print_status(ndev->phydev); 1579} 1580 1581static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1582{ 1583 struct netsec_priv *priv = dev_id; 1584 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1585 unsigned long flags; 1586 1587 /* Disable interrupts */ 1588 if (status & NETSEC_IRQ_TX) { 1589 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1590 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1591 } 1592 if (status & NETSEC_IRQ_RX) { 1593 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1594 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1595 } 1596 1597 spin_lock_irqsave(&priv->reglock, flags); 1598 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1599 spin_unlock_irqrestore(&priv->reglock, flags); 1600 1601 napi_schedule(&priv->napi); 1602 1603 return IRQ_HANDLED; 1604} 1605 1606static int netsec_netdev_open(struct net_device *ndev) 1607{ 1608 struct netsec_priv *priv = netdev_priv(ndev); 1609 int ret; 1610 1611 pm_runtime_get_sync(priv->dev); 1612 1613 netsec_setup_tx_dring(priv); 1614 ret = netsec_setup_rx_dring(priv); 1615 if (ret) { 1616 netif_err(priv, probe, priv->ndev, 1617 "%s: fail setup ring\n", __func__); 1618 goto err1; 1619 } 1620 1621 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1622 IRQF_SHARED, "netsec", priv); 1623 if (ret) { 1624 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1625 goto err2; 1626 } 1627 1628 if (dev_of_node(priv->dev)) { 1629 if (!of_phy_connect(priv->ndev, priv->phy_np, 1630 netsec_phy_adjust_link, 0, 1631 priv->phy_interface)) { 1632 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1633 ret = -ENODEV; 1634 goto err3; 1635 } 1636 } else { 1637 ret = phy_connect_direct(priv->ndev, priv->phydev, 1638 netsec_phy_adjust_link, 1639 priv->phy_interface); 1640 if (ret) { 1641 netif_err(priv, link, priv->ndev, 1642 "phy_connect_direct() failed (%d)\n", ret); 1643 goto err3; 1644 } 1645 } 1646 1647 phy_start(ndev->phydev); 1648 1649 netsec_start_gmac(priv); 1650 napi_enable(&priv->napi); 1651 netif_start_queue(ndev); 1652 1653 /* Enable TX+RX intr. */ 1654 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1655 1656 return 0; 1657err3: 1658 free_irq(priv->ndev->irq, priv); 1659err2: 1660 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1661err1: 1662 pm_runtime_put_sync(priv->dev); 1663 return ret; 1664} 1665 1666static int netsec_netdev_stop(struct net_device *ndev) 1667{ 1668 int ret; 1669 struct netsec_priv *priv = netdev_priv(ndev); 1670 1671 netif_stop_queue(priv->ndev); 1672 dma_wmb(); 1673 1674 napi_disable(&priv->napi); 1675 1676 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1677 netsec_stop_gmac(priv); 1678 1679 free_irq(priv->ndev->irq, priv); 1680 1681 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1682 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1683 1684 phy_stop(ndev->phydev); 1685 phy_disconnect(ndev->phydev); 1686 1687 ret = netsec_reset_hardware(priv, false); 1688 1689 pm_runtime_put_sync(priv->dev); 1690 1691 return ret; 1692} 1693 1694static int netsec_netdev_init(struct net_device *ndev) 1695{ 1696 struct netsec_priv *priv = netdev_priv(ndev); 1697 int ret; 1698 u16 data; 1699 1700 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM); 1701 1702 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1703 if (ret) 1704 return ret; 1705 1706 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1707 if (ret) 1708 goto err1; 1709 1710 /* set phy power down */ 1711 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR); 1712 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, 1713 data | BMCR_PDOWN); 1714 1715 ret = netsec_reset_hardware(priv, true); 1716 if (ret) 1717 goto err2; 1718 1719 /* Restore phy power state */ 1720 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data); 1721 1722 spin_lock_init(&priv->desc_ring[NETSEC_RING_TX].lock); 1723 spin_lock_init(&priv->desc_ring[NETSEC_RING_RX].lock); 1724 1725 return 0; 1726err2: 1727 netsec_free_dring(priv, NETSEC_RING_RX); 1728err1: 1729 netsec_free_dring(priv, NETSEC_RING_TX); 1730 return ret; 1731} 1732 1733static void netsec_netdev_uninit(struct net_device *ndev) 1734{ 1735 struct netsec_priv *priv = netdev_priv(ndev); 1736 1737 netsec_free_dring(priv, NETSEC_RING_RX); 1738 netsec_free_dring(priv, NETSEC_RING_TX); 1739} 1740 1741static int netsec_netdev_set_features(struct net_device *ndev, 1742 netdev_features_t features) 1743{ 1744 struct netsec_priv *priv = netdev_priv(ndev); 1745 1746 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1747 1748 return 0; 1749} 1750 1751static int netsec_xdp_xmit(struct net_device *ndev, int n, 1752 struct xdp_frame **frames, u32 flags) 1753{ 1754 struct netsec_priv *priv = netdev_priv(ndev); 1755 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 1756 int drops = 0; 1757 int i; 1758 1759 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1760 return -EINVAL; 1761 1762 spin_lock(&tx_ring->lock); 1763 for (i = 0; i < n; i++) { 1764 struct xdp_frame *xdpf = frames[i]; 1765 int err; 1766 1767 err = netsec_xdp_queue_one(priv, xdpf, true); 1768 if (err != NETSEC_XDP_TX) { 1769 xdp_return_frame_rx_napi(xdpf); 1770 drops++; 1771 } else { 1772 tx_ring->xdp_xmit++; 1773 } 1774 } 1775 spin_unlock(&tx_ring->lock); 1776 1777 if (unlikely(flags & XDP_XMIT_FLUSH)) { 1778 netsec_xdp_ring_tx_db(priv, tx_ring->xdp_xmit); 1779 tx_ring->xdp_xmit = 0; 1780 } 1781 1782 return n - drops; 1783} 1784 1785static int netsec_xdp_setup(struct netsec_priv *priv, struct bpf_prog *prog, 1786 struct netlink_ext_ack *extack) 1787{ 1788 struct net_device *dev = priv->ndev; 1789 struct bpf_prog *old_prog; 1790 1791 /* For now just support only the usual MTU sized frames */ 1792 if (prog && dev->mtu > 1500) { 1793 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 1794 return -EOPNOTSUPP; 1795 } 1796 1797 if (netif_running(dev)) 1798 netsec_netdev_stop(dev); 1799 1800 /* Detach old prog, if any */ 1801 old_prog = xchg(&priv->xdp_prog, prog); 1802 if (old_prog) 1803 bpf_prog_put(old_prog); 1804 1805 if (netif_running(dev)) 1806 netsec_netdev_open(dev); 1807 1808 return 0; 1809} 1810 1811static int netsec_xdp(struct net_device *ndev, struct netdev_bpf *xdp) 1812{ 1813 struct netsec_priv *priv = netdev_priv(ndev); 1814 1815 switch (xdp->command) { 1816 case XDP_SETUP_PROG: 1817 return netsec_xdp_setup(priv, xdp->prog, xdp->extack); 1818 default: 1819 return -EINVAL; 1820 } 1821} 1822 1823static const struct net_device_ops netsec_netdev_ops = { 1824 .ndo_init = netsec_netdev_init, 1825 .ndo_uninit = netsec_netdev_uninit, 1826 .ndo_open = netsec_netdev_open, 1827 .ndo_stop = netsec_netdev_stop, 1828 .ndo_start_xmit = netsec_netdev_start_xmit, 1829 .ndo_set_features = netsec_netdev_set_features, 1830 .ndo_set_mac_address = eth_mac_addr, 1831 .ndo_validate_addr = eth_validate_addr, 1832 .ndo_do_ioctl = phy_do_ioctl, 1833 .ndo_xdp_xmit = netsec_xdp_xmit, 1834 .ndo_bpf = netsec_xdp, 1835}; 1836 1837static int netsec_of_probe(struct platform_device *pdev, 1838 struct netsec_priv *priv, u32 *phy_addr) 1839{ 1840 int err; 1841 1842 err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_interface); 1843 if (err) { 1844 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1845 return err; 1846 } 1847 1848 /* 1849 * SynQuacer is physically configured with TX and RX delays 1850 * but the standard firmware claimed otherwise for a long 1851 * time, ignore it. 1852 */ 1853 if (of_machine_is_compatible("socionext,developer-box") && 1854 priv->phy_interface != PHY_INTERFACE_MODE_RGMII_ID) { 1855 dev_warn(&pdev->dev, "Outdated firmware reports incorrect PHY mode, overriding\n"); 1856 priv->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 1857 } 1858 1859 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1860 if (!priv->phy_np) { 1861 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1862 return -EINVAL; 1863 } 1864 1865 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np); 1866 1867 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1868 if (IS_ERR(priv->clk)) { 1869 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1870 return PTR_ERR(priv->clk); 1871 } 1872 priv->freq = clk_get_rate(priv->clk); 1873 1874 return 0; 1875} 1876 1877static int netsec_acpi_probe(struct platform_device *pdev, 1878 struct netsec_priv *priv, u32 *phy_addr) 1879{ 1880 int ret; 1881 1882 if (!IS_ENABLED(CONFIG_ACPI)) 1883 return -ENODEV; 1884 1885 /* ACPI systems are assumed to configure the PHY in firmware, so 1886 * there is really no need to discover the PHY mode from the DSDT. 1887 * Since firmware is known to exist in the field that configures the 1888 * PHY correctly but passes the wrong mode string in the phy-mode 1889 * device property, we have no choice but to ignore it. 1890 */ 1891 priv->phy_interface = PHY_INTERFACE_MODE_NA; 1892 1893 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1894 if (ret) { 1895 dev_err(&pdev->dev, 1896 "missing required property 'phy-channel'\n"); 1897 return ret; 1898 } 1899 1900 ret = device_property_read_u32(&pdev->dev, 1901 "socionext,phy-clock-frequency", 1902 &priv->freq); 1903 if (ret) 1904 dev_err(&pdev->dev, 1905 "missing required property 'socionext,phy-clock-frequency'\n"); 1906 return ret; 1907} 1908 1909static void netsec_unregister_mdio(struct netsec_priv *priv) 1910{ 1911 struct phy_device *phydev = priv->phydev; 1912 1913 if (!dev_of_node(priv->dev) && phydev) { 1914 phy_device_remove(phydev); 1915 phy_device_free(phydev); 1916 } 1917 1918 mdiobus_unregister(priv->mii_bus); 1919} 1920 1921static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1922{ 1923 struct mii_bus *bus; 1924 int ret; 1925 1926 bus = devm_mdiobus_alloc(priv->dev); 1927 if (!bus) 1928 return -ENOMEM; 1929 1930 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1931 bus->priv = priv; 1932 bus->name = "SNI NETSEC MDIO"; 1933 bus->read = netsec_phy_read; 1934 bus->write = netsec_phy_write; 1935 bus->parent = priv->dev; 1936 priv->mii_bus = bus; 1937 1938 if (dev_of_node(priv->dev)) { 1939 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1940 1941 mdio_node = of_get_child_by_name(parent, "mdio"); 1942 if (mdio_node) { 1943 parent = mdio_node; 1944 } else { 1945 /* older f/w doesn't populate the mdio subnode, 1946 * allow relaxed upgrade of f/w in due time. 1947 */ 1948 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1949 } 1950 1951 ret = of_mdiobus_register(bus, parent); 1952 of_node_put(mdio_node); 1953 1954 if (ret) { 1955 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1956 return ret; 1957 } 1958 } else { 1959 /* Mask out all PHYs from auto probing. */ 1960 bus->phy_mask = ~0; 1961 ret = mdiobus_register(bus); 1962 if (ret) { 1963 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1964 return ret; 1965 } 1966 1967 priv->phydev = get_phy_device(bus, phy_addr, false); 1968 if (IS_ERR(priv->phydev)) { 1969 ret = PTR_ERR(priv->phydev); 1970 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1971 priv->phydev = NULL; 1972 mdiobus_unregister(bus); 1973 return -ENODEV; 1974 } 1975 1976 ret = phy_device_register(priv->phydev); 1977 if (ret) { 1978 phy_device_free(priv->phydev); 1979 mdiobus_unregister(bus); 1980 dev_err(priv->dev, 1981 "phy_device_register err(%d)\n", ret); 1982 } 1983 } 1984 1985 return ret; 1986} 1987 1988static int netsec_probe(struct platform_device *pdev) 1989{ 1990 struct resource *mmio_res, *eeprom_res, *irq_res; 1991 u8 *mac, macbuf[ETH_ALEN]; 1992 struct netsec_priv *priv; 1993 u32 hw_ver, phy_addr = 0; 1994 struct net_device *ndev; 1995 int ret; 1996 1997 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1998 if (!mmio_res) { 1999 dev_err(&pdev->dev, "No MMIO resource found.\n"); 2000 return -ENODEV; 2001 } 2002 2003 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2004 if (!eeprom_res) { 2005 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 2006 return -ENODEV; 2007 } 2008 2009 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2010 if (!irq_res) { 2011 dev_err(&pdev->dev, "No IRQ resource found.\n"); 2012 return -ENODEV; 2013 } 2014 2015 ndev = alloc_etherdev(sizeof(*priv)); 2016 if (!ndev) 2017 return -ENOMEM; 2018 2019 priv = netdev_priv(ndev); 2020 2021 spin_lock_init(&priv->reglock); 2022 SET_NETDEV_DEV(ndev, &pdev->dev); 2023 platform_set_drvdata(pdev, priv); 2024 ndev->irq = irq_res->start; 2025 priv->dev = &pdev->dev; 2026 priv->ndev = ndev; 2027 2028 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 2029 NETIF_MSG_LINK | NETIF_MSG_PROBE; 2030 2031 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 2032 resource_size(mmio_res)); 2033 if (!priv->ioaddr) { 2034 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 2035 ret = -ENXIO; 2036 goto free_ndev; 2037 } 2038 2039 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 2040 resource_size(eeprom_res)); 2041 if (!priv->eeprom_base) { 2042 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 2043 ret = -ENXIO; 2044 goto free_ndev; 2045 } 2046 2047 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 2048 if (mac) 2049 ether_addr_copy(ndev->dev_addr, mac); 2050 2051 if (priv->eeprom_base && 2052 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 2053 void __iomem *macp = priv->eeprom_base + 2054 NETSEC_EEPROM_MAC_ADDRESS; 2055 2056 ndev->dev_addr[0] = readb(macp + 3); 2057 ndev->dev_addr[1] = readb(macp + 2); 2058 ndev->dev_addr[2] = readb(macp + 1); 2059 ndev->dev_addr[3] = readb(macp + 0); 2060 ndev->dev_addr[4] = readb(macp + 7); 2061 ndev->dev_addr[5] = readb(macp + 6); 2062 } 2063 2064 if (!is_valid_ether_addr(ndev->dev_addr)) { 2065 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 2066 eth_hw_addr_random(ndev); 2067 } 2068 2069 if (dev_of_node(&pdev->dev)) 2070 ret = netsec_of_probe(pdev, priv, &phy_addr); 2071 else 2072 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 2073 if (ret) 2074 goto free_ndev; 2075 2076 priv->phy_addr = phy_addr; 2077 2078 if (!priv->freq) { 2079 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 2080 ret = -ENODEV; 2081 goto free_ndev; 2082 } 2083 2084 /* default for throughput */ 2085 priv->et_coalesce.rx_coalesce_usecs = 500; 2086 priv->et_coalesce.rx_max_coalesced_frames = 8; 2087 priv->et_coalesce.tx_coalesce_usecs = 500; 2088 priv->et_coalesce.tx_max_coalesced_frames = 8; 2089 2090 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 2091 &ndev->max_mtu); 2092 if (ret < 0) 2093 ndev->max_mtu = ETH_DATA_LEN; 2094 2095 /* runtime_pm coverage just for probe, open/close also cover it */ 2096 pm_runtime_enable(&pdev->dev); 2097 pm_runtime_get_sync(&pdev->dev); 2098 2099 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 2100 /* this driver only supports F_TAIKI style NETSEC */ 2101 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 2102 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 2103 ret = -ENODEV; 2104 goto pm_disable; 2105 } 2106 2107 dev_info(&pdev->dev, "hardware revision %d.%d\n", 2108 hw_ver >> 16, hw_ver & 0xffff); 2109 2110 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT); 2111 2112 ndev->netdev_ops = &netsec_netdev_ops; 2113 ndev->ethtool_ops = &netsec_ethtool_ops; 2114 2115 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 2116 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2117 ndev->hw_features = ndev->features; 2118 2119 priv->rx_cksum_offload_flag = true; 2120 2121 ret = netsec_register_mdio(priv, phy_addr); 2122 if (ret) 2123 goto unreg_napi; 2124 2125 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 2126 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 2127 2128 ret = register_netdev(ndev); 2129 if (ret) { 2130 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 2131 goto unreg_mii; 2132 } 2133 2134 pm_runtime_put_sync(&pdev->dev); 2135 return 0; 2136 2137unreg_mii: 2138 netsec_unregister_mdio(priv); 2139unreg_napi: 2140 netif_napi_del(&priv->napi); 2141pm_disable: 2142 pm_runtime_put_sync(&pdev->dev); 2143 pm_runtime_disable(&pdev->dev); 2144free_ndev: 2145 free_netdev(ndev); 2146 dev_err(&pdev->dev, "init failed\n"); 2147 2148 return ret; 2149} 2150 2151static int netsec_remove(struct platform_device *pdev) 2152{ 2153 struct netsec_priv *priv = platform_get_drvdata(pdev); 2154 2155 unregister_netdev(priv->ndev); 2156 2157 netsec_unregister_mdio(priv); 2158 2159 netif_napi_del(&priv->napi); 2160 2161 pm_runtime_disable(&pdev->dev); 2162 free_netdev(priv->ndev); 2163 2164 return 0; 2165} 2166 2167#ifdef CONFIG_PM 2168static int netsec_runtime_suspend(struct device *dev) 2169{ 2170 struct netsec_priv *priv = dev_get_drvdata(dev); 2171 2172 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 2173 2174 clk_disable_unprepare(priv->clk); 2175 2176 return 0; 2177} 2178 2179static int netsec_runtime_resume(struct device *dev) 2180{ 2181 struct netsec_priv *priv = dev_get_drvdata(dev); 2182 2183 clk_prepare_enable(priv->clk); 2184 2185 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 2186 NETSEC_CLK_EN_REG_DOM_C | 2187 NETSEC_CLK_EN_REG_DOM_G); 2188 return 0; 2189} 2190#endif 2191 2192static const struct dev_pm_ops netsec_pm_ops = { 2193 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 2194}; 2195 2196static const struct of_device_id netsec_dt_ids[] = { 2197 { .compatible = "socionext,synquacer-netsec" }, 2198 { } 2199}; 2200MODULE_DEVICE_TABLE(of, netsec_dt_ids); 2201 2202#ifdef CONFIG_ACPI 2203static const struct acpi_device_id netsec_acpi_ids[] = { 2204 { "SCX0001" }, 2205 { } 2206}; 2207MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 2208#endif 2209 2210static struct platform_driver netsec_driver = { 2211 .probe = netsec_probe, 2212 .remove = netsec_remove, 2213 .driver = { 2214 .name = "netsec", 2215 .pm = &netsec_pm_ops, 2216 .of_match_table = netsec_dt_ids, 2217 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 2218 }, 2219}; 2220module_platform_driver(netsec_driver); 2221 2222MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 2223MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 2224MODULE_DESCRIPTION("NETSEC Ethernet driver"); 2225MODULE_LICENSE("GPL"); 2226