1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * smc91x.c 4 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. 5 * 6 * Copyright (C) 1996 by Erik Stahlman 7 * Copyright (C) 2001 Standard Microsystems Corporation 8 * Developed by Simple Network Magic Corporation 9 * Copyright (C) 2003 Monta Vista Software, Inc. 10 * Unified SMC91x driver by Nicolas Pitre 11 * 12 * Arguments: 13 * io = for the base address 14 * irq = for the IRQ 15 * nowait = 0 for normal wait states, 1 eliminates additional wait states 16 * 17 * original author: 18 * Erik Stahlman <erik@vt.edu> 19 * 20 * hardware multicast code: 21 * Peter Cammaert <pc@denkart.be> 22 * 23 * contributors: 24 * Daris A Nevil <dnevil@snmc.com> 25 * Nicolas Pitre <nico@fluxnic.net> 26 * Russell King <rmk@arm.linux.org.uk> 27 * 28 * History: 29 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet 30 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" 31 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 32 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 33 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 34 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support 35 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, 36 * more bus abstraction, big cleanup, etc. 37 * 29/09/03 Russell King - add driver model support 38 * - ethtool support 39 * - convert to use generic MII interface 40 * - add link up/down notification 41 * - don't try to handle full negotiation in 42 * smc_phy_configure 43 * - clean up (and fix stack overrun) in PHY 44 * MII read/write functions 45 * 22/09/04 Nicolas Pitre big update (see commit log for details) 46 */ 47static const char version[] = 48 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>"; 49 50/* Debugging level */ 51#ifndef SMC_DEBUG 52#define SMC_DEBUG 0 53#endif 54 55 56#include <linux/module.h> 57#include <linux/kernel.h> 58#include <linux/sched.h> 59#include <linux/delay.h> 60#include <linux/interrupt.h> 61#include <linux/irq.h> 62#include <linux/errno.h> 63#include <linux/ioport.h> 64#include <linux/crc32.h> 65#include <linux/platform_device.h> 66#include <linux/spinlock.h> 67#include <linux/ethtool.h> 68#include <linux/mii.h> 69#include <linux/workqueue.h> 70#include <linux/of.h> 71#include <linux/of_device.h> 72#include <linux/of_gpio.h> 73 74#include <linux/netdevice.h> 75#include <linux/etherdevice.h> 76#include <linux/skbuff.h> 77 78#include <asm/io.h> 79 80#include "smc91x.h" 81 82#if defined(CONFIG_ASSABET_NEPONSET) 83#include <mach/assabet.h> 84#include <mach/neponset.h> 85#endif 86 87#ifndef SMC_NOWAIT 88# define SMC_NOWAIT 0 89#endif 90static int nowait = SMC_NOWAIT; 91module_param(nowait, int, 0400); 92MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); 93 94/* 95 * Transmit timeout, default 5 seconds. 96 */ 97static int watchdog = 1000; 98module_param(watchdog, int, 0400); 99MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 100 101MODULE_LICENSE("GPL"); 102MODULE_ALIAS("platform:smc91x"); 103 104/* 105 * The internal workings of the driver. If you are changing anything 106 * here with the SMC stuff, you should have the datasheet and know 107 * what you are doing. 108 */ 109#define CARDNAME "smc91x" 110 111/* 112 * Use power-down feature of the chip 113 */ 114#define POWER_DOWN 1 115 116/* 117 * Wait time for memory to be free. This probably shouldn't be 118 * tuned that much, as waiting for this means nothing else happens 119 * in the system 120 */ 121#define MEMORY_WAIT_TIME 16 122 123/* 124 * The maximum number of processing loops allowed for each call to the 125 * IRQ handler. 126 */ 127#define MAX_IRQ_LOOPS 8 128 129/* 130 * This selects whether TX packets are sent one by one to the SMC91x internal 131 * memory and throttled until transmission completes. This may prevent 132 * RX overruns a litle by keeping much of the memory free for RX packets 133 * but to the expense of reduced TX throughput and increased IRQ overhead. 134 * Note this is not a cure for a too slow data bus or too high IRQ latency. 135 */ 136#define THROTTLE_TX_PKTS 0 137 138/* 139 * The MII clock high/low times. 2x this number gives the MII clock period 140 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) 141 */ 142#define MII_DELAY 1 143 144#define DBG(n, dev, fmt, ...) \ 145 do { \ 146 if (SMC_DEBUG >= (n)) \ 147 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 148 } while (0) 149 150#define PRINTK(dev, fmt, ...) \ 151 do { \ 152 if (SMC_DEBUG > 0) \ 153 netdev_info(dev, fmt, ##__VA_ARGS__); \ 154 else \ 155 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 156 } while (0) 157 158#if SMC_DEBUG > 3 159static void PRINT_PKT(u_char *buf, int length) 160{ 161 int i; 162 int remainder; 163 int lines; 164 165 lines = length / 16; 166 remainder = length % 16; 167 168 for (i = 0; i < lines ; i ++) { 169 int cur; 170 printk(KERN_DEBUG); 171 for (cur = 0; cur < 8; cur++) { 172 u_char a, b; 173 a = *buf++; 174 b = *buf++; 175 pr_cont("%02x%02x ", a, b); 176 } 177 pr_cont("\n"); 178 } 179 printk(KERN_DEBUG); 180 for (i = 0; i < remainder/2 ; i++) { 181 u_char a, b; 182 a = *buf++; 183 b = *buf++; 184 pr_cont("%02x%02x ", a, b); 185 } 186 pr_cont("\n"); 187} 188#else 189static inline void PRINT_PKT(u_char *buf, int length) { } 190#endif 191 192 193/* this enables an interrupt in the interrupt mask register */ 194#define SMC_ENABLE_INT(lp, x) do { \ 195 unsigned char mask; \ 196 unsigned long smc_enable_flags; \ 197 spin_lock_irqsave(&lp->lock, smc_enable_flags); \ 198 mask = SMC_GET_INT_MASK(lp); \ 199 mask |= (x); \ 200 SMC_SET_INT_MASK(lp, mask); \ 201 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ 202} while (0) 203 204/* this disables an interrupt from the interrupt mask register */ 205#define SMC_DISABLE_INT(lp, x) do { \ 206 unsigned char mask; \ 207 unsigned long smc_disable_flags; \ 208 spin_lock_irqsave(&lp->lock, smc_disable_flags); \ 209 mask = SMC_GET_INT_MASK(lp); \ 210 mask &= ~(x); \ 211 SMC_SET_INT_MASK(lp, mask); \ 212 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ 213} while (0) 214 215/* 216 * Wait while MMU is busy. This is usually in the order of a few nanosecs 217 * if at all, but let's avoid deadlocking the system if the hardware 218 * decides to go south. 219 */ 220#define SMC_WAIT_MMU_BUSY(lp) do { \ 221 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ 222 unsigned long timeout = jiffies + 2; \ 223 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ 224 if (time_after(jiffies, timeout)) { \ 225 netdev_dbg(dev, "timeout %s line %d\n", \ 226 __FILE__, __LINE__); \ 227 break; \ 228 } \ 229 cpu_relax(); \ 230 } \ 231 } \ 232} while (0) 233 234 235/* 236 * this does a soft reset on the device 237 */ 238static void smc_reset(struct net_device *dev) 239{ 240 struct smc_local *lp = netdev_priv(dev); 241 void __iomem *ioaddr = lp->base; 242 unsigned int ctl, cfg; 243 struct sk_buff *pending_skb; 244 245 DBG(2, dev, "%s\n", __func__); 246 247 /* Disable all interrupts, block TX tasklet */ 248 spin_lock_irq(&lp->lock); 249 SMC_SELECT_BANK(lp, 2); 250 SMC_SET_INT_MASK(lp, 0); 251 pending_skb = lp->pending_tx_skb; 252 lp->pending_tx_skb = NULL; 253 spin_unlock_irq(&lp->lock); 254 255 /* free any pending tx skb */ 256 if (pending_skb) { 257 dev_kfree_skb(pending_skb); 258 dev->stats.tx_errors++; 259 dev->stats.tx_aborted_errors++; 260 } 261 262 /* 263 * This resets the registers mostly to defaults, but doesn't 264 * affect EEPROM. That seems unnecessary 265 */ 266 SMC_SELECT_BANK(lp, 0); 267 SMC_SET_RCR(lp, RCR_SOFTRST); 268 269 /* 270 * Setup the Configuration Register 271 * This is necessary because the CONFIG_REG is not affected 272 * by a soft reset 273 */ 274 SMC_SELECT_BANK(lp, 1); 275 276 cfg = CONFIG_DEFAULT; 277 278 /* 279 * Setup for fast accesses if requested. If the card/system 280 * can't handle it then there will be no recovery except for 281 * a hard reset or power cycle 282 */ 283 if (lp->cfg.flags & SMC91X_NOWAIT) 284 cfg |= CONFIG_NO_WAIT; 285 286 /* 287 * Release from possible power-down state 288 * Configuration register is not affected by Soft Reset 289 */ 290 cfg |= CONFIG_EPH_POWER_EN; 291 292 SMC_SET_CONFIG(lp, cfg); 293 294 /* this should pause enough for the chip to be happy */ 295 /* 296 * elaborate? What does the chip _need_? --jgarzik 297 * 298 * This seems to be undocumented, but something the original 299 * driver(s) have always done. Suspect undocumented timing 300 * info/determined empirically. --rmk 301 */ 302 udelay(1); 303 304 /* Disable transmit and receive functionality */ 305 SMC_SELECT_BANK(lp, 0); 306 SMC_SET_RCR(lp, RCR_CLEAR); 307 SMC_SET_TCR(lp, TCR_CLEAR); 308 309 SMC_SELECT_BANK(lp, 1); 310 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; 311 312 /* 313 * Set the control register to automatically release successfully 314 * transmitted packets, to make the best use out of our limited 315 * memory 316 */ 317 if(!THROTTLE_TX_PKTS) 318 ctl |= CTL_AUTO_RELEASE; 319 else 320 ctl &= ~CTL_AUTO_RELEASE; 321 SMC_SET_CTL(lp, ctl); 322 323 /* Reset the MMU */ 324 SMC_SELECT_BANK(lp, 2); 325 SMC_SET_MMU_CMD(lp, MC_RESET); 326 SMC_WAIT_MMU_BUSY(lp); 327} 328 329/* 330 * Enable Interrupts, Receive, and Transmit 331 */ 332static void smc_enable(struct net_device *dev) 333{ 334 struct smc_local *lp = netdev_priv(dev); 335 void __iomem *ioaddr = lp->base; 336 int mask; 337 338 DBG(2, dev, "%s\n", __func__); 339 340 /* see the header file for options in TCR/RCR DEFAULT */ 341 SMC_SELECT_BANK(lp, 0); 342 SMC_SET_TCR(lp, lp->tcr_cur_mode); 343 SMC_SET_RCR(lp, lp->rcr_cur_mode); 344 345 SMC_SELECT_BANK(lp, 1); 346 SMC_SET_MAC_ADDR(lp, dev->dev_addr); 347 348 /* now, enable interrupts */ 349 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; 350 if (lp->version >= (CHIP_91100 << 4)) 351 mask |= IM_MDINT; 352 SMC_SELECT_BANK(lp, 2); 353 SMC_SET_INT_MASK(lp, mask); 354 355 /* 356 * From this point the register bank must _NOT_ be switched away 357 * to something else than bank 2 without proper locking against 358 * races with any tasklet or interrupt handlers until smc_shutdown() 359 * or smc_reset() is called. 360 */ 361} 362 363/* 364 * this puts the device in an inactive state 365 */ 366static void smc_shutdown(struct net_device *dev) 367{ 368 struct smc_local *lp = netdev_priv(dev); 369 void __iomem *ioaddr = lp->base; 370 struct sk_buff *pending_skb; 371 372 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 373 374 /* no more interrupts for me */ 375 spin_lock_irq(&lp->lock); 376 SMC_SELECT_BANK(lp, 2); 377 SMC_SET_INT_MASK(lp, 0); 378 pending_skb = lp->pending_tx_skb; 379 lp->pending_tx_skb = NULL; 380 spin_unlock_irq(&lp->lock); 381 dev_kfree_skb(pending_skb); 382 383 /* and tell the card to stay away from that nasty outside world */ 384 SMC_SELECT_BANK(lp, 0); 385 SMC_SET_RCR(lp, RCR_CLEAR); 386 SMC_SET_TCR(lp, TCR_CLEAR); 387 388#ifdef POWER_DOWN 389 /* finally, shut the chip down */ 390 SMC_SELECT_BANK(lp, 1); 391 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); 392#endif 393} 394 395/* 396 * This is the procedure to handle the receipt of a packet. 397 */ 398static inline void smc_rcv(struct net_device *dev) 399{ 400 struct smc_local *lp = netdev_priv(dev); 401 void __iomem *ioaddr = lp->base; 402 unsigned int packet_number, status, packet_len; 403 404 DBG(3, dev, "%s\n", __func__); 405 406 packet_number = SMC_GET_RXFIFO(lp); 407 if (unlikely(packet_number & RXFIFO_REMPTY)) { 408 PRINTK(dev, "smc_rcv with nothing on FIFO.\n"); 409 return; 410 } 411 412 /* read from start of packet */ 413 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); 414 415 /* First two words are status and packet length */ 416 SMC_GET_PKT_HDR(lp, status, packet_len); 417 packet_len &= 0x07ff; /* mask off top bits */ 418 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", 419 packet_number, status, packet_len, packet_len); 420 421 back: 422 if (unlikely(packet_len < 6 || status & RS_ERRORS)) { 423 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { 424 /* accept VLAN packets */ 425 status &= ~RS_TOOLONG; 426 goto back; 427 } 428 if (packet_len < 6) { 429 /* bloody hardware */ 430 netdev_err(dev, "fubar (rxlen %u status %x\n", 431 packet_len, status); 432 status |= RS_TOOSHORT; 433 } 434 SMC_WAIT_MMU_BUSY(lp); 435 SMC_SET_MMU_CMD(lp, MC_RELEASE); 436 dev->stats.rx_errors++; 437 if (status & RS_ALGNERR) 438 dev->stats.rx_frame_errors++; 439 if (status & (RS_TOOSHORT | RS_TOOLONG)) 440 dev->stats.rx_length_errors++; 441 if (status & RS_BADCRC) 442 dev->stats.rx_crc_errors++; 443 } else { 444 struct sk_buff *skb; 445 unsigned char *data; 446 unsigned int data_len; 447 448 /* set multicast stats */ 449 if (status & RS_MULTICAST) 450 dev->stats.multicast++; 451 452 /* 453 * Actual payload is packet_len - 6 (or 5 if odd byte). 454 * We want skb_reserve(2) and the final ctrl word 455 * (2 bytes, possibly containing the payload odd byte). 456 * Furthermore, we add 2 bytes to allow rounding up to 457 * multiple of 4 bytes on 32 bit buses. 458 * Hence packet_len - 6 + 2 + 2 + 2. 459 */ 460 skb = netdev_alloc_skb(dev, packet_len); 461 if (unlikely(skb == NULL)) { 462 SMC_WAIT_MMU_BUSY(lp); 463 SMC_SET_MMU_CMD(lp, MC_RELEASE); 464 dev->stats.rx_dropped++; 465 return; 466 } 467 468 /* Align IP header to 32 bits */ 469 skb_reserve(skb, 2); 470 471 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ 472 if (lp->version == 0x90) 473 status |= RS_ODDFRAME; 474 475 /* 476 * If odd length: packet_len - 5, 477 * otherwise packet_len - 6. 478 * With the trailing ctrl byte it's packet_len - 4. 479 */ 480 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); 481 data = skb_put(skb, data_len); 482 SMC_PULL_DATA(lp, data, packet_len - 4); 483 484 SMC_WAIT_MMU_BUSY(lp); 485 SMC_SET_MMU_CMD(lp, MC_RELEASE); 486 487 PRINT_PKT(data, packet_len - 4); 488 489 skb->protocol = eth_type_trans(skb, dev); 490 netif_rx(skb); 491 dev->stats.rx_packets++; 492 dev->stats.rx_bytes += data_len; 493 } 494} 495 496#ifdef CONFIG_SMP 497/* 498 * On SMP we have the following problem: 499 * 500 * A = smc_hardware_send_pkt() 501 * B = smc_hard_start_xmit() 502 * C = smc_interrupt() 503 * 504 * A and B can never be executed simultaneously. However, at least on UP, 505 * it is possible (and even desirable) for C to interrupt execution of 506 * A or B in order to have better RX reliability and avoid overruns. 507 * C, just like A and B, must have exclusive access to the chip and 508 * each of them must lock against any other concurrent access. 509 * Unfortunately this is not possible to have C suspend execution of A or 510 * B taking place on another CPU. On UP this is no an issue since A and B 511 * are run from softirq context and C from hard IRQ context, and there is 512 * no other CPU where concurrent access can happen. 513 * If ever there is a way to force at least B and C to always be executed 514 * on the same CPU then we could use read/write locks to protect against 515 * any other concurrent access and C would always interrupt B. But life 516 * isn't that easy in a SMP world... 517 */ 518#define smc_special_trylock(lock, flags) \ 519({ \ 520 int __ret; \ 521 local_irq_save(flags); \ 522 __ret = spin_trylock(lock); \ 523 if (!__ret) \ 524 local_irq_restore(flags); \ 525 __ret; \ 526}) 527#define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) 528#define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) 529#else 530#define smc_special_trylock(lock, flags) ((void)flags, true) 531#define smc_special_lock(lock, flags) do { flags = 0; } while (0) 532#define smc_special_unlock(lock, flags) do { flags = 0; } while (0) 533#endif 534 535/* 536 * This is called to actually send a packet to the chip. 537 */ 538static void smc_hardware_send_pkt(struct tasklet_struct *t) 539{ 540 struct smc_local *lp = from_tasklet(lp, t, tx_task); 541 struct net_device *dev = lp->dev; 542 void __iomem *ioaddr = lp->base; 543 struct sk_buff *skb; 544 unsigned int packet_no, len; 545 unsigned char *buf; 546 unsigned long flags; 547 548 DBG(3, dev, "%s\n", __func__); 549 550 if (!smc_special_trylock(&lp->lock, flags)) { 551 netif_stop_queue(dev); 552 tasklet_schedule(&lp->tx_task); 553 return; 554 } 555 556 skb = lp->pending_tx_skb; 557 if (unlikely(!skb)) { 558 smc_special_unlock(&lp->lock, flags); 559 return; 560 } 561 lp->pending_tx_skb = NULL; 562 563 packet_no = SMC_GET_AR(lp); 564 if (unlikely(packet_no & AR_FAILED)) { 565 netdev_err(dev, "Memory allocation failed.\n"); 566 dev->stats.tx_errors++; 567 dev->stats.tx_fifo_errors++; 568 smc_special_unlock(&lp->lock, flags); 569 goto done; 570 } 571 572 /* point to the beginning of the packet */ 573 SMC_SET_PN(lp, packet_no); 574 SMC_SET_PTR(lp, PTR_AUTOINC); 575 576 buf = skb->data; 577 len = skb->len; 578 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", 579 packet_no, len, len, buf); 580 PRINT_PKT(buf, len); 581 582 /* 583 * Send the packet length (+6 for status words, length, and ctl. 584 * The card will pad to 64 bytes with zeroes if packet is too small. 585 */ 586 SMC_PUT_PKT_HDR(lp, 0, len + 6); 587 588 /* send the actual data */ 589 SMC_PUSH_DATA(lp, buf, len & ~1); 590 591 /* Send final ctl word with the last byte if there is one */ 592 SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr, 593 DATA_REG(lp)); 594 595 /* 596 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will 597 * have the effect of having at most one packet queued for TX 598 * in the chip's memory at all time. 599 * 600 * If THROTTLE_TX_PKTS is not set then the queue is stopped only 601 * when memory allocation (MC_ALLOC) does not succeed right away. 602 */ 603 if (THROTTLE_TX_PKTS) 604 netif_stop_queue(dev); 605 606 /* queue the packet for TX */ 607 SMC_SET_MMU_CMD(lp, MC_ENQUEUE); 608 smc_special_unlock(&lp->lock, flags); 609 610 netif_trans_update(dev); 611 dev->stats.tx_packets++; 612 dev->stats.tx_bytes += len; 613 614 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); 615 616done: if (!THROTTLE_TX_PKTS) 617 netif_wake_queue(dev); 618 619 dev_consume_skb_any(skb); 620} 621 622/* 623 * Since I am not sure if I will have enough room in the chip's ram 624 * to store the packet, I call this routine which either sends it 625 * now, or set the card to generates an interrupt when ready 626 * for the packet. 627 */ 628static netdev_tx_t 629smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 630{ 631 struct smc_local *lp = netdev_priv(dev); 632 void __iomem *ioaddr = lp->base; 633 unsigned int numPages, poll_count, status; 634 unsigned long flags; 635 636 DBG(3, dev, "%s\n", __func__); 637 638 BUG_ON(lp->pending_tx_skb != NULL); 639 640 /* 641 * The MMU wants the number of pages to be the number of 256 bytes 642 * 'pages', minus 1 (since a packet can't ever have 0 pages :)) 643 * 644 * The 91C111 ignores the size bits, but earlier models don't. 645 * 646 * Pkt size for allocating is data length +6 (for additional status 647 * words, length and ctl) 648 * 649 * If odd size then last byte is included in ctl word. 650 */ 651 numPages = ((skb->len & ~1) + (6 - 1)) >> 8; 652 if (unlikely(numPages > 7)) { 653 netdev_warn(dev, "Far too big packet error.\n"); 654 dev->stats.tx_errors++; 655 dev->stats.tx_dropped++; 656 dev_kfree_skb_any(skb); 657 return NETDEV_TX_OK; 658 } 659 660 smc_special_lock(&lp->lock, flags); 661 662 /* now, try to allocate the memory */ 663 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); 664 665 /* 666 * Poll the chip for a short amount of time in case the 667 * allocation succeeds quickly. 668 */ 669 poll_count = MEMORY_WAIT_TIME; 670 do { 671 status = SMC_GET_INT(lp); 672 if (status & IM_ALLOC_INT) { 673 SMC_ACK_INT(lp, IM_ALLOC_INT); 674 break; 675 } 676 } while (--poll_count); 677 678 smc_special_unlock(&lp->lock, flags); 679 680 lp->pending_tx_skb = skb; 681 if (!poll_count) { 682 /* oh well, wait until the chip finds memory later */ 683 netif_stop_queue(dev); 684 DBG(2, dev, "TX memory allocation deferred.\n"); 685 SMC_ENABLE_INT(lp, IM_ALLOC_INT); 686 } else { 687 /* 688 * Allocation succeeded: push packet to the chip's own memory 689 * immediately. 690 */ 691 smc_hardware_send_pkt(&lp->tx_task); 692 } 693 694 return NETDEV_TX_OK; 695} 696 697/* 698 * This handles a TX interrupt, which is only called when: 699 * - a TX error occurred, or 700 * - CTL_AUTO_RELEASE is not set and TX of a packet completed. 701 */ 702static void smc_tx(struct net_device *dev) 703{ 704 struct smc_local *lp = netdev_priv(dev); 705 void __iomem *ioaddr = lp->base; 706 unsigned int saved_packet, packet_no, tx_status, pkt_len; 707 708 DBG(3, dev, "%s\n", __func__); 709 710 /* If the TX FIFO is empty then nothing to do */ 711 packet_no = SMC_GET_TXFIFO(lp); 712 if (unlikely(packet_no & TXFIFO_TEMPTY)) { 713 PRINTK(dev, "smc_tx with nothing on FIFO.\n"); 714 return; 715 } 716 717 /* select packet to read from */ 718 saved_packet = SMC_GET_PN(lp); 719 SMC_SET_PN(lp, packet_no); 720 721 /* read the first word (status word) from this packet */ 722 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); 723 SMC_GET_PKT_HDR(lp, tx_status, pkt_len); 724 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n", 725 tx_status, packet_no); 726 727 if (!(tx_status & ES_TX_SUC)) 728 dev->stats.tx_errors++; 729 730 if (tx_status & ES_LOSTCARR) 731 dev->stats.tx_carrier_errors++; 732 733 if (tx_status & (ES_LATCOL | ES_16COL)) { 734 PRINTK(dev, "%s occurred on last xmit\n", 735 (tx_status & ES_LATCOL) ? 736 "late collision" : "too many collisions"); 737 dev->stats.tx_window_errors++; 738 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { 739 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n"); 740 } 741 } 742 743 /* kill the packet */ 744 SMC_WAIT_MMU_BUSY(lp); 745 SMC_SET_MMU_CMD(lp, MC_FREEPKT); 746 747 /* Don't restore Packet Number Reg until busy bit is cleared */ 748 SMC_WAIT_MMU_BUSY(lp); 749 SMC_SET_PN(lp, saved_packet); 750 751 /* re-enable transmit */ 752 SMC_SELECT_BANK(lp, 0); 753 SMC_SET_TCR(lp, lp->tcr_cur_mode); 754 SMC_SELECT_BANK(lp, 2); 755} 756 757 758/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ 759 760static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) 761{ 762 struct smc_local *lp = netdev_priv(dev); 763 void __iomem *ioaddr = lp->base; 764 unsigned int mii_reg, mask; 765 766 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 767 mii_reg |= MII_MDOE; 768 769 for (mask = 1 << (bits - 1); mask; mask >>= 1) { 770 if (val & mask) 771 mii_reg |= MII_MDO; 772 else 773 mii_reg &= ~MII_MDO; 774 775 SMC_SET_MII(lp, mii_reg); 776 udelay(MII_DELAY); 777 SMC_SET_MII(lp, mii_reg | MII_MCLK); 778 udelay(MII_DELAY); 779 } 780} 781 782static unsigned int smc_mii_in(struct net_device *dev, int bits) 783{ 784 struct smc_local *lp = netdev_priv(dev); 785 void __iomem *ioaddr = lp->base; 786 unsigned int mii_reg, mask, val; 787 788 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 789 SMC_SET_MII(lp, mii_reg); 790 791 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { 792 if (SMC_GET_MII(lp) & MII_MDI) 793 val |= mask; 794 795 SMC_SET_MII(lp, mii_reg); 796 udelay(MII_DELAY); 797 SMC_SET_MII(lp, mii_reg | MII_MCLK); 798 udelay(MII_DELAY); 799 } 800 801 return val; 802} 803 804/* 805 * Reads a register from the MII Management serial interface 806 */ 807static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) 808{ 809 struct smc_local *lp = netdev_priv(dev); 810 void __iomem *ioaddr = lp->base; 811 unsigned int phydata; 812 813 SMC_SELECT_BANK(lp, 3); 814 815 /* Idle - 32 ones */ 816 smc_mii_out(dev, 0xffffffff, 32); 817 818 /* Start code (01) + read (10) + phyaddr + phyreg */ 819 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); 820 821 /* Turnaround (2bits) + phydata */ 822 phydata = smc_mii_in(dev, 18); 823 824 /* Return to idle state */ 825 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 826 827 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 828 __func__, phyaddr, phyreg, phydata); 829 830 SMC_SELECT_BANK(lp, 2); 831 return phydata; 832} 833 834/* 835 * Writes a register to the MII Management serial interface 836 */ 837static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, 838 int phydata) 839{ 840 struct smc_local *lp = netdev_priv(dev); 841 void __iomem *ioaddr = lp->base; 842 843 SMC_SELECT_BANK(lp, 3); 844 845 /* Idle - 32 ones */ 846 smc_mii_out(dev, 0xffffffff, 32); 847 848 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ 849 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); 850 851 /* Return to idle state */ 852 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 853 854 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 855 __func__, phyaddr, phyreg, phydata); 856 857 SMC_SELECT_BANK(lp, 2); 858} 859 860/* 861 * Finds and reports the PHY address 862 */ 863static void smc_phy_detect(struct net_device *dev) 864{ 865 struct smc_local *lp = netdev_priv(dev); 866 int phyaddr; 867 868 DBG(2, dev, "%s\n", __func__); 869 870 lp->phy_type = 0; 871 872 /* 873 * Scan all 32 PHY addresses if necessary, starting at 874 * PHY#1 to PHY#31, and then PHY#0 last. 875 */ 876 for (phyaddr = 1; phyaddr < 33; ++phyaddr) { 877 unsigned int id1, id2; 878 879 /* Read the PHY identifiers */ 880 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); 881 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); 882 883 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n", 884 id1, id2); 885 886 /* Make sure it is a valid identifier */ 887 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && 888 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { 889 /* Save the PHY's address */ 890 lp->mii.phy_id = phyaddr & 31; 891 lp->phy_type = id1 << 16 | id2; 892 break; 893 } 894 } 895} 896 897/* 898 * Sets the PHY to a configuration as determined by the user 899 */ 900static int smc_phy_fixed(struct net_device *dev) 901{ 902 struct smc_local *lp = netdev_priv(dev); 903 void __iomem *ioaddr = lp->base; 904 int phyaddr = lp->mii.phy_id; 905 int bmcr, cfg1; 906 907 DBG(3, dev, "%s\n", __func__); 908 909 /* Enter Link Disable state */ 910 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); 911 cfg1 |= PHY_CFG1_LNKDIS; 912 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); 913 914 /* 915 * Set our fixed capabilities 916 * Disable auto-negotiation 917 */ 918 bmcr = 0; 919 920 if (lp->ctl_rfduplx) 921 bmcr |= BMCR_FULLDPLX; 922 923 if (lp->ctl_rspeed == 100) 924 bmcr |= BMCR_SPEED100; 925 926 /* Write our capabilities to the phy control register */ 927 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); 928 929 /* Re-Configure the Receive/Phy Control register */ 930 SMC_SELECT_BANK(lp, 0); 931 SMC_SET_RPC(lp, lp->rpc_cur_mode); 932 SMC_SELECT_BANK(lp, 2); 933 934 return 1; 935} 936 937/** 938 * smc_phy_reset - reset the phy 939 * @dev: net device 940 * @phy: phy address 941 * 942 * Issue a software reset for the specified PHY and 943 * wait up to 100ms for the reset to complete. We should 944 * not access the PHY for 50ms after issuing the reset. 945 * 946 * The time to wait appears to be dependent on the PHY. 947 * 948 * Must be called with lp->lock locked. 949 */ 950static int smc_phy_reset(struct net_device *dev, int phy) 951{ 952 struct smc_local *lp = netdev_priv(dev); 953 unsigned int bmcr; 954 int timeout; 955 956 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); 957 958 for (timeout = 2; timeout; timeout--) { 959 spin_unlock_irq(&lp->lock); 960 msleep(50); 961 spin_lock_irq(&lp->lock); 962 963 bmcr = smc_phy_read(dev, phy, MII_BMCR); 964 if (!(bmcr & BMCR_RESET)) 965 break; 966 } 967 968 return bmcr & BMCR_RESET; 969} 970 971/** 972 * smc_phy_powerdown - powerdown phy 973 * @dev: net device 974 * 975 * Power down the specified PHY 976 */ 977static void smc_phy_powerdown(struct net_device *dev) 978{ 979 struct smc_local *lp = netdev_priv(dev); 980 unsigned int bmcr; 981 int phy = lp->mii.phy_id; 982 983 if (lp->phy_type == 0) 984 return; 985 986 /* We need to ensure that no calls to smc_phy_configure are 987 pending. 988 */ 989 cancel_work_sync(&lp->phy_configure); 990 991 bmcr = smc_phy_read(dev, phy, MII_BMCR); 992 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); 993} 994 995/** 996 * smc_phy_check_media - check the media status and adjust TCR 997 * @dev: net device 998 * @init: set true for initialisation 999 * 1000 * Select duplex mode depending on negotiation state. This 1001 * also updates our carrier state. 1002 */ 1003static void smc_phy_check_media(struct net_device *dev, int init) 1004{ 1005 struct smc_local *lp = netdev_priv(dev); 1006 void __iomem *ioaddr = lp->base; 1007 1008 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 1009 /* duplex state has changed */ 1010 if (lp->mii.full_duplex) { 1011 lp->tcr_cur_mode |= TCR_SWFDUP; 1012 } else { 1013 lp->tcr_cur_mode &= ~TCR_SWFDUP; 1014 } 1015 1016 SMC_SELECT_BANK(lp, 0); 1017 SMC_SET_TCR(lp, lp->tcr_cur_mode); 1018 } 1019} 1020 1021/* 1022 * Configures the specified PHY through the MII management interface 1023 * using Autonegotiation. 1024 * Calls smc_phy_fixed() if the user has requested a certain config. 1025 * If RPC ANEG bit is set, the media selection is dependent purely on 1026 * the selection by the MII (either in the MII BMCR reg or the result 1027 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection 1028 * is controlled by the RPC SPEED and RPC DPLX bits. 1029 */ 1030static void smc_phy_configure(struct work_struct *work) 1031{ 1032 struct smc_local *lp = 1033 container_of(work, struct smc_local, phy_configure); 1034 struct net_device *dev = lp->dev; 1035 void __iomem *ioaddr = lp->base; 1036 int phyaddr = lp->mii.phy_id; 1037 int my_phy_caps; /* My PHY capabilities */ 1038 int my_ad_caps; /* My Advertised capabilities */ 1039 1040 DBG(3, dev, "smc_program_phy()\n"); 1041 1042 spin_lock_irq(&lp->lock); 1043 1044 /* 1045 * We should not be called if phy_type is zero. 1046 */ 1047 if (lp->phy_type == 0) 1048 goto smc_phy_configure_exit; 1049 1050 if (smc_phy_reset(dev, phyaddr)) { 1051 netdev_info(dev, "PHY reset timed out\n"); 1052 goto smc_phy_configure_exit; 1053 } 1054 1055 /* 1056 * Enable PHY Interrupts (for register 18) 1057 * Interrupts listed here are disabled 1058 */ 1059 smc_phy_write(dev, phyaddr, PHY_MASK_REG, 1060 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | 1061 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | 1062 PHY_INT_SPDDET | PHY_INT_DPLXDET); 1063 1064 /* Configure the Receive/Phy Control register */ 1065 SMC_SELECT_BANK(lp, 0); 1066 SMC_SET_RPC(lp, lp->rpc_cur_mode); 1067 1068 /* If the user requested no auto neg, then go set his request */ 1069 if (lp->mii.force_media) { 1070 smc_phy_fixed(dev); 1071 goto smc_phy_configure_exit; 1072 } 1073 1074 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 1075 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); 1076 1077 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 1078 netdev_info(dev, "Auto negotiation NOT supported\n"); 1079 smc_phy_fixed(dev); 1080 goto smc_phy_configure_exit; 1081 } 1082 1083 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ 1084 1085 if (my_phy_caps & BMSR_100BASE4) 1086 my_ad_caps |= ADVERTISE_100BASE4; 1087 if (my_phy_caps & BMSR_100FULL) 1088 my_ad_caps |= ADVERTISE_100FULL; 1089 if (my_phy_caps & BMSR_100HALF) 1090 my_ad_caps |= ADVERTISE_100HALF; 1091 if (my_phy_caps & BMSR_10FULL) 1092 my_ad_caps |= ADVERTISE_10FULL; 1093 if (my_phy_caps & BMSR_10HALF) 1094 my_ad_caps |= ADVERTISE_10HALF; 1095 1096 /* Disable capabilities not selected by our user */ 1097 if (lp->ctl_rspeed != 100) 1098 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); 1099 1100 if (!lp->ctl_rfduplx) 1101 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 1102 1103 /* Update our Auto-Neg Advertisement Register */ 1104 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); 1105 lp->mii.advertising = my_ad_caps; 1106 1107 /* 1108 * Read the register back. Without this, it appears that when 1109 * auto-negotiation is restarted, sometimes it isn't ready and 1110 * the link does not come up. 1111 */ 1112 smc_phy_read(dev, phyaddr, MII_ADVERTISE); 1113 1114 DBG(2, dev, "phy caps=%x\n", my_phy_caps); 1115 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps); 1116 1117 /* Restart auto-negotiation process in order to advertise my caps */ 1118 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 1119 1120 smc_phy_check_media(dev, 1); 1121 1122smc_phy_configure_exit: 1123 SMC_SELECT_BANK(lp, 2); 1124 spin_unlock_irq(&lp->lock); 1125} 1126 1127/* 1128 * smc_phy_interrupt 1129 * 1130 * Purpose: Handle interrupts relating to PHY register 18. This is 1131 * called from the "hard" interrupt handler under our private spinlock. 1132 */ 1133static void smc_phy_interrupt(struct net_device *dev) 1134{ 1135 struct smc_local *lp = netdev_priv(dev); 1136 int phyaddr = lp->mii.phy_id; 1137 int phy18; 1138 1139 DBG(2, dev, "%s\n", __func__); 1140 1141 if (lp->phy_type == 0) 1142 return; 1143 1144 for(;;) { 1145 smc_phy_check_media(dev, 0); 1146 1147 /* Read PHY Register 18, Status Output */ 1148 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); 1149 if ((phy18 & PHY_INT_INT) == 0) 1150 break; 1151 } 1152} 1153 1154/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1155 1156static void smc_10bt_check_media(struct net_device *dev, int init) 1157{ 1158 struct smc_local *lp = netdev_priv(dev); 1159 void __iomem *ioaddr = lp->base; 1160 unsigned int old_carrier, new_carrier; 1161 1162 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1163 1164 SMC_SELECT_BANK(lp, 0); 1165 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; 1166 SMC_SELECT_BANK(lp, 2); 1167 1168 if (init || (old_carrier != new_carrier)) { 1169 if (!new_carrier) { 1170 netif_carrier_off(dev); 1171 } else { 1172 netif_carrier_on(dev); 1173 } 1174 if (netif_msg_link(lp)) 1175 netdev_info(dev, "link %s\n", 1176 new_carrier ? "up" : "down"); 1177 } 1178} 1179 1180static void smc_eph_interrupt(struct net_device *dev) 1181{ 1182 struct smc_local *lp = netdev_priv(dev); 1183 void __iomem *ioaddr = lp->base; 1184 unsigned int ctl; 1185 1186 smc_10bt_check_media(dev, 0); 1187 1188 SMC_SELECT_BANK(lp, 1); 1189 ctl = SMC_GET_CTL(lp); 1190 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); 1191 SMC_SET_CTL(lp, ctl); 1192 SMC_SELECT_BANK(lp, 2); 1193} 1194 1195/* 1196 * This is the main routine of the driver, to handle the device when 1197 * it needs some attention. 1198 */ 1199static irqreturn_t smc_interrupt(int irq, void *dev_id) 1200{ 1201 struct net_device *dev = dev_id; 1202 struct smc_local *lp = netdev_priv(dev); 1203 void __iomem *ioaddr = lp->base; 1204 int status, mask, timeout, card_stats; 1205 int saved_pointer; 1206 1207 DBG(3, dev, "%s\n", __func__); 1208 1209 spin_lock(&lp->lock); 1210 1211 /* A preamble may be used when there is a potential race 1212 * between the interruptible transmit functions and this 1213 * ISR. */ 1214 SMC_INTERRUPT_PREAMBLE; 1215 1216 saved_pointer = SMC_GET_PTR(lp); 1217 mask = SMC_GET_INT_MASK(lp); 1218 SMC_SET_INT_MASK(lp, 0); 1219 1220 /* set a timeout value, so I don't stay here forever */ 1221 timeout = MAX_IRQ_LOOPS; 1222 1223 do { 1224 status = SMC_GET_INT(lp); 1225 1226 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1227 status, mask, 1228 ({ int meminfo; SMC_SELECT_BANK(lp, 0); 1229 meminfo = SMC_GET_MIR(lp); 1230 SMC_SELECT_BANK(lp, 2); meminfo; }), 1231 SMC_GET_FIFO(lp)); 1232 1233 status &= mask; 1234 if (!status) 1235 break; 1236 1237 if (status & IM_TX_INT) { 1238 /* do this before RX as it will free memory quickly */ 1239 DBG(3, dev, "TX int\n"); 1240 smc_tx(dev); 1241 SMC_ACK_INT(lp, IM_TX_INT); 1242 if (THROTTLE_TX_PKTS) 1243 netif_wake_queue(dev); 1244 } else if (status & IM_RCV_INT) { 1245 DBG(3, dev, "RX irq\n"); 1246 smc_rcv(dev); 1247 } else if (status & IM_ALLOC_INT) { 1248 DBG(3, dev, "Allocation irq\n"); 1249 tasklet_hi_schedule(&lp->tx_task); 1250 mask &= ~IM_ALLOC_INT; 1251 } else if (status & IM_TX_EMPTY_INT) { 1252 DBG(3, dev, "TX empty\n"); 1253 mask &= ~IM_TX_EMPTY_INT; 1254 1255 /* update stats */ 1256 SMC_SELECT_BANK(lp, 0); 1257 card_stats = SMC_GET_COUNTER(lp); 1258 SMC_SELECT_BANK(lp, 2); 1259 1260 /* single collisions */ 1261 dev->stats.collisions += card_stats & 0xF; 1262 card_stats >>= 4; 1263 1264 /* multiple collisions */ 1265 dev->stats.collisions += card_stats & 0xF; 1266 } else if (status & IM_RX_OVRN_INT) { 1267 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n", 1268 ({ int eph_st; SMC_SELECT_BANK(lp, 0); 1269 eph_st = SMC_GET_EPH_STATUS(lp); 1270 SMC_SELECT_BANK(lp, 2); eph_st; })); 1271 SMC_ACK_INT(lp, IM_RX_OVRN_INT); 1272 dev->stats.rx_errors++; 1273 dev->stats.rx_fifo_errors++; 1274 } else if (status & IM_EPH_INT) { 1275 smc_eph_interrupt(dev); 1276 } else if (status & IM_MDINT) { 1277 SMC_ACK_INT(lp, IM_MDINT); 1278 smc_phy_interrupt(dev); 1279 } else if (status & IM_ERCV_INT) { 1280 SMC_ACK_INT(lp, IM_ERCV_INT); 1281 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n"); 1282 } 1283 } while (--timeout); 1284 1285 /* restore register states */ 1286 SMC_SET_PTR(lp, saved_pointer); 1287 SMC_SET_INT_MASK(lp, mask); 1288 spin_unlock(&lp->lock); 1289 1290#ifndef CONFIG_NET_POLL_CONTROLLER 1291 if (timeout == MAX_IRQ_LOOPS) 1292 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n", 1293 mask); 1294#endif 1295 DBG(3, dev, "Interrupt done (%d loops)\n", 1296 MAX_IRQ_LOOPS - timeout); 1297 1298 /* 1299 * We return IRQ_HANDLED unconditionally here even if there was 1300 * nothing to do. There is a possibility that a packet might 1301 * get enqueued into the chip right after TX_EMPTY_INT is raised 1302 * but just before the CPU acknowledges the IRQ. 1303 * Better take an unneeded IRQ in some occasions than complexifying 1304 * the code for all cases. 1305 */ 1306 return IRQ_HANDLED; 1307} 1308 1309#ifdef CONFIG_NET_POLL_CONTROLLER 1310/* 1311 * Polling receive - used by netconsole and other diagnostic tools 1312 * to allow network i/o with interrupts disabled. 1313 */ 1314static void smc_poll_controller(struct net_device *dev) 1315{ 1316 disable_irq(dev->irq); 1317 smc_interrupt(dev->irq, dev); 1318 enable_irq(dev->irq); 1319} 1320#endif 1321 1322/* Our watchdog timed out. Called by the networking layer */ 1323static void smc_timeout(struct net_device *dev, unsigned int txqueue) 1324{ 1325 struct smc_local *lp = netdev_priv(dev); 1326 void __iomem *ioaddr = lp->base; 1327 int status, mask, eph_st, meminfo, fifo; 1328 1329 DBG(2, dev, "%s\n", __func__); 1330 1331 spin_lock_irq(&lp->lock); 1332 status = SMC_GET_INT(lp); 1333 mask = SMC_GET_INT_MASK(lp); 1334 fifo = SMC_GET_FIFO(lp); 1335 SMC_SELECT_BANK(lp, 0); 1336 eph_st = SMC_GET_EPH_STATUS(lp); 1337 meminfo = SMC_GET_MIR(lp); 1338 SMC_SELECT_BANK(lp, 2); 1339 spin_unlock_irq(&lp->lock); 1340 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", 1341 status, mask, meminfo, fifo, eph_st); 1342 1343 smc_reset(dev); 1344 smc_enable(dev); 1345 1346 /* 1347 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1348 * smc_phy_configure() calls msleep() which calls schedule_timeout() 1349 * which calls schedule(). Hence we use a work queue. 1350 */ 1351 if (lp->phy_type != 0) 1352 schedule_work(&lp->phy_configure); 1353 1354 /* We can accept TX packets again */ 1355 netif_trans_update(dev); /* prevent tx timeout */ 1356 netif_wake_queue(dev); 1357} 1358 1359/* 1360 * This routine will, depending on the values passed to it, 1361 * either make it accept multicast packets, go into 1362 * promiscuous mode (for TCPDUMP and cousins) or accept 1363 * a select set of multicast packets 1364 */ 1365static void smc_set_multicast_list(struct net_device *dev) 1366{ 1367 struct smc_local *lp = netdev_priv(dev); 1368 void __iomem *ioaddr = lp->base; 1369 unsigned char multicast_table[8]; 1370 int update_multicast = 0; 1371 1372 DBG(2, dev, "%s\n", __func__); 1373 1374 if (dev->flags & IFF_PROMISC) { 1375 DBG(2, dev, "RCR_PRMS\n"); 1376 lp->rcr_cur_mode |= RCR_PRMS; 1377 } 1378 1379/* BUG? I never disable promiscuous mode if multicasting was turned on. 1380 Now, I turn off promiscuous mode, but I don't do anything to multicasting 1381 when promiscuous mode is turned on. 1382*/ 1383 1384 /* 1385 * Here, I am setting this to accept all multicast packets. 1386 * I don't need to zero the multicast table, because the flag is 1387 * checked before the table is 1388 */ 1389 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { 1390 DBG(2, dev, "RCR_ALMUL\n"); 1391 lp->rcr_cur_mode |= RCR_ALMUL; 1392 } 1393 1394 /* 1395 * This sets the internal hardware table to filter out unwanted 1396 * multicast packets before they take up memory. 1397 * 1398 * The SMC chip uses a hash table where the high 6 bits of the CRC of 1399 * address are the offset into the table. If that bit is 1, then the 1400 * multicast packet is accepted. Otherwise, it's dropped silently. 1401 * 1402 * To use the 6 bits as an offset into the table, the high 3 bits are 1403 * the number of the 8 bit register, while the low 3 bits are the bit 1404 * within that register. 1405 */ 1406 else if (!netdev_mc_empty(dev)) { 1407 struct netdev_hw_addr *ha; 1408 1409 /* table for flipping the order of 3 bits */ 1410 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; 1411 1412 /* start with a table of all zeros: reject all */ 1413 memset(multicast_table, 0, sizeof(multicast_table)); 1414 1415 netdev_for_each_mc_addr(ha, dev) { 1416 int position; 1417 1418 /* only use the low order bits */ 1419 position = crc32_le(~0, ha->addr, 6) & 0x3f; 1420 1421 /* do some messy swapping to put the bit in the right spot */ 1422 multicast_table[invert3[position&7]] |= 1423 (1<<invert3[(position>>3)&7]); 1424 } 1425 1426 /* be sure I get rid of flags I might have set */ 1427 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1428 1429 /* now, the table can be loaded into the chipset */ 1430 update_multicast = 1; 1431 } else { 1432 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n"); 1433 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1434 1435 /* 1436 * since I'm disabling all multicast entirely, I need to 1437 * clear the multicast list 1438 */ 1439 memset(multicast_table, 0, sizeof(multicast_table)); 1440 update_multicast = 1; 1441 } 1442 1443 spin_lock_irq(&lp->lock); 1444 SMC_SELECT_BANK(lp, 0); 1445 SMC_SET_RCR(lp, lp->rcr_cur_mode); 1446 if (update_multicast) { 1447 SMC_SELECT_BANK(lp, 3); 1448 SMC_SET_MCAST(lp, multicast_table); 1449 } 1450 SMC_SELECT_BANK(lp, 2); 1451 spin_unlock_irq(&lp->lock); 1452} 1453 1454 1455/* 1456 * Open and Initialize the board 1457 * 1458 * Set up everything, reset the card, etc.. 1459 */ 1460static int 1461smc_open(struct net_device *dev) 1462{ 1463 struct smc_local *lp = netdev_priv(dev); 1464 1465 DBG(2, dev, "%s\n", __func__); 1466 1467 /* Setup the default Register Modes */ 1468 lp->tcr_cur_mode = TCR_DEFAULT; 1469 lp->rcr_cur_mode = RCR_DEFAULT; 1470 lp->rpc_cur_mode = RPC_DEFAULT | 1471 lp->cfg.leda << RPC_LSXA_SHFT | 1472 lp->cfg.ledb << RPC_LSXB_SHFT; 1473 1474 /* 1475 * If we are not using a MII interface, we need to 1476 * monitor our own carrier signal to detect faults. 1477 */ 1478 if (lp->phy_type == 0) 1479 lp->tcr_cur_mode |= TCR_MON_CSN; 1480 1481 /* reset the hardware */ 1482 smc_reset(dev); 1483 smc_enable(dev); 1484 1485 /* Configure the PHY, initialize the link state */ 1486 if (lp->phy_type != 0) 1487 smc_phy_configure(&lp->phy_configure); 1488 else { 1489 spin_lock_irq(&lp->lock); 1490 smc_10bt_check_media(dev, 1); 1491 spin_unlock_irq(&lp->lock); 1492 } 1493 1494 netif_start_queue(dev); 1495 return 0; 1496} 1497 1498/* 1499 * smc_close 1500 * 1501 * this makes the board clean up everything that it can 1502 * and not talk to the outside world. Caused by 1503 * an 'ifconfig ethX down' 1504 */ 1505static int smc_close(struct net_device *dev) 1506{ 1507 struct smc_local *lp = netdev_priv(dev); 1508 1509 DBG(2, dev, "%s\n", __func__); 1510 1511 netif_stop_queue(dev); 1512 netif_carrier_off(dev); 1513 1514 /* clear everything */ 1515 smc_shutdown(dev); 1516 tasklet_kill(&lp->tx_task); 1517 smc_phy_powerdown(dev); 1518 return 0; 1519} 1520 1521/* 1522 * Ethtool support 1523 */ 1524static int 1525smc_ethtool_get_link_ksettings(struct net_device *dev, 1526 struct ethtool_link_ksettings *cmd) 1527{ 1528 struct smc_local *lp = netdev_priv(dev); 1529 1530 if (lp->phy_type != 0) { 1531 spin_lock_irq(&lp->lock); 1532 mii_ethtool_get_link_ksettings(&lp->mii, cmd); 1533 spin_unlock_irq(&lp->lock); 1534 } else { 1535 u32 supported = SUPPORTED_10baseT_Half | 1536 SUPPORTED_10baseT_Full | 1537 SUPPORTED_TP | SUPPORTED_AUI; 1538 1539 if (lp->ctl_rspeed == 10) 1540 cmd->base.speed = SPEED_10; 1541 else if (lp->ctl_rspeed == 100) 1542 cmd->base.speed = SPEED_100; 1543 1544 cmd->base.autoneg = AUTONEG_DISABLE; 1545 cmd->base.port = 0; 1546 cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ? 1547 DUPLEX_FULL : DUPLEX_HALF; 1548 1549 ethtool_convert_legacy_u32_to_link_mode( 1550 cmd->link_modes.supported, supported); 1551 } 1552 1553 return 0; 1554} 1555 1556static int 1557smc_ethtool_set_link_ksettings(struct net_device *dev, 1558 const struct ethtool_link_ksettings *cmd) 1559{ 1560 struct smc_local *lp = netdev_priv(dev); 1561 int ret; 1562 1563 if (lp->phy_type != 0) { 1564 spin_lock_irq(&lp->lock); 1565 ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd); 1566 spin_unlock_irq(&lp->lock); 1567 } else { 1568 if (cmd->base.autoneg != AUTONEG_DISABLE || 1569 cmd->base.speed != SPEED_10 || 1570 (cmd->base.duplex != DUPLEX_HALF && 1571 cmd->base.duplex != DUPLEX_FULL) || 1572 (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI)) 1573 return -EINVAL; 1574 1575// lp->port = cmd->base.port; 1576 lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL; 1577 1578// if (netif_running(dev)) 1579// smc_set_port(dev); 1580 1581 ret = 0; 1582 } 1583 1584 return ret; 1585} 1586 1587static void 1588smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1589{ 1590 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 1591 strlcpy(info->version, version, sizeof(info->version)); 1592 strlcpy(info->bus_info, dev_name(dev->dev.parent), 1593 sizeof(info->bus_info)); 1594} 1595 1596static int smc_ethtool_nwayreset(struct net_device *dev) 1597{ 1598 struct smc_local *lp = netdev_priv(dev); 1599 int ret = -EINVAL; 1600 1601 if (lp->phy_type != 0) { 1602 spin_lock_irq(&lp->lock); 1603 ret = mii_nway_restart(&lp->mii); 1604 spin_unlock_irq(&lp->lock); 1605 } 1606 1607 return ret; 1608} 1609 1610static u32 smc_ethtool_getmsglevel(struct net_device *dev) 1611{ 1612 struct smc_local *lp = netdev_priv(dev); 1613 return lp->msg_enable; 1614} 1615 1616static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) 1617{ 1618 struct smc_local *lp = netdev_priv(dev); 1619 lp->msg_enable = level; 1620} 1621 1622static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) 1623{ 1624 u16 ctl; 1625 struct smc_local *lp = netdev_priv(dev); 1626 void __iomem *ioaddr = lp->base; 1627 1628 spin_lock_irq(&lp->lock); 1629 /* load word into GP register */ 1630 SMC_SELECT_BANK(lp, 1); 1631 SMC_SET_GP(lp, word); 1632 /* set the address to put the data in EEPROM */ 1633 SMC_SELECT_BANK(lp, 2); 1634 SMC_SET_PTR(lp, addr); 1635 /* tell it to write */ 1636 SMC_SELECT_BANK(lp, 1); 1637 ctl = SMC_GET_CTL(lp); 1638 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); 1639 /* wait for it to finish */ 1640 do { 1641 udelay(1); 1642 } while (SMC_GET_CTL(lp) & CTL_STORE); 1643 /* clean up */ 1644 SMC_SET_CTL(lp, ctl); 1645 SMC_SELECT_BANK(lp, 2); 1646 spin_unlock_irq(&lp->lock); 1647 return 0; 1648} 1649 1650static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) 1651{ 1652 u16 ctl; 1653 struct smc_local *lp = netdev_priv(dev); 1654 void __iomem *ioaddr = lp->base; 1655 1656 spin_lock_irq(&lp->lock); 1657 /* set the EEPROM address to get the data from */ 1658 SMC_SELECT_BANK(lp, 2); 1659 SMC_SET_PTR(lp, addr | PTR_READ); 1660 /* tell it to load */ 1661 SMC_SELECT_BANK(lp, 1); 1662 SMC_SET_GP(lp, 0xffff); /* init to known */ 1663 ctl = SMC_GET_CTL(lp); 1664 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); 1665 /* wait for it to finish */ 1666 do { 1667 udelay(1); 1668 } while (SMC_GET_CTL(lp) & CTL_RELOAD); 1669 /* read word from GP register */ 1670 *word = SMC_GET_GP(lp); 1671 /* clean up */ 1672 SMC_SET_CTL(lp, ctl); 1673 SMC_SELECT_BANK(lp, 2); 1674 spin_unlock_irq(&lp->lock); 1675 return 0; 1676} 1677 1678static int smc_ethtool_geteeprom_len(struct net_device *dev) 1679{ 1680 return 0x23 * 2; 1681} 1682 1683static int smc_ethtool_geteeprom(struct net_device *dev, 1684 struct ethtool_eeprom *eeprom, u8 *data) 1685{ 1686 int i; 1687 int imax; 1688 1689 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n", 1690 eeprom->len, eeprom->offset, eeprom->offset); 1691 imax = smc_ethtool_geteeprom_len(dev); 1692 for (i = 0; i < eeprom->len; i += 2) { 1693 int ret; 1694 u16 wbuf; 1695 int offset = i + eeprom->offset; 1696 if (offset > imax) 1697 break; 1698 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); 1699 if (ret != 0) 1700 return ret; 1701 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); 1702 data[i] = (wbuf >> 8) & 0xff; 1703 data[i+1] = wbuf & 0xff; 1704 } 1705 return 0; 1706} 1707 1708static int smc_ethtool_seteeprom(struct net_device *dev, 1709 struct ethtool_eeprom *eeprom, u8 *data) 1710{ 1711 int i; 1712 int imax; 1713 1714 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n", 1715 eeprom->len, eeprom->offset, eeprom->offset); 1716 imax = smc_ethtool_geteeprom_len(dev); 1717 for (i = 0; i < eeprom->len; i += 2) { 1718 int ret; 1719 u16 wbuf; 1720 int offset = i + eeprom->offset; 1721 if (offset > imax) 1722 break; 1723 wbuf = (data[i] << 8) | data[i + 1]; 1724 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); 1725 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); 1726 if (ret != 0) 1727 return ret; 1728 } 1729 return 0; 1730} 1731 1732 1733static const struct ethtool_ops smc_ethtool_ops = { 1734 .get_drvinfo = smc_ethtool_getdrvinfo, 1735 1736 .get_msglevel = smc_ethtool_getmsglevel, 1737 .set_msglevel = smc_ethtool_setmsglevel, 1738 .nway_reset = smc_ethtool_nwayreset, 1739 .get_link = ethtool_op_get_link, 1740 .get_eeprom_len = smc_ethtool_geteeprom_len, 1741 .get_eeprom = smc_ethtool_geteeprom, 1742 .set_eeprom = smc_ethtool_seteeprom, 1743 .get_link_ksettings = smc_ethtool_get_link_ksettings, 1744 .set_link_ksettings = smc_ethtool_set_link_ksettings, 1745}; 1746 1747static const struct net_device_ops smc_netdev_ops = { 1748 .ndo_open = smc_open, 1749 .ndo_stop = smc_close, 1750 .ndo_start_xmit = smc_hard_start_xmit, 1751 .ndo_tx_timeout = smc_timeout, 1752 .ndo_set_rx_mode = smc_set_multicast_list, 1753 .ndo_validate_addr = eth_validate_addr, 1754 .ndo_set_mac_address = eth_mac_addr, 1755#ifdef CONFIG_NET_POLL_CONTROLLER 1756 .ndo_poll_controller = smc_poll_controller, 1757#endif 1758}; 1759 1760/* 1761 * smc_findirq 1762 * 1763 * This routine has a simple purpose -- make the SMC chip generate an 1764 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1765 */ 1766/* 1767 * does this still work? 1768 * 1769 * I just deleted auto_irq.c, since it was never built... 1770 * --jgarzik 1771 */ 1772static int smc_findirq(struct smc_local *lp) 1773{ 1774 void __iomem *ioaddr = lp->base; 1775 int timeout = 20; 1776 unsigned long cookie; 1777 1778 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__); 1779 1780 cookie = probe_irq_on(); 1781 1782 /* 1783 * What I try to do here is trigger an ALLOC_INT. This is done 1784 * by allocating a small chunk of memory, which will give an interrupt 1785 * when done. 1786 */ 1787 /* enable ALLOCation interrupts ONLY */ 1788 SMC_SELECT_BANK(lp, 2); 1789 SMC_SET_INT_MASK(lp, IM_ALLOC_INT); 1790 1791 /* 1792 * Allocate 512 bytes of memory. Note that the chip was just 1793 * reset so all the memory is available 1794 */ 1795 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); 1796 1797 /* 1798 * Wait until positive that the interrupt has been generated 1799 */ 1800 do { 1801 int int_status; 1802 udelay(10); 1803 int_status = SMC_GET_INT(lp); 1804 if (int_status & IM_ALLOC_INT) 1805 break; /* got the interrupt */ 1806 } while (--timeout); 1807 1808 /* 1809 * there is really nothing that I can do here if timeout fails, 1810 * as autoirq_report will return a 0 anyway, which is what I 1811 * want in this case. Plus, the clean up is needed in both 1812 * cases. 1813 */ 1814 1815 /* and disable all interrupts again */ 1816 SMC_SET_INT_MASK(lp, 0); 1817 1818 /* and return what I found */ 1819 return probe_irq_off(cookie); 1820} 1821 1822/* 1823 * Function: smc_probe(unsigned long ioaddr) 1824 * 1825 * Purpose: 1826 * Tests to see if a given ioaddr points to an SMC91x chip. 1827 * Returns a 0 on success 1828 * 1829 * Algorithm: 1830 * (1) see if the high byte of BANK_SELECT is 0x33 1831 * (2) compare the ioaddr with the base register's address 1832 * (3) see if I recognize the chip ID in the appropriate register 1833 * 1834 * Here I do typical initialization tasks. 1835 * 1836 * o Initialize the structure if needed 1837 * o print out my vanity message if not done so already 1838 * o print out what type of hardware is detected 1839 * o print out the ethernet address 1840 * o find the IRQ 1841 * o set up my private data 1842 * o configure the dev structure with my subroutines 1843 * o actually GRAB the irq. 1844 * o GRAB the region 1845 */ 1846static int smc_probe(struct net_device *dev, void __iomem *ioaddr, 1847 unsigned long irq_flags) 1848{ 1849 struct smc_local *lp = netdev_priv(dev); 1850 int retval; 1851 unsigned int val, revision_register; 1852 const char *version_string; 1853 1854 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 1855 1856 /* First, see if the high byte is 0x33 */ 1857 val = SMC_CURRENT_BANK(lp); 1858 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n", 1859 CARDNAME, val); 1860 if ((val & 0xFF00) != 0x3300) { 1861 if ((val & 0xFF) == 0x33) { 1862 netdev_warn(dev, 1863 "%s: Detected possible byte-swapped interface at IOADDR %p\n", 1864 CARDNAME, ioaddr); 1865 } 1866 retval = -ENODEV; 1867 goto err_out; 1868 } 1869 1870 /* 1871 * The above MIGHT indicate a device, but I need to write to 1872 * further test this. 1873 */ 1874 SMC_SELECT_BANK(lp, 0); 1875 val = SMC_CURRENT_BANK(lp); 1876 if ((val & 0xFF00) != 0x3300) { 1877 retval = -ENODEV; 1878 goto err_out; 1879 } 1880 1881 /* 1882 * well, we've already written once, so hopefully another 1883 * time won't hurt. This time, I need to switch the bank 1884 * register to bank 1, so I can access the base address 1885 * register 1886 */ 1887 SMC_SELECT_BANK(lp, 1); 1888 val = SMC_GET_BASE(lp); 1889 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1890 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { 1891 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n", 1892 CARDNAME, ioaddr, val); 1893 } 1894 1895 /* 1896 * check if the revision register is something that I 1897 * recognize. These might need to be added to later, 1898 * as future revisions could be added. 1899 */ 1900 SMC_SELECT_BANK(lp, 3); 1901 revision_register = SMC_GET_REV(lp); 1902 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register); 1903 version_string = chip_ids[ (revision_register >> 4) & 0xF]; 1904 if (!version_string || (revision_register & 0xff00) != 0x3300) { 1905 /* I don't recognize this chip, so... */ 1906 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n", 1907 CARDNAME, ioaddr, revision_register); 1908 1909 retval = -ENODEV; 1910 goto err_out; 1911 } 1912 1913 /* At this point I'll assume that the chip is an SMC91x. */ 1914 pr_info_once("%s\n", version); 1915 1916 /* fill in some of the fields */ 1917 dev->base_addr = (unsigned long)ioaddr; 1918 lp->base = ioaddr; 1919 lp->version = revision_register & 0xff; 1920 spin_lock_init(&lp->lock); 1921 1922 /* Get the MAC address */ 1923 SMC_SELECT_BANK(lp, 1); 1924 SMC_GET_MAC_ADDR(lp, dev->dev_addr); 1925 1926 /* now, reset the chip, and put it into a known state */ 1927 smc_reset(dev); 1928 1929 /* 1930 * If dev->irq is 0, then the device has to be banged on to see 1931 * what the IRQ is. 1932 * 1933 * This banging doesn't always detect the IRQ, for unknown reasons. 1934 * a workaround is to reset the chip and try again. 1935 * 1936 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to 1937 * be what is requested on the command line. I don't do that, mostly 1938 * because the card that I have uses a non-standard method of accessing 1939 * the IRQs, and because this _should_ work in most configurations. 1940 * 1941 * Specifying an IRQ is done with the assumption that the user knows 1942 * what (s)he is doing. No checking is done!!!! 1943 */ 1944 if (dev->irq < 1) { 1945 int trials; 1946 1947 trials = 3; 1948 while (trials--) { 1949 dev->irq = smc_findirq(lp); 1950 if (dev->irq) 1951 break; 1952 /* kick the card and try again */ 1953 smc_reset(dev); 1954 } 1955 } 1956 if (dev->irq == 0) { 1957 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n"); 1958 retval = -ENODEV; 1959 goto err_out; 1960 } 1961 dev->irq = irq_canonicalize(dev->irq); 1962 1963 dev->watchdog_timeo = msecs_to_jiffies(watchdog); 1964 dev->netdev_ops = &smc_netdev_ops; 1965 dev->ethtool_ops = &smc_ethtool_ops; 1966 1967 tasklet_setup(&lp->tx_task, smc_hardware_send_pkt); 1968 INIT_WORK(&lp->phy_configure, smc_phy_configure); 1969 lp->dev = dev; 1970 lp->mii.phy_id_mask = 0x1f; 1971 lp->mii.reg_num_mask = 0x1f; 1972 lp->mii.force_media = 0; 1973 lp->mii.full_duplex = 0; 1974 lp->mii.dev = dev; 1975 lp->mii.mdio_read = smc_phy_read; 1976 lp->mii.mdio_write = smc_phy_write; 1977 1978 /* 1979 * Locate the phy, if any. 1980 */ 1981 if (lp->version >= (CHIP_91100 << 4)) 1982 smc_phy_detect(dev); 1983 1984 /* then shut everything down to save power */ 1985 smc_shutdown(dev); 1986 smc_phy_powerdown(dev); 1987 1988 /* Set default parameters */ 1989 lp->msg_enable = NETIF_MSG_LINK; 1990 lp->ctl_rfduplx = 0; 1991 lp->ctl_rspeed = 10; 1992 1993 if (lp->version >= (CHIP_91100 << 4)) { 1994 lp->ctl_rfduplx = 1; 1995 lp->ctl_rspeed = 100; 1996 } 1997 1998 /* Grab the IRQ */ 1999 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); 2000 if (retval) 2001 goto err_out; 2002 2003#ifdef CONFIG_ARCH_PXA 2004# ifdef SMC_USE_PXA_DMA 2005 lp->cfg.flags |= SMC91X_USE_DMA; 2006# endif 2007 if (lp->cfg.flags & SMC91X_USE_DMA) { 2008 dma_cap_mask_t mask; 2009 2010 dma_cap_zero(mask); 2011 dma_cap_set(DMA_SLAVE, mask); 2012 lp->dma_chan = dma_request_channel(mask, NULL, NULL); 2013 } 2014#endif 2015 2016 retval = register_netdev(dev); 2017 if (retval == 0) { 2018 /* now, print out the card info, in a short format.. */ 2019 netdev_info(dev, "%s (rev %d) at %p IRQ %d", 2020 version_string, revision_register & 0x0f, 2021 lp->base, dev->irq); 2022 2023 if (lp->dma_chan) 2024 pr_cont(" DMA %p", lp->dma_chan); 2025 2026 pr_cont("%s%s\n", 2027 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", 2028 THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); 2029 2030 if (!is_valid_ether_addr(dev->dev_addr)) { 2031 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n"); 2032 } else { 2033 /* Print the Ethernet address */ 2034 netdev_info(dev, "Ethernet addr: %pM\n", 2035 dev->dev_addr); 2036 } 2037 2038 if (lp->phy_type == 0) { 2039 PRINTK(dev, "No PHY found\n"); 2040 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { 2041 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n"); 2042 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { 2043 PRINTK(dev, "PHY LAN83C180\n"); 2044 } 2045 } 2046 2047err_out: 2048#ifdef CONFIG_ARCH_PXA 2049 if (retval && lp->dma_chan) 2050 dma_release_channel(lp->dma_chan); 2051#endif 2052 return retval; 2053} 2054 2055static int smc_enable_device(struct platform_device *pdev) 2056{ 2057 struct net_device *ndev = platform_get_drvdata(pdev); 2058 struct smc_local *lp = netdev_priv(ndev); 2059 unsigned long flags; 2060 unsigned char ecor, ecsr; 2061 void __iomem *addr; 2062 struct resource * res; 2063 2064 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2065 if (!res) 2066 return 0; 2067 2068 /* 2069 * Map the attribute space. This is overkill, but clean. 2070 */ 2071 addr = ioremap(res->start, ATTRIB_SIZE); 2072 if (!addr) 2073 return -ENOMEM; 2074 2075 /* 2076 * Reset the device. We must disable IRQs around this 2077 * since a reset causes the IRQ line become active. 2078 */ 2079 local_irq_save(flags); 2080 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; 2081 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); 2082 readb(addr + (ECOR << SMC_IO_SHIFT)); 2083 2084 /* 2085 * Wait 100us for the chip to reset. 2086 */ 2087 udelay(100); 2088 2089 /* 2090 * The device will ignore all writes to the enable bit while 2091 * reset is asserted, even if the reset bit is cleared in the 2092 * same write. Must clear reset first, then enable the device. 2093 */ 2094 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); 2095 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); 2096 2097 /* 2098 * Set the appropriate byte/word mode. 2099 */ 2100 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; 2101 if (!SMC_16BIT(lp)) 2102 ecsr |= ECSR_IOIS8; 2103 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); 2104 local_irq_restore(flags); 2105 2106 iounmap(addr); 2107 2108 /* 2109 * Wait for the chip to wake up. We could poll the control 2110 * register in the main register space, but that isn't mapped 2111 * yet. We know this is going to take 750us. 2112 */ 2113 msleep(1); 2114 2115 return 0; 2116} 2117 2118static int smc_request_attrib(struct platform_device *pdev, 2119 struct net_device *ndev) 2120{ 2121 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2122 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2123 2124 if (!res) 2125 return 0; 2126 2127 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) 2128 return -EBUSY; 2129 2130 return 0; 2131} 2132 2133static void smc_release_attrib(struct platform_device *pdev, 2134 struct net_device *ndev) 2135{ 2136 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2137 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2138 2139 if (res) 2140 release_mem_region(res->start, ATTRIB_SIZE); 2141} 2142 2143static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) 2144{ 2145 if (SMC_CAN_USE_DATACS) { 2146 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2147 struct smc_local *lp = netdev_priv(ndev); 2148 2149 if (!res) 2150 return; 2151 2152 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { 2153 netdev_info(ndev, "%s: failed to request datacs memory region.\n", 2154 CARDNAME); 2155 return; 2156 } 2157 2158 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); 2159 } 2160} 2161 2162static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) 2163{ 2164 if (SMC_CAN_USE_DATACS) { 2165 struct smc_local *lp = netdev_priv(ndev); 2166 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2167 2168 if (lp->datacs) 2169 iounmap(lp->datacs); 2170 2171 lp->datacs = NULL; 2172 2173 if (res) 2174 release_mem_region(res->start, SMC_DATA_EXTENT); 2175 } 2176} 2177 2178static const struct acpi_device_id smc91x_acpi_match[] = { 2179 { "LNRO0003", 0 }, 2180 { } 2181}; 2182MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match); 2183 2184#if IS_BUILTIN(CONFIG_OF) 2185static const struct of_device_id smc91x_match[] = { 2186 { .compatible = "smsc,lan91c94", }, 2187 { .compatible = "smsc,lan91c111", }, 2188 {}, 2189}; 2190MODULE_DEVICE_TABLE(of, smc91x_match); 2191 2192/** 2193 * of_try_set_control_gpio - configure a gpio if it exists 2194 */ 2195static int try_toggle_control_gpio(struct device *dev, 2196 struct gpio_desc **desc, 2197 const char *name, int index, 2198 int value, unsigned int nsdelay) 2199{ 2200 struct gpio_desc *gpio = *desc; 2201 enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH; 2202 2203 gpio = devm_gpiod_get_index_optional(dev, name, index, flags); 2204 if (IS_ERR(gpio)) 2205 return PTR_ERR(gpio); 2206 2207 if (gpio) { 2208 if (nsdelay) 2209 usleep_range(nsdelay, 2 * nsdelay); 2210 gpiod_set_value_cansleep(gpio, value); 2211 } 2212 *desc = gpio; 2213 2214 return 0; 2215} 2216#endif 2217 2218/* 2219 * smc_init(void) 2220 * Input parameters: 2221 * dev->base_addr == 0, try to find all possible locations 2222 * dev->base_addr > 0x1ff, this is the address to check 2223 * dev->base_addr == <anything else>, return failure code 2224 * 2225 * Output: 2226 * 0 --> there is a device 2227 * anything else, error 2228 */ 2229static int smc_drv_probe(struct platform_device *pdev) 2230{ 2231 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); 2232 const struct of_device_id *match = NULL; 2233 struct smc_local *lp; 2234 struct net_device *ndev; 2235 struct resource *res; 2236 unsigned int __iomem *addr; 2237 unsigned long irq_flags = SMC_IRQ_FLAGS; 2238 unsigned long irq_resflags; 2239 int ret; 2240 2241 ndev = alloc_etherdev(sizeof(struct smc_local)); 2242 if (!ndev) { 2243 ret = -ENOMEM; 2244 goto out; 2245 } 2246 SET_NETDEV_DEV(ndev, &pdev->dev); 2247 2248 /* get configuration from platform data, only allow use of 2249 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. 2250 */ 2251 2252 lp = netdev_priv(ndev); 2253 lp->cfg.flags = 0; 2254 2255 if (pd) { 2256 memcpy(&lp->cfg, pd, sizeof(lp->cfg)); 2257 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); 2258 2259 if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) { 2260 dev_err(&pdev->dev, 2261 "at least one of 8-bit or 16-bit access support is required.\n"); 2262 ret = -ENXIO; 2263 goto out_free_netdev; 2264 } 2265 } 2266 2267#if IS_BUILTIN(CONFIG_OF) 2268 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev); 2269 if (match) { 2270 u32 val; 2271 2272 /* Optional pwrdwn GPIO configured? */ 2273 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio, 2274 "power", 0, 0, 100); 2275 if (ret) 2276 goto out_free_netdev; 2277 2278 /* 2279 * Optional reset GPIO configured? Minimum 100 ns reset needed 2280 * according to LAN91C96 datasheet page 14. 2281 */ 2282 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio, 2283 "reset", 0, 0, 100); 2284 if (ret) 2285 goto out_free_netdev; 2286 2287 /* 2288 * Need to wait for optional EEPROM to load, max 750 us according 2289 * to LAN91C96 datasheet page 55. 2290 */ 2291 if (lp->reset_gpio) 2292 usleep_range(750, 1000); 2293 2294 /* Combination of IO widths supported, default to 16-bit */ 2295 if (!device_property_read_u32(&pdev->dev, "reg-io-width", 2296 &val)) { 2297 if (val & 1) 2298 lp->cfg.flags |= SMC91X_USE_8BIT; 2299 if ((val == 0) || (val & 2)) 2300 lp->cfg.flags |= SMC91X_USE_16BIT; 2301 if (val & 4) 2302 lp->cfg.flags |= SMC91X_USE_32BIT; 2303 } else { 2304 lp->cfg.flags |= SMC91X_USE_16BIT; 2305 } 2306 if (!device_property_read_u32(&pdev->dev, "reg-shift", 2307 &val)) 2308 lp->io_shift = val; 2309 lp->cfg.pxa_u16_align4 = 2310 device_property_read_bool(&pdev->dev, "pxa-u16-align4"); 2311 } 2312#endif 2313 2314 if (!pd && !match) { 2315 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; 2316 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; 2317 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; 2318 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; 2319 } 2320 2321 if (!lp->cfg.leda && !lp->cfg.ledb) { 2322 lp->cfg.leda = RPC_LSA_DEFAULT; 2323 lp->cfg.ledb = RPC_LSB_DEFAULT; 2324 } 2325 2326 ndev->dma = (unsigned char)-1; 2327 2328 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2329 if (!res) 2330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2331 if (!res) { 2332 ret = -ENODEV; 2333 goto out_free_netdev; 2334 } 2335 2336 2337 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { 2338 ret = -EBUSY; 2339 goto out_free_netdev; 2340 } 2341 2342 ndev->irq = platform_get_irq(pdev, 0); 2343 if (ndev->irq < 0) { 2344 ret = ndev->irq; 2345 goto out_release_io; 2346 } 2347 /* 2348 * If this platform does not specify any special irqflags, or if 2349 * the resource supplies a trigger, override the irqflags with 2350 * the trigger flags from the resource. 2351 */ 2352 irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq)); 2353 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK) 2354 irq_flags = irq_resflags & IRQF_TRIGGER_MASK; 2355 2356 ret = smc_request_attrib(pdev, ndev); 2357 if (ret) 2358 goto out_release_io; 2359#if defined(CONFIG_ASSABET_NEPONSET) 2360 if (machine_is_assabet() && machine_has_neponset()) 2361 neponset_ncr_set(NCR_ENET_OSC_EN); 2362#endif 2363 platform_set_drvdata(pdev, ndev); 2364 ret = smc_enable_device(pdev); 2365 if (ret) 2366 goto out_release_attrib; 2367 2368 addr = ioremap(res->start, SMC_IO_EXTENT); 2369 if (!addr) { 2370 ret = -ENOMEM; 2371 goto out_release_attrib; 2372 } 2373 2374#ifdef CONFIG_ARCH_PXA 2375 { 2376 struct smc_local *lp = netdev_priv(ndev); 2377 lp->device = &pdev->dev; 2378 lp->physaddr = res->start; 2379 2380 } 2381#endif 2382 2383 ret = smc_probe(ndev, addr, irq_flags); 2384 if (ret != 0) 2385 goto out_iounmap; 2386 2387 smc_request_datacs(pdev, ndev); 2388 2389 return 0; 2390 2391 out_iounmap: 2392 iounmap(addr); 2393 out_release_attrib: 2394 smc_release_attrib(pdev, ndev); 2395 out_release_io: 2396 release_mem_region(res->start, SMC_IO_EXTENT); 2397 out_free_netdev: 2398 free_netdev(ndev); 2399 out: 2400 pr_info("%s: not found (%d).\n", CARDNAME, ret); 2401 2402 return ret; 2403} 2404 2405static int smc_drv_remove(struct platform_device *pdev) 2406{ 2407 struct net_device *ndev = platform_get_drvdata(pdev); 2408 struct smc_local *lp = netdev_priv(ndev); 2409 struct resource *res; 2410 2411 unregister_netdev(ndev); 2412 2413 free_irq(ndev->irq, ndev); 2414 2415#ifdef CONFIG_ARCH_PXA 2416 if (lp->dma_chan) 2417 dma_release_channel(lp->dma_chan); 2418#endif 2419 iounmap(lp->base); 2420 2421 smc_release_datacs(pdev,ndev); 2422 smc_release_attrib(pdev,ndev); 2423 2424 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2425 if (!res) 2426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2427 release_mem_region(res->start, SMC_IO_EXTENT); 2428 2429 free_netdev(ndev); 2430 2431 return 0; 2432} 2433 2434static int smc_drv_suspend(struct device *dev) 2435{ 2436 struct net_device *ndev = dev_get_drvdata(dev); 2437 2438 if (ndev) { 2439 if (netif_running(ndev)) { 2440 netif_device_detach(ndev); 2441 smc_shutdown(ndev); 2442 smc_phy_powerdown(ndev); 2443 } 2444 } 2445 return 0; 2446} 2447 2448static int smc_drv_resume(struct device *dev) 2449{ 2450 struct platform_device *pdev = to_platform_device(dev); 2451 struct net_device *ndev = platform_get_drvdata(pdev); 2452 2453 if (ndev) { 2454 struct smc_local *lp = netdev_priv(ndev); 2455 smc_enable_device(pdev); 2456 if (netif_running(ndev)) { 2457 smc_reset(ndev); 2458 smc_enable(ndev); 2459 if (lp->phy_type != 0) 2460 smc_phy_configure(&lp->phy_configure); 2461 netif_device_attach(ndev); 2462 } 2463 } 2464 return 0; 2465} 2466 2467static const struct dev_pm_ops smc_drv_pm_ops = { 2468 .suspend = smc_drv_suspend, 2469 .resume = smc_drv_resume, 2470}; 2471 2472static struct platform_driver smc_driver = { 2473 .probe = smc_drv_probe, 2474 .remove = smc_drv_remove, 2475 .driver = { 2476 .name = CARDNAME, 2477 .pm = &smc_drv_pm_ops, 2478 .of_match_table = of_match_ptr(smc91x_match), 2479 .acpi_match_table = smc91x_acpi_match, 2480 }, 2481}; 2482 2483module_platform_driver(smc_driver); 2484