1// SPDX-License-Identifier: GPL-2.0-only 2/**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2010-2012 Solarflare Communications Inc. 5 */ 6#include <linux/pci.h> 7#include <linux/module.h> 8#include "net_driver.h" 9#include "efx.h" 10#include "efx_channels.h" 11#include "nic.h" 12#include "io.h" 13#include "mcdi.h" 14#include "filter.h" 15#include "mcdi_pcol.h" 16#include "farch_regs.h" 17#include "siena_sriov.h" 18#include "vfdi.h" 19 20/* Number of longs required to track all the VIs in a VF */ 21#define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX) 22 23/* Maximum number of RX queues supported */ 24#define VF_MAX_RX_QUEUES 63 25 26/** 27 * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour 28 * @VF_TX_FILTER_OFF: Disabled 29 * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only 30 * 2 TX queues allowed per VF. 31 * @VF_TX_FILTER_ON: Enabled 32 */ 33enum efx_vf_tx_filter_mode { 34 VF_TX_FILTER_OFF, 35 VF_TX_FILTER_AUTO, 36 VF_TX_FILTER_ON, 37}; 38 39/** 40 * struct siena_vf - Back-end resource and protocol state for a PCI VF 41 * @efx: The Efx NIC owning this VF 42 * @pci_rid: The PCI requester ID for this VF 43 * @pci_name: The PCI name (formatted address) of this VF 44 * @index: Index of VF within its port and PF. 45 * @req: VFDI incoming request work item. Incoming USR_EV events are received 46 * by the NAPI handler, but must be handled by executing MCDI requests 47 * inside a work item. 48 * @req_addr: VFDI incoming request DMA address (in VF's PCI address space). 49 * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member. 50 * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member. 51 * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by 52 * @status_lock 53 * @busy: VFDI request queued to be processed or being processed. Receiving 54 * a VFDI request when @busy is set is an error condition. 55 * @buf: Incoming VFDI requests are DMA from the VF into this buffer. 56 * @buftbl_base: Buffer table entries for this VF start at this index. 57 * @rx_filtering: Receive filtering has been requested by the VF driver. 58 * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request. 59 * @rx_filter_qid: VF relative qid for RX filter requested by VF. 60 * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported. 61 * @tx_filter_mode: Transmit MAC filtering mode. 62 * @tx_filter_id: Transmit MAC filter ID. 63 * @addr: The MAC address and outer vlan tag of the VF. 64 * @status_addr: VF DMA address of page for &struct vfdi_status updates. 65 * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr, 66 * @peer_page_addrs and @peer_page_count from simultaneous 67 * updates by the VM and consumption by 68 * efx_siena_sriov_update_vf_addr() 69 * @peer_page_addrs: Pointer to an array of guest pages for local addresses. 70 * @peer_page_count: Number of entries in @peer_page_count. 71 * @evq0_addrs: Array of guest pages backing evq0. 72 * @evq0_count: Number of entries in @evq0_addrs. 73 * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler 74 * to wait for flush completions. 75 * @txq_lock: Mutex for TX queue allocation. 76 * @txq_mask: Mask of initialized transmit queues. 77 * @txq_count: Number of initialized transmit queues. 78 * @rxq_mask: Mask of initialized receive queues. 79 * @rxq_count: Number of initialized receive queues. 80 * @rxq_retry_mask: Mask or receive queues that need to be flushed again 81 * due to flush failure. 82 * @rxq_retry_count: Number of receive queues in @rxq_retry_mask. 83 * @reset_work: Work item to schedule a VF reset. 84 */ 85struct siena_vf { 86 struct efx_nic *efx; 87 unsigned int pci_rid; 88 char pci_name[13]; /* dddd:bb:dd.f */ 89 unsigned int index; 90 struct work_struct req; 91 u64 req_addr; 92 int req_type; 93 unsigned req_seqno; 94 unsigned msg_seqno; 95 bool busy; 96 struct efx_buffer buf; 97 unsigned buftbl_base; 98 bool rx_filtering; 99 enum efx_filter_flags rx_filter_flags; 100 unsigned rx_filter_qid; 101 int rx_filter_id; 102 enum efx_vf_tx_filter_mode tx_filter_mode; 103 int tx_filter_id; 104 struct vfdi_endpoint addr; 105 u64 status_addr; 106 struct mutex status_lock; 107 u64 *peer_page_addrs; 108 unsigned peer_page_count; 109 u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) / 110 EFX_BUF_SIZE]; 111 unsigned evq0_count; 112 wait_queue_head_t flush_waitq; 113 struct mutex txq_lock; 114 unsigned long txq_mask[VI_MASK_LENGTH]; 115 unsigned txq_count; 116 unsigned long rxq_mask[VI_MASK_LENGTH]; 117 unsigned rxq_count; 118 unsigned long rxq_retry_mask[VI_MASK_LENGTH]; 119 atomic_t rxq_retry_count; 120 struct work_struct reset_work; 121}; 122 123struct efx_memcpy_req { 124 unsigned int from_rid; 125 void *from_buf; 126 u64 from_addr; 127 unsigned int to_rid; 128 u64 to_addr; 129 unsigned length; 130}; 131 132/** 133 * struct efx_local_addr - A MAC address on the vswitch without a VF. 134 * 135 * Siena does not have a switch, so VFs can't transmit data to each 136 * other. Instead the VFs must be made aware of the local addresses 137 * on the vswitch, so that they can arrange for an alternative 138 * software datapath to be used. 139 * 140 * @link: List head for insertion into efx->local_addr_list. 141 * @addr: Ethernet address 142 */ 143struct efx_local_addr { 144 struct list_head link; 145 u8 addr[ETH_ALEN]; 146}; 147 148/** 149 * struct efx_endpoint_page - Page of vfdi_endpoint structures 150 * 151 * @link: List head for insertion into efx->local_page_list. 152 * @ptr: Pointer to page. 153 * @addr: DMA address of page. 154 */ 155struct efx_endpoint_page { 156 struct list_head link; 157 void *ptr; 158 dma_addr_t addr; 159}; 160 161/* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */ 162#define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \ 163 ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid)) 164#define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \ 165 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \ 166 (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE)) 167#define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \ 168 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \ 169 (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE)) 170 171#define EFX_FIELD_MASK(_field) \ 172 ((1 << _field ## _WIDTH) - 1) 173 174/* VFs can only use this many transmit channels */ 175static unsigned int vf_max_tx_channels = 2; 176module_param(vf_max_tx_channels, uint, 0444); 177MODULE_PARM_DESC(vf_max_tx_channels, 178 "Limit the number of TX channels VFs can use"); 179 180static int max_vfs = -1; 181module_param(max_vfs, int, 0444); 182MODULE_PARM_DESC(max_vfs, 183 "Reduce the number of VFs initialized by the driver"); 184 185/* Workqueue used by VFDI communication. We can't use the global 186 * workqueue because it may be running the VF driver's probe() 187 * routine, which will be blocked there waiting for a VFDI response. 188 */ 189static struct workqueue_struct *vfdi_workqueue; 190 191static unsigned abs_index(struct siena_vf *vf, unsigned index) 192{ 193 return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index; 194} 195 196static int efx_siena_sriov_cmd(struct efx_nic *efx, bool enable, 197 unsigned *vi_scale_out, unsigned *vf_total_out) 198{ 199 MCDI_DECLARE_BUF(inbuf, MC_CMD_SRIOV_IN_LEN); 200 MCDI_DECLARE_BUF(outbuf, MC_CMD_SRIOV_OUT_LEN); 201 unsigned vi_scale, vf_total; 202 size_t outlen; 203 int rc; 204 205 MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0); 206 MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE); 207 MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count); 208 209 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN, 210 outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen); 211 if (rc) 212 return rc; 213 if (outlen < MC_CMD_SRIOV_OUT_LEN) 214 return -EIO; 215 216 vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL); 217 vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE); 218 if (vi_scale > EFX_VI_SCALE_MAX) 219 return -EOPNOTSUPP; 220 221 if (vi_scale_out) 222 *vi_scale_out = vi_scale; 223 if (vf_total_out) 224 *vf_total_out = vf_total; 225 226 return 0; 227} 228 229static void efx_siena_sriov_usrev(struct efx_nic *efx, bool enabled) 230{ 231 struct siena_nic_data *nic_data = efx->nic_data; 232 efx_oword_t reg; 233 234 EFX_POPULATE_OWORD_2(reg, 235 FRF_CZ_USREV_DIS, enabled ? 0 : 1, 236 FRF_CZ_DFLT_EVQ, nic_data->vfdi_channel->channel); 237 efx_writeo(efx, ®, FR_CZ_USR_EV_CFG); 238} 239 240static int efx_siena_sriov_memcpy(struct efx_nic *efx, 241 struct efx_memcpy_req *req, 242 unsigned int count) 243{ 244 MCDI_DECLARE_BUF(inbuf, MCDI_CTL_SDU_LEN_MAX_V1); 245 MCDI_DECLARE_STRUCT_PTR(record); 246 unsigned int index, used; 247 u64 from_addr; 248 u32 from_rid; 249 int rc; 250 251 mb(); /* Finish writing source/reading dest before DMA starts */ 252 253 if (WARN_ON(count > MC_CMD_MEMCPY_IN_RECORD_MAXNUM)) 254 return -ENOBUFS; 255 used = MC_CMD_MEMCPY_IN_LEN(count); 256 257 for (index = 0; index < count; index++) { 258 record = MCDI_ARRAY_STRUCT_PTR(inbuf, MEMCPY_IN_RECORD, index); 259 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_NUM_RECORDS, 260 count); 261 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID, 262 req->to_rid); 263 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR, 264 req->to_addr); 265 if (req->from_buf == NULL) { 266 from_rid = req->from_rid; 267 from_addr = req->from_addr; 268 } else { 269 if (WARN_ON(used + req->length > 270 MCDI_CTL_SDU_LEN_MAX_V1)) { 271 rc = -ENOBUFS; 272 goto out; 273 } 274 275 from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE; 276 from_addr = used; 277 memcpy(_MCDI_PTR(inbuf, used), req->from_buf, 278 req->length); 279 used += req->length; 280 } 281 282 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid); 283 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR, 284 from_addr); 285 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH, 286 req->length); 287 288 ++req; 289 } 290 291 rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL); 292out: 293 mb(); /* Don't write source/read dest before DMA is complete */ 294 295 return rc; 296} 297 298/* The TX filter is entirely controlled by this driver, and is modified 299 * underneath the feet of the VF 300 */ 301static void efx_siena_sriov_reset_tx_filter(struct siena_vf *vf) 302{ 303 struct efx_nic *efx = vf->efx; 304 struct efx_filter_spec filter; 305 u16 vlan; 306 int rc; 307 308 if (vf->tx_filter_id != -1) { 309 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED, 310 vf->tx_filter_id); 311 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n", 312 vf->pci_name, vf->tx_filter_id); 313 vf->tx_filter_id = -1; 314 } 315 316 if (is_zero_ether_addr(vf->addr.mac_addr)) 317 return; 318 319 /* Turn on TX filtering automatically if not explicitly 320 * enabled or disabled. 321 */ 322 if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2) 323 vf->tx_filter_mode = VF_TX_FILTER_ON; 324 325 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK; 326 efx_filter_init_tx(&filter, abs_index(vf, 0)); 327 rc = efx_filter_set_eth_local(&filter, 328 vlan ? vlan : EFX_FILTER_VID_UNSPEC, 329 vf->addr.mac_addr); 330 BUG_ON(rc); 331 332 rc = efx_filter_insert_filter(efx, &filter, true); 333 if (rc < 0) { 334 netif_warn(efx, hw, efx->net_dev, 335 "Unable to migrate tx filter for vf %s\n", 336 vf->pci_name); 337 } else { 338 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n", 339 vf->pci_name, rc); 340 vf->tx_filter_id = rc; 341 } 342} 343 344/* The RX filter is managed here on behalf of the VF driver */ 345static void efx_siena_sriov_reset_rx_filter(struct siena_vf *vf) 346{ 347 struct efx_nic *efx = vf->efx; 348 struct efx_filter_spec filter; 349 u16 vlan; 350 int rc; 351 352 if (vf->rx_filter_id != -1) { 353 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED, 354 vf->rx_filter_id); 355 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n", 356 vf->pci_name, vf->rx_filter_id); 357 vf->rx_filter_id = -1; 358 } 359 360 if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr)) 361 return; 362 363 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK; 364 efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED, 365 vf->rx_filter_flags, 366 abs_index(vf, vf->rx_filter_qid)); 367 rc = efx_filter_set_eth_local(&filter, 368 vlan ? vlan : EFX_FILTER_VID_UNSPEC, 369 vf->addr.mac_addr); 370 BUG_ON(rc); 371 372 rc = efx_filter_insert_filter(efx, &filter, true); 373 if (rc < 0) { 374 netif_warn(efx, hw, efx->net_dev, 375 "Unable to insert rx filter for vf %s\n", 376 vf->pci_name); 377 } else { 378 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n", 379 vf->pci_name, rc); 380 vf->rx_filter_id = rc; 381 } 382} 383 384static void __efx_siena_sriov_update_vf_addr(struct siena_vf *vf) 385{ 386 struct efx_nic *efx = vf->efx; 387 struct siena_nic_data *nic_data = efx->nic_data; 388 389 efx_siena_sriov_reset_tx_filter(vf); 390 efx_siena_sriov_reset_rx_filter(vf); 391 queue_work(vfdi_workqueue, &nic_data->peer_work); 392} 393 394/* Push the peer list to this VF. The caller must hold status_lock to interlock 395 * with VFDI requests, and they must be serialised against manipulation of 396 * local_page_list, either by acquiring local_lock or by running from 397 * efx_siena_sriov_peer_work() 398 */ 399static void __efx_siena_sriov_push_vf_status(struct siena_vf *vf) 400{ 401 struct efx_nic *efx = vf->efx; 402 struct siena_nic_data *nic_data = efx->nic_data; 403 struct vfdi_status *status = nic_data->vfdi_status.addr; 404 struct efx_memcpy_req copy[4]; 405 struct efx_endpoint_page *epp; 406 unsigned int pos, count; 407 unsigned data_offset; 408 efx_qword_t event; 409 410 WARN_ON(!mutex_is_locked(&vf->status_lock)); 411 WARN_ON(!vf->status_addr); 412 413 status->local = vf->addr; 414 status->generation_end = ++status->generation_start; 415 416 memset(copy, '\0', sizeof(copy)); 417 /* Write generation_start */ 418 copy[0].from_buf = &status->generation_start; 419 copy[0].to_rid = vf->pci_rid; 420 copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status, 421 generation_start); 422 copy[0].length = sizeof(status->generation_start); 423 /* DMA the rest of the structure (excluding the generations). This 424 * assumes that the non-generation portion of vfdi_status is in 425 * one chunk starting at the version member. 426 */ 427 data_offset = offsetof(struct vfdi_status, version); 428 copy[1].from_rid = efx->pci_dev->devfn; 429 copy[1].from_addr = nic_data->vfdi_status.dma_addr + data_offset; 430 copy[1].to_rid = vf->pci_rid; 431 copy[1].to_addr = vf->status_addr + data_offset; 432 copy[1].length = status->length - data_offset; 433 434 /* Copy the peer pages */ 435 pos = 2; 436 count = 0; 437 list_for_each_entry(epp, &nic_data->local_page_list, link) { 438 if (count == vf->peer_page_count) { 439 /* The VF driver will know they need to provide more 440 * pages because peer_addr_count is too large. 441 */ 442 break; 443 } 444 copy[pos].from_buf = NULL; 445 copy[pos].from_rid = efx->pci_dev->devfn; 446 copy[pos].from_addr = epp->addr; 447 copy[pos].to_rid = vf->pci_rid; 448 copy[pos].to_addr = vf->peer_page_addrs[count]; 449 copy[pos].length = EFX_PAGE_SIZE; 450 451 if (++pos == ARRAY_SIZE(copy)) { 452 efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy)); 453 pos = 0; 454 } 455 ++count; 456 } 457 458 /* Write generation_end */ 459 copy[pos].from_buf = &status->generation_end; 460 copy[pos].to_rid = vf->pci_rid; 461 copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status, 462 generation_end); 463 copy[pos].length = sizeof(status->generation_end); 464 efx_siena_sriov_memcpy(efx, copy, pos + 1); 465 466 /* Notify the guest */ 467 EFX_POPULATE_QWORD_3(event, 468 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV, 469 VFDI_EV_SEQ, (vf->msg_seqno & 0xff), 470 VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS); 471 ++vf->msg_seqno; 472 efx_farch_generate_event(efx, 473 EFX_VI_BASE + vf->index * efx_vf_size(efx), 474 &event); 475} 476 477static void efx_siena_sriov_bufs(struct efx_nic *efx, unsigned offset, 478 u64 *addr, unsigned count) 479{ 480 efx_qword_t buf; 481 unsigned pos; 482 483 for (pos = 0; pos < count; ++pos) { 484 EFX_POPULATE_QWORD_3(buf, 485 FRF_AZ_BUF_ADR_REGION, 0, 486 FRF_AZ_BUF_ADR_FBUF, 487 addr ? addr[pos] >> 12 : 0, 488 FRF_AZ_BUF_OWNER_ID_FBUF, 0); 489 efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL, 490 &buf, offset + pos); 491 } 492} 493 494static bool bad_vf_index(struct efx_nic *efx, unsigned index) 495{ 496 return index >= efx_vf_size(efx); 497} 498 499static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count) 500{ 501 unsigned max_buf_count = max_entry_count * 502 sizeof(efx_qword_t) / EFX_BUF_SIZE; 503 504 return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count); 505} 506 507/* Check that VI specified by per-port index belongs to a VF. 508 * Optionally set VF index and VI index within the VF. 509 */ 510static bool map_vi_index(struct efx_nic *efx, unsigned abs_index, 511 struct siena_vf **vf_out, unsigned *rel_index_out) 512{ 513 struct siena_nic_data *nic_data = efx->nic_data; 514 unsigned vf_i; 515 516 if (abs_index < EFX_VI_BASE) 517 return true; 518 vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx); 519 if (vf_i >= efx->vf_init_count) 520 return true; 521 522 if (vf_out) 523 *vf_out = nic_data->vf + vf_i; 524 if (rel_index_out) 525 *rel_index_out = abs_index % efx_vf_size(efx); 526 return false; 527} 528 529static int efx_vfdi_init_evq(struct siena_vf *vf) 530{ 531 struct efx_nic *efx = vf->efx; 532 struct vfdi_req *req = vf->buf.addr; 533 unsigned vf_evq = req->u.init_evq.index; 534 unsigned buf_count = req->u.init_evq.buf_count; 535 unsigned abs_evq = abs_index(vf, vf_evq); 536 unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq); 537 efx_oword_t reg; 538 539 if (bad_vf_index(efx, vf_evq) || 540 bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) { 541 if (net_ratelimit()) 542 netif_err(efx, hw, efx->net_dev, 543 "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n", 544 vf->pci_name, vf_evq, buf_count); 545 return VFDI_RC_EINVAL; 546 } 547 548 efx_siena_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count); 549 550 EFX_POPULATE_OWORD_3(reg, 551 FRF_CZ_TIMER_Q_EN, 1, 552 FRF_CZ_HOST_NOTIFY_MODE, 0, 553 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 554 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, abs_evq); 555 EFX_POPULATE_OWORD_3(reg, 556 FRF_AZ_EVQ_EN, 1, 557 FRF_AZ_EVQ_SIZE, __ffs(buf_count), 558 FRF_AZ_EVQ_BUF_BASE_ID, buftbl); 559 efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, abs_evq); 560 561 if (vf_evq == 0) { 562 memcpy(vf->evq0_addrs, req->u.init_evq.addr, 563 buf_count * sizeof(u64)); 564 vf->evq0_count = buf_count; 565 } 566 567 return VFDI_RC_SUCCESS; 568} 569 570static int efx_vfdi_init_rxq(struct siena_vf *vf) 571{ 572 struct efx_nic *efx = vf->efx; 573 struct vfdi_req *req = vf->buf.addr; 574 unsigned vf_rxq = req->u.init_rxq.index; 575 unsigned vf_evq = req->u.init_rxq.evq; 576 unsigned buf_count = req->u.init_rxq.buf_count; 577 unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq); 578 unsigned label; 579 efx_oword_t reg; 580 581 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) || 582 vf_rxq >= VF_MAX_RX_QUEUES || 583 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) { 584 if (net_ratelimit()) 585 netif_err(efx, hw, efx->net_dev, 586 "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d " 587 "buf_count %d\n", vf->pci_name, vf_rxq, 588 vf_evq, buf_count); 589 return VFDI_RC_EINVAL; 590 } 591 if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask)) 592 ++vf->rxq_count; 593 efx_siena_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count); 594 595 label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL); 596 EFX_POPULATE_OWORD_6(reg, 597 FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl, 598 FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq), 599 FRF_AZ_RX_DESCQ_LABEL, label, 600 FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count), 601 FRF_AZ_RX_DESCQ_JUMBO, 602 !!(req->u.init_rxq.flags & 603 VFDI_RXQ_FLAG_SCATTER_EN), 604 FRF_AZ_RX_DESCQ_EN, 1); 605 efx_writeo_table(efx, ®, FR_BZ_RX_DESC_PTR_TBL, 606 abs_index(vf, vf_rxq)); 607 608 return VFDI_RC_SUCCESS; 609} 610 611static int efx_vfdi_init_txq(struct siena_vf *vf) 612{ 613 struct efx_nic *efx = vf->efx; 614 struct vfdi_req *req = vf->buf.addr; 615 unsigned vf_txq = req->u.init_txq.index; 616 unsigned vf_evq = req->u.init_txq.evq; 617 unsigned buf_count = req->u.init_txq.buf_count; 618 unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq); 619 unsigned label, eth_filt_en; 620 efx_oword_t reg; 621 622 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) || 623 vf_txq >= vf_max_tx_channels || 624 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) { 625 if (net_ratelimit()) 626 netif_err(efx, hw, efx->net_dev, 627 "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d " 628 "buf_count %d\n", vf->pci_name, vf_txq, 629 vf_evq, buf_count); 630 return VFDI_RC_EINVAL; 631 } 632 633 mutex_lock(&vf->txq_lock); 634 if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask)) 635 ++vf->txq_count; 636 mutex_unlock(&vf->txq_lock); 637 efx_siena_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count); 638 639 eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON; 640 641 label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL); 642 EFX_POPULATE_OWORD_8(reg, 643 FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U), 644 FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en, 645 FRF_AZ_TX_DESCQ_EN, 1, 646 FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl, 647 FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq), 648 FRF_AZ_TX_DESCQ_LABEL, label, 649 FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count), 650 FRF_BZ_TX_NON_IP_DROP_DIS, 1); 651 efx_writeo_table(efx, ®, FR_BZ_TX_DESC_PTR_TBL, 652 abs_index(vf, vf_txq)); 653 654 return VFDI_RC_SUCCESS; 655} 656 657/* Returns true when efx_vfdi_fini_all_queues should wake */ 658static bool efx_vfdi_flush_wake(struct siena_vf *vf) 659{ 660 /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */ 661 smp_mb(); 662 663 return (!vf->txq_count && !vf->rxq_count) || 664 atomic_read(&vf->rxq_retry_count); 665} 666 667static void efx_vfdi_flush_clear(struct siena_vf *vf) 668{ 669 memset(vf->txq_mask, 0, sizeof(vf->txq_mask)); 670 vf->txq_count = 0; 671 memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask)); 672 vf->rxq_count = 0; 673 memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask)); 674 atomic_set(&vf->rxq_retry_count, 0); 675} 676 677static int efx_vfdi_fini_all_queues(struct siena_vf *vf) 678{ 679 struct efx_nic *efx = vf->efx; 680 efx_oword_t reg; 681 unsigned count = efx_vf_size(efx); 682 unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx); 683 unsigned timeout = HZ; 684 unsigned index, rxqs_count; 685 MCDI_DECLARE_BUF(inbuf, MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX); 686 int rc; 687 688 BUILD_BUG_ON(VF_MAX_RX_QUEUES > 689 MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM); 690 691 rtnl_lock(); 692 siena_prepare_flush(efx); 693 rtnl_unlock(); 694 695 /* Flush all the initialized queues */ 696 rxqs_count = 0; 697 for (index = 0; index < count; ++index) { 698 if (test_bit(index, vf->txq_mask)) { 699 EFX_POPULATE_OWORD_2(reg, 700 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, 701 FRF_AZ_TX_FLUSH_DESCQ, 702 vf_offset + index); 703 efx_writeo(efx, ®, FR_AZ_TX_FLUSH_DESCQ); 704 } 705 if (test_bit(index, vf->rxq_mask)) { 706 MCDI_SET_ARRAY_DWORD( 707 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, 708 rxqs_count, vf_offset + index); 709 rxqs_count++; 710 } 711 } 712 713 atomic_set(&vf->rxq_retry_count, 0); 714 while (timeout && (vf->rxq_count || vf->txq_count)) { 715 rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf, 716 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(rxqs_count), 717 NULL, 0, NULL); 718 WARN_ON(rc < 0); 719 720 timeout = wait_event_timeout(vf->flush_waitq, 721 efx_vfdi_flush_wake(vf), 722 timeout); 723 rxqs_count = 0; 724 for (index = 0; index < count; ++index) { 725 if (test_and_clear_bit(index, vf->rxq_retry_mask)) { 726 atomic_dec(&vf->rxq_retry_count); 727 MCDI_SET_ARRAY_DWORD( 728 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, 729 rxqs_count, vf_offset + index); 730 rxqs_count++; 731 } 732 } 733 } 734 735 rtnl_lock(); 736 siena_finish_flush(efx); 737 rtnl_unlock(); 738 739 /* Irrespective of success/failure, fini the queues */ 740 EFX_ZERO_OWORD(reg); 741 for (index = 0; index < count; ++index) { 742 efx_writeo_table(efx, ®, FR_BZ_RX_DESC_PTR_TBL, 743 vf_offset + index); 744 efx_writeo_table(efx, ®, FR_BZ_TX_DESC_PTR_TBL, 745 vf_offset + index); 746 efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, 747 vf_offset + index); 748 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, 749 vf_offset + index); 750 } 751 efx_siena_sriov_bufs(efx, vf->buftbl_base, NULL, 752 EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx)); 753 efx_vfdi_flush_clear(vf); 754 755 vf->evq0_count = 0; 756 757 return timeout ? 0 : VFDI_RC_ETIMEDOUT; 758} 759 760static int efx_vfdi_insert_filter(struct siena_vf *vf) 761{ 762 struct efx_nic *efx = vf->efx; 763 struct siena_nic_data *nic_data = efx->nic_data; 764 struct vfdi_req *req = vf->buf.addr; 765 unsigned vf_rxq = req->u.mac_filter.rxq; 766 unsigned flags; 767 768 if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) { 769 if (net_ratelimit()) 770 netif_err(efx, hw, efx->net_dev, 771 "ERROR: Invalid INSERT_FILTER from %s: rxq %d " 772 "flags 0x%x\n", vf->pci_name, vf_rxq, 773 req->u.mac_filter.flags); 774 return VFDI_RC_EINVAL; 775 } 776 777 flags = 0; 778 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS) 779 flags |= EFX_FILTER_FLAG_RX_RSS; 780 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER) 781 flags |= EFX_FILTER_FLAG_RX_SCATTER; 782 vf->rx_filter_flags = flags; 783 vf->rx_filter_qid = vf_rxq; 784 vf->rx_filtering = true; 785 786 efx_siena_sriov_reset_rx_filter(vf); 787 queue_work(vfdi_workqueue, &nic_data->peer_work); 788 789 return VFDI_RC_SUCCESS; 790} 791 792static int efx_vfdi_remove_all_filters(struct siena_vf *vf) 793{ 794 struct efx_nic *efx = vf->efx; 795 struct siena_nic_data *nic_data = efx->nic_data; 796 797 vf->rx_filtering = false; 798 efx_siena_sriov_reset_rx_filter(vf); 799 queue_work(vfdi_workqueue, &nic_data->peer_work); 800 801 return VFDI_RC_SUCCESS; 802} 803 804static int efx_vfdi_set_status_page(struct siena_vf *vf) 805{ 806 struct efx_nic *efx = vf->efx; 807 struct siena_nic_data *nic_data = efx->nic_data; 808 struct vfdi_req *req = vf->buf.addr; 809 u64 page_count = req->u.set_status_page.peer_page_count; 810 u64 max_page_count = 811 (EFX_PAGE_SIZE - 812 offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0])) 813 / sizeof(req->u.set_status_page.peer_page_addr[0]); 814 815 if (!req->u.set_status_page.dma_addr || page_count > max_page_count) { 816 if (net_ratelimit()) 817 netif_err(efx, hw, efx->net_dev, 818 "ERROR: Invalid SET_STATUS_PAGE from %s\n", 819 vf->pci_name); 820 return VFDI_RC_EINVAL; 821 } 822 823 mutex_lock(&nic_data->local_lock); 824 mutex_lock(&vf->status_lock); 825 vf->status_addr = req->u.set_status_page.dma_addr; 826 827 kfree(vf->peer_page_addrs); 828 vf->peer_page_addrs = NULL; 829 vf->peer_page_count = 0; 830 831 if (page_count) { 832 vf->peer_page_addrs = kcalloc(page_count, sizeof(u64), 833 GFP_KERNEL); 834 if (vf->peer_page_addrs) { 835 memcpy(vf->peer_page_addrs, 836 req->u.set_status_page.peer_page_addr, 837 page_count * sizeof(u64)); 838 vf->peer_page_count = page_count; 839 } 840 } 841 842 __efx_siena_sriov_push_vf_status(vf); 843 mutex_unlock(&vf->status_lock); 844 mutex_unlock(&nic_data->local_lock); 845 846 return VFDI_RC_SUCCESS; 847} 848 849static int efx_vfdi_clear_status_page(struct siena_vf *vf) 850{ 851 mutex_lock(&vf->status_lock); 852 vf->status_addr = 0; 853 mutex_unlock(&vf->status_lock); 854 855 return VFDI_RC_SUCCESS; 856} 857 858typedef int (*efx_vfdi_op_t)(struct siena_vf *vf); 859 860static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = { 861 [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq, 862 [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq, 863 [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq, 864 [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues, 865 [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter, 866 [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters, 867 [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page, 868 [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page, 869}; 870 871static void efx_siena_sriov_vfdi(struct work_struct *work) 872{ 873 struct siena_vf *vf = container_of(work, struct siena_vf, req); 874 struct efx_nic *efx = vf->efx; 875 struct vfdi_req *req = vf->buf.addr; 876 struct efx_memcpy_req copy[2]; 877 int rc; 878 879 /* Copy this page into the local address space */ 880 memset(copy, '\0', sizeof(copy)); 881 copy[0].from_rid = vf->pci_rid; 882 copy[0].from_addr = vf->req_addr; 883 copy[0].to_rid = efx->pci_dev->devfn; 884 copy[0].to_addr = vf->buf.dma_addr; 885 copy[0].length = EFX_PAGE_SIZE; 886 rc = efx_siena_sriov_memcpy(efx, copy, 1); 887 if (rc) { 888 /* If we can't get the request, we can't reply to the caller */ 889 if (net_ratelimit()) 890 netif_err(efx, hw, efx->net_dev, 891 "ERROR: Unable to fetch VFDI request from %s rc %d\n", 892 vf->pci_name, -rc); 893 vf->busy = false; 894 return; 895 } 896 897 if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) { 898 rc = vfdi_ops[req->op](vf); 899 if (rc == 0) { 900 netif_dbg(efx, hw, efx->net_dev, 901 "vfdi request %d from %s ok\n", 902 req->op, vf->pci_name); 903 } 904 } else { 905 netif_dbg(efx, hw, efx->net_dev, 906 "ERROR: Unrecognised request %d from VF %s addr " 907 "%llx\n", req->op, vf->pci_name, 908 (unsigned long long)vf->req_addr); 909 rc = VFDI_RC_EOPNOTSUPP; 910 } 911 912 /* Allow subsequent VF requests */ 913 vf->busy = false; 914 smp_wmb(); 915 916 /* Respond to the request */ 917 req->rc = rc; 918 req->op = VFDI_OP_RESPONSE; 919 920 memset(copy, '\0', sizeof(copy)); 921 copy[0].from_buf = &req->rc; 922 copy[0].to_rid = vf->pci_rid; 923 copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc); 924 copy[0].length = sizeof(req->rc); 925 copy[1].from_buf = &req->op; 926 copy[1].to_rid = vf->pci_rid; 927 copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op); 928 copy[1].length = sizeof(req->op); 929 930 (void)efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy)); 931} 932 933 934 935/* After a reset the event queues inside the guests no longer exist. Fill the 936 * event ring in guest memory with VFDI reset events, then (re-initialise) the 937 * event queue to raise an interrupt. The guest driver will then recover. 938 */ 939 940static void efx_siena_sriov_reset_vf(struct siena_vf *vf, 941 struct efx_buffer *buffer) 942{ 943 struct efx_nic *efx = vf->efx; 944 struct efx_memcpy_req copy_req[4]; 945 efx_qword_t event; 946 unsigned int pos, count, k, buftbl, abs_evq; 947 efx_oword_t reg; 948 efx_dword_t ptr; 949 int rc; 950 951 BUG_ON(buffer->len != EFX_PAGE_SIZE); 952 953 if (!vf->evq0_count) 954 return; 955 BUG_ON(vf->evq0_count & (vf->evq0_count - 1)); 956 957 mutex_lock(&vf->status_lock); 958 EFX_POPULATE_QWORD_3(event, 959 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV, 960 VFDI_EV_SEQ, vf->msg_seqno, 961 VFDI_EV_TYPE, VFDI_EV_TYPE_RESET); 962 vf->msg_seqno++; 963 for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event)) 964 memcpy(buffer->addr + pos, &event, sizeof(event)); 965 966 for (pos = 0; pos < vf->evq0_count; pos += count) { 967 count = min_t(unsigned, vf->evq0_count - pos, 968 ARRAY_SIZE(copy_req)); 969 for (k = 0; k < count; k++) { 970 copy_req[k].from_buf = NULL; 971 copy_req[k].from_rid = efx->pci_dev->devfn; 972 copy_req[k].from_addr = buffer->dma_addr; 973 copy_req[k].to_rid = vf->pci_rid; 974 copy_req[k].to_addr = vf->evq0_addrs[pos + k]; 975 copy_req[k].length = EFX_PAGE_SIZE; 976 } 977 rc = efx_siena_sriov_memcpy(efx, copy_req, count); 978 if (rc) { 979 if (net_ratelimit()) 980 netif_err(efx, hw, efx->net_dev, 981 "ERROR: Unable to notify %s of reset" 982 ": %d\n", vf->pci_name, -rc); 983 break; 984 } 985 } 986 987 /* Reinitialise, arm and trigger evq0 */ 988 abs_evq = abs_index(vf, 0); 989 buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0); 990 efx_siena_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count); 991 992 EFX_POPULATE_OWORD_3(reg, 993 FRF_CZ_TIMER_Q_EN, 1, 994 FRF_CZ_HOST_NOTIFY_MODE, 0, 995 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 996 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, abs_evq); 997 EFX_POPULATE_OWORD_3(reg, 998 FRF_AZ_EVQ_EN, 1, 999 FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count), 1000 FRF_AZ_EVQ_BUF_BASE_ID, buftbl); 1001 efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, abs_evq); 1002 EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0); 1003 efx_writed(efx, &ptr, FR_BZ_EVQ_RPTR + FR_BZ_EVQ_RPTR_STEP * abs_evq); 1004 1005 mutex_unlock(&vf->status_lock); 1006} 1007 1008static void efx_siena_sriov_reset_vf_work(struct work_struct *work) 1009{ 1010 struct siena_vf *vf = container_of(work, struct siena_vf, req); 1011 struct efx_nic *efx = vf->efx; 1012 struct efx_buffer buf; 1013 1014 if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) { 1015 efx_siena_sriov_reset_vf(vf, &buf); 1016 efx_nic_free_buffer(efx, &buf); 1017 } 1018} 1019 1020static void efx_siena_sriov_handle_no_channel(struct efx_nic *efx) 1021{ 1022 netif_err(efx, drv, efx->net_dev, 1023 "ERROR: IOV requires MSI-X and 1 additional interrupt" 1024 "vector. IOV disabled\n"); 1025 efx->vf_count = 0; 1026} 1027 1028static int efx_siena_sriov_probe_channel(struct efx_channel *channel) 1029{ 1030 struct siena_nic_data *nic_data = channel->efx->nic_data; 1031 nic_data->vfdi_channel = channel; 1032 1033 return 0; 1034} 1035 1036static void 1037efx_siena_sriov_get_channel_name(struct efx_channel *channel, 1038 char *buf, size_t len) 1039{ 1040 snprintf(buf, len, "%s-iov", channel->efx->name); 1041} 1042 1043static const struct efx_channel_type efx_siena_sriov_channel_type = { 1044 .handle_no_channel = efx_siena_sriov_handle_no_channel, 1045 .pre_probe = efx_siena_sriov_probe_channel, 1046 .post_remove = efx_channel_dummy_op_void, 1047 .get_name = efx_siena_sriov_get_channel_name, 1048 /* no copy operation; channel must not be reallocated */ 1049 .keep_eventq = true, 1050}; 1051 1052void efx_siena_sriov_probe(struct efx_nic *efx) 1053{ 1054 unsigned count; 1055 1056 if (!max_vfs) 1057 return; 1058 1059 if (efx_siena_sriov_cmd(efx, false, &efx->vi_scale, &count)) { 1060 pci_info(efx->pci_dev, "no SR-IOV VFs probed\n"); 1061 return; 1062 } 1063 if (count > 0 && count > max_vfs) 1064 count = max_vfs; 1065 1066 /* efx_nic_dimension_resources() will reduce vf_count as appopriate */ 1067 efx->vf_count = count; 1068 1069 efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_siena_sriov_channel_type; 1070} 1071 1072/* Copy the list of individual addresses into the vfdi_status.peers 1073 * array and auxiliary pages, protected by %local_lock. Drop that lock 1074 * and then broadcast the address list to every VF. 1075 */ 1076static void efx_siena_sriov_peer_work(struct work_struct *data) 1077{ 1078 struct siena_nic_data *nic_data = container_of(data, 1079 struct siena_nic_data, 1080 peer_work); 1081 struct efx_nic *efx = nic_data->efx; 1082 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr; 1083 struct siena_vf *vf; 1084 struct efx_local_addr *local_addr; 1085 struct vfdi_endpoint *peer; 1086 struct efx_endpoint_page *epp; 1087 struct list_head pages; 1088 unsigned int peer_space; 1089 unsigned int peer_count; 1090 unsigned int pos; 1091 1092 mutex_lock(&nic_data->local_lock); 1093 1094 /* Move the existing peer pages off %local_page_list */ 1095 INIT_LIST_HEAD(&pages); 1096 list_splice_tail_init(&nic_data->local_page_list, &pages); 1097 1098 /* Populate the VF addresses starting from entry 1 (entry 0 is 1099 * the PF address) 1100 */ 1101 peer = vfdi_status->peers + 1; 1102 peer_space = ARRAY_SIZE(vfdi_status->peers) - 1; 1103 peer_count = 1; 1104 for (pos = 0; pos < efx->vf_count; ++pos) { 1105 vf = nic_data->vf + pos; 1106 1107 mutex_lock(&vf->status_lock); 1108 if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) { 1109 *peer++ = vf->addr; 1110 ++peer_count; 1111 --peer_space; 1112 BUG_ON(peer_space == 0); 1113 } 1114 mutex_unlock(&vf->status_lock); 1115 } 1116 1117 /* Fill the remaining addresses */ 1118 list_for_each_entry(local_addr, &nic_data->local_addr_list, link) { 1119 ether_addr_copy(peer->mac_addr, local_addr->addr); 1120 peer->tci = 0; 1121 ++peer; 1122 ++peer_count; 1123 if (--peer_space == 0) { 1124 if (list_empty(&pages)) { 1125 epp = kmalloc(sizeof(*epp), GFP_KERNEL); 1126 if (!epp) 1127 break; 1128 epp->ptr = dma_alloc_coherent( 1129 &efx->pci_dev->dev, EFX_PAGE_SIZE, 1130 &epp->addr, GFP_KERNEL); 1131 if (!epp->ptr) { 1132 kfree(epp); 1133 break; 1134 } 1135 } else { 1136 epp = list_first_entry( 1137 &pages, struct efx_endpoint_page, link); 1138 list_del(&epp->link); 1139 } 1140 1141 list_add_tail(&epp->link, &nic_data->local_page_list); 1142 peer = (struct vfdi_endpoint *)epp->ptr; 1143 peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint); 1144 } 1145 } 1146 vfdi_status->peer_count = peer_count; 1147 mutex_unlock(&nic_data->local_lock); 1148 1149 /* Free any now unused endpoint pages */ 1150 while (!list_empty(&pages)) { 1151 epp = list_first_entry( 1152 &pages, struct efx_endpoint_page, link); 1153 list_del(&epp->link); 1154 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE, 1155 epp->ptr, epp->addr); 1156 kfree(epp); 1157 } 1158 1159 /* Finally, push the pages */ 1160 for (pos = 0; pos < efx->vf_count; ++pos) { 1161 vf = nic_data->vf + pos; 1162 1163 mutex_lock(&vf->status_lock); 1164 if (vf->status_addr) 1165 __efx_siena_sriov_push_vf_status(vf); 1166 mutex_unlock(&vf->status_lock); 1167 } 1168} 1169 1170static void efx_siena_sriov_free_local(struct efx_nic *efx) 1171{ 1172 struct siena_nic_data *nic_data = efx->nic_data; 1173 struct efx_local_addr *local_addr; 1174 struct efx_endpoint_page *epp; 1175 1176 while (!list_empty(&nic_data->local_addr_list)) { 1177 local_addr = list_first_entry(&nic_data->local_addr_list, 1178 struct efx_local_addr, link); 1179 list_del(&local_addr->link); 1180 kfree(local_addr); 1181 } 1182 1183 while (!list_empty(&nic_data->local_page_list)) { 1184 epp = list_first_entry(&nic_data->local_page_list, 1185 struct efx_endpoint_page, link); 1186 list_del(&epp->link); 1187 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE, 1188 epp->ptr, epp->addr); 1189 kfree(epp); 1190 } 1191} 1192 1193static int efx_siena_sriov_vf_alloc(struct efx_nic *efx) 1194{ 1195 unsigned index; 1196 struct siena_vf *vf; 1197 struct siena_nic_data *nic_data = efx->nic_data; 1198 1199 nic_data->vf = kcalloc(efx->vf_count, sizeof(*nic_data->vf), 1200 GFP_KERNEL); 1201 if (!nic_data->vf) 1202 return -ENOMEM; 1203 1204 for (index = 0; index < efx->vf_count; ++index) { 1205 vf = nic_data->vf + index; 1206 1207 vf->efx = efx; 1208 vf->index = index; 1209 vf->rx_filter_id = -1; 1210 vf->tx_filter_mode = VF_TX_FILTER_AUTO; 1211 vf->tx_filter_id = -1; 1212 INIT_WORK(&vf->req, efx_siena_sriov_vfdi); 1213 INIT_WORK(&vf->reset_work, efx_siena_sriov_reset_vf_work); 1214 init_waitqueue_head(&vf->flush_waitq); 1215 mutex_init(&vf->status_lock); 1216 mutex_init(&vf->txq_lock); 1217 } 1218 1219 return 0; 1220} 1221 1222static void efx_siena_sriov_vfs_fini(struct efx_nic *efx) 1223{ 1224 struct siena_nic_data *nic_data = efx->nic_data; 1225 struct siena_vf *vf; 1226 unsigned int pos; 1227 1228 for (pos = 0; pos < efx->vf_count; ++pos) { 1229 vf = nic_data->vf + pos; 1230 1231 efx_nic_free_buffer(efx, &vf->buf); 1232 kfree(vf->peer_page_addrs); 1233 vf->peer_page_addrs = NULL; 1234 vf->peer_page_count = 0; 1235 1236 vf->evq0_count = 0; 1237 } 1238} 1239 1240static int efx_siena_sriov_vfs_init(struct efx_nic *efx) 1241{ 1242 struct pci_dev *pci_dev = efx->pci_dev; 1243 struct siena_nic_data *nic_data = efx->nic_data; 1244 unsigned index, devfn, sriov, buftbl_base; 1245 u16 offset, stride; 1246 struct siena_vf *vf; 1247 int rc; 1248 1249 sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV); 1250 if (!sriov) 1251 return -ENOENT; 1252 1253 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset); 1254 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride); 1255 1256 buftbl_base = nic_data->vf_buftbl_base; 1257 devfn = pci_dev->devfn + offset; 1258 for (index = 0; index < efx->vf_count; ++index) { 1259 vf = nic_data->vf + index; 1260 1261 /* Reserve buffer entries */ 1262 vf->buftbl_base = buftbl_base; 1263 buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx); 1264 1265 vf->pci_rid = devfn; 1266 snprintf(vf->pci_name, sizeof(vf->pci_name), 1267 "%04x:%02x:%02x.%d", 1268 pci_domain_nr(pci_dev->bus), pci_dev->bus->number, 1269 PCI_SLOT(devfn), PCI_FUNC(devfn)); 1270 1271 rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE, 1272 GFP_KERNEL); 1273 if (rc) 1274 goto fail; 1275 1276 devfn += stride; 1277 } 1278 1279 return 0; 1280 1281fail: 1282 efx_siena_sriov_vfs_fini(efx); 1283 return rc; 1284} 1285 1286int efx_siena_sriov_init(struct efx_nic *efx) 1287{ 1288 struct net_device *net_dev = efx->net_dev; 1289 struct siena_nic_data *nic_data = efx->nic_data; 1290 struct vfdi_status *vfdi_status; 1291 int rc; 1292 1293 /* Ensure there's room for vf_channel */ 1294 BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE); 1295 /* Ensure that VI_BASE is aligned on VI_SCALE */ 1296 BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1)); 1297 1298 if (efx->vf_count == 0) 1299 return 0; 1300 1301 rc = efx_siena_sriov_cmd(efx, true, NULL, NULL); 1302 if (rc) 1303 goto fail_cmd; 1304 1305 rc = efx_nic_alloc_buffer(efx, &nic_data->vfdi_status, 1306 sizeof(*vfdi_status), GFP_KERNEL); 1307 if (rc) 1308 goto fail_status; 1309 vfdi_status = nic_data->vfdi_status.addr; 1310 memset(vfdi_status, 0, sizeof(*vfdi_status)); 1311 vfdi_status->version = 1; 1312 vfdi_status->length = sizeof(*vfdi_status); 1313 vfdi_status->max_tx_channels = vf_max_tx_channels; 1314 vfdi_status->vi_scale = efx->vi_scale; 1315 vfdi_status->rss_rxq_count = efx->rss_spread; 1316 vfdi_status->peer_count = 1 + efx->vf_count; 1317 vfdi_status->timer_quantum_ns = efx->timer_quantum_ns; 1318 1319 rc = efx_siena_sriov_vf_alloc(efx); 1320 if (rc) 1321 goto fail_alloc; 1322 1323 mutex_init(&nic_data->local_lock); 1324 INIT_WORK(&nic_data->peer_work, efx_siena_sriov_peer_work); 1325 INIT_LIST_HEAD(&nic_data->local_addr_list); 1326 INIT_LIST_HEAD(&nic_data->local_page_list); 1327 1328 rc = efx_siena_sriov_vfs_init(efx); 1329 if (rc) 1330 goto fail_vfs; 1331 1332 rtnl_lock(); 1333 ether_addr_copy(vfdi_status->peers[0].mac_addr, net_dev->dev_addr); 1334 efx->vf_init_count = efx->vf_count; 1335 rtnl_unlock(); 1336 1337 efx_siena_sriov_usrev(efx, true); 1338 1339 /* At this point we must be ready to accept VFDI requests */ 1340 1341 rc = pci_enable_sriov(efx->pci_dev, efx->vf_count); 1342 if (rc) 1343 goto fail_pci; 1344 1345 netif_info(efx, probe, net_dev, 1346 "enabled SR-IOV for %d VFs, %d VI per VF\n", 1347 efx->vf_count, efx_vf_size(efx)); 1348 return 0; 1349 1350fail_pci: 1351 efx_siena_sriov_usrev(efx, false); 1352 rtnl_lock(); 1353 efx->vf_init_count = 0; 1354 rtnl_unlock(); 1355 efx_siena_sriov_vfs_fini(efx); 1356fail_vfs: 1357 cancel_work_sync(&nic_data->peer_work); 1358 efx_siena_sriov_free_local(efx); 1359 kfree(nic_data->vf); 1360fail_alloc: 1361 efx_nic_free_buffer(efx, &nic_data->vfdi_status); 1362fail_status: 1363 efx_siena_sriov_cmd(efx, false, NULL, NULL); 1364fail_cmd: 1365 return rc; 1366} 1367 1368void efx_siena_sriov_fini(struct efx_nic *efx) 1369{ 1370 struct siena_vf *vf; 1371 unsigned int pos; 1372 struct siena_nic_data *nic_data = efx->nic_data; 1373 1374 if (efx->vf_init_count == 0) 1375 return; 1376 1377 /* Disable all interfaces to reconfiguration */ 1378 BUG_ON(nic_data->vfdi_channel->enabled); 1379 efx_siena_sriov_usrev(efx, false); 1380 rtnl_lock(); 1381 efx->vf_init_count = 0; 1382 rtnl_unlock(); 1383 1384 /* Flush all reconfiguration work */ 1385 for (pos = 0; pos < efx->vf_count; ++pos) { 1386 vf = nic_data->vf + pos; 1387 cancel_work_sync(&vf->req); 1388 cancel_work_sync(&vf->reset_work); 1389 } 1390 cancel_work_sync(&nic_data->peer_work); 1391 1392 pci_disable_sriov(efx->pci_dev); 1393 1394 /* Tear down back-end state */ 1395 efx_siena_sriov_vfs_fini(efx); 1396 efx_siena_sriov_free_local(efx); 1397 kfree(nic_data->vf); 1398 efx_nic_free_buffer(efx, &nic_data->vfdi_status); 1399 efx_siena_sriov_cmd(efx, false, NULL, NULL); 1400} 1401 1402void efx_siena_sriov_event(struct efx_channel *channel, efx_qword_t *event) 1403{ 1404 struct efx_nic *efx = channel->efx; 1405 struct siena_vf *vf; 1406 unsigned qid, seq, type, data; 1407 1408 qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID); 1409 1410 /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */ 1411 BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0); 1412 seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ); 1413 type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE); 1414 data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA); 1415 1416 netif_vdbg(efx, hw, efx->net_dev, 1417 "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n", 1418 qid, seq, type, data); 1419 1420 if (map_vi_index(efx, qid, &vf, NULL)) 1421 return; 1422 if (vf->busy) 1423 goto error; 1424 1425 if (type == VFDI_EV_TYPE_REQ_WORD0) { 1426 /* Resynchronise */ 1427 vf->req_type = VFDI_EV_TYPE_REQ_WORD0; 1428 vf->req_seqno = seq + 1; 1429 vf->req_addr = 0; 1430 } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type) 1431 goto error; 1432 1433 switch (vf->req_type) { 1434 case VFDI_EV_TYPE_REQ_WORD0: 1435 case VFDI_EV_TYPE_REQ_WORD1: 1436 case VFDI_EV_TYPE_REQ_WORD2: 1437 vf->req_addr |= (u64)data << (vf->req_type << 4); 1438 ++vf->req_type; 1439 return; 1440 1441 case VFDI_EV_TYPE_REQ_WORD3: 1442 vf->req_addr |= (u64)data << 48; 1443 vf->req_type = VFDI_EV_TYPE_REQ_WORD0; 1444 vf->busy = true; 1445 queue_work(vfdi_workqueue, &vf->req); 1446 return; 1447 } 1448 1449error: 1450 if (net_ratelimit()) 1451 netif_err(efx, hw, efx->net_dev, 1452 "ERROR: Screaming VFDI request from %s\n", 1453 vf->pci_name); 1454 /* Reset the request and sequence number */ 1455 vf->req_type = VFDI_EV_TYPE_REQ_WORD0; 1456 vf->req_seqno = seq + 1; 1457} 1458 1459void efx_siena_sriov_flr(struct efx_nic *efx, unsigned vf_i) 1460{ 1461 struct siena_nic_data *nic_data = efx->nic_data; 1462 struct siena_vf *vf; 1463 1464 if (vf_i > efx->vf_init_count) 1465 return; 1466 vf = nic_data->vf + vf_i; 1467 netif_info(efx, hw, efx->net_dev, 1468 "FLR on VF %s\n", vf->pci_name); 1469 1470 vf->status_addr = 0; 1471 efx_vfdi_remove_all_filters(vf); 1472 efx_vfdi_flush_clear(vf); 1473 1474 vf->evq0_count = 0; 1475} 1476 1477int efx_siena_sriov_mac_address_changed(struct efx_nic *efx) 1478{ 1479 struct siena_nic_data *nic_data = efx->nic_data; 1480 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr; 1481 1482 if (!efx->vf_init_count) 1483 return 0; 1484 ether_addr_copy(vfdi_status->peers[0].mac_addr, 1485 efx->net_dev->dev_addr); 1486 queue_work(vfdi_workqueue, &nic_data->peer_work); 1487 1488 return 0; 1489} 1490 1491void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1492{ 1493 struct siena_vf *vf; 1494 unsigned queue, qid; 1495 1496 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 1497 if (map_vi_index(efx, queue, &vf, &qid)) 1498 return; 1499 /* Ignore flush completions triggered by an FLR */ 1500 if (!test_bit(qid, vf->txq_mask)) 1501 return; 1502 1503 __clear_bit(qid, vf->txq_mask); 1504 --vf->txq_count; 1505 1506 if (efx_vfdi_flush_wake(vf)) 1507 wake_up(&vf->flush_waitq); 1508} 1509 1510void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1511{ 1512 struct siena_vf *vf; 1513 unsigned ev_failed, queue, qid; 1514 1515 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 1516 ev_failed = EFX_QWORD_FIELD(*event, 1517 FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 1518 if (map_vi_index(efx, queue, &vf, &qid)) 1519 return; 1520 if (!test_bit(qid, vf->rxq_mask)) 1521 return; 1522 1523 if (ev_failed) { 1524 set_bit(qid, vf->rxq_retry_mask); 1525 atomic_inc(&vf->rxq_retry_count); 1526 } else { 1527 __clear_bit(qid, vf->rxq_mask); 1528 --vf->rxq_count; 1529 } 1530 if (efx_vfdi_flush_wake(vf)) 1531 wake_up(&vf->flush_waitq); 1532} 1533 1534/* Called from napi. Schedule the reset work item */ 1535void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) 1536{ 1537 struct siena_vf *vf; 1538 unsigned int rel; 1539 1540 if (map_vi_index(efx, dmaq, &vf, &rel)) 1541 return; 1542 1543 if (net_ratelimit()) 1544 netif_err(efx, hw, efx->net_dev, 1545 "VF %d DMA Q %d reports descriptor fetch error.\n", 1546 vf->index, rel); 1547 queue_work(vfdi_workqueue, &vf->reset_work); 1548} 1549 1550/* Reset all VFs */ 1551void efx_siena_sriov_reset(struct efx_nic *efx) 1552{ 1553 struct siena_nic_data *nic_data = efx->nic_data; 1554 unsigned int vf_i; 1555 struct efx_buffer buf; 1556 struct siena_vf *vf; 1557 1558 ASSERT_RTNL(); 1559 1560 if (efx->vf_init_count == 0) 1561 return; 1562 1563 efx_siena_sriov_usrev(efx, true); 1564 (void)efx_siena_sriov_cmd(efx, true, NULL, NULL); 1565 1566 if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) 1567 return; 1568 1569 for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) { 1570 vf = nic_data->vf + vf_i; 1571 efx_siena_sriov_reset_vf(vf, &buf); 1572 } 1573 1574 efx_nic_free_buffer(efx, &buf); 1575} 1576 1577int efx_init_sriov(void) 1578{ 1579 /* A single threaded workqueue is sufficient. efx_siena_sriov_vfdi() and 1580 * efx_siena_sriov_peer_work() spend almost all their time sleeping for 1581 * MCDI to complete anyway 1582 */ 1583 vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi"); 1584 if (!vfdi_workqueue) 1585 return -ENOMEM; 1586 return 0; 1587} 1588 1589void efx_fini_sriov(void) 1590{ 1591 destroy_workqueue(vfdi_workqueue); 1592} 1593 1594int efx_siena_sriov_set_vf_mac(struct efx_nic *efx, int vf_i, u8 *mac) 1595{ 1596 struct siena_nic_data *nic_data = efx->nic_data; 1597 struct siena_vf *vf; 1598 1599 if (vf_i >= efx->vf_init_count) 1600 return -EINVAL; 1601 vf = nic_data->vf + vf_i; 1602 1603 mutex_lock(&vf->status_lock); 1604 ether_addr_copy(vf->addr.mac_addr, mac); 1605 __efx_siena_sriov_update_vf_addr(vf); 1606 mutex_unlock(&vf->status_lock); 1607 1608 return 0; 1609} 1610 1611int efx_siena_sriov_set_vf_vlan(struct efx_nic *efx, int vf_i, 1612 u16 vlan, u8 qos) 1613{ 1614 struct siena_nic_data *nic_data = efx->nic_data; 1615 struct siena_vf *vf; 1616 u16 tci; 1617 1618 if (vf_i >= efx->vf_init_count) 1619 return -EINVAL; 1620 vf = nic_data->vf + vf_i; 1621 1622 mutex_lock(&vf->status_lock); 1623 tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT); 1624 vf->addr.tci = htons(tci); 1625 __efx_siena_sriov_update_vf_addr(vf); 1626 mutex_unlock(&vf->status_lock); 1627 1628 return 0; 1629} 1630 1631int efx_siena_sriov_set_vf_spoofchk(struct efx_nic *efx, int vf_i, 1632 bool spoofchk) 1633{ 1634 struct siena_nic_data *nic_data = efx->nic_data; 1635 struct siena_vf *vf; 1636 int rc; 1637 1638 if (vf_i >= efx->vf_init_count) 1639 return -EINVAL; 1640 vf = nic_data->vf + vf_i; 1641 1642 mutex_lock(&vf->txq_lock); 1643 if (vf->txq_count == 0) { 1644 vf->tx_filter_mode = 1645 spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF; 1646 rc = 0; 1647 } else { 1648 /* This cannot be changed while TX queues are running */ 1649 rc = -EBUSY; 1650 } 1651 mutex_unlock(&vf->txq_lock); 1652 return rc; 1653} 1654 1655int efx_siena_sriov_get_vf_config(struct efx_nic *efx, int vf_i, 1656 struct ifla_vf_info *ivi) 1657{ 1658 struct siena_nic_data *nic_data = efx->nic_data; 1659 struct siena_vf *vf; 1660 u16 tci; 1661 1662 if (vf_i >= efx->vf_init_count) 1663 return -EINVAL; 1664 vf = nic_data->vf + vf_i; 1665 1666 ivi->vf = vf_i; 1667 ether_addr_copy(ivi->mac, vf->addr.mac_addr); 1668 ivi->max_tx_rate = 0; 1669 ivi->min_tx_rate = 0; 1670 tci = ntohs(vf->addr.tci); 1671 ivi->vlan = tci & VLAN_VID_MASK; 1672 ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7; 1673 ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON; 1674 1675 return 0; 1676} 1677 1678bool efx_siena_sriov_wanted(struct efx_nic *efx) 1679{ 1680 return efx->vf_count != 0; 1681} 1682 1683int efx_siena_sriov_configure(struct efx_nic *efx, int num_vfs) 1684{ 1685 return 0; 1686} 1687