1// SPDX-License-Identifier: GPL-2.0-only 2/**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2005-2006 Fen Systems Ltd. 5 * Copyright 2006-2013 Solarflare Communications Inc. 6 */ 7 8#include <linux/bitops.h> 9#include <linux/delay.h> 10#include <linux/pci.h> 11#include <linux/module.h> 12#include <linux/slab.h> 13#include <linux/random.h> 14#include "net_driver.h" 15#include "bitfield.h" 16#include "efx.h" 17#include "efx_common.h" 18#include "nic.h" 19#include "farch_regs.h" 20#include "io.h" 21#include "workarounds.h" 22#include "mcdi.h" 23#include "mcdi_pcol.h" 24#include "mcdi_port.h" 25#include "mcdi_port_common.h" 26#include "selftest.h" 27#include "siena_sriov.h" 28 29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ 30 31static void siena_init_wol(struct efx_nic *efx); 32 33 34static void siena_push_irq_moderation(struct efx_channel *channel) 35{ 36 struct efx_nic *efx = channel->efx; 37 efx_dword_t timer_cmd; 38 39 if (channel->irq_moderation_us) { 40 unsigned int ticks; 41 42 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us); 43 EFX_POPULATE_DWORD_2(timer_cmd, 44 FRF_CZ_TC_TIMER_MODE, 45 FFE_CZ_TIMER_MODE_INT_HLDOFF, 46 FRF_CZ_TC_TIMER_VAL, 47 ticks - 1); 48 } else { 49 EFX_POPULATE_DWORD_2(timer_cmd, 50 FRF_CZ_TC_TIMER_MODE, 51 FFE_CZ_TIMER_MODE_DIS, 52 FRF_CZ_TC_TIMER_VAL, 0); 53 } 54 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, 55 channel->channel); 56} 57 58void siena_prepare_flush(struct efx_nic *efx) 59{ 60 if (efx->fc_disable++ == 0) 61 efx_mcdi_set_mac(efx); 62} 63 64void siena_finish_flush(struct efx_nic *efx) 65{ 66 if (--efx->fc_disable == 0) 67 efx_mcdi_set_mac(efx); 68} 69 70static const struct efx_farch_register_test siena_register_tests[] = { 71 { FR_AZ_ADR_REGION, 72 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, 73 { FR_CZ_USR_EV_CFG, 74 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, 75 { FR_AZ_RX_CFG, 76 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, 77 { FR_AZ_TX_CFG, 78 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, 79 { FR_AZ_TX_RESERVED, 80 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, 81 { FR_AZ_SRM_TX_DC_CFG, 82 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, 83 { FR_AZ_RX_DC_CFG, 84 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, 85 { FR_AZ_RX_DC_PF_WM, 86 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, 87 { FR_BZ_DP_CTRL, 88 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, 89 { FR_BZ_RX_RSS_TKEY, 90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, 91 { FR_CZ_RX_RSS_IPV6_REG1, 92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, 93 { FR_CZ_RX_RSS_IPV6_REG2, 94 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, 95 { FR_CZ_RX_RSS_IPV6_REG3, 96 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, 97}; 98 99static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 100{ 101 enum reset_type reset_method = RESET_TYPE_ALL; 102 int rc, rc2; 103 104 efx_reset_down(efx, reset_method); 105 106 /* Reset the chip immediately so that it is completely 107 * quiescent regardless of what any VF driver does. 108 */ 109 rc = efx_mcdi_reset(efx, reset_method); 110 if (rc) 111 goto out; 112 113 tests->registers = 114 efx_farch_test_registers(efx, siena_register_tests, 115 ARRAY_SIZE(siena_register_tests)) 116 ? -1 : 1; 117 118 rc = efx_mcdi_reset(efx, reset_method); 119out: 120 rc2 = efx_reset_up(efx, reset_method, rc == 0); 121 return rc ? rc : rc2; 122} 123 124/************************************************************************** 125 * 126 * PTP 127 * 128 ************************************************************************** 129 */ 130 131static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 132{ 133 _efx_writed(efx, cpu_to_le32(host_time), 134 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST); 135} 136 137static int siena_ptp_set_ts_config(struct efx_nic *efx, 138 struct hwtstamp_config *init) 139{ 140 int rc; 141 142 switch (init->rx_filter) { 143 case HWTSTAMP_FILTER_NONE: 144 /* if TX timestamping is still requested then leave PTP on */ 145 return efx_ptp_change_mode(efx, 146 init->tx_type != HWTSTAMP_TX_OFF, 147 efx_ptp_get_mode(efx)); 148 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 149 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 150 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 151 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 152 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1); 153 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 154 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 155 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 156 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 157 rc = efx_ptp_change_mode(efx, true, 158 MC_CMD_PTP_MODE_V2_ENHANCED); 159 /* bug 33070 - old versions of the firmware do not support the 160 * improved UUID filtering option. Similarly old versions of the 161 * application do not expect it to be enabled. If the firmware 162 * does not accept the enhanced mode, fall back to the standard 163 * PTP v2 UUID filtering. */ 164 if (rc != 0) 165 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2); 166 return rc; 167 default: 168 return -ERANGE; 169 } 170} 171 172/************************************************************************** 173 * 174 * Device reset 175 * 176 ************************************************************************** 177 */ 178 179static int siena_map_reset_flags(u32 *flags) 180{ 181 enum { 182 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER | 183 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 184 ETH_RESET_PHY), 185 SIENA_RESET_MC = (SIENA_RESET_PORT | 186 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT), 187 }; 188 189 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) { 190 *flags &= ~SIENA_RESET_MC; 191 return RESET_TYPE_WORLD; 192 } 193 194 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) { 195 *flags &= ~SIENA_RESET_PORT; 196 return RESET_TYPE_ALL; 197 } 198 199 /* no invisible reset implemented */ 200 201 return -EINVAL; 202} 203 204#ifdef CONFIG_EEH 205/* When a PCI device is isolated from the bus, a subsequent MMIO read is 206 * required for the kernel EEH mechanisms to notice. As the Solarflare driver 207 * was written to minimise MMIO read (for latency) then a periodic call to check 208 * the EEH status of the device is required so that device recovery can happen 209 * in a timely fashion. 210 */ 211static void siena_monitor(struct efx_nic *efx) 212{ 213 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); 214 215 eeh_dev_check_failure(eehdev); 216} 217#endif 218 219static int siena_probe_nvconfig(struct efx_nic *efx) 220{ 221 u32 caps = 0; 222 int rc; 223 224 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps); 225 226 efx->timer_quantum_ns = 227 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ? 228 3072 : 6144; /* 768 cycles */ 229 efx->timer_max_ns = efx->type->timer_period_max * 230 efx->timer_quantum_ns; 231 232 return rc; 233} 234 235static int siena_dimension_resources(struct efx_nic *efx) 236{ 237 /* Each port has a small block of internal SRAM dedicated to 238 * the buffer table and descriptor caches. In theory we can 239 * map both blocks to one port, but we don't. 240 */ 241 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2); 242 return 0; 243} 244 245/* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3) 246 * for memory. 247 */ 248static unsigned int siena_mem_bar(struct efx_nic *efx) 249{ 250 return 2; 251} 252 253static unsigned int siena_mem_map_size(struct efx_nic *efx) 254{ 255 return FR_CZ_MC_TREG_SMEM + 256 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS; 257} 258 259static int siena_probe_nic(struct efx_nic *efx) 260{ 261 struct siena_nic_data *nic_data; 262 efx_oword_t reg; 263 int rc; 264 265 /* Allocate storage for hardware specific data */ 266 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); 267 if (!nic_data) 268 return -ENOMEM; 269 nic_data->efx = efx; 270 efx->nic_data = nic_data; 271 272 if (efx_farch_fpga_ver(efx) != 0) { 273 netif_err(efx, probe, efx->net_dev, 274 "Siena FPGA not supported\n"); 275 rc = -ENODEV; 276 goto fail1; 277 } 278 279 efx->max_channels = EFX_MAX_CHANNELS; 280 efx->max_vis = EFX_MAX_CHANNELS; 281 efx->max_tx_channels = EFX_MAX_CHANNELS; 282 efx->tx_queues_per_channel = 4; 283 284 efx_reado(efx, ®, FR_AZ_CS_DEBUG); 285 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; 286 287 rc = efx_mcdi_init(efx); 288 if (rc) 289 goto fail1; 290 291 /* Now we can reset the NIC */ 292 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 293 if (rc) { 294 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); 295 goto fail3; 296 } 297 298 siena_init_wol(efx); 299 300 /* Allocate memory for INT_KER */ 301 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t), 302 GFP_KERNEL); 303 if (rc) 304 goto fail4; 305 BUG_ON(efx->irq_status.dma_addr & 0x0f); 306 307 netif_dbg(efx, probe, efx->net_dev, 308 "INT_KER at %llx (virt %p phys %llx)\n", 309 (unsigned long long)efx->irq_status.dma_addr, 310 efx->irq_status.addr, 311 (unsigned long long)virt_to_phys(efx->irq_status.addr)); 312 313 /* Read in the non-volatile configuration */ 314 rc = siena_probe_nvconfig(efx); 315 if (rc == -EINVAL) { 316 netif_err(efx, probe, efx->net_dev, 317 "NVRAM is invalid therefore using defaults\n"); 318 efx->phy_type = PHY_TYPE_NONE; 319 efx->mdio.prtad = MDIO_PRTAD_NONE; 320 } else if (rc) { 321 goto fail5; 322 } 323 324 rc = efx_mcdi_mon_probe(efx); 325 if (rc) 326 goto fail5; 327 328#ifdef CONFIG_SFC_SRIOV 329 efx_siena_sriov_probe(efx); 330#endif 331 efx_ptp_defer_probe_with_channel(efx); 332 333 return 0; 334 335fail5: 336 efx_nic_free_buffer(efx, &efx->irq_status); 337fail4: 338fail3: 339 efx_mcdi_detach(efx); 340 efx_mcdi_fini(efx); 341fail1: 342 kfree(efx->nic_data); 343 return rc; 344} 345 346static int siena_rx_pull_rss_config(struct efx_nic *efx) 347{ 348 efx_oword_t temp; 349 350 /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the 351 * first 128 bits of the same key, assuming it's been set by 352 * siena_rx_push_rss_config, below) 353 */ 354 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); 355 memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp)); 356 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); 357 memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp)); 358 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); 359 memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp, 360 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); 361 efx_farch_rx_pull_indir_table(efx); 362 return 0; 363} 364 365static int siena_rx_push_rss_config(struct efx_nic *efx, bool user, 366 const u32 *rx_indir_table, const u8 *key) 367{ 368 efx_oword_t temp; 369 370 /* Set hash key for IPv4 */ 371 if (key) 372 memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp)); 373 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp)); 374 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); 375 376 /* Enable IPv6 RSS */ 377 BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) < 378 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || 379 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); 380 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp)); 381 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); 382 memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp)); 383 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); 384 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, 385 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); 386 memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp), 387 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); 388 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); 389 390 memcpy(efx->rss_context.rx_indir_table, rx_indir_table, 391 sizeof(efx->rss_context.rx_indir_table)); 392 efx_farch_rx_push_indir_table(efx); 393 394 return 0; 395} 396 397/* This call performs hardware-specific global initialisation, such as 398 * defining the descriptor cache sizes and number of RSS channels. 399 * It does not set up any buffers, descriptor rings or event queues. 400 */ 401static int siena_init_nic(struct efx_nic *efx) 402{ 403 efx_oword_t temp; 404 int rc; 405 406 /* Recover from a failed assertion post-reset */ 407 rc = efx_mcdi_handle_assertion(efx); 408 if (rc) 409 return rc; 410 411 /* Squash TX of packets of 16 bytes or less */ 412 efx_reado(efx, &temp, FR_AZ_TX_RESERVED); 413 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); 414 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); 415 416 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 417 * descriptors (which is bad). 418 */ 419 efx_reado(efx, &temp, FR_AZ_TX_CFG); 420 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); 421 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); 422 efx_writeo(efx, &temp, FR_AZ_TX_CFG); 423 424 efx_reado(efx, &temp, FR_AZ_RX_CFG); 425 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); 426 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); 427 /* Enable hash insertion. This is broken for the 'Falcon' hash 428 * if IPv6 hashing is also enabled, so also select Toeplitz 429 * TCP/IPv4 and IPv4 hashes. */ 430 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1); 431 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1); 432 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1); 433 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE, 434 EFX_RX_USR_BUF_SIZE >> 5); 435 efx_writeo(efx, &temp, FR_AZ_RX_CFG); 436 437 siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL); 438 efx->rss_context.context_id = 0; /* indicates RSS is active */ 439 440 /* Enable event logging */ 441 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 442 if (rc) 443 return rc; 444 445 /* Set destination of both TX and RX Flush events */ 446 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); 447 efx_writeo(efx, &temp, FR_BZ_DP_CTRL); 448 449 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); 450 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); 451 452 efx_farch_init_common(efx); 453 return 0; 454} 455 456static void siena_remove_nic(struct efx_nic *efx) 457{ 458 efx_mcdi_mon_remove(efx); 459 460 efx_nic_free_buffer(efx, &efx->irq_status); 461 462 efx_mcdi_reset(efx, RESET_TYPE_ALL); 463 464 efx_mcdi_detach(efx); 465 efx_mcdi_fini(efx); 466 467 /* Tear down the private nic state */ 468 kfree(efx->nic_data); 469 efx->nic_data = NULL; 470} 471 472#define SIENA_DMA_STAT(ext_name, mcdi_name) \ 473 [SIENA_STAT_ ## ext_name] = \ 474 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 475#define SIENA_OTHER_STAT(ext_name) \ 476 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 } 477#define GENERIC_SW_STAT(ext_name) \ 478 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 479 480static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = { 481 SIENA_DMA_STAT(tx_bytes, TX_BYTES), 482 SIENA_OTHER_STAT(tx_good_bytes), 483 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES), 484 SIENA_DMA_STAT(tx_packets, TX_PKTS), 485 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS), 486 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS), 487 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS), 488 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), 489 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), 490 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), 491 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS), 492 SIENA_DMA_STAT(tx_64, TX_64_PKTS), 493 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), 494 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), 495 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), 496 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), 497 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 498 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 499 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS), 500 SIENA_OTHER_STAT(tx_collision), 501 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS), 502 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS), 503 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS), 504 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS), 505 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS), 506 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS), 507 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS), 508 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS), 509 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS), 510 SIENA_DMA_STAT(rx_bytes, RX_BYTES), 511 SIENA_OTHER_STAT(rx_good_bytes), 512 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES), 513 SIENA_DMA_STAT(rx_packets, RX_PKTS), 514 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS), 515 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), 516 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS), 517 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS), 518 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), 519 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), 520 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), 521 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), 522 SIENA_DMA_STAT(rx_64, RX_64_PKTS), 523 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), 524 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), 525 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), 526 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), 527 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 528 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 529 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), 530 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), 531 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), 532 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS), 533 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS), 534 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), 535 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), 536 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS), 537 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS), 538 GENERIC_SW_STAT(rx_nodesc_trunc), 539 GENERIC_SW_STAT(rx_noskb_drops), 540}; 541static const unsigned long siena_stat_mask[] = { 542 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL, 543}; 544 545static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names) 546{ 547 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT, 548 siena_stat_mask, names); 549} 550 551static int siena_try_update_nic_stats(struct efx_nic *efx) 552{ 553 struct siena_nic_data *nic_data = efx->nic_data; 554 u64 *stats = nic_data->stats; 555 __le64 *dma_stats; 556 __le64 generation_start, generation_end; 557 558 dma_stats = efx->stats_buffer.addr; 559 560 generation_end = dma_stats[efx->num_mac_stats - 1]; 561 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 562 return 0; 563 rmb(); 564 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask, 565 stats, efx->stats_buffer.addr, false); 566 rmb(); 567 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 568 if (generation_end != generation_start) 569 return -EAGAIN; 570 571 /* Update derived statistics */ 572 efx_nic_fix_nodesc_drop_stat(efx, 573 &stats[SIENA_STAT_rx_nodesc_drop_cnt]); 574 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes], 575 stats[SIENA_STAT_tx_bytes] - 576 stats[SIENA_STAT_tx_bad_bytes]); 577 stats[SIENA_STAT_tx_collision] = 578 stats[SIENA_STAT_tx_single_collision] + 579 stats[SIENA_STAT_tx_multiple_collision] + 580 stats[SIENA_STAT_tx_excessive_collision] + 581 stats[SIENA_STAT_tx_late_collision]; 582 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes], 583 stats[SIENA_STAT_rx_bytes] - 584 stats[SIENA_STAT_rx_bad_bytes]); 585 efx_update_sw_stats(efx, stats); 586 return 0; 587} 588 589static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats, 590 struct rtnl_link_stats64 *core_stats) 591{ 592 struct siena_nic_data *nic_data = efx->nic_data; 593 u64 *stats = nic_data->stats; 594 int retry; 595 596 /* If we're unlucky enough to read statistics wduring the DMA, wait 597 * up to 10ms for it to finish (typically takes <500us) */ 598 for (retry = 0; retry < 100; ++retry) { 599 if (siena_try_update_nic_stats(efx) == 0) 600 break; 601 udelay(100); 602 } 603 604 if (full_stats) 605 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT); 606 607 if (core_stats) { 608 core_stats->rx_packets = stats[SIENA_STAT_rx_packets]; 609 core_stats->tx_packets = stats[SIENA_STAT_tx_packets]; 610 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes]; 611 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes]; 612 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] + 613 stats[GENERIC_STAT_rx_nodesc_trunc] + 614 stats[GENERIC_STAT_rx_noskb_drops]; 615 core_stats->multicast = stats[SIENA_STAT_rx_multicast]; 616 core_stats->collisions = stats[SIENA_STAT_tx_collision]; 617 core_stats->rx_length_errors = 618 stats[SIENA_STAT_rx_gtjumbo] + 619 stats[SIENA_STAT_rx_length_error]; 620 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad]; 621 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error]; 622 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow]; 623 core_stats->tx_window_errors = 624 stats[SIENA_STAT_tx_late_collision]; 625 626 core_stats->rx_errors = (core_stats->rx_length_errors + 627 core_stats->rx_crc_errors + 628 core_stats->rx_frame_errors + 629 stats[SIENA_STAT_rx_symbol_error]); 630 core_stats->tx_errors = (core_stats->tx_window_errors + 631 stats[SIENA_STAT_tx_bad]); 632 } 633 634 return SIENA_STAT_COUNT; 635} 636 637static int siena_mac_reconfigure(struct efx_nic *efx, bool mtu_only __always_unused) 638{ 639 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN); 640 int rc; 641 642 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN != 643 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST + 644 sizeof(efx->multicast_hash)); 645 646 efx_farch_filter_sync_rx_mode(efx); 647 648 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 649 650 rc = efx_mcdi_set_mac(efx); 651 if (rc != 0) 652 return rc; 653 654 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0), 655 efx->multicast_hash.byte, sizeof(efx->multicast_hash)); 656 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH, 657 inbuf, sizeof(inbuf), NULL, 0, NULL); 658} 659 660/************************************************************************** 661 * 662 * Wake on LAN 663 * 664 ************************************************************************** 665 */ 666 667static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 668{ 669 struct siena_nic_data *nic_data = efx->nic_data; 670 671 wol->supported = WAKE_MAGIC; 672 if (nic_data->wol_filter_id != -1) 673 wol->wolopts = WAKE_MAGIC; 674 else 675 wol->wolopts = 0; 676 memset(&wol->sopass, 0, sizeof(wol->sopass)); 677} 678 679 680static int siena_set_wol(struct efx_nic *efx, u32 type) 681{ 682 struct siena_nic_data *nic_data = efx->nic_data; 683 int rc; 684 685 if (type & ~WAKE_MAGIC) 686 return -EINVAL; 687 688 if (type & WAKE_MAGIC) { 689 if (nic_data->wol_filter_id != -1) 690 efx_mcdi_wol_filter_remove(efx, 691 nic_data->wol_filter_id); 692 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr, 693 &nic_data->wol_filter_id); 694 if (rc) 695 goto fail; 696 697 pci_wake_from_d3(efx->pci_dev, true); 698 } else { 699 rc = efx_mcdi_wol_filter_reset(efx); 700 nic_data->wol_filter_id = -1; 701 pci_wake_from_d3(efx->pci_dev, false); 702 if (rc) 703 goto fail; 704 } 705 706 return 0; 707 fail: 708 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n", 709 __func__, type, rc); 710 return rc; 711} 712 713 714static void siena_init_wol(struct efx_nic *efx) 715{ 716 struct siena_nic_data *nic_data = efx->nic_data; 717 int rc; 718 719 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); 720 721 if (rc != 0) { 722 /* If it failed, attempt to get into a synchronised 723 * state with MC by resetting any set WoL filters */ 724 efx_mcdi_wol_filter_reset(efx); 725 nic_data->wol_filter_id = -1; 726 } else if (nic_data->wol_filter_id != -1) { 727 pci_wake_from_d3(efx->pci_dev, true); 728 } 729} 730 731/************************************************************************** 732 * 733 * MCDI 734 * 735 ************************************************************************** 736 */ 737 738#define MCDI_PDU(efx) \ 739 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST) 740#define MCDI_DOORBELL(efx) \ 741 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST) 742#define MCDI_STATUS(efx) \ 743 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST) 744 745static void siena_mcdi_request(struct efx_nic *efx, 746 const efx_dword_t *hdr, size_t hdr_len, 747 const efx_dword_t *sdu, size_t sdu_len) 748{ 749 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); 750 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx); 751 unsigned int i; 752 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4); 753 754 EFX_WARN_ON_PARANOID(hdr_len != 4); 755 756 efx_writed(efx, hdr, pdu); 757 758 for (i = 0; i < inlen_dw; i++) 759 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i); 760 761 /* Ensure the request is written out before the doorbell */ 762 wmb(); 763 764 /* ring the doorbell with a distinctive value */ 765 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell); 766} 767 768static bool siena_mcdi_poll_response(struct efx_nic *efx) 769{ 770 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); 771 efx_dword_t hdr; 772 773 efx_readd(efx, &hdr, pdu); 774 775 /* All 1's indicates that shared memory is in reset (and is 776 * not a valid hdr). Wait for it to come out reset before 777 * completing the command 778 */ 779 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff && 780 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 781} 782 783static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 784 size_t offset, size_t outlen) 785{ 786 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); 787 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4); 788 int i; 789 790 for (i = 0; i < outlen_dw; i++) 791 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i); 792} 793 794static int siena_mcdi_poll_reboot(struct efx_nic *efx) 795{ 796 struct siena_nic_data *nic_data = efx->nic_data; 797 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx); 798 efx_dword_t reg; 799 u32 value; 800 801 efx_readd(efx, ®, addr); 802 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 803 804 if (value == 0) 805 return 0; 806 807 EFX_ZERO_DWORD(reg); 808 efx_writed(efx, ®, addr); 809 810 /* MAC statistics have been cleared on the NIC; clear the local 811 * copies that we update with efx_update_diff_stat(). 812 */ 813 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0; 814 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0; 815 816 if (value == MC_STATUS_DWORD_ASSERT) 817 return -EINTR; 818 else 819 return -EIO; 820} 821 822/************************************************************************** 823 * 824 * MTD 825 * 826 ************************************************************************** 827 */ 828 829#ifdef CONFIG_SFC_MTD 830 831struct siena_nvram_type_info { 832 int port; 833 const char *name; 834}; 835 836static const struct siena_nvram_type_info siena_nvram_types[] = { 837 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" }, 838 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" }, 839 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" }, 840 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" }, 841 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" }, 842 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" }, 843 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" }, 844 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" }, 845 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" }, 846 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" }, 847 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" }, 848 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" }, 849 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" }, 850}; 851 852static int siena_mtd_probe_partition(struct efx_nic *efx, 853 struct efx_mcdi_mtd_partition *part, 854 unsigned int type) 855{ 856 const struct siena_nvram_type_info *info; 857 size_t size, erase_size; 858 bool protected; 859 int rc; 860 861 if (type >= ARRAY_SIZE(siena_nvram_types) || 862 siena_nvram_types[type].name == NULL) 863 return -ENODEV; 864 865 info = &siena_nvram_types[type]; 866 867 if (info->port != efx_port_num(efx)) 868 return -ENODEV; 869 870 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 871 if (rc) 872 return rc; 873 if (protected) 874 return -ENODEV; /* hide it */ 875 876 part->nvram_type = type; 877 part->common.dev_type_name = "Siena NVRAM manager"; 878 part->common.type_name = info->name; 879 880 part->common.mtd.type = MTD_NORFLASH; 881 part->common.mtd.flags = MTD_CAP_NORFLASH; 882 part->common.mtd.size = size; 883 part->common.mtd.erasesize = erase_size; 884 885 return 0; 886} 887 888static int siena_mtd_get_fw_subtypes(struct efx_nic *efx, 889 struct efx_mcdi_mtd_partition *parts, 890 size_t n_parts) 891{ 892 uint16_t fw_subtype_list[ 893 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM]; 894 size_t i; 895 int rc; 896 897 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL); 898 if (rc) 899 return rc; 900 901 for (i = 0; i < n_parts; i++) 902 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type]; 903 904 return 0; 905} 906 907static int siena_mtd_probe(struct efx_nic *efx) 908{ 909 struct efx_mcdi_mtd_partition *parts; 910 u32 nvram_types; 911 unsigned int type; 912 size_t n_parts; 913 int rc; 914 915 ASSERT_RTNL(); 916 917 rc = efx_mcdi_nvram_types(efx, &nvram_types); 918 if (rc) 919 return rc; 920 921 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL); 922 if (!parts) 923 return -ENOMEM; 924 925 type = 0; 926 n_parts = 0; 927 928 while (nvram_types != 0) { 929 if (nvram_types & 1) { 930 rc = siena_mtd_probe_partition(efx, &parts[n_parts], 931 type); 932 if (rc == 0) 933 n_parts++; 934 else if (rc != -ENODEV) 935 goto fail; 936 } 937 type++; 938 nvram_types >>= 1; 939 } 940 941 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts); 942 if (rc) 943 goto fail; 944 945 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 946fail: 947 if (rc) 948 kfree(parts); 949 return rc; 950} 951 952#endif /* CONFIG_SFC_MTD */ 953 954static unsigned int siena_check_caps(const struct efx_nic *efx, 955 u8 flag, u32 offset) 956{ 957 /* Siena did not support MC_CMD_GET_CAPABILITIES */ 958 return 0; 959} 960 961/************************************************************************** 962 * 963 * Revision-dependent attributes used by efx.c and nic.c 964 * 965 ************************************************************************** 966 */ 967 968const struct efx_nic_type siena_a0_nic_type = { 969 .is_vf = false, 970 .mem_bar = siena_mem_bar, 971 .mem_map_size = siena_mem_map_size, 972 .probe = siena_probe_nic, 973 .remove = siena_remove_nic, 974 .init = siena_init_nic, 975 .dimension_resources = siena_dimension_resources, 976 .fini = efx_port_dummy_op_void, 977#ifdef CONFIG_EEH 978 .monitor = siena_monitor, 979#else 980 .monitor = NULL, 981#endif 982 .map_reset_reason = efx_mcdi_map_reset_reason, 983 .map_reset_flags = siena_map_reset_flags, 984 .reset = efx_mcdi_reset, 985 .probe_port = efx_mcdi_port_probe, 986 .remove_port = efx_mcdi_port_remove, 987 .fini_dmaq = efx_farch_fini_dmaq, 988 .prepare_flush = siena_prepare_flush, 989 .finish_flush = siena_finish_flush, 990 .prepare_flr = efx_port_dummy_op_void, 991 .finish_flr = efx_farch_finish_flr, 992 .describe_stats = siena_describe_nic_stats, 993 .update_stats = siena_update_nic_stats, 994 .start_stats = efx_mcdi_mac_start_stats, 995 .pull_stats = efx_mcdi_mac_pull_stats, 996 .stop_stats = efx_mcdi_mac_stop_stats, 997 .push_irq_moderation = siena_push_irq_moderation, 998 .reconfigure_mac = siena_mac_reconfigure, 999 .check_mac_fault = efx_mcdi_mac_check_fault, 1000 .reconfigure_port = efx_mcdi_port_reconfigure, 1001 .get_wol = siena_get_wol, 1002 .set_wol = siena_set_wol, 1003 .resume_wol = siena_init_wol, 1004 .test_chip = siena_test_chip, 1005 .test_nvram = efx_mcdi_nvram_test_all, 1006 .mcdi_request = siena_mcdi_request, 1007 .mcdi_poll_response = siena_mcdi_poll_response, 1008 .mcdi_read_response = siena_mcdi_read_response, 1009 .mcdi_poll_reboot = siena_mcdi_poll_reboot, 1010 .irq_enable_master = efx_farch_irq_enable_master, 1011 .irq_test_generate = efx_farch_irq_test_generate, 1012 .irq_disable_non_ev = efx_farch_irq_disable_master, 1013 .irq_handle_msi = efx_farch_msi_interrupt, 1014 .irq_handle_legacy = efx_farch_legacy_interrupt, 1015 .tx_probe = efx_farch_tx_probe, 1016 .tx_init = efx_farch_tx_init, 1017 .tx_remove = efx_farch_tx_remove, 1018 .tx_write = efx_farch_tx_write, 1019 .tx_limit_len = efx_farch_tx_limit_len, 1020 .tx_enqueue = __efx_enqueue_skb, 1021 .rx_push_rss_config = siena_rx_push_rss_config, 1022 .rx_pull_rss_config = siena_rx_pull_rss_config, 1023 .rx_probe = efx_farch_rx_probe, 1024 .rx_init = efx_farch_rx_init, 1025 .rx_remove = efx_farch_rx_remove, 1026 .rx_write = efx_farch_rx_write, 1027 .rx_defer_refill = efx_farch_rx_defer_refill, 1028 .rx_packet = __efx_rx_packet, 1029 .ev_probe = efx_farch_ev_probe, 1030 .ev_init = efx_farch_ev_init, 1031 .ev_fini = efx_farch_ev_fini, 1032 .ev_remove = efx_farch_ev_remove, 1033 .ev_process = efx_farch_ev_process, 1034 .ev_read_ack = efx_farch_ev_read_ack, 1035 .ev_test_generate = efx_farch_ev_test_generate, 1036 .filter_table_probe = efx_farch_filter_table_probe, 1037 .filter_table_restore = efx_farch_filter_table_restore, 1038 .filter_table_remove = efx_farch_filter_table_remove, 1039 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter, 1040 .filter_insert = efx_farch_filter_insert, 1041 .filter_remove_safe = efx_farch_filter_remove_safe, 1042 .filter_get_safe = efx_farch_filter_get_safe, 1043 .filter_clear_rx = efx_farch_filter_clear_rx, 1044 .filter_count_rx_used = efx_farch_filter_count_rx_used, 1045 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit, 1046 .filter_get_rx_ids = efx_farch_filter_get_rx_ids, 1047#ifdef CONFIG_RFS_ACCEL 1048 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one, 1049#endif 1050#ifdef CONFIG_SFC_MTD 1051 .mtd_probe = siena_mtd_probe, 1052 .mtd_rename = efx_mcdi_mtd_rename, 1053 .mtd_read = efx_mcdi_mtd_read, 1054 .mtd_erase = efx_mcdi_mtd_erase, 1055 .mtd_write = efx_mcdi_mtd_write, 1056 .mtd_sync = efx_mcdi_mtd_sync, 1057#endif 1058 .ptp_write_host_time = siena_ptp_write_host_time, 1059 .ptp_set_ts_config = siena_ptp_set_ts_config, 1060#ifdef CONFIG_SFC_SRIOV 1061 .sriov_configure = efx_siena_sriov_configure, 1062 .sriov_init = efx_siena_sriov_init, 1063 .sriov_fini = efx_siena_sriov_fini, 1064 .sriov_wanted = efx_siena_sriov_wanted, 1065 .sriov_reset = efx_siena_sriov_reset, 1066 .sriov_flr = efx_siena_sriov_flr, 1067 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac, 1068 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan, 1069 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk, 1070 .sriov_get_vf_config = efx_siena_sriov_get_vf_config, 1071 .vswitching_probe = efx_port_dummy_op_int, 1072 .vswitching_restore = efx_port_dummy_op_int, 1073 .vswitching_remove = efx_port_dummy_op_void, 1074 .set_mac_address = efx_siena_sriov_mac_address_changed, 1075#endif 1076 1077 .revision = EFX_REV_SIENA_A0, 1078 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, 1079 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, 1080 .buf_tbl_base = FR_BZ_BUF_FULL_TBL, 1081 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, 1082 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, 1083 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), 1084 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE, 1085 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST, 1086 .rx_buffer_padding = 0, 1087 .can_rx_scatter = true, 1088 .option_descriptors = false, 1089 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 1090 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH, 1091 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1092 NETIF_F_RXHASH | NETIF_F_NTUPLE), 1093 .mcdi_max_ver = 1, 1094 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS, 1095 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE | 1096 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT | 1097 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT), 1098 .rx_hash_key_size = 16, 1099 .check_caps = siena_check_caps, 1100 .sensor_event = efx_mcdi_sensor_event, 1101}; 1102