1// SPDX-License-Identifier: GPL-2.0-only 2/**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11#include "net_driver.h" 12#include <linux/module.h> 13#include "efx_channels.h" 14#include "efx.h" 15#include "efx_common.h" 16#include "tx_common.h" 17#include "rx_common.h" 18#include "nic.h" 19#include "sriov.h" 20 21/* This is the first interrupt mode to try out of: 22 * 0 => MSI-X 23 * 1 => MSI 24 * 2 => legacy 25 */ 26unsigned int efx_interrupt_mode = EFX_INT_MODE_MSIX; 27 28/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 29 * i.e. the number of CPUs among which we may distribute simultaneous 30 * interrupt handling. 31 * 32 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 33 * The default (0) means to assign an interrupt to each core. 34 */ 35unsigned int rss_cpus; 36 37static unsigned int irq_adapt_low_thresh = 8000; 38module_param(irq_adapt_low_thresh, uint, 0644); 39MODULE_PARM_DESC(irq_adapt_low_thresh, 40 "Threshold score for reducing IRQ moderation"); 41 42static unsigned int irq_adapt_high_thresh = 16000; 43module_param(irq_adapt_high_thresh, uint, 0644); 44MODULE_PARM_DESC(irq_adapt_high_thresh, 45 "Threshold score for increasing IRQ moderation"); 46 47/* This is the weight assigned to each of the (per-channel) virtual 48 * NAPI devices. 49 */ 50static int napi_weight = 64; 51 52/*************** 53 * Housekeeping 54 ***************/ 55 56int efx_channel_dummy_op_int(struct efx_channel *channel) 57{ 58 return 0; 59} 60 61void efx_channel_dummy_op_void(struct efx_channel *channel) 62{ 63} 64 65static const struct efx_channel_type efx_default_channel_type = { 66 .pre_probe = efx_channel_dummy_op_int, 67 .post_remove = efx_channel_dummy_op_void, 68 .get_name = efx_get_channel_name, 69 .copy = efx_copy_channel, 70 .want_txqs = efx_default_channel_want_txqs, 71 .keep_eventq = false, 72 .want_pio = true, 73}; 74 75/************* 76 * INTERRUPTS 77 *************/ 78 79static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 80{ 81 cpumask_var_t thread_mask; 82 unsigned int count; 83 int cpu; 84 85 if (rss_cpus) { 86 count = rss_cpus; 87 } else { 88 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 89 netif_warn(efx, probe, efx->net_dev, 90 "RSS disabled due to allocation failure\n"); 91 return 1; 92 } 93 94 count = 0; 95 for_each_online_cpu(cpu) { 96 if (!cpumask_test_cpu(cpu, thread_mask)) { 97 ++count; 98 cpumask_or(thread_mask, thread_mask, 99 topology_sibling_cpumask(cpu)); 100 } 101 } 102 103 free_cpumask_var(thread_mask); 104 } 105 106 if (count > EFX_MAX_RX_QUEUES) { 107 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 108 "Reducing number of rx queues from %u to %u.\n", 109 count, EFX_MAX_RX_QUEUES); 110 count = EFX_MAX_RX_QUEUES; 111 } 112 113 /* If RSS is requested for the PF *and* VFs then we can't write RSS 114 * table entries that are inaccessible to VFs 115 */ 116#ifdef CONFIG_SFC_SRIOV 117 if (efx->type->sriov_wanted) { 118 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 119 count > efx_vf_size(efx)) { 120 netif_warn(efx, probe, efx->net_dev, 121 "Reducing number of RSS channels from %u to %u for " 122 "VF support. Increase vf-msix-limit to use more " 123 "channels on the PF.\n", 124 count, efx_vf_size(efx)); 125 count = efx_vf_size(efx); 126 } 127 } 128#endif 129 130 return count; 131} 132 133static int efx_allocate_msix_channels(struct efx_nic *efx, 134 unsigned int max_channels, 135 unsigned int extra_channels, 136 unsigned int parallelism) 137{ 138 unsigned int n_channels = parallelism; 139 int vec_count; 140 int n_xdp_tx; 141 int n_xdp_ev; 142 143 if (efx_separate_tx_channels) 144 n_channels *= 2; 145 n_channels += extra_channels; 146 147 /* To allow XDP transmit to happen from arbitrary NAPI contexts 148 * we allocate a TX queue per CPU. We share event queues across 149 * multiple tx queues, assuming tx and ev queues are both 150 * maximum size. 151 */ 152 153 n_xdp_tx = num_possible_cpus(); 154 n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_MAX_TXQ_PER_CHANNEL); 155 156 vec_count = pci_msix_vec_count(efx->pci_dev); 157 if (vec_count < 0) 158 return vec_count; 159 160 max_channels = min_t(unsigned int, vec_count, max_channels); 161 162 /* Check resources. 163 * We need a channel per event queue, plus a VI per tx queue. 164 * This may be more pessimistic than it needs to be. 165 */ 166 if (n_channels + n_xdp_ev > max_channels) { 167 netif_err(efx, drv, efx->net_dev, 168 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 169 n_xdp_ev, n_channels, max_channels); 170 efx->n_xdp_channels = 0; 171 efx->xdp_tx_per_channel = 0; 172 efx->xdp_tx_queue_count = 0; 173 } else if (n_channels + n_xdp_tx > efx->max_vis) { 174 netif_err(efx, drv, efx->net_dev, 175 "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n", 176 n_xdp_tx, n_channels, efx->max_vis); 177 efx->n_xdp_channels = 0; 178 efx->xdp_tx_per_channel = 0; 179 efx->xdp_tx_queue_count = 0; 180 } else { 181 efx->n_xdp_channels = n_xdp_ev; 182 efx->xdp_tx_per_channel = EFX_MAX_TXQ_PER_CHANNEL; 183 efx->xdp_tx_queue_count = n_xdp_tx; 184 n_channels += n_xdp_ev; 185 netif_dbg(efx, drv, efx->net_dev, 186 "Allocating %d TX and %d event queues for XDP\n", 187 n_xdp_tx, n_xdp_ev); 188 } 189 190 if (vec_count < n_channels) { 191 netif_err(efx, drv, efx->net_dev, 192 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", 193 vec_count, n_channels); 194 netif_err(efx, drv, efx->net_dev, 195 "WARNING: Performance may be reduced.\n"); 196 n_channels = vec_count; 197 } 198 199 n_channels = min(n_channels, max_channels); 200 201 efx->n_channels = n_channels; 202 203 /* Ignore XDP tx channels when creating rx channels. */ 204 n_channels -= efx->n_xdp_channels; 205 206 if (efx_separate_tx_channels) { 207 efx->n_tx_channels = 208 min(max(n_channels / 2, 1U), 209 efx->max_tx_channels); 210 efx->tx_channel_offset = 211 n_channels - efx->n_tx_channels; 212 efx->n_rx_channels = 213 max(n_channels - 214 efx->n_tx_channels, 1U); 215 } else { 216 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); 217 efx->tx_channel_offset = 0; 218 efx->n_rx_channels = n_channels; 219 } 220 221 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); 222 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); 223 224 efx->xdp_channel_offset = n_channels; 225 226 netif_dbg(efx, drv, efx->net_dev, 227 "Allocating %u RX channels\n", 228 efx->n_rx_channels); 229 230 return efx->n_channels; 231} 232 233/* Probe the number and type of interrupts we are able to obtain, and 234 * the resulting numbers of channels and RX queues. 235 */ 236int efx_probe_interrupts(struct efx_nic *efx) 237{ 238 unsigned int extra_channels = 0; 239 unsigned int rss_spread; 240 unsigned int i, j; 241 int rc; 242 243 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 244 if (efx->extra_channel_type[i]) 245 ++extra_channels; 246 247 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 248 unsigned int parallelism = efx_wanted_parallelism(efx); 249 struct msix_entry xentries[EFX_MAX_CHANNELS]; 250 unsigned int n_channels; 251 252 rc = efx_allocate_msix_channels(efx, efx->max_channels, 253 extra_channels, parallelism); 254 if (rc >= 0) { 255 n_channels = rc; 256 for (i = 0; i < n_channels; i++) 257 xentries[i].entry = i; 258 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, 259 n_channels); 260 } 261 if (rc < 0) { 262 /* Fall back to single channel MSI */ 263 netif_err(efx, drv, efx->net_dev, 264 "could not enable MSI-X\n"); 265 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 266 efx->interrupt_mode = EFX_INT_MODE_MSI; 267 else 268 return rc; 269 } else if (rc < n_channels) { 270 netif_err(efx, drv, efx->net_dev, 271 "WARNING: Insufficient MSI-X vectors" 272 " available (%d < %u).\n", rc, n_channels); 273 netif_err(efx, drv, efx->net_dev, 274 "WARNING: Performance may be reduced.\n"); 275 n_channels = rc; 276 } 277 278 if (rc > 0) { 279 for (i = 0; i < efx->n_channels; i++) 280 efx_get_channel(efx, i)->irq = 281 xentries[i].vector; 282 } 283 } 284 285 /* Try single interrupt MSI */ 286 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 287 efx->n_channels = 1; 288 efx->n_rx_channels = 1; 289 efx->n_tx_channels = 1; 290 efx->tx_channel_offset = 0; 291 efx->n_xdp_channels = 0; 292 efx->xdp_channel_offset = efx->n_channels; 293 rc = pci_enable_msi(efx->pci_dev); 294 if (rc == 0) { 295 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 296 } else { 297 netif_err(efx, drv, efx->net_dev, 298 "could not enable MSI\n"); 299 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 300 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 301 else 302 return rc; 303 } 304 } 305 306 /* Assume legacy interrupts */ 307 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 308 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 309 efx->n_rx_channels = 1; 310 efx->n_tx_channels = 1; 311 efx->tx_channel_offset = efx_separate_tx_channels ? 1 : 0; 312 efx->n_xdp_channels = 0; 313 efx->xdp_channel_offset = efx->n_channels; 314 efx->legacy_irq = efx->pci_dev->irq; 315 } 316 317 /* Assign extra channels if possible, before XDP channels */ 318 efx->n_extra_tx_channels = 0; 319 j = efx->xdp_channel_offset; 320 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 321 if (!efx->extra_channel_type[i]) 322 continue; 323 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { 324 efx->extra_channel_type[i]->handle_no_channel(efx); 325 } else { 326 --j; 327 efx_get_channel(efx, j)->type = 328 efx->extra_channel_type[i]; 329 if (efx_channel_has_tx_queues(efx_get_channel(efx, j))) 330 efx->n_extra_tx_channels++; 331 } 332 } 333 334 rss_spread = efx->n_rx_channels; 335 /* RSS might be usable on VFs even if it is disabled on the PF */ 336#ifdef CONFIG_SFC_SRIOV 337 if (efx->type->sriov_wanted) { 338 efx->rss_spread = ((rss_spread > 1 || 339 !efx->type->sriov_wanted(efx)) ? 340 rss_spread : efx_vf_size(efx)); 341 return 0; 342 } 343#endif 344 efx->rss_spread = rss_spread; 345 346 return 0; 347} 348 349#if defined(CONFIG_SMP) 350void efx_set_interrupt_affinity(struct efx_nic *efx) 351{ 352 struct efx_channel *channel; 353 unsigned int cpu; 354 355 efx_for_each_channel(channel, efx) { 356 cpu = cpumask_local_spread(channel->channel, 357 pcibus_to_node(efx->pci_dev->bus)); 358 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); 359 } 360} 361 362void efx_clear_interrupt_affinity(struct efx_nic *efx) 363{ 364 struct efx_channel *channel; 365 366 efx_for_each_channel(channel, efx) 367 irq_set_affinity_hint(channel->irq, NULL); 368} 369#else 370void 371efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 372{ 373} 374 375void 376efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 377{ 378} 379#endif /* CONFIG_SMP */ 380 381void efx_remove_interrupts(struct efx_nic *efx) 382{ 383 struct efx_channel *channel; 384 385 /* Remove MSI/MSI-X interrupts */ 386 efx_for_each_channel(channel, efx) 387 channel->irq = 0; 388 pci_disable_msi(efx->pci_dev); 389 pci_disable_msix(efx->pci_dev); 390 391 /* Remove legacy interrupt */ 392 efx->legacy_irq = 0; 393} 394 395/*************** 396 * EVENT QUEUES 397 ***************/ 398 399/* Create event queue 400 * Event queue memory allocations are done only once. If the channel 401 * is reset, the memory buffer will be reused; this guards against 402 * errors during channel reset and also simplifies interrupt handling. 403 */ 404int efx_probe_eventq(struct efx_channel *channel) 405{ 406 struct efx_nic *efx = channel->efx; 407 unsigned long entries; 408 409 netif_dbg(efx, probe, efx->net_dev, 410 "chan %d create event queue\n", channel->channel); 411 412 /* Build an event queue with room for one event per tx and rx buffer, 413 * plus some extra for link state events and MCDI completions. 414 */ 415 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 416 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 417 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 418 419 return efx_nic_probe_eventq(channel); 420} 421 422/* Prepare channel's event queue */ 423int efx_init_eventq(struct efx_channel *channel) 424{ 425 struct efx_nic *efx = channel->efx; 426 int rc; 427 428 EFX_WARN_ON_PARANOID(channel->eventq_init); 429 430 netif_dbg(efx, drv, efx->net_dev, 431 "chan %d init event queue\n", channel->channel); 432 433 rc = efx_nic_init_eventq(channel); 434 if (rc == 0) { 435 efx->type->push_irq_moderation(channel); 436 channel->eventq_read_ptr = 0; 437 channel->eventq_init = true; 438 } 439 return rc; 440} 441 442/* Enable event queue processing and NAPI */ 443void efx_start_eventq(struct efx_channel *channel) 444{ 445 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 446 "chan %d start event queue\n", channel->channel); 447 448 /* Make sure the NAPI handler sees the enabled flag set */ 449 channel->enabled = true; 450 smp_wmb(); 451 452 napi_enable(&channel->napi_str); 453 efx_nic_eventq_read_ack(channel); 454} 455 456/* Disable event queue processing and NAPI */ 457void efx_stop_eventq(struct efx_channel *channel) 458{ 459 if (!channel->enabled) 460 return; 461 462 napi_disable(&channel->napi_str); 463 channel->enabled = false; 464} 465 466void efx_fini_eventq(struct efx_channel *channel) 467{ 468 if (!channel->eventq_init) 469 return; 470 471 netif_dbg(channel->efx, drv, channel->efx->net_dev, 472 "chan %d fini event queue\n", channel->channel); 473 474 efx_nic_fini_eventq(channel); 475 channel->eventq_init = false; 476} 477 478void efx_remove_eventq(struct efx_channel *channel) 479{ 480 netif_dbg(channel->efx, drv, channel->efx->net_dev, 481 "chan %d remove event queue\n", channel->channel); 482 483 efx_nic_remove_eventq(channel); 484} 485 486/************************************************************************** 487 * 488 * Channel handling 489 * 490 *************************************************************************/ 491 492#ifdef CONFIG_RFS_ACCEL 493static void efx_filter_rfs_expire(struct work_struct *data) 494{ 495 struct delayed_work *dwork = to_delayed_work(data); 496 struct efx_channel *channel; 497 unsigned int time, quota; 498 499 channel = container_of(dwork, struct efx_channel, filter_work); 500 time = jiffies - channel->rfs_last_expiry; 501 quota = channel->rfs_filter_count * time / (30 * HZ); 502 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) 503 channel->rfs_last_expiry += time; 504 /* Ensure we do more work eventually even if NAPI poll is not happening */ 505 schedule_delayed_work(dwork, 30 * HZ); 506} 507#endif 508 509/* Allocate and initialise a channel structure. */ 510static struct efx_channel *efx_alloc_channel(struct efx_nic *efx, int i) 511{ 512 struct efx_rx_queue *rx_queue; 513 struct efx_tx_queue *tx_queue; 514 struct efx_channel *channel; 515 int j; 516 517 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 518 if (!channel) 519 return NULL; 520 521 channel->efx = efx; 522 channel->channel = i; 523 channel->type = &efx_default_channel_type; 524 525 for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) { 526 tx_queue = &channel->tx_queue[j]; 527 tx_queue->efx = efx; 528 tx_queue->queue = -1; 529 tx_queue->label = j; 530 tx_queue->channel = channel; 531 } 532 533#ifdef CONFIG_RFS_ACCEL 534 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 535#endif 536 537 rx_queue = &channel->rx_queue; 538 rx_queue->efx = efx; 539 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 540 541 return channel; 542} 543 544int efx_init_channels(struct efx_nic *efx) 545{ 546 unsigned int i; 547 548 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 549 efx->channel[i] = efx_alloc_channel(efx, i); 550 if (!efx->channel[i]) 551 return -ENOMEM; 552 efx->msi_context[i].efx = efx; 553 efx->msi_context[i].index = i; 554 } 555 556 /* Higher numbered interrupt modes are less capable! */ 557 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 558 efx_interrupt_mode); 559 560 efx->max_channels = EFX_MAX_CHANNELS; 561 efx->max_tx_channels = EFX_MAX_CHANNELS; 562 563 return 0; 564} 565 566void efx_fini_channels(struct efx_nic *efx) 567{ 568 unsigned int i; 569 570 for (i = 0; i < EFX_MAX_CHANNELS; i++) 571 if (efx->channel[i]) { 572 kfree(efx->channel[i]); 573 efx->channel[i] = NULL; 574 } 575} 576 577/* Allocate and initialise a channel structure, copying parameters 578 * (but not resources) from an old channel structure. 579 */ 580struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel) 581{ 582 struct efx_rx_queue *rx_queue; 583 struct efx_tx_queue *tx_queue; 584 struct efx_channel *channel; 585 int j; 586 587 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 588 if (!channel) 589 return NULL; 590 591 *channel = *old_channel; 592 593 channel->napi_dev = NULL; 594 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 595 channel->napi_str.napi_id = 0; 596 channel->napi_str.state = 0; 597 memset(&channel->eventq, 0, sizeof(channel->eventq)); 598 599 for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) { 600 tx_queue = &channel->tx_queue[j]; 601 if (tx_queue->channel) 602 tx_queue->channel = channel; 603 tx_queue->buffer = NULL; 604 tx_queue->cb_page = NULL; 605 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 606 } 607 608 rx_queue = &channel->rx_queue; 609 rx_queue->buffer = NULL; 610 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 611 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 612#ifdef CONFIG_RFS_ACCEL 613 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 614#endif 615 616 return channel; 617} 618 619static int efx_probe_channel(struct efx_channel *channel) 620{ 621 struct efx_tx_queue *tx_queue; 622 struct efx_rx_queue *rx_queue; 623 int rc; 624 625 netif_dbg(channel->efx, probe, channel->efx->net_dev, 626 "creating channel %d\n", channel->channel); 627 628 rc = channel->type->pre_probe(channel); 629 if (rc) 630 goto fail; 631 632 rc = efx_probe_eventq(channel); 633 if (rc) 634 goto fail; 635 636 efx_for_each_channel_tx_queue(tx_queue, channel) { 637 rc = efx_probe_tx_queue(tx_queue); 638 if (rc) 639 goto fail; 640 } 641 642 efx_for_each_channel_rx_queue(rx_queue, channel) { 643 rc = efx_probe_rx_queue(rx_queue); 644 if (rc) 645 goto fail; 646 } 647 648 channel->rx_list = NULL; 649 650 return 0; 651 652fail: 653 efx_remove_channel(channel); 654 return rc; 655} 656 657void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 658{ 659 struct efx_nic *efx = channel->efx; 660 const char *type; 661 int number; 662 663 number = channel->channel; 664 665 if (number >= efx->xdp_channel_offset && 666 !WARN_ON_ONCE(!efx->n_xdp_channels)) { 667 type = "-xdp"; 668 number -= efx->xdp_channel_offset; 669 } else if (efx->tx_channel_offset == 0) { 670 type = ""; 671 } else if (number < efx->tx_channel_offset) { 672 type = "-rx"; 673 } else { 674 type = "-tx"; 675 number -= efx->tx_channel_offset; 676 } 677 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 678} 679 680void efx_set_channel_names(struct efx_nic *efx) 681{ 682 struct efx_channel *channel; 683 684 efx_for_each_channel(channel, efx) 685 channel->type->get_name(channel, 686 efx->msi_context[channel->channel].name, 687 sizeof(efx->msi_context[0].name)); 688} 689 690int efx_probe_channels(struct efx_nic *efx) 691{ 692 struct efx_channel *channel; 693 int rc; 694 695 /* Restart special buffer allocation */ 696 efx->next_buffer_table = 0; 697 698 /* Probe channels in reverse, so that any 'extra' channels 699 * use the start of the buffer table. This allows the traffic 700 * channels to be resized without moving them or wasting the 701 * entries before them. 702 */ 703 efx_for_each_channel_rev(channel, efx) { 704 rc = efx_probe_channel(channel); 705 if (rc) { 706 netif_err(efx, probe, efx->net_dev, 707 "failed to create channel %d\n", 708 channel->channel); 709 goto fail; 710 } 711 } 712 efx_set_channel_names(efx); 713 714 return 0; 715 716fail: 717 efx_remove_channels(efx); 718 return rc; 719} 720 721void efx_remove_channel(struct efx_channel *channel) 722{ 723 struct efx_tx_queue *tx_queue; 724 struct efx_rx_queue *rx_queue; 725 726 netif_dbg(channel->efx, drv, channel->efx->net_dev, 727 "destroy chan %d\n", channel->channel); 728 729 efx_for_each_channel_rx_queue(rx_queue, channel) 730 efx_remove_rx_queue(rx_queue); 731 efx_for_each_channel_tx_queue(tx_queue, channel) 732 efx_remove_tx_queue(tx_queue); 733 efx_remove_eventq(channel); 734 channel->type->post_remove(channel); 735} 736 737void efx_remove_channels(struct efx_nic *efx) 738{ 739 struct efx_channel *channel; 740 741 efx_for_each_channel(channel, efx) 742 efx_remove_channel(channel); 743 744 kfree(efx->xdp_tx_queues); 745} 746 747int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 748{ 749 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel, 750 *ptp_channel = efx_ptp_channel(efx); 751 struct efx_ptp_data *ptp_data = efx->ptp_data; 752 unsigned int i, next_buffer_table = 0; 753 u32 old_rxq_entries, old_txq_entries; 754 int rc, rc2; 755 756 rc = efx_check_disabled(efx); 757 if (rc) 758 return rc; 759 760 /* Not all channels should be reallocated. We must avoid 761 * reallocating their buffer table entries. 762 */ 763 efx_for_each_channel(channel, efx) { 764 struct efx_rx_queue *rx_queue; 765 struct efx_tx_queue *tx_queue; 766 767 if (channel->type->copy) 768 continue; 769 next_buffer_table = max(next_buffer_table, 770 channel->eventq.index + 771 channel->eventq.entries); 772 efx_for_each_channel_rx_queue(rx_queue, channel) 773 next_buffer_table = max(next_buffer_table, 774 rx_queue->rxd.index + 775 rx_queue->rxd.entries); 776 efx_for_each_channel_tx_queue(tx_queue, channel) 777 next_buffer_table = max(next_buffer_table, 778 tx_queue->txd.index + 779 tx_queue->txd.entries); 780 } 781 782 efx_device_detach_sync(efx); 783 efx_stop_all(efx); 784 efx_soft_disable_interrupts(efx); 785 786 /* Clone channels (where possible) */ 787 memset(other_channel, 0, sizeof(other_channel)); 788 for (i = 0; i < efx->n_channels; i++) { 789 channel = efx->channel[i]; 790 if (channel->type->copy) 791 channel = channel->type->copy(channel); 792 if (!channel) { 793 rc = -ENOMEM; 794 goto out; 795 } 796 other_channel[i] = channel; 797 } 798 799 /* Swap entry counts and channel pointers */ 800 old_rxq_entries = efx->rxq_entries; 801 old_txq_entries = efx->txq_entries; 802 efx->rxq_entries = rxq_entries; 803 efx->txq_entries = txq_entries; 804 for (i = 0; i < efx->n_channels; i++) 805 swap(efx->channel[i], other_channel[i]); 806 807 /* Restart buffer table allocation */ 808 efx->next_buffer_table = next_buffer_table; 809 810 for (i = 0; i < efx->n_channels; i++) { 811 channel = efx->channel[i]; 812 if (!channel->type->copy) 813 continue; 814 rc = efx_probe_channel(channel); 815 if (rc) 816 goto rollback; 817 efx_init_napi_channel(efx->channel[i]); 818 } 819 820out: 821 efx->ptp_data = NULL; 822 /* Destroy unused channel structures */ 823 for (i = 0; i < efx->n_channels; i++) { 824 channel = other_channel[i]; 825 if (channel && channel->type->copy) { 826 efx_fini_napi_channel(channel); 827 efx_remove_channel(channel); 828 kfree(channel); 829 } 830 } 831 832 efx->ptp_data = ptp_data; 833 rc2 = efx_soft_enable_interrupts(efx); 834 if (rc2) { 835 rc = rc ? rc : rc2; 836 netif_err(efx, drv, efx->net_dev, 837 "unable to restart interrupts on channel reallocation\n"); 838 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 839 } else { 840 efx_start_all(efx); 841 efx_device_attach_if_not_resetting(efx); 842 } 843 return rc; 844 845rollback: 846 /* Swap back */ 847 efx->rxq_entries = old_rxq_entries; 848 efx->txq_entries = old_txq_entries; 849 for (i = 0; i < efx->n_channels; i++) 850 swap(efx->channel[i], other_channel[i]); 851 efx_ptp_update_channel(efx, ptp_channel); 852 goto out; 853} 854 855int efx_set_channels(struct efx_nic *efx) 856{ 857 struct efx_tx_queue *tx_queue; 858 struct efx_channel *channel; 859 unsigned int next_queue = 0; 860 int xdp_queue_number; 861 int rc; 862 863 if (efx->xdp_tx_queue_count) { 864 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); 865 866 /* Allocate array for XDP TX queue lookup. */ 867 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, 868 sizeof(*efx->xdp_tx_queues), 869 GFP_KERNEL); 870 if (!efx->xdp_tx_queues) 871 return -ENOMEM; 872 } 873 874 /* We need to mark which channels really have RX and TX 875 * queues, and adjust the TX queue numbers if we have separate 876 * RX-only and TX-only channels. 877 */ 878 xdp_queue_number = 0; 879 efx_for_each_channel(channel, efx) { 880 if (channel->channel < efx->n_rx_channels) 881 channel->rx_queue.core_index = channel->channel; 882 else 883 channel->rx_queue.core_index = -1; 884 885 if (channel->channel >= efx->tx_channel_offset) { 886 if (efx_channel_is_xdp_tx(channel)) { 887 efx_for_each_channel_tx_queue(tx_queue, channel) { 888 tx_queue->queue = next_queue++; 889 890 /* We may have a few left-over XDP TX 891 * queues owing to xdp_tx_queue_count 892 * not dividing evenly by EFX_MAX_TXQ_PER_CHANNEL. 893 * We still allocate and probe those 894 * TXQs, but never use them. 895 */ 896 if (xdp_queue_number < efx->xdp_tx_queue_count) { 897 netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is XDP %u, HW %u\n", 898 channel->channel, tx_queue->label, 899 xdp_queue_number, tx_queue->queue); 900 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; 901 xdp_queue_number++; 902 } 903 } 904 } else { 905 efx_for_each_channel_tx_queue(tx_queue, channel) { 906 tx_queue->queue = next_queue++; 907 netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is HW %u\n", 908 channel->channel, tx_queue->label, 909 tx_queue->queue); 910 } 911 } 912 } 913 } 914 WARN_ON(xdp_queue_number != efx->xdp_tx_queue_count); 915 916 rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 917 if (rc) 918 return rc; 919 return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 920} 921 922bool efx_default_channel_want_txqs(struct efx_channel *channel) 923{ 924 return channel->channel - channel->efx->tx_channel_offset < 925 channel->efx->n_tx_channels; 926} 927 928/************* 929 * START/STOP 930 *************/ 931 932int efx_soft_enable_interrupts(struct efx_nic *efx) 933{ 934 struct efx_channel *channel, *end_channel; 935 int rc; 936 937 BUG_ON(efx->state == STATE_DISABLED); 938 939 efx->irq_soft_enabled = true; 940 smp_wmb(); 941 942 efx_for_each_channel(channel, efx) { 943 if (!channel->type->keep_eventq) { 944 rc = efx_init_eventq(channel); 945 if (rc) 946 goto fail; 947 } 948 efx_start_eventq(channel); 949 } 950 951 efx_mcdi_mode_event(efx); 952 953 return 0; 954fail: 955 end_channel = channel; 956 efx_for_each_channel(channel, efx) { 957 if (channel == end_channel) 958 break; 959 efx_stop_eventq(channel); 960 if (!channel->type->keep_eventq) 961 efx_fini_eventq(channel); 962 } 963 964 return rc; 965} 966 967void efx_soft_disable_interrupts(struct efx_nic *efx) 968{ 969 struct efx_channel *channel; 970 971 if (efx->state == STATE_DISABLED) 972 return; 973 974 efx_mcdi_mode_poll(efx); 975 976 efx->irq_soft_enabled = false; 977 smp_wmb(); 978 979 if (efx->legacy_irq) 980 synchronize_irq(efx->legacy_irq); 981 982 efx_for_each_channel(channel, efx) { 983 if (channel->irq) 984 synchronize_irq(channel->irq); 985 986 efx_stop_eventq(channel); 987 if (!channel->type->keep_eventq) 988 efx_fini_eventq(channel); 989 } 990 991 /* Flush the asynchronous MCDI request queue */ 992 efx_mcdi_flush_async(efx); 993} 994 995int efx_enable_interrupts(struct efx_nic *efx) 996{ 997 struct efx_channel *channel, *end_channel; 998 int rc; 999 1000 /* TODO: Is this really a bug? */ 1001 BUG_ON(efx->state == STATE_DISABLED); 1002 1003 if (efx->eeh_disabled_legacy_irq) { 1004 enable_irq(efx->legacy_irq); 1005 efx->eeh_disabled_legacy_irq = false; 1006 } 1007 1008 efx->type->irq_enable_master(efx); 1009 1010 efx_for_each_channel(channel, efx) { 1011 if (channel->type->keep_eventq) { 1012 rc = efx_init_eventq(channel); 1013 if (rc) 1014 goto fail; 1015 } 1016 } 1017 1018 rc = efx_soft_enable_interrupts(efx); 1019 if (rc) 1020 goto fail; 1021 1022 return 0; 1023 1024fail: 1025 end_channel = channel; 1026 efx_for_each_channel(channel, efx) { 1027 if (channel == end_channel) 1028 break; 1029 if (channel->type->keep_eventq) 1030 efx_fini_eventq(channel); 1031 } 1032 1033 efx->type->irq_disable_non_ev(efx); 1034 1035 return rc; 1036} 1037 1038void efx_disable_interrupts(struct efx_nic *efx) 1039{ 1040 struct efx_channel *channel; 1041 1042 efx_soft_disable_interrupts(efx); 1043 1044 efx_for_each_channel(channel, efx) { 1045 if (channel->type->keep_eventq) 1046 efx_fini_eventq(channel); 1047 } 1048 1049 efx->type->irq_disable_non_ev(efx); 1050} 1051 1052void efx_start_channels(struct efx_nic *efx) 1053{ 1054 struct efx_tx_queue *tx_queue; 1055 struct efx_rx_queue *rx_queue; 1056 struct efx_channel *channel; 1057 1058 efx_for_each_channel(channel, efx) { 1059 efx_for_each_channel_tx_queue(tx_queue, channel) { 1060 efx_init_tx_queue(tx_queue); 1061 atomic_inc(&efx->active_queues); 1062 } 1063 1064 efx_for_each_channel_rx_queue(rx_queue, channel) { 1065 efx_init_rx_queue(rx_queue); 1066 atomic_inc(&efx->active_queues); 1067 efx_stop_eventq(channel); 1068 efx_fast_push_rx_descriptors(rx_queue, false); 1069 efx_start_eventq(channel); 1070 } 1071 1072 WARN_ON(channel->rx_pkt_n_frags); 1073 } 1074} 1075 1076void efx_stop_channels(struct efx_nic *efx) 1077{ 1078 struct efx_tx_queue *tx_queue; 1079 struct efx_rx_queue *rx_queue; 1080 struct efx_channel *channel; 1081 int rc = 0; 1082 1083 /* Stop RX refill */ 1084 efx_for_each_channel(channel, efx) { 1085 efx_for_each_channel_rx_queue(rx_queue, channel) 1086 rx_queue->refill_enabled = false; 1087 } 1088 1089 efx_for_each_channel(channel, efx) { 1090 /* RX packet processing is pipelined, so wait for the 1091 * NAPI handler to complete. At least event queue 0 1092 * might be kept active by non-data events, so don't 1093 * use napi_synchronize() but actually disable NAPI 1094 * temporarily. 1095 */ 1096 if (efx_channel_has_rx_queue(channel)) { 1097 efx_stop_eventq(channel); 1098 efx_start_eventq(channel); 1099 } 1100 } 1101 1102 if (efx->type->fini_dmaq) 1103 rc = efx->type->fini_dmaq(efx); 1104 1105 if (rc) { 1106 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 1107 } else { 1108 netif_dbg(efx, drv, efx->net_dev, 1109 "successfully flushed all queues\n"); 1110 } 1111 1112 efx_for_each_channel(channel, efx) { 1113 efx_for_each_channel_rx_queue(rx_queue, channel) 1114 efx_fini_rx_queue(rx_queue); 1115 efx_for_each_channel_tx_queue(tx_queue, channel) 1116 efx_fini_tx_queue(tx_queue); 1117 } 1118} 1119 1120/************************************************************************** 1121 * 1122 * NAPI interface 1123 * 1124 *************************************************************************/ 1125 1126/* Process channel's event queue 1127 * 1128 * This function is responsible for processing the event queue of a 1129 * single channel. The caller must guarantee that this function will 1130 * never be concurrently called more than once on the same channel, 1131 * though different channels may be being processed concurrently. 1132 */ 1133static int efx_process_channel(struct efx_channel *channel, int budget) 1134{ 1135 struct efx_tx_queue *tx_queue; 1136 struct list_head rx_list; 1137 int spent; 1138 1139 if (unlikely(!channel->enabled)) 1140 return 0; 1141 1142 /* Prepare the batch receive list */ 1143 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); 1144 INIT_LIST_HEAD(&rx_list); 1145 channel->rx_list = &rx_list; 1146 1147 efx_for_each_channel_tx_queue(tx_queue, channel) { 1148 tx_queue->pkts_compl = 0; 1149 tx_queue->bytes_compl = 0; 1150 } 1151 1152 spent = efx_nic_process_eventq(channel, budget); 1153 if (spent && efx_channel_has_rx_queue(channel)) { 1154 struct efx_rx_queue *rx_queue = 1155 efx_channel_get_rx_queue(channel); 1156 1157 efx_rx_flush_packet(channel); 1158 efx_fast_push_rx_descriptors(rx_queue, true); 1159 } 1160 1161 /* Update BQL */ 1162 efx_for_each_channel_tx_queue(tx_queue, channel) { 1163 if (tx_queue->bytes_compl) { 1164 netdev_tx_completed_queue(tx_queue->core_txq, 1165 tx_queue->pkts_compl, 1166 tx_queue->bytes_compl); 1167 } 1168 } 1169 1170 /* Receive any packets we queued up */ 1171 netif_receive_skb_list(channel->rx_list); 1172 channel->rx_list = NULL; 1173 1174 return spent; 1175} 1176 1177static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 1178{ 1179 int step = efx->irq_mod_step_us; 1180 1181 if (channel->irq_mod_score < irq_adapt_low_thresh) { 1182 if (channel->irq_moderation_us > step) { 1183 channel->irq_moderation_us -= step; 1184 efx->type->push_irq_moderation(channel); 1185 } 1186 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 1187 if (channel->irq_moderation_us < 1188 efx->irq_rx_moderation_us) { 1189 channel->irq_moderation_us += step; 1190 efx->type->push_irq_moderation(channel); 1191 } 1192 } 1193 1194 channel->irq_count = 0; 1195 channel->irq_mod_score = 0; 1196} 1197 1198/* NAPI poll handler 1199 * 1200 * NAPI guarantees serialisation of polls of the same device, which 1201 * provides the guarantee required by efx_process_channel(). 1202 */ 1203static int efx_poll(struct napi_struct *napi, int budget) 1204{ 1205 struct efx_channel *channel = 1206 container_of(napi, struct efx_channel, napi_str); 1207 struct efx_nic *efx = channel->efx; 1208#ifdef CONFIG_RFS_ACCEL 1209 unsigned int time; 1210#endif 1211 int spent; 1212 1213 netif_vdbg(efx, intr, efx->net_dev, 1214 "channel %d NAPI poll executing on CPU %d\n", 1215 channel->channel, raw_smp_processor_id()); 1216 1217 spent = efx_process_channel(channel, budget); 1218 1219 xdp_do_flush_map(); 1220 1221 if (spent < budget) { 1222 if (efx_channel_has_rx_queue(channel) && 1223 efx->irq_rx_adaptive && 1224 unlikely(++channel->irq_count == 1000)) { 1225 efx_update_irq_mod(efx, channel); 1226 } 1227 1228#ifdef CONFIG_RFS_ACCEL 1229 /* Perhaps expire some ARFS filters */ 1230 time = jiffies - channel->rfs_last_expiry; 1231 /* Would our quota be >= 20? */ 1232 if (channel->rfs_filter_count * time >= 600 * HZ) 1233 mod_delayed_work(system_wq, &channel->filter_work, 0); 1234#endif 1235 1236 /* There is no race here; although napi_disable() will 1237 * only wait for napi_complete(), this isn't a problem 1238 * since efx_nic_eventq_read_ack() will have no effect if 1239 * interrupts have already been disabled. 1240 */ 1241 if (napi_complete_done(napi, spent)) 1242 efx_nic_eventq_read_ack(channel); 1243 } 1244 1245 return spent; 1246} 1247 1248void efx_init_napi_channel(struct efx_channel *channel) 1249{ 1250 struct efx_nic *efx = channel->efx; 1251 1252 channel->napi_dev = efx->net_dev; 1253 netif_napi_add(channel->napi_dev, &channel->napi_str, 1254 efx_poll, napi_weight); 1255} 1256 1257void efx_init_napi(struct efx_nic *efx) 1258{ 1259 struct efx_channel *channel; 1260 1261 efx_for_each_channel(channel, efx) 1262 efx_init_napi_channel(channel); 1263} 1264 1265void efx_fini_napi_channel(struct efx_channel *channel) 1266{ 1267 if (channel->napi_dev) 1268 netif_napi_del(&channel->napi_str); 1269 1270 channel->napi_dev = NULL; 1271} 1272 1273void efx_fini_napi(struct efx_nic *efx) 1274{ 1275 struct efx_channel *channel; 1276 1277 efx_for_each_channel(channel, efx) 1278 efx_fini_napi_channel(channel); 1279} 1280