1/* SPDX-License-Identifier: GPL-2.0 */
2/*  SuperH Ethernet device driver
3 *
4 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
6 */
7
8#ifndef __SH_ETH_H__
9#define __SH_ETH_H__
10
11#define CARDNAME	"sh-eth"
12#define TX_TIMEOUT	(5*HZ)
13#define TX_RING_SIZE	64	/* Tx ring size */
14#define RX_RING_SIZE	64	/* Rx ring size */
15#define TX_RING_MIN	64
16#define RX_RING_MIN	64
17#define TX_RING_MAX	1024
18#define RX_RING_MAX	1024
19#define PKT_BUF_SZ	1538
20#define SH_ETH_TSU_TIMEOUT_MS	500
21#define SH_ETH_TSU_CAM_ENTRIES	32
22
23enum {
24	/* IMPORTANT: To keep ethtool register dump working, add new
25	 * register names immediately before SH_ETH_MAX_REGISTER_OFFSET.
26	 */
27
28	/* E-DMAC registers */
29	EDSR = 0,
30	EDMR,
31	EDTRR,
32	EDRRR,
33	EESR,
34	EESIPR,
35	TDLAR,
36	TDFAR,
37	TDFXR,
38	TDFFR,
39	RDLAR,
40	RDFAR,
41	RDFXR,
42	RDFFR,
43	TRSCER,
44	RMFCR,
45	TFTR,
46	FDR,
47	RMCR,
48	EDOCR,
49	TFUCR,
50	RFOCR,
51	RMIIMODE,
52	FCFTR,
53	RPADIR,
54	TRIMD,
55	RBWAR,
56	TBRAR,
57
58	/* Ether registers */
59	ECMR,
60	ECSR,
61	ECSIPR,
62	PIR,
63	PSR,
64	RDMLR,
65	PIPR,
66	RFLR,
67	IPGR,
68	APR,
69	MPR,
70	PFTCR,
71	PFRCR,
72	RFCR,
73	RFCF,
74	TPAUSER,
75	TPAUSECR,
76	BCFR,
77	BCFRR,
78	GECMR,
79	BCULR,
80	MAHR,
81	MALR,
82	TROCR,
83	CDCR,
84	LCCR,
85	CNDCR,
86	CEFCR,
87	FRECR,
88	TSFRCR,
89	TLFRCR,
90	CERCR,
91	CEECR,
92	MAFCR,
93	RTRATE,
94	CSMR,
95	RMII_MII,
96
97	/* TSU Absolute address */
98	ARSTR,
99	TSU_CTRST,
100	TSU_FWEN0,
101	TSU_FWEN1,
102	TSU_FCM,
103	TSU_BSYSL0,
104	TSU_BSYSL1,
105	TSU_PRISL0,
106	TSU_PRISL1,
107	TSU_FWSL0,
108	TSU_FWSL1,
109	TSU_FWSLC,
110	TSU_QTAG0,			/* Same as TSU_QTAGM0 */
111	TSU_QTAG1,			/* Same as TSU_QTAGM1 */
112	TSU_QTAGM0,
113	TSU_QTAGM1,
114	TSU_FWSR,
115	TSU_FWINMK,
116	TSU_ADQT0,
117	TSU_ADQT1,
118	TSU_VTAG0,
119	TSU_VTAG1,
120	TSU_ADSBSY,
121	TSU_TEN,
122	TSU_POST1,
123	TSU_POST2,
124	TSU_POST3,
125	TSU_POST4,
126	TSU_ADRH0,
127	/* TSU_ADR{H,L}{0..31} are assumed to be contiguous */
128
129	TXNLCR0,
130	TXALCR0,
131	RXNLCR0,
132	RXALCR0,
133	FWNLCR0,
134	FWALCR0,
135	TXNLCR1,
136	TXALCR1,
137	RXNLCR1,
138	RXALCR1,
139	FWNLCR1,
140	FWALCR1,
141
142	/* This value must be written at last. */
143	SH_ETH_MAX_REGISTER_OFFSET,
144};
145
146enum {
147	SH_ETH_REG_GIGABIT,
148	SH_ETH_REG_FAST_RCAR,
149	SH_ETH_REG_FAST_SH4,
150	SH_ETH_REG_FAST_SH3_SH2
151};
152
153/* Driver's parameters */
154#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS)
155#define SH_ETH_RX_ALIGN		32
156#else
157#define SH_ETH_RX_ALIGN		2
158#endif
159
160/* Register's bits
161 */
162/* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */
163enum EDSR_BIT {
164	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
165};
166#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
167
168/* GECMR : sh7734, sh7763 and r8a7740 only */
169enum GECMR_BIT {
170	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
171};
172
173/* EDMR */
174enum DMAC_M_BIT {
175	EDMR_NBST = 0x80,
176	EDMR_EL = 0x40, /* Litte endian */
177	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
178	EDMR_SRST_GETHER = 0x03,
179	EDMR_SRST_ETHER = 0x01,
180};
181
182/* EDTRR */
183enum DMAC_T_BIT {
184	EDTRR_TRNS_GETHER = 0x03,
185	EDTRR_TRNS_ETHER = 0x01,
186};
187
188/* EDRRR */
189enum EDRRR_R_BIT {
190	EDRRR_R = 0x01,
191};
192
193/* TPAUSER */
194enum TPAUSER_BIT {
195	TPAUSER_TPAUSE = 0x0000ffff,
196	TPAUSER_UNLIMITED = 0,
197};
198
199/* BCFR */
200enum BCFR_BIT {
201	BCFR_RPAUSE = 0x0000ffff,
202	BCFR_UNLIMITED = 0,
203};
204
205/* PIR */
206enum PIR_BIT {
207	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
208};
209
210/* PSR */
211enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
212
213/* EESR */
214enum EESR_BIT {
215	EESR_TWB1	= 0x80000000,
216	EESR_TWB	= 0x40000000,	/* same as TWB0 */
217	EESR_TC1	= 0x20000000,
218	EESR_TUC	= 0x10000000,
219	EESR_ROC	= 0x08000000,
220	EESR_TABT	= 0x04000000,
221	EESR_RABT	= 0x02000000,
222	EESR_RFRMER	= 0x01000000,	/* same as RFCOF */
223	EESR_ADE	= 0x00800000,
224	EESR_ECI	= 0x00400000,
225	EESR_FTC	= 0x00200000,	/* same as TC or TC0 */
226	EESR_TDE	= 0x00100000,
227	EESR_TFE	= 0x00080000,	/* same as TFUF */
228	EESR_FRC	= 0x00040000,	/* same as FR */
229	EESR_RDE	= 0x00020000,
230	EESR_RFE	= 0x00010000,
231	EESR_CND	= 0x00000800,
232	EESR_DLC	= 0x00000400,
233	EESR_CD		= 0x00000200,
234	EESR_TRO	= 0x00000100,
235	EESR_RMAF	= 0x00000080,
236	EESR_CEEF	= 0x00000040,
237	EESR_CELF	= 0x00000020,
238	EESR_RRF	= 0x00000010,
239	EESR_RTLF	= 0x00000008,
240	EESR_RTSF	= 0x00000004,
241	EESR_PRE	= 0x00000002,
242	EESR_CERF	= 0x00000001,
243};
244
245#define EESR_RX_CHECK		(EESR_FRC  | /* Frame recv */		\
246				 EESR_RMAF | /* Multicast address recv */ \
247				 EESR_RRF  | /* Bit frame recv */	\
248				 EESR_RTLF | /* Long frame recv */	\
249				 EESR_RTSF | /* Short frame recv */	\
250				 EESR_PRE  | /* PHY-LSI recv error */	\
251				 EESR_CERF)  /* Recv frame CRC error */
252
253#define DEFAULT_TX_CHECK	(EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
254				 EESR_TRO)
255#define DEFAULT_EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
256				 EESR_RDE | EESR_RFRMER | EESR_ADE | \
257				 EESR_TFE | EESR_TDE)
258
259/* EESIPR */
260enum EESIPR_BIT {
261	EESIPR_TWB1IP	= 0x80000000,
262	EESIPR_TWBIP	= 0x40000000,	/* same as TWB0IP */
263	EESIPR_TC1IP	= 0x20000000,
264	EESIPR_TUCIP	= 0x10000000,
265	EESIPR_ROCIP	= 0x08000000,
266	EESIPR_TABTIP	= 0x04000000,
267	EESIPR_RABTIP	= 0x02000000,
268	EESIPR_RFCOFIP	= 0x01000000,
269	EESIPR_ADEIP	= 0x00800000,
270	EESIPR_ECIIP	= 0x00400000,
271	EESIPR_FTCIP	= 0x00200000,	/* same as TC0IP */
272	EESIPR_TDEIP	= 0x00100000,
273	EESIPR_TFUFIP	= 0x00080000,
274	EESIPR_FRIP	= 0x00040000,
275	EESIPR_RDEIP	= 0x00020000,
276	EESIPR_RFOFIP	= 0x00010000,
277	EESIPR_CNDIP	= 0x00000800,
278	EESIPR_DLCIP	= 0x00000400,
279	EESIPR_CDIP	= 0x00000200,
280	EESIPR_TROIP	= 0x00000100,
281	EESIPR_RMAFIP	= 0x00000080,
282	EESIPR_CEEFIP	= 0x00000040,
283	EESIPR_CELFIP	= 0x00000020,
284	EESIPR_RRFIP	= 0x00000010,
285	EESIPR_RTLFIP	= 0x00000008,
286	EESIPR_RTSFIP	= 0x00000004,
287	EESIPR_PREIP	= 0x00000002,
288	EESIPR_CERFIP	= 0x00000001,
289};
290
291/* Receive descriptor 0 bits */
292enum RD_STS_BIT {
293	RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
294	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
295	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
296	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
297	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
298	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
299	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
300	RD_RFS1 = 0x00000001,
301};
302#define RDF1ST	RD_RFP1
303#define RDFEND	RD_RFP0
304#define RD_RFP	(RD_RFP1|RD_RFP0)
305
306/* Receive descriptor 1 bits */
307enum RD_LEN_BIT {
308	RD_RFL	= 0x0000ffff,	/* receive frame  length */
309	RD_RBL	= 0xffff0000,	/* receive buffer length */
310};
311
312/* FCFTR */
313enum FCFTR_BIT {
314	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
315	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
316	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
317};
318#define DEFAULT_FIFO_F_D_RFF	(FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
319#define DEFAULT_FIFO_F_D_RFD	(FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
320
321/* Transmit descriptor 0 bits */
322enum TD_STS_BIT {
323	TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
324	TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
325	TD_TFE  = 0x08000000, TD_TWBI = 0x04000000,
326};
327#define TDF1ST	TD_TFP1
328#define TDFEND	TD_TFP0
329#define TD_TFP	(TD_TFP1|TD_TFP0)
330
331/* Transmit descriptor 1 bits */
332enum TD_LEN_BIT {
333	TD_TBL	= 0xffff0000,	/* transmit buffer length */
334};
335
336/* RMCR */
337enum RMCR_BIT {
338	RMCR_RNC = 0x00000001,
339};
340
341/* ECMR */
342enum FELIC_MODE_BIT {
343	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
344	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
345	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
346	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
347	ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
348	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
349	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
350};
351
352/* ECSR */
353enum ECSR_STATUS_BIT {
354	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
355	ECSR_LCHNG = 0x04,
356	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
357};
358
359#define DEFAULT_ECSR_INIT	(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
360				 ECSR_ICD | ECSIPR_MPDIP)
361
362/* ECSIPR */
363enum ECSIPR_STATUS_MASK_BIT {
364	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
365	ECSIPR_LCHNGIP = 0x04,
366	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
367};
368
369#define DEFAULT_ECSIPR_INIT	(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
370				 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
371
372/* APR */
373enum APR_BIT {
374	APR_AP = 0x0000ffff,
375};
376
377/* MPR */
378enum MPR_BIT {
379	MPR_MP = 0x0000ffff,
380};
381
382/* TRSCER */
383enum DESC_I_BIT {
384	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
385	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
386	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
387	DESC_I_RINT1 = 0x0001,
388};
389
390#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)
391
392/* RPADIR */
393enum RPADIR_BIT {
394	RPADIR_PADS = 0x1f0000, RPADIR_PADR = 0xffff,
395};
396
397/* FDR */
398#define DEFAULT_FDR_INIT	0x00000707
399
400/* ARSTR */
401enum ARSTR_BIT { ARSTR_ARST = 0x00000001, };
402
403/* TSU_FWEN0 */
404enum TSU_FWEN0_BIT {
405	TSU_FWEN0_0 = 0x00000001,
406};
407
408/* TSU_ADSBSY */
409enum TSU_ADSBSY_BIT {
410	TSU_ADSBSY_0 = 0x00000001,
411};
412
413/* TSU_TEN */
414enum TSU_TEN_BIT {
415	TSU_TEN_0 = 0x80000000,
416};
417
418/* TSU_FWSL0 */
419enum TSU_FWSL0_BIT {
420	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
421	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
422	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
423};
424
425/* TSU_FWSLC */
426enum TSU_FWSLC_BIT {
427	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
428	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
429	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
430	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
431	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
432};
433
434/* TSU_VTAGn */
435#define TSU_VTAG_ENABLE		0x80000000
436#define TSU_VTAG_VID_MASK	0x00000fff
437
438/* The sh ether Tx buffer descriptors.
439 * This structure should be 20 bytes.
440 */
441struct sh_eth_txdesc {
442	u32 status;		/* TD0 */
443	u32 len;		/* TD1 */
444	u32 addr;		/* TD2 */
445	u32 pad0;		/* padding data */
446} __aligned(2) __packed;
447
448/* The sh ether Rx buffer descriptors.
449 * This structure should be 20 bytes.
450 */
451struct sh_eth_rxdesc {
452	u32 status;		/* RD0 */
453	u32 len;		/* RD1 */
454	u32 addr;		/* RD2 */
455	u32 pad0;		/* padding data */
456} __aligned(2) __packed;
457
458/* This structure is used by each CPU dependency handling. */
459struct sh_eth_cpu_data {
460	/* mandatory functions */
461	int (*soft_reset)(struct net_device *ndev);
462
463	/* optional functions */
464	void (*chip_reset)(struct net_device *ndev);
465	void (*set_duplex)(struct net_device *ndev);
466	void (*set_rate)(struct net_device *ndev);
467
468	/* mandatory initialize value */
469	int register_type;
470	u32 edtrr_trns;
471	u32 eesipr_value;
472
473	/* optional initialize value */
474	u32 ecsr_value;
475	u32 ecsipr_value;
476	u32 fdr_value;
477	u32 fcftr_value;
478
479	/* interrupt checking mask */
480	u32 tx_check;
481	u32 eesr_err_check;
482
483	/* Error mask */
484	u32 trscer_err_mask;
485
486	/* hardware features */
487	unsigned long irq_flags; /* IRQ configuration flags */
488	unsigned no_psr:1;	/* EtherC DOES NOT have PSR */
489	unsigned apr:1;		/* EtherC has APR */
490	unsigned mpr:1;		/* EtherC has MPR */
491	unsigned tpauser:1;	/* EtherC has TPAUSER */
492	unsigned gecmr:1;	/* EtherC has GECMR */
493	unsigned bculr:1;	/* EtherC has BCULR */
494	unsigned tsu:1;		/* EtherC has TSU */
495	unsigned hw_swap:1;	/* E-DMAC has DE bit in EDMR */
496	unsigned nbst:1;	/* E-DMAC has NBST bit in EDMR */
497	unsigned rpadir:1;	/* E-DMAC has RPADIR */
498	unsigned no_trimd:1;	/* E-DMAC DOES NOT have TRIMD */
499	unsigned no_ade:1;	/* E-DMAC DOES NOT have ADE bit in EESR */
500	unsigned no_xdfar:1;	/* E-DMAC DOES NOT have RDFAR/TDFAR */
501	unsigned xdfar_rw:1;	/* E-DMAC has writeable RDFAR/TDFAR */
502	unsigned csmr:1;	/* E-DMAC has CSMR */
503	unsigned rx_csum:1;	/* EtherC has ECMR.RCSC */
504	unsigned select_mii:1;	/* EtherC has RMII_MII (MII select register) */
505	unsigned rmiimode:1;	/* EtherC has RMIIMODE register */
506	unsigned rtrate:1;	/* EtherC has RTRATE register */
507	unsigned magic:1;	/* EtherC has ECMR.MPDE and ECSR.MPD */
508	unsigned no_tx_cntrs:1;	/* EtherC DOES NOT have TX error counters */
509	unsigned cexcr:1;	/* EtherC has CERCR/CEECR */
510	unsigned dual_port:1;	/* Dual EtherC/E-DMAC */
511};
512
513struct sh_eth_private {
514	struct platform_device *pdev;
515	struct sh_eth_cpu_data *cd;
516	const u16 *reg_offset;
517	void __iomem *addr;
518	void __iomem *tsu_addr;
519	struct clk *clk;
520	u32 num_rx_ring;
521	u32 num_tx_ring;
522	dma_addr_t rx_desc_dma;
523	dma_addr_t tx_desc_dma;
524	struct sh_eth_rxdesc *rx_ring;
525	struct sh_eth_txdesc *tx_ring;
526	struct sk_buff **rx_skbuff;
527	struct sk_buff **tx_skbuff;
528	spinlock_t lock;		/* Register access lock */
529	u32 cur_rx, dirty_rx;		/* Producer/consumer ring indices */
530	u32 cur_tx, dirty_tx;
531	u32 rx_buf_sz;			/* Based on MTU+slack. */
532	struct napi_struct napi;
533	bool irq_enabled;
534	/* MII transceiver section. */
535	u32 phy_id;			/* PHY ID */
536	struct mii_bus *mii_bus;	/* MDIO bus control */
537	int link;
538	phy_interface_t phy_interface;
539	int msg_enable;
540	int speed;
541	int duplex;
542	int port;			/* for TSU */
543	int vlan_num_ids;		/* for VLAN tag filter */
544
545	unsigned no_ether_link:1;
546	unsigned ether_link_active_low:1;
547	unsigned is_opened:1;
548	unsigned wol_enabled:1;
549};
550
551#endif	/* #ifndef __SH_ETH_H__ */
552