1// SPDX-License-Identifier: GPL-2.0 2/* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11#include <linux/cache.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/etherdevice.h> 17#include <linux/ethtool.h> 18#include <linux/if_vlan.h> 19#include <linux/kernel.h> 20#include <linux/list.h> 21#include <linux/module.h> 22#include <linux/net_tstamp.h> 23#include <linux/of.h> 24#include <linux/of_device.h> 25#include <linux/of_irq.h> 26#include <linux/of_mdio.h> 27#include <linux/of_net.h> 28#include <linux/pm_runtime.h> 29#include <linux/slab.h> 30#include <linux/spinlock.h> 31#include <linux/sys_soc.h> 32 33#include <asm/div64.h> 34 35#include "ravb.h" 36 37#define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46}; 47 48static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51}; 52 53void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55{ 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57} 58 59int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60{ 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69} 70 71static int ravb_config(struct net_device *ndev) 72{ 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83} 84 85static void ravb_set_rate(struct net_device *ndev) 86{ 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97} 98 99static void ravb_set_buffer_align(struct sk_buff *skb) 100{ 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105} 106 107/* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 113{ 114 if (!IS_ERR(mac)) { 115 ether_addr_copy(ndev->dev_addr, mac); 116 } else { 117 u32 mahr = ravb_read(ndev, MAHR); 118 u32 malr = ravb_read(ndev, MALR); 119 120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 124 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 125 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 126 } 127} 128 129static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 130{ 131 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 132 mdiobb); 133 134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 135} 136 137/* MDC pin control */ 138static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 139{ 140 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 141} 142 143/* Data I/O pin control */ 144static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 145{ 146 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 147} 148 149/* Set data bit */ 150static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 151{ 152 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 153} 154 155/* Get data bit */ 156static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 157{ 158 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 159 mdiobb); 160 161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 162} 163 164/* MDIO bus control struct */ 165static const struct mdiobb_ops bb_ops = { 166 .owner = THIS_MODULE, 167 .set_mdc = ravb_set_mdc, 168 .set_mdio_dir = ravb_set_mdio_dir, 169 .set_mdio_data = ravb_set_mdio_data, 170 .get_mdio_data = ravb_get_mdio_data, 171}; 172 173/* Free TX skb function for AVB-IP */ 174static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 175{ 176 struct ravb_private *priv = netdev_priv(ndev); 177 struct net_device_stats *stats = &priv->stats[q]; 178 int num_tx_desc = priv->num_tx_desc; 179 struct ravb_tx_desc *desc; 180 int free_num = 0; 181 int entry; 182 u32 size; 183 184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 185 bool txed; 186 187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 188 num_tx_desc); 189 desc = &priv->tx_ring[q][entry]; 190 txed = desc->die_dt == DT_FEMPTY; 191 if (free_txed_only && !txed) 192 break; 193 /* Descriptor type must be checked before all other reads */ 194 dma_rmb(); 195 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 196 /* Free the original skb. */ 197 if (priv->tx_skb[q][entry / num_tx_desc]) { 198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 199 size, DMA_TO_DEVICE); 200 /* Last packet descriptor? */ 201 if (entry % num_tx_desc == num_tx_desc - 1) { 202 entry /= num_tx_desc; 203 dev_kfree_skb_any(priv->tx_skb[q][entry]); 204 priv->tx_skb[q][entry] = NULL; 205 if (txed) 206 stats->tx_packets++; 207 } 208 free_num++; 209 } 210 if (txed) 211 stats->tx_bytes += size; 212 desc->die_dt = DT_EEMPTY; 213 } 214 return free_num; 215} 216 217/* Free skb's and DMA buffers for Ethernet AVB */ 218static void ravb_ring_free(struct net_device *ndev, int q) 219{ 220 struct ravb_private *priv = netdev_priv(ndev); 221 int num_tx_desc = priv->num_tx_desc; 222 int ring_size; 223 int i; 224 225 if (priv->rx_ring[q]) { 226 for (i = 0; i < priv->num_rx_ring[q]; i++) { 227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 228 229 if (!dma_mapping_error(ndev->dev.parent, 230 le32_to_cpu(desc->dptr))) 231 dma_unmap_single(ndev->dev.parent, 232 le32_to_cpu(desc->dptr), 233 RX_BUF_SZ, 234 DMA_FROM_DEVICE); 235 } 236 ring_size = sizeof(struct ravb_ex_rx_desc) * 237 (priv->num_rx_ring[q] + 1); 238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 239 priv->rx_desc_dma[q]); 240 priv->rx_ring[q] = NULL; 241 } 242 243 if (priv->tx_ring[q]) { 244 ravb_tx_free(ndev, q, false); 245 246 ring_size = sizeof(struct ravb_tx_desc) * 247 (priv->num_tx_ring[q] * num_tx_desc + 1); 248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 249 priv->tx_desc_dma[q]); 250 priv->tx_ring[q] = NULL; 251 } 252 253 /* Free RX skb ringbuffer */ 254 if (priv->rx_skb[q]) { 255 for (i = 0; i < priv->num_rx_ring[q]; i++) 256 dev_kfree_skb(priv->rx_skb[q][i]); 257 } 258 kfree(priv->rx_skb[q]); 259 priv->rx_skb[q] = NULL; 260 261 /* Free aligned TX buffers */ 262 kfree(priv->tx_align[q]); 263 priv->tx_align[q] = NULL; 264 265 /* Free TX skb ringbuffer. 266 * SKBs are freed by ravb_tx_free() call above. 267 */ 268 kfree(priv->tx_skb[q]); 269 priv->tx_skb[q] = NULL; 270} 271 272/* Format skb and descriptor buffer for Ethernet AVB */ 273static void ravb_ring_format(struct net_device *ndev, int q) 274{ 275 struct ravb_private *priv = netdev_priv(ndev); 276 int num_tx_desc = priv->num_tx_desc; 277 struct ravb_ex_rx_desc *rx_desc; 278 struct ravb_tx_desc *tx_desc; 279 struct ravb_desc *desc; 280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 282 num_tx_desc; 283 dma_addr_t dma_addr; 284 int i; 285 286 priv->cur_rx[q] = 0; 287 priv->cur_tx[q] = 0; 288 priv->dirty_rx[q] = 0; 289 priv->dirty_tx[q] = 0; 290 291 memset(priv->rx_ring[q], 0, rx_ring_size); 292 /* Build RX ring buffer */ 293 for (i = 0; i < priv->num_rx_ring[q]; i++) { 294 /* RX descriptor */ 295 rx_desc = &priv->rx_ring[q][i]; 296 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 298 RX_BUF_SZ, 299 DMA_FROM_DEVICE); 300 /* We just set the data size to 0 for a failed mapping which 301 * should prevent DMA from happening... 302 */ 303 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 304 rx_desc->ds_cc = cpu_to_le16(0); 305 rx_desc->dptr = cpu_to_le32(dma_addr); 306 rx_desc->die_dt = DT_FEMPTY; 307 } 308 rx_desc = &priv->rx_ring[q][i]; 309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 310 rx_desc->die_dt = DT_LINKFIX; /* type */ 311 312 memset(priv->tx_ring[q], 0, tx_ring_size); 313 /* Build TX ring buffer */ 314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 315 i++, tx_desc++) { 316 tx_desc->die_dt = DT_EEMPTY; 317 if (num_tx_desc > 1) { 318 tx_desc++; 319 tx_desc->die_dt = DT_EEMPTY; 320 } 321 } 322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 323 tx_desc->die_dt = DT_LINKFIX; /* type */ 324 325 /* RX descriptor base address for best effort */ 326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 327 desc->die_dt = DT_LINKFIX; /* type */ 328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 329 330 /* TX descriptor base address for best effort */ 331 desc = &priv->desc_bat[q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 334} 335 336/* Init skb and descriptor buffer for Ethernet AVB */ 337static int ravb_ring_init(struct net_device *ndev, int q) 338{ 339 struct ravb_private *priv = netdev_priv(ndev); 340 int num_tx_desc = priv->num_tx_desc; 341 struct sk_buff *skb; 342 int ring_size; 343 int i; 344 345 /* Allocate RX and TX skb rings */ 346 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 347 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 348 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 349 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 350 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 351 goto error; 352 353 for (i = 0; i < priv->num_rx_ring[q]; i++) { 354 skb = netdev_alloc_skb(ndev, RX_BUF_SZ + RAVB_ALIGN - 1); 355 if (!skb) 356 goto error; 357 ravb_set_buffer_align(skb); 358 priv->rx_skb[q][i] = skb; 359 } 360 361 if (num_tx_desc > 1) { 362 /* Allocate rings for the aligned buffers */ 363 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 364 DPTR_ALIGN - 1, GFP_KERNEL); 365 if (!priv->tx_align[q]) 366 goto error; 367 } 368 369 /* Allocate all RX descriptors. */ 370 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 371 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 372 &priv->rx_desc_dma[q], 373 GFP_KERNEL); 374 if (!priv->rx_ring[q]) 375 goto error; 376 377 priv->dirty_rx[q] = 0; 378 379 /* Allocate all TX descriptors. */ 380 ring_size = sizeof(struct ravb_tx_desc) * 381 (priv->num_tx_ring[q] * num_tx_desc + 1); 382 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 383 &priv->tx_desc_dma[q], 384 GFP_KERNEL); 385 if (!priv->tx_ring[q]) 386 goto error; 387 388 return 0; 389 390error: 391 ravb_ring_free(ndev, q); 392 393 return -ENOMEM; 394} 395 396/* E-MAC init function */ 397static void ravb_emac_init(struct net_device *ndev) 398{ 399 /* Receive frame limit set register */ 400 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 401 402 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 403 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 404 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 405 ECMR_TE | ECMR_RE, ECMR); 406 407 ravb_set_rate(ndev); 408 409 /* Set MAC address */ 410 ravb_write(ndev, 411 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 412 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 413 ravb_write(ndev, 414 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 415 416 /* E-MAC status register clear */ 417 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 418 419 /* E-MAC interrupt enable register */ 420 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 421} 422 423/* Device init function for Ethernet AVB */ 424static int ravb_dmac_init(struct net_device *ndev) 425{ 426 struct ravb_private *priv = netdev_priv(ndev); 427 int error; 428 429 /* Set CONFIG mode */ 430 error = ravb_config(ndev); 431 if (error) 432 return error; 433 434 error = ravb_ring_init(ndev, RAVB_BE); 435 if (error) 436 return error; 437 error = ravb_ring_init(ndev, RAVB_NC); 438 if (error) { 439 ravb_ring_free(ndev, RAVB_BE); 440 return error; 441 } 442 443 /* Descriptor format */ 444 ravb_ring_format(ndev, RAVB_BE); 445 ravb_ring_format(ndev, RAVB_NC); 446 447 /* Set AVB RX */ 448 ravb_write(ndev, 449 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 450 451 /* Set FIFO size */ 452 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 453 454 /* Timestamp enable */ 455 ravb_write(ndev, TCCR_TFEN, TCCR); 456 457 /* Interrupt init: */ 458 if (priv->chip_id == RCAR_GEN3) { 459 /* Clear DIL.DPLx */ 460 ravb_write(ndev, 0, DIL); 461 /* Set queue specific interrupt */ 462 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 463 } 464 /* Frame receive */ 465 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 466 /* Disable FIFO full warning */ 467 ravb_write(ndev, 0, RIC1); 468 /* Receive FIFO full error, descriptor empty */ 469 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 470 /* Frame transmitted, timestamp FIFO updated */ 471 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 472 473 /* Setting the control will start the AVB-DMAC process. */ 474 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 475 476 return 0; 477} 478 479static void ravb_get_tx_tstamp(struct net_device *ndev) 480{ 481 struct ravb_private *priv = netdev_priv(ndev); 482 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 483 struct skb_shared_hwtstamps shhwtstamps; 484 struct sk_buff *skb; 485 struct timespec64 ts; 486 u16 tag, tfa_tag; 487 int count; 488 u32 tfa2; 489 490 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 491 while (count--) { 492 tfa2 = ravb_read(ndev, TFA2); 493 tfa_tag = (tfa2 & TFA2_TST) >> 16; 494 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 495 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 496 ravb_read(ndev, TFA1); 497 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 498 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 499 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 500 list) { 501 skb = ts_skb->skb; 502 tag = ts_skb->tag; 503 list_del(&ts_skb->list); 504 kfree(ts_skb); 505 if (tag == tfa_tag) { 506 skb_tstamp_tx(skb, &shhwtstamps); 507 dev_consume_skb_any(skb); 508 break; 509 } else { 510 dev_kfree_skb_any(skb); 511 } 512 } 513 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 514 } 515} 516 517static void ravb_rx_csum(struct sk_buff *skb) 518{ 519 u8 *hw_csum; 520 521 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 522 * appended to packet data 523 */ 524 if (unlikely(skb->len < sizeof(__sum16))) 525 return; 526 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 527 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 528 skb->ip_summed = CHECKSUM_COMPLETE; 529 skb_trim(skb, skb->len - sizeof(__sum16)); 530} 531 532/* Packet receive function for Ethernet AVB */ 533static bool ravb_rx(struct net_device *ndev, int *quota, int q) 534{ 535 struct ravb_private *priv = netdev_priv(ndev); 536 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 537 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 538 priv->cur_rx[q]; 539 struct net_device_stats *stats = &priv->stats[q]; 540 struct ravb_ex_rx_desc *desc; 541 struct sk_buff *skb; 542 dma_addr_t dma_addr; 543 struct timespec64 ts; 544 u8 desc_status; 545 u16 pkt_len; 546 int limit; 547 548 boguscnt = min(boguscnt, *quota); 549 limit = boguscnt; 550 desc = &priv->rx_ring[q][entry]; 551 while (desc->die_dt != DT_FEMPTY) { 552 /* Descriptor type must be checked before all other reads */ 553 dma_rmb(); 554 desc_status = desc->msc; 555 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 556 557 if (--boguscnt < 0) 558 break; 559 560 /* We use 0-byte descriptors to mark the DMA mapping errors */ 561 if (!pkt_len) 562 continue; 563 564 if (desc_status & MSC_MC) 565 stats->multicast++; 566 567 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 568 MSC_CEEF)) { 569 stats->rx_errors++; 570 if (desc_status & MSC_CRC) 571 stats->rx_crc_errors++; 572 if (desc_status & MSC_RFE) 573 stats->rx_frame_errors++; 574 if (desc_status & (MSC_RTLF | MSC_RTSF)) 575 stats->rx_length_errors++; 576 if (desc_status & MSC_CEEF) 577 stats->rx_missed_errors++; 578 } else { 579 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 580 581 skb = priv->rx_skb[q][entry]; 582 priv->rx_skb[q][entry] = NULL; 583 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 584 RX_BUF_SZ, 585 DMA_FROM_DEVICE); 586 get_ts &= (q == RAVB_NC) ? 587 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 588 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 589 if (get_ts) { 590 struct skb_shared_hwtstamps *shhwtstamps; 591 592 shhwtstamps = skb_hwtstamps(skb); 593 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 594 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 595 32) | le32_to_cpu(desc->ts_sl); 596 ts.tv_nsec = le32_to_cpu(desc->ts_n); 597 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 598 } 599 600 skb_put(skb, pkt_len); 601 skb->protocol = eth_type_trans(skb, ndev); 602 if (ndev->features & NETIF_F_RXCSUM) 603 ravb_rx_csum(skb); 604 napi_gro_receive(&priv->napi[q], skb); 605 stats->rx_packets++; 606 stats->rx_bytes += pkt_len; 607 } 608 609 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 610 desc = &priv->rx_ring[q][entry]; 611 } 612 613 /* Refill the RX ring buffers. */ 614 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 615 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 616 desc = &priv->rx_ring[q][entry]; 617 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 618 619 if (!priv->rx_skb[q][entry]) { 620 skb = netdev_alloc_skb(ndev, 621 RX_BUF_SZ + 622 RAVB_ALIGN - 1); 623 if (!skb) 624 break; /* Better luck next round. */ 625 ravb_set_buffer_align(skb); 626 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 627 le16_to_cpu(desc->ds_cc), 628 DMA_FROM_DEVICE); 629 skb_checksum_none_assert(skb); 630 /* We just set the data size to 0 for a failed mapping 631 * which should prevent DMA from happening... 632 */ 633 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 634 desc->ds_cc = cpu_to_le16(0); 635 desc->dptr = cpu_to_le32(dma_addr); 636 priv->rx_skb[q][entry] = skb; 637 } 638 /* Descriptor type must be set after all the above writes */ 639 dma_wmb(); 640 desc->die_dt = DT_FEMPTY; 641 } 642 643 *quota -= limit - (++boguscnt); 644 645 return boguscnt <= 0; 646} 647 648static void ravb_rcv_snd_disable(struct net_device *ndev) 649{ 650 /* Disable TX and RX */ 651 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 652} 653 654static void ravb_rcv_snd_enable(struct net_device *ndev) 655{ 656 /* Enable TX and RX */ 657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 658} 659 660/* function for waiting dma process finished */ 661static int ravb_stop_dma(struct net_device *ndev) 662{ 663 int error; 664 665 /* Wait for stopping the hardware TX process */ 666 error = ravb_wait(ndev, TCCR, 667 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 668 if (error) 669 return error; 670 671 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 672 0); 673 if (error) 674 return error; 675 676 /* Stop the E-MAC's RX/TX processes. */ 677 ravb_rcv_snd_disable(ndev); 678 679 /* Wait for stopping the RX DMA process */ 680 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 681 if (error) 682 return error; 683 684 /* Stop AVB-DMAC process */ 685 return ravb_config(ndev); 686} 687 688/* E-MAC interrupt handler */ 689static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 690{ 691 struct ravb_private *priv = netdev_priv(ndev); 692 u32 ecsr, psr; 693 694 ecsr = ravb_read(ndev, ECSR); 695 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 696 697 if (ecsr & ECSR_MPD) 698 pm_wakeup_event(&priv->pdev->dev, 0); 699 if (ecsr & ECSR_ICD) 700 ndev->stats.tx_carrier_errors++; 701 if (ecsr & ECSR_LCHNG) { 702 /* Link changed */ 703 if (priv->no_avb_link) 704 return; 705 psr = ravb_read(ndev, PSR); 706 if (priv->avb_link_active_low) 707 psr ^= PSR_LMON; 708 if (!(psr & PSR_LMON)) { 709 /* DIsable RX and TX */ 710 ravb_rcv_snd_disable(ndev); 711 } else { 712 /* Enable RX and TX */ 713 ravb_rcv_snd_enable(ndev); 714 } 715 } 716} 717 718static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 719{ 720 struct net_device *ndev = dev_id; 721 struct ravb_private *priv = netdev_priv(ndev); 722 723 spin_lock(&priv->lock); 724 ravb_emac_interrupt_unlocked(ndev); 725 spin_unlock(&priv->lock); 726 return IRQ_HANDLED; 727} 728 729/* Error interrupt handler */ 730static void ravb_error_interrupt(struct net_device *ndev) 731{ 732 struct ravb_private *priv = netdev_priv(ndev); 733 u32 eis, ris2; 734 735 eis = ravb_read(ndev, EIS); 736 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 737 if (eis & EIS_QFS) { 738 ris2 = ravb_read(ndev, RIS2); 739 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 740 RIS2); 741 742 /* Receive Descriptor Empty int */ 743 if (ris2 & RIS2_QFF0) 744 priv->stats[RAVB_BE].rx_over_errors++; 745 746 /* Receive Descriptor Empty int */ 747 if (ris2 & RIS2_QFF1) 748 priv->stats[RAVB_NC].rx_over_errors++; 749 750 /* Receive FIFO Overflow int */ 751 if (ris2 & RIS2_RFFF) 752 priv->rx_fifo_errors++; 753 } 754} 755 756static bool ravb_queue_interrupt(struct net_device *ndev, int q) 757{ 758 struct ravb_private *priv = netdev_priv(ndev); 759 u32 ris0 = ravb_read(ndev, RIS0); 760 u32 ric0 = ravb_read(ndev, RIC0); 761 u32 tis = ravb_read(ndev, TIS); 762 u32 tic = ravb_read(ndev, TIC); 763 764 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 765 if (napi_schedule_prep(&priv->napi[q])) { 766 /* Mask RX and TX interrupts */ 767 if (priv->chip_id == RCAR_GEN2) { 768 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 769 ravb_write(ndev, tic & ~BIT(q), TIC); 770 } else { 771 ravb_write(ndev, BIT(q), RID0); 772 ravb_write(ndev, BIT(q), TID); 773 } 774 __napi_schedule(&priv->napi[q]); 775 } else { 776 netdev_warn(ndev, 777 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 778 ris0, ric0); 779 netdev_warn(ndev, 780 " tx status 0x%08x, tx mask 0x%08x.\n", 781 tis, tic); 782 } 783 return true; 784 } 785 return false; 786} 787 788static bool ravb_timestamp_interrupt(struct net_device *ndev) 789{ 790 u32 tis = ravb_read(ndev, TIS); 791 792 if (tis & TIS_TFUF) { 793 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 794 ravb_get_tx_tstamp(ndev); 795 return true; 796 } 797 return false; 798} 799 800static irqreturn_t ravb_interrupt(int irq, void *dev_id) 801{ 802 struct net_device *ndev = dev_id; 803 struct ravb_private *priv = netdev_priv(ndev); 804 irqreturn_t result = IRQ_NONE; 805 u32 iss; 806 807 spin_lock(&priv->lock); 808 /* Get interrupt status */ 809 iss = ravb_read(ndev, ISS); 810 811 /* Received and transmitted interrupts */ 812 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 813 int q; 814 815 /* Timestamp updated */ 816 if (ravb_timestamp_interrupt(ndev)) 817 result = IRQ_HANDLED; 818 819 /* Network control and best effort queue RX/TX */ 820 for (q = RAVB_NC; q >= RAVB_BE; q--) { 821 if (ravb_queue_interrupt(ndev, q)) 822 result = IRQ_HANDLED; 823 } 824 } 825 826 /* E-MAC status summary */ 827 if (iss & ISS_MS) { 828 ravb_emac_interrupt_unlocked(ndev); 829 result = IRQ_HANDLED; 830 } 831 832 /* Error status summary */ 833 if (iss & ISS_ES) { 834 ravb_error_interrupt(ndev); 835 result = IRQ_HANDLED; 836 } 837 838 /* gPTP interrupt status summary */ 839 if (iss & ISS_CGIS) { 840 ravb_ptp_interrupt(ndev); 841 result = IRQ_HANDLED; 842 } 843 844 spin_unlock(&priv->lock); 845 return result; 846} 847 848/* Timestamp/Error/gPTP interrupt handler */ 849static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 850{ 851 struct net_device *ndev = dev_id; 852 struct ravb_private *priv = netdev_priv(ndev); 853 irqreturn_t result = IRQ_NONE; 854 u32 iss; 855 856 spin_lock(&priv->lock); 857 /* Get interrupt status */ 858 iss = ravb_read(ndev, ISS); 859 860 /* Timestamp updated */ 861 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 862 result = IRQ_HANDLED; 863 864 /* Error status summary */ 865 if (iss & ISS_ES) { 866 ravb_error_interrupt(ndev); 867 result = IRQ_HANDLED; 868 } 869 870 /* gPTP interrupt status summary */ 871 if (iss & ISS_CGIS) { 872 ravb_ptp_interrupt(ndev); 873 result = IRQ_HANDLED; 874 } 875 876 spin_unlock(&priv->lock); 877 return result; 878} 879 880static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 881{ 882 struct net_device *ndev = dev_id; 883 struct ravb_private *priv = netdev_priv(ndev); 884 irqreturn_t result = IRQ_NONE; 885 886 spin_lock(&priv->lock); 887 888 /* Network control/Best effort queue RX/TX */ 889 if (ravb_queue_interrupt(ndev, q)) 890 result = IRQ_HANDLED; 891 892 spin_unlock(&priv->lock); 893 return result; 894} 895 896static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 897{ 898 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 899} 900 901static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 902{ 903 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 904} 905 906static int ravb_poll(struct napi_struct *napi, int budget) 907{ 908 struct net_device *ndev = napi->dev; 909 struct ravb_private *priv = netdev_priv(ndev); 910 unsigned long flags; 911 int q = napi - priv->napi; 912 int mask = BIT(q); 913 int quota = budget; 914 915 /* Processing RX Descriptor Ring */ 916 /* Clear RX interrupt */ 917 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 918 if (ravb_rx(ndev, "a, q)) 919 goto out; 920 921 /* Processing RX Descriptor Ring */ 922 spin_lock_irqsave(&priv->lock, flags); 923 /* Clear TX interrupt */ 924 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 925 ravb_tx_free(ndev, q, true); 926 netif_wake_subqueue(ndev, q); 927 spin_unlock_irqrestore(&priv->lock, flags); 928 929 napi_complete(napi); 930 931 /* Re-enable RX/TX interrupts */ 932 spin_lock_irqsave(&priv->lock, flags); 933 if (priv->chip_id == RCAR_GEN2) { 934 ravb_modify(ndev, RIC0, mask, mask); 935 ravb_modify(ndev, TIC, mask, mask); 936 } else { 937 ravb_write(ndev, mask, RIE0); 938 ravb_write(ndev, mask, TIE); 939 } 940 spin_unlock_irqrestore(&priv->lock, flags); 941 942 /* Receive error message handling */ 943 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 944 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 945 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 946 ndev->stats.rx_over_errors = priv->rx_over_errors; 947 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 948 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 949out: 950 return budget - quota; 951} 952 953/* PHY state control function */ 954static void ravb_adjust_link(struct net_device *ndev) 955{ 956 struct ravb_private *priv = netdev_priv(ndev); 957 struct phy_device *phydev = ndev->phydev; 958 bool new_state = false; 959 unsigned long flags; 960 961 spin_lock_irqsave(&priv->lock, flags); 962 963 /* Disable TX and RX right over here, if E-MAC change is ignored */ 964 if (priv->no_avb_link) 965 ravb_rcv_snd_disable(ndev); 966 967 if (phydev->link) { 968 if (phydev->speed != priv->speed) { 969 new_state = true; 970 priv->speed = phydev->speed; 971 ravb_set_rate(ndev); 972 } 973 if (!priv->link) { 974 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 975 new_state = true; 976 priv->link = phydev->link; 977 } 978 } else if (priv->link) { 979 new_state = true; 980 priv->link = 0; 981 priv->speed = 0; 982 } 983 984 /* Enable TX and RX right over here, if E-MAC change is ignored */ 985 if (priv->no_avb_link && phydev->link) 986 ravb_rcv_snd_enable(ndev); 987 988 spin_unlock_irqrestore(&priv->lock, flags); 989 990 if (new_state && netif_msg_link(priv)) 991 phy_print_status(phydev); 992} 993 994static const struct soc_device_attribute r8a7795es10[] = { 995 { .soc_id = "r8a7795", .revision = "ES1.0", }, 996 { /* sentinel */ } 997}; 998 999/* PHY init function */ 1000static int ravb_phy_init(struct net_device *ndev) 1001{ 1002 struct device_node *np = ndev->dev.parent->of_node; 1003 struct ravb_private *priv = netdev_priv(ndev); 1004 struct phy_device *phydev; 1005 struct device_node *pn; 1006 phy_interface_t iface; 1007 int err; 1008 1009 priv->link = 0; 1010 priv->speed = 0; 1011 1012 /* Try connecting to PHY */ 1013 pn = of_parse_phandle(np, "phy-handle", 0); 1014 if (!pn) { 1015 /* In the case of a fixed PHY, the DT node associated 1016 * to the PHY is the Ethernet MAC DT node. 1017 */ 1018 if (of_phy_is_fixed_link(np)) { 1019 err = of_phy_register_fixed_link(np); 1020 if (err) 1021 return err; 1022 } 1023 pn = of_node_get(np); 1024 } 1025 1026 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1027 : priv->phy_interface; 1028 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1029 of_node_put(pn); 1030 if (!phydev) { 1031 netdev_err(ndev, "failed to connect PHY\n"); 1032 err = -ENOENT; 1033 goto err_deregister_fixed_link; 1034 } 1035 1036 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1037 * at this time. 1038 */ 1039 if (soc_device_match(r8a7795es10)) { 1040 err = phy_set_max_speed(phydev, SPEED_100); 1041 if (err) { 1042 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1043 goto err_phy_disconnect; 1044 } 1045 1046 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1047 } 1048 1049 /* 10BASE, Pause and Asym Pause is not supported */ 1050 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1051 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1052 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1053 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1054 1055 /* Half Duplex is not supported */ 1056 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1057 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1058 1059 phy_attached_info(phydev); 1060 1061 return 0; 1062 1063err_phy_disconnect: 1064 phy_disconnect(phydev); 1065err_deregister_fixed_link: 1066 if (of_phy_is_fixed_link(np)) 1067 of_phy_deregister_fixed_link(np); 1068 1069 return err; 1070} 1071 1072/* PHY control start function */ 1073static int ravb_phy_start(struct net_device *ndev) 1074{ 1075 int error; 1076 1077 error = ravb_phy_init(ndev); 1078 if (error) 1079 return error; 1080 1081 phy_start(ndev->phydev); 1082 1083 return 0; 1084} 1085 1086static u32 ravb_get_msglevel(struct net_device *ndev) 1087{ 1088 struct ravb_private *priv = netdev_priv(ndev); 1089 1090 return priv->msg_enable; 1091} 1092 1093static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1094{ 1095 struct ravb_private *priv = netdev_priv(ndev); 1096 1097 priv->msg_enable = value; 1098} 1099 1100static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1101 "rx_queue_0_current", 1102 "tx_queue_0_current", 1103 "rx_queue_0_dirty", 1104 "tx_queue_0_dirty", 1105 "rx_queue_0_packets", 1106 "tx_queue_0_packets", 1107 "rx_queue_0_bytes", 1108 "tx_queue_0_bytes", 1109 "rx_queue_0_mcast_packets", 1110 "rx_queue_0_errors", 1111 "rx_queue_0_crc_errors", 1112 "rx_queue_0_frame_errors", 1113 "rx_queue_0_length_errors", 1114 "rx_queue_0_missed_errors", 1115 "rx_queue_0_over_errors", 1116 1117 "rx_queue_1_current", 1118 "tx_queue_1_current", 1119 "rx_queue_1_dirty", 1120 "tx_queue_1_dirty", 1121 "rx_queue_1_packets", 1122 "tx_queue_1_packets", 1123 "rx_queue_1_bytes", 1124 "tx_queue_1_bytes", 1125 "rx_queue_1_mcast_packets", 1126 "rx_queue_1_errors", 1127 "rx_queue_1_crc_errors", 1128 "rx_queue_1_frame_errors", 1129 "rx_queue_1_length_errors", 1130 "rx_queue_1_missed_errors", 1131 "rx_queue_1_over_errors", 1132}; 1133 1134#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1135 1136static int ravb_get_sset_count(struct net_device *netdev, int sset) 1137{ 1138 switch (sset) { 1139 case ETH_SS_STATS: 1140 return RAVB_STATS_LEN; 1141 default: 1142 return -EOPNOTSUPP; 1143 } 1144} 1145 1146static void ravb_get_ethtool_stats(struct net_device *ndev, 1147 struct ethtool_stats *estats, u64 *data) 1148{ 1149 struct ravb_private *priv = netdev_priv(ndev); 1150 int i = 0; 1151 int q; 1152 1153 /* Device-specific stats */ 1154 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1155 struct net_device_stats *stats = &priv->stats[q]; 1156 1157 data[i++] = priv->cur_rx[q]; 1158 data[i++] = priv->cur_tx[q]; 1159 data[i++] = priv->dirty_rx[q]; 1160 data[i++] = priv->dirty_tx[q]; 1161 data[i++] = stats->rx_packets; 1162 data[i++] = stats->tx_packets; 1163 data[i++] = stats->rx_bytes; 1164 data[i++] = stats->tx_bytes; 1165 data[i++] = stats->multicast; 1166 data[i++] = stats->rx_errors; 1167 data[i++] = stats->rx_crc_errors; 1168 data[i++] = stats->rx_frame_errors; 1169 data[i++] = stats->rx_length_errors; 1170 data[i++] = stats->rx_missed_errors; 1171 data[i++] = stats->rx_over_errors; 1172 } 1173} 1174 1175static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1176{ 1177 switch (stringset) { 1178 case ETH_SS_STATS: 1179 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1180 break; 1181 } 1182} 1183 1184static void ravb_get_ringparam(struct net_device *ndev, 1185 struct ethtool_ringparam *ring) 1186{ 1187 struct ravb_private *priv = netdev_priv(ndev); 1188 1189 ring->rx_max_pending = BE_RX_RING_MAX; 1190 ring->tx_max_pending = BE_TX_RING_MAX; 1191 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1192 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1193} 1194 1195static int ravb_set_ringparam(struct net_device *ndev, 1196 struct ethtool_ringparam *ring) 1197{ 1198 struct ravb_private *priv = netdev_priv(ndev); 1199 int error; 1200 1201 if (ring->tx_pending > BE_TX_RING_MAX || 1202 ring->rx_pending > BE_RX_RING_MAX || 1203 ring->tx_pending < BE_TX_RING_MIN || 1204 ring->rx_pending < BE_RX_RING_MIN) 1205 return -EINVAL; 1206 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1207 return -EINVAL; 1208 1209 if (netif_running(ndev)) { 1210 netif_device_detach(ndev); 1211 /* Stop PTP Clock driver */ 1212 if (priv->chip_id == RCAR_GEN2) 1213 ravb_ptp_stop(ndev); 1214 /* Wait for DMA stopping */ 1215 error = ravb_stop_dma(ndev); 1216 if (error) { 1217 netdev_err(ndev, 1218 "cannot set ringparam! Any AVB processes are still running?\n"); 1219 return error; 1220 } 1221 synchronize_irq(ndev->irq); 1222 1223 /* Free all the skb's in the RX queue and the DMA buffers. */ 1224 ravb_ring_free(ndev, RAVB_BE); 1225 ravb_ring_free(ndev, RAVB_NC); 1226 } 1227 1228 /* Set new parameters */ 1229 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1230 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1231 1232 if (netif_running(ndev)) { 1233 error = ravb_dmac_init(ndev); 1234 if (error) { 1235 netdev_err(ndev, 1236 "%s: ravb_dmac_init() failed, error %d\n", 1237 __func__, error); 1238 return error; 1239 } 1240 1241 ravb_emac_init(ndev); 1242 1243 /* Initialise PTP Clock driver */ 1244 if (priv->chip_id == RCAR_GEN2) 1245 ravb_ptp_init(ndev, priv->pdev); 1246 1247 netif_device_attach(ndev); 1248 } 1249 1250 return 0; 1251} 1252 1253static int ravb_get_ts_info(struct net_device *ndev, 1254 struct ethtool_ts_info *info) 1255{ 1256 struct ravb_private *priv = netdev_priv(ndev); 1257 1258 info->so_timestamping = 1259 SOF_TIMESTAMPING_TX_SOFTWARE | 1260 SOF_TIMESTAMPING_RX_SOFTWARE | 1261 SOF_TIMESTAMPING_SOFTWARE | 1262 SOF_TIMESTAMPING_TX_HARDWARE | 1263 SOF_TIMESTAMPING_RX_HARDWARE | 1264 SOF_TIMESTAMPING_RAW_HARDWARE; 1265 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1266 info->rx_filters = 1267 (1 << HWTSTAMP_FILTER_NONE) | 1268 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1269 (1 << HWTSTAMP_FILTER_ALL); 1270 info->phc_index = ptp_clock_index(priv->ptp.clock); 1271 1272 return 0; 1273} 1274 1275static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1276{ 1277 struct ravb_private *priv = netdev_priv(ndev); 1278 1279 wol->supported = WAKE_MAGIC; 1280 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1281} 1282 1283static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1284{ 1285 struct ravb_private *priv = netdev_priv(ndev); 1286 1287 if (wol->wolopts & ~WAKE_MAGIC) 1288 return -EOPNOTSUPP; 1289 1290 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1291 1292 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1293 1294 return 0; 1295} 1296 1297static const struct ethtool_ops ravb_ethtool_ops = { 1298 .nway_reset = phy_ethtool_nway_reset, 1299 .get_msglevel = ravb_get_msglevel, 1300 .set_msglevel = ravb_set_msglevel, 1301 .get_link = ethtool_op_get_link, 1302 .get_strings = ravb_get_strings, 1303 .get_ethtool_stats = ravb_get_ethtool_stats, 1304 .get_sset_count = ravb_get_sset_count, 1305 .get_ringparam = ravb_get_ringparam, 1306 .set_ringparam = ravb_set_ringparam, 1307 .get_ts_info = ravb_get_ts_info, 1308 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1309 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1310 .get_wol = ravb_get_wol, 1311 .set_wol = ravb_set_wol, 1312}; 1313 1314static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1315 struct net_device *ndev, struct device *dev, 1316 const char *ch) 1317{ 1318 char *name; 1319 int error; 1320 1321 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1322 if (!name) 1323 return -ENOMEM; 1324 error = request_irq(irq, handler, 0, name, ndev); 1325 if (error) 1326 netdev_err(ndev, "cannot request IRQ %s\n", name); 1327 1328 return error; 1329} 1330 1331/* Network device open function for Ethernet AVB */ 1332static int ravb_open(struct net_device *ndev) 1333{ 1334 struct ravb_private *priv = netdev_priv(ndev); 1335 struct platform_device *pdev = priv->pdev; 1336 struct device *dev = &pdev->dev; 1337 int error; 1338 1339 napi_enable(&priv->napi[RAVB_BE]); 1340 napi_enable(&priv->napi[RAVB_NC]); 1341 1342 if (priv->chip_id == RCAR_GEN2) { 1343 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1344 ndev->name, ndev); 1345 if (error) { 1346 netdev_err(ndev, "cannot request IRQ\n"); 1347 goto out_napi_off; 1348 } 1349 } else { 1350 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1351 dev, "ch22:multi"); 1352 if (error) 1353 goto out_napi_off; 1354 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1355 dev, "ch24:emac"); 1356 if (error) 1357 goto out_free_irq; 1358 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1359 ndev, dev, "ch0:rx_be"); 1360 if (error) 1361 goto out_free_irq_emac; 1362 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1363 ndev, dev, "ch18:tx_be"); 1364 if (error) 1365 goto out_free_irq_be_rx; 1366 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1367 ndev, dev, "ch1:rx_nc"); 1368 if (error) 1369 goto out_free_irq_be_tx; 1370 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1371 ndev, dev, "ch19:tx_nc"); 1372 if (error) 1373 goto out_free_irq_nc_rx; 1374 } 1375 1376 /* Device init */ 1377 error = ravb_dmac_init(ndev); 1378 if (error) 1379 goto out_free_irq_nc_tx; 1380 ravb_emac_init(ndev); 1381 1382 /* Initialise PTP Clock driver */ 1383 if (priv->chip_id == RCAR_GEN2) 1384 ravb_ptp_init(ndev, priv->pdev); 1385 1386 /* PHY control start */ 1387 error = ravb_phy_start(ndev); 1388 if (error) 1389 goto out_ptp_stop; 1390 1391 netif_tx_start_all_queues(ndev); 1392 1393 return 0; 1394 1395out_ptp_stop: 1396 /* Stop PTP Clock driver */ 1397 if (priv->chip_id == RCAR_GEN2) 1398 ravb_ptp_stop(ndev); 1399out_free_irq_nc_tx: 1400 if (priv->chip_id == RCAR_GEN2) 1401 goto out_free_irq; 1402 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1403out_free_irq_nc_rx: 1404 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1405out_free_irq_be_tx: 1406 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1407out_free_irq_be_rx: 1408 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1409out_free_irq_emac: 1410 free_irq(priv->emac_irq, ndev); 1411out_free_irq: 1412 free_irq(ndev->irq, ndev); 1413out_napi_off: 1414 napi_disable(&priv->napi[RAVB_NC]); 1415 napi_disable(&priv->napi[RAVB_BE]); 1416 return error; 1417} 1418 1419/* Timeout function for Ethernet AVB */ 1420static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1421{ 1422 struct ravb_private *priv = netdev_priv(ndev); 1423 1424 netif_err(priv, tx_err, ndev, 1425 "transmit timed out, status %08x, resetting...\n", 1426 ravb_read(ndev, ISS)); 1427 1428 /* tx_errors count up */ 1429 ndev->stats.tx_errors++; 1430 1431 schedule_work(&priv->work); 1432} 1433 1434static void ravb_tx_timeout_work(struct work_struct *work) 1435{ 1436 struct ravb_private *priv = container_of(work, struct ravb_private, 1437 work); 1438 struct net_device *ndev = priv->ndev; 1439 int error; 1440 1441 if (!rtnl_trylock()) { 1442 usleep_range(1000, 2000); 1443 schedule_work(&priv->work); 1444 return; 1445 } 1446 1447 netif_tx_stop_all_queues(ndev); 1448 1449 /* Stop PTP Clock driver */ 1450 if (priv->chip_id == RCAR_GEN2) 1451 ravb_ptp_stop(ndev); 1452 1453 /* Wait for DMA stopping */ 1454 if (ravb_stop_dma(ndev)) { 1455 /* If ravb_stop_dma() fails, the hardware is still operating 1456 * for TX and/or RX. So, this should not call the following 1457 * functions because ravb_dmac_init() is possible to fail too. 1458 * Also, this should not retry ravb_stop_dma() again and again 1459 * here because it's possible to wait forever. So, this just 1460 * re-enables the TX and RX and skip the following 1461 * re-initialization procedure. 1462 */ 1463 ravb_rcv_snd_enable(ndev); 1464 goto out; 1465 } 1466 1467 ravb_ring_free(ndev, RAVB_BE); 1468 ravb_ring_free(ndev, RAVB_NC); 1469 1470 /* Device init */ 1471 error = ravb_dmac_init(ndev); 1472 if (error) { 1473 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1474 * should return here to avoid re-enabling the TX and RX in 1475 * ravb_emac_init(). 1476 */ 1477 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1478 __func__, error); 1479 goto out_unlock; 1480 } 1481 ravb_emac_init(ndev); 1482 1483out: 1484 /* Initialise PTP Clock driver */ 1485 if (priv->chip_id == RCAR_GEN2) 1486 ravb_ptp_init(ndev, priv->pdev); 1487 1488 netif_tx_start_all_queues(ndev); 1489 1490out_unlock: 1491 rtnl_unlock(); 1492} 1493 1494/* Packet transmit function for Ethernet AVB */ 1495static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1496{ 1497 struct ravb_private *priv = netdev_priv(ndev); 1498 int num_tx_desc = priv->num_tx_desc; 1499 u16 q = skb_get_queue_mapping(skb); 1500 struct ravb_tstamp_skb *ts_skb; 1501 struct ravb_tx_desc *desc; 1502 unsigned long flags; 1503 dma_addr_t dma_addr; 1504 void *buffer; 1505 u32 entry; 1506 u32 len; 1507 1508 spin_lock_irqsave(&priv->lock, flags); 1509 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1510 num_tx_desc) { 1511 netif_err(priv, tx_queued, ndev, 1512 "still transmitting with the full ring!\n"); 1513 netif_stop_subqueue(ndev, q); 1514 spin_unlock_irqrestore(&priv->lock, flags); 1515 return NETDEV_TX_BUSY; 1516 } 1517 1518 if (skb_put_padto(skb, ETH_ZLEN)) 1519 goto exit; 1520 1521 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1522 priv->tx_skb[q][entry / num_tx_desc] = skb; 1523 1524 if (num_tx_desc > 1) { 1525 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1526 entry / num_tx_desc * DPTR_ALIGN; 1527 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1528 1529 /* Zero length DMA descriptors are problematic as they seem 1530 * to terminate DMA transfers. Avoid them by simply using a 1531 * length of DPTR_ALIGN (4) when skb data is aligned to 1532 * DPTR_ALIGN. 1533 * 1534 * As skb is guaranteed to have at least ETH_ZLEN (60) 1535 * bytes of data by the call to skb_put_padto() above this 1536 * is safe with respect to both the length of the first DMA 1537 * descriptor (len) overflowing the available data and the 1538 * length of the second DMA descriptor (skb->len - len) 1539 * being negative. 1540 */ 1541 if (len == 0) 1542 len = DPTR_ALIGN; 1543 1544 memcpy(buffer, skb->data, len); 1545 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1546 DMA_TO_DEVICE); 1547 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1548 goto drop; 1549 1550 desc = &priv->tx_ring[q][entry]; 1551 desc->ds_tagl = cpu_to_le16(len); 1552 desc->dptr = cpu_to_le32(dma_addr); 1553 1554 buffer = skb->data + len; 1555 len = skb->len - len; 1556 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1557 DMA_TO_DEVICE); 1558 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1559 goto unmap; 1560 1561 desc++; 1562 } else { 1563 desc = &priv->tx_ring[q][entry]; 1564 len = skb->len; 1565 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1566 DMA_TO_DEVICE); 1567 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1568 goto drop; 1569 } 1570 desc->ds_tagl = cpu_to_le16(len); 1571 desc->dptr = cpu_to_le32(dma_addr); 1572 1573 /* TX timestamp required */ 1574 if (q == RAVB_NC) { 1575 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1576 if (!ts_skb) { 1577 if (num_tx_desc > 1) { 1578 desc--; 1579 dma_unmap_single(ndev->dev.parent, dma_addr, 1580 len, DMA_TO_DEVICE); 1581 } 1582 goto unmap; 1583 } 1584 ts_skb->skb = skb_get(skb); 1585 ts_skb->tag = priv->ts_skb_tag++; 1586 priv->ts_skb_tag &= 0x3ff; 1587 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1588 1589 /* TAG and timestamp required flag */ 1590 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1591 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1592 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1593 } 1594 1595 skb_tx_timestamp(skb); 1596 /* Descriptor type must be set after all the above writes */ 1597 dma_wmb(); 1598 if (num_tx_desc > 1) { 1599 desc->die_dt = DT_FEND; 1600 desc--; 1601 desc->die_dt = DT_FSTART; 1602 } else { 1603 desc->die_dt = DT_FSINGLE; 1604 } 1605 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1606 1607 priv->cur_tx[q] += num_tx_desc; 1608 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1609 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1610 !ravb_tx_free(ndev, q, true)) 1611 netif_stop_subqueue(ndev, q); 1612 1613exit: 1614 spin_unlock_irqrestore(&priv->lock, flags); 1615 return NETDEV_TX_OK; 1616 1617unmap: 1618 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1619 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1620drop: 1621 dev_kfree_skb_any(skb); 1622 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1623 goto exit; 1624} 1625 1626static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1627 struct net_device *sb_dev) 1628{ 1629 /* If skb needs TX timestamp, it is handled in network control queue */ 1630 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1631 RAVB_BE; 1632 1633} 1634 1635static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1636{ 1637 struct ravb_private *priv = netdev_priv(ndev); 1638 struct net_device_stats *nstats, *stats0, *stats1; 1639 1640 nstats = &ndev->stats; 1641 stats0 = &priv->stats[RAVB_BE]; 1642 stats1 = &priv->stats[RAVB_NC]; 1643 1644 if (priv->chip_id == RCAR_GEN3) { 1645 nstats->tx_dropped += ravb_read(ndev, TROCR); 1646 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1647 } 1648 1649 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1650 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1651 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1652 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1653 nstats->multicast = stats0->multicast + stats1->multicast; 1654 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1655 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1656 nstats->rx_frame_errors = 1657 stats0->rx_frame_errors + stats1->rx_frame_errors; 1658 nstats->rx_length_errors = 1659 stats0->rx_length_errors + stats1->rx_length_errors; 1660 nstats->rx_missed_errors = 1661 stats0->rx_missed_errors + stats1->rx_missed_errors; 1662 nstats->rx_over_errors = 1663 stats0->rx_over_errors + stats1->rx_over_errors; 1664 1665 return nstats; 1666} 1667 1668/* Update promiscuous bit */ 1669static void ravb_set_rx_mode(struct net_device *ndev) 1670{ 1671 struct ravb_private *priv = netdev_priv(ndev); 1672 unsigned long flags; 1673 1674 spin_lock_irqsave(&priv->lock, flags); 1675 ravb_modify(ndev, ECMR, ECMR_PRM, 1676 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1677 spin_unlock_irqrestore(&priv->lock, flags); 1678} 1679 1680/* Device close function for Ethernet AVB */ 1681static int ravb_close(struct net_device *ndev) 1682{ 1683 struct device_node *np = ndev->dev.parent->of_node; 1684 struct ravb_private *priv = netdev_priv(ndev); 1685 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1686 1687 netif_tx_stop_all_queues(ndev); 1688 1689 /* Disable interrupts by clearing the interrupt masks. */ 1690 ravb_write(ndev, 0, RIC0); 1691 ravb_write(ndev, 0, RIC2); 1692 ravb_write(ndev, 0, TIC); 1693 1694 /* Stop PTP Clock driver */ 1695 if (priv->chip_id == RCAR_GEN2) 1696 ravb_ptp_stop(ndev); 1697 1698 /* Set the config mode to stop the AVB-DMAC's processes */ 1699 if (ravb_stop_dma(ndev) < 0) 1700 netdev_err(ndev, 1701 "device will be stopped after h/w processes are done.\n"); 1702 1703 /* Clear the timestamp list */ 1704 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1705 list_del(&ts_skb->list); 1706 kfree_skb(ts_skb->skb); 1707 kfree(ts_skb); 1708 } 1709 1710 /* PHY disconnect */ 1711 if (ndev->phydev) { 1712 phy_stop(ndev->phydev); 1713 phy_disconnect(ndev->phydev); 1714 if (of_phy_is_fixed_link(np)) 1715 of_phy_deregister_fixed_link(np); 1716 } 1717 1718 cancel_work_sync(&priv->work); 1719 1720 if (priv->chip_id != RCAR_GEN2) { 1721 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1722 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1723 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1724 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1725 free_irq(priv->emac_irq, ndev); 1726 } 1727 free_irq(ndev->irq, ndev); 1728 1729 napi_disable(&priv->napi[RAVB_NC]); 1730 napi_disable(&priv->napi[RAVB_BE]); 1731 1732 /* Free all the skb's in the RX queue and the DMA buffers. */ 1733 ravb_ring_free(ndev, RAVB_BE); 1734 ravb_ring_free(ndev, RAVB_NC); 1735 1736 return 0; 1737} 1738 1739static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1740{ 1741 struct ravb_private *priv = netdev_priv(ndev); 1742 struct hwtstamp_config config; 1743 1744 config.flags = 0; 1745 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1746 HWTSTAMP_TX_OFF; 1747 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 1748 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 1749 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1750 break; 1751 case RAVB_RXTSTAMP_TYPE_ALL: 1752 config.rx_filter = HWTSTAMP_FILTER_ALL; 1753 break; 1754 default: 1755 config.rx_filter = HWTSTAMP_FILTER_NONE; 1756 } 1757 1758 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1759 -EFAULT : 0; 1760} 1761 1762/* Control hardware time stamping */ 1763static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1764{ 1765 struct ravb_private *priv = netdev_priv(ndev); 1766 struct hwtstamp_config config; 1767 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1768 u32 tstamp_tx_ctrl; 1769 1770 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1771 return -EFAULT; 1772 1773 /* Reserved for future extensions */ 1774 if (config.flags) 1775 return -EINVAL; 1776 1777 switch (config.tx_type) { 1778 case HWTSTAMP_TX_OFF: 1779 tstamp_tx_ctrl = 0; 1780 break; 1781 case HWTSTAMP_TX_ON: 1782 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1783 break; 1784 default: 1785 return -ERANGE; 1786 } 1787 1788 switch (config.rx_filter) { 1789 case HWTSTAMP_FILTER_NONE: 1790 tstamp_rx_ctrl = 0; 1791 break; 1792 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1793 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1794 break; 1795 default: 1796 config.rx_filter = HWTSTAMP_FILTER_ALL; 1797 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1798 } 1799 1800 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1801 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1802 1803 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1804 -EFAULT : 0; 1805} 1806 1807/* ioctl to device function */ 1808static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1809{ 1810 struct phy_device *phydev = ndev->phydev; 1811 1812 if (!netif_running(ndev)) 1813 return -EINVAL; 1814 1815 if (!phydev) 1816 return -ENODEV; 1817 1818 switch (cmd) { 1819 case SIOCGHWTSTAMP: 1820 return ravb_hwtstamp_get(ndev, req); 1821 case SIOCSHWTSTAMP: 1822 return ravb_hwtstamp_set(ndev, req); 1823 } 1824 1825 return phy_mii_ioctl(phydev, req, cmd); 1826} 1827 1828static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1829{ 1830 struct ravb_private *priv = netdev_priv(ndev); 1831 1832 ndev->mtu = new_mtu; 1833 1834 if (netif_running(ndev)) { 1835 synchronize_irq(priv->emac_irq); 1836 ravb_emac_init(ndev); 1837 } 1838 1839 netdev_update_features(ndev); 1840 1841 return 0; 1842} 1843 1844static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1845{ 1846 struct ravb_private *priv = netdev_priv(ndev); 1847 unsigned long flags; 1848 1849 spin_lock_irqsave(&priv->lock, flags); 1850 1851 /* Disable TX and RX */ 1852 ravb_rcv_snd_disable(ndev); 1853 1854 /* Modify RX Checksum setting */ 1855 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1856 1857 /* Enable TX and RX */ 1858 ravb_rcv_snd_enable(ndev); 1859 1860 spin_unlock_irqrestore(&priv->lock, flags); 1861} 1862 1863static int ravb_set_features(struct net_device *ndev, 1864 netdev_features_t features) 1865{ 1866 netdev_features_t changed = ndev->features ^ features; 1867 1868 if (changed & NETIF_F_RXCSUM) 1869 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1870 1871 ndev->features = features; 1872 1873 return 0; 1874} 1875 1876static const struct net_device_ops ravb_netdev_ops = { 1877 .ndo_open = ravb_open, 1878 .ndo_stop = ravb_close, 1879 .ndo_start_xmit = ravb_start_xmit, 1880 .ndo_select_queue = ravb_select_queue, 1881 .ndo_get_stats = ravb_get_stats, 1882 .ndo_set_rx_mode = ravb_set_rx_mode, 1883 .ndo_tx_timeout = ravb_tx_timeout, 1884 .ndo_do_ioctl = ravb_do_ioctl, 1885 .ndo_change_mtu = ravb_change_mtu, 1886 .ndo_validate_addr = eth_validate_addr, 1887 .ndo_set_mac_address = eth_mac_addr, 1888 .ndo_set_features = ravb_set_features, 1889}; 1890 1891/* MDIO bus init function */ 1892static int ravb_mdio_init(struct ravb_private *priv) 1893{ 1894 struct platform_device *pdev = priv->pdev; 1895 struct device *dev = &pdev->dev; 1896 int error; 1897 1898 /* Bitbang init */ 1899 priv->mdiobb.ops = &bb_ops; 1900 1901 /* MII controller setting */ 1902 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1903 if (!priv->mii_bus) 1904 return -ENOMEM; 1905 1906 /* Hook up MII support for ethtool */ 1907 priv->mii_bus->name = "ravb_mii"; 1908 priv->mii_bus->parent = dev; 1909 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1910 pdev->name, pdev->id); 1911 1912 /* Register MDIO bus */ 1913 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1914 if (error) 1915 goto out_free_bus; 1916 1917 return 0; 1918 1919out_free_bus: 1920 free_mdio_bitbang(priv->mii_bus); 1921 return error; 1922} 1923 1924/* MDIO bus release function */ 1925static int ravb_mdio_release(struct ravb_private *priv) 1926{ 1927 /* Unregister mdio bus */ 1928 mdiobus_unregister(priv->mii_bus); 1929 1930 /* Free bitbang info */ 1931 free_mdio_bitbang(priv->mii_bus); 1932 1933 return 0; 1934} 1935 1936static const struct of_device_id ravb_match_table[] = { 1937 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1938 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1939 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1940 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1941 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1942 { } 1943}; 1944MODULE_DEVICE_TABLE(of, ravb_match_table); 1945 1946static int ravb_set_gti(struct net_device *ndev) 1947{ 1948 struct ravb_private *priv = netdev_priv(ndev); 1949 struct device *dev = ndev->dev.parent; 1950 unsigned long rate; 1951 uint64_t inc; 1952 1953 rate = clk_get_rate(priv->clk); 1954 if (!rate) 1955 return -EINVAL; 1956 1957 inc = 1000000000ULL << 20; 1958 do_div(inc, rate); 1959 1960 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1961 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1962 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1963 return -EINVAL; 1964 } 1965 1966 ravb_write(ndev, inc, GTI); 1967 1968 return 0; 1969} 1970 1971static void ravb_set_config_mode(struct net_device *ndev) 1972{ 1973 struct ravb_private *priv = netdev_priv(ndev); 1974 1975 if (priv->chip_id == RCAR_GEN2) { 1976 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1977 /* Set CSEL value */ 1978 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1979 } else { 1980 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1981 CCC_GAC | CCC_CSEL_HPB); 1982 } 1983} 1984 1985static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = { 1986 { .soc_id = "r8a774c0" }, 1987 { .soc_id = "r8a77990" }, 1988 { .soc_id = "r8a77995" }, 1989 { /* sentinel */ } 1990}; 1991 1992/* Set tx and rx clock internal delay modes */ 1993static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1994{ 1995 struct ravb_private *priv = netdev_priv(ndev); 1996 bool explicit_delay = false; 1997 u32 delay; 1998 1999 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2000 /* Valid values are 0 and 1800, according to DT bindings */ 2001 priv->rxcidm = !!delay; 2002 explicit_delay = true; 2003 } 2004 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2005 /* Valid values are 0 and 2000, according to DT bindings */ 2006 priv->txcidm = !!delay; 2007 explicit_delay = true; 2008 } 2009 2010 if (explicit_delay) 2011 return; 2012 2013 /* Fall back to legacy rgmii-*id behavior */ 2014 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2015 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2016 priv->rxcidm = 1; 2017 priv->rgmii_override = 1; 2018 } 2019 2020 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2021 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2022 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match), 2023 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree", 2024 phy_modes(priv->phy_interface))) { 2025 priv->txcidm = 1; 2026 priv->rgmii_override = 1; 2027 } 2028 } 2029} 2030 2031static void ravb_set_delay_mode(struct net_device *ndev) 2032{ 2033 struct ravb_private *priv = netdev_priv(ndev); 2034 u32 set = 0; 2035 2036 if (priv->rxcidm) 2037 set |= APSR_DM_RDM; 2038 if (priv->txcidm) 2039 set |= APSR_DM_TDM; 2040 ravb_modify(ndev, APSR, APSR_DM, set); 2041} 2042 2043static int ravb_probe(struct platform_device *pdev) 2044{ 2045 struct device_node *np = pdev->dev.of_node; 2046 struct ravb_private *priv; 2047 enum ravb_chip_id chip_id; 2048 struct net_device *ndev; 2049 int error, irq, q; 2050 struct resource *res; 2051 int i; 2052 2053 if (!np) { 2054 dev_err(&pdev->dev, 2055 "this driver is required to be instantiated from device tree\n"); 2056 return -EINVAL; 2057 } 2058 2059 /* Get base address */ 2060 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2061 if (!res) { 2062 dev_err(&pdev->dev, "invalid resource\n"); 2063 return -EINVAL; 2064 } 2065 2066 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2067 NUM_TX_QUEUE, NUM_RX_QUEUE); 2068 if (!ndev) 2069 return -ENOMEM; 2070 2071 ndev->features = NETIF_F_RXCSUM; 2072 ndev->hw_features = NETIF_F_RXCSUM; 2073 2074 pm_runtime_enable(&pdev->dev); 2075 error = pm_runtime_resume_and_get(&pdev->dev); 2076 if (error < 0) 2077 goto out_rpm_disable; 2078 2079 /* The Ether-specific entries in the device structure. */ 2080 ndev->base_addr = res->start; 2081 2082 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2083 2084 if (chip_id == RCAR_GEN3) 2085 irq = platform_get_irq_byname(pdev, "ch22"); 2086 else 2087 irq = platform_get_irq(pdev, 0); 2088 if (irq < 0) { 2089 error = irq; 2090 goto out_release; 2091 } 2092 ndev->irq = irq; 2093 2094 SET_NETDEV_DEV(ndev, &pdev->dev); 2095 2096 priv = netdev_priv(ndev); 2097 priv->ndev = ndev; 2098 priv->pdev = pdev; 2099 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2100 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2101 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2102 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2103 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2104 if (IS_ERR(priv->addr)) { 2105 error = PTR_ERR(priv->addr); 2106 goto out_release; 2107 } 2108 2109 spin_lock_init(&priv->lock); 2110 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2111 2112 error = of_get_phy_mode(np, &priv->phy_interface); 2113 if (error && error != -ENODEV) 2114 goto out_release; 2115 2116 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2117 priv->avb_link_active_low = 2118 of_property_read_bool(np, "renesas,ether-link-active-low"); 2119 2120 if (chip_id == RCAR_GEN3) { 2121 irq = platform_get_irq_byname(pdev, "ch24"); 2122 if (irq < 0) { 2123 error = irq; 2124 goto out_release; 2125 } 2126 priv->emac_irq = irq; 2127 for (i = 0; i < NUM_RX_QUEUE; i++) { 2128 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2129 if (irq < 0) { 2130 error = irq; 2131 goto out_release; 2132 } 2133 priv->rx_irqs[i] = irq; 2134 } 2135 for (i = 0; i < NUM_TX_QUEUE; i++) { 2136 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2137 if (irq < 0) { 2138 error = irq; 2139 goto out_release; 2140 } 2141 priv->tx_irqs[i] = irq; 2142 } 2143 } 2144 2145 priv->chip_id = chip_id; 2146 2147 priv->clk = devm_clk_get(&pdev->dev, NULL); 2148 if (IS_ERR(priv->clk)) { 2149 error = PTR_ERR(priv->clk); 2150 goto out_release; 2151 } 2152 2153 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2154 ndev->min_mtu = ETH_MIN_MTU; 2155 2156 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2157 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2158 2159 /* Set function */ 2160 ndev->netdev_ops = &ravb_netdev_ops; 2161 ndev->ethtool_ops = &ravb_ethtool_ops; 2162 2163 /* Set AVB config mode */ 2164 ravb_set_config_mode(ndev); 2165 2166 /* Set GTI value */ 2167 error = ravb_set_gti(ndev); 2168 if (error) 2169 goto out_release; 2170 2171 /* Request GTI loading */ 2172 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2173 2174 if (priv->chip_id != RCAR_GEN2) { 2175 ravb_parse_delay_mode(np, ndev); 2176 ravb_set_delay_mode(ndev); 2177 } 2178 2179 /* Allocate descriptor base address table */ 2180 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2181 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2182 &priv->desc_bat_dma, GFP_KERNEL); 2183 if (!priv->desc_bat) { 2184 dev_err(&pdev->dev, 2185 "Cannot allocate desc base address table (size %d bytes)\n", 2186 priv->desc_bat_size); 2187 error = -ENOMEM; 2188 goto out_release; 2189 } 2190 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2191 priv->desc_bat[q].die_dt = DT_EOS; 2192 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2193 2194 /* Initialise HW timestamp list */ 2195 INIT_LIST_HEAD(&priv->ts_skb_list); 2196 2197 /* Initialise PTP Clock driver */ 2198 if (chip_id != RCAR_GEN2) 2199 ravb_ptp_init(ndev, pdev); 2200 2201 /* Debug message level */ 2202 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2203 2204 /* Read and set MAC address */ 2205 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2206 if (!is_valid_ether_addr(ndev->dev_addr)) { 2207 dev_warn(&pdev->dev, 2208 "no valid MAC address supplied, using a random one\n"); 2209 eth_hw_addr_random(ndev); 2210 } 2211 2212 /* MDIO bus init */ 2213 error = ravb_mdio_init(priv); 2214 if (error) { 2215 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2216 goto out_dma_free; 2217 } 2218 2219 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2220 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2221 2222 /* Network device register */ 2223 error = register_netdev(ndev); 2224 if (error) 2225 goto out_napi_del; 2226 2227 device_set_wakeup_capable(&pdev->dev, 1); 2228 2229 /* Print device information */ 2230 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2231 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2232 2233 platform_set_drvdata(pdev, ndev); 2234 2235 return 0; 2236 2237out_napi_del: 2238 netif_napi_del(&priv->napi[RAVB_NC]); 2239 netif_napi_del(&priv->napi[RAVB_BE]); 2240 ravb_mdio_release(priv); 2241out_dma_free: 2242 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2243 priv->desc_bat_dma); 2244 2245 /* Stop PTP Clock driver */ 2246 if (chip_id != RCAR_GEN2) 2247 ravb_ptp_stop(ndev); 2248out_release: 2249 free_netdev(ndev); 2250 2251 pm_runtime_put(&pdev->dev); 2252out_rpm_disable: 2253 pm_runtime_disable(&pdev->dev); 2254 return error; 2255} 2256 2257static int ravb_remove(struct platform_device *pdev) 2258{ 2259 struct net_device *ndev = platform_get_drvdata(pdev); 2260 struct ravb_private *priv = netdev_priv(ndev); 2261 2262 /* Stop PTP Clock driver */ 2263 if (priv->chip_id != RCAR_GEN2) 2264 ravb_ptp_stop(ndev); 2265 2266 /* Set reset mode */ 2267 ravb_write(ndev, CCC_OPC_RESET, CCC); 2268 unregister_netdev(ndev); 2269 netif_napi_del(&priv->napi[RAVB_NC]); 2270 netif_napi_del(&priv->napi[RAVB_BE]); 2271 ravb_mdio_release(priv); 2272 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2273 priv->desc_bat_dma); 2274 pm_runtime_put_sync(&pdev->dev); 2275 pm_runtime_disable(&pdev->dev); 2276 free_netdev(ndev); 2277 platform_set_drvdata(pdev, NULL); 2278 2279 return 0; 2280} 2281 2282static int ravb_wol_setup(struct net_device *ndev) 2283{ 2284 struct ravb_private *priv = netdev_priv(ndev); 2285 2286 /* Disable interrupts by clearing the interrupt masks. */ 2287 ravb_write(ndev, 0, RIC0); 2288 ravb_write(ndev, 0, RIC2); 2289 ravb_write(ndev, 0, TIC); 2290 2291 /* Only allow ECI interrupts */ 2292 synchronize_irq(priv->emac_irq); 2293 napi_disable(&priv->napi[RAVB_NC]); 2294 napi_disable(&priv->napi[RAVB_BE]); 2295 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2296 2297 /* Enable MagicPacket */ 2298 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2299 2300 return enable_irq_wake(priv->emac_irq); 2301} 2302 2303static int ravb_wol_restore(struct net_device *ndev) 2304{ 2305 struct ravb_private *priv = netdev_priv(ndev); 2306 int ret; 2307 2308 napi_enable(&priv->napi[RAVB_NC]); 2309 napi_enable(&priv->napi[RAVB_BE]); 2310 2311 /* Disable MagicPacket */ 2312 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2313 2314 ret = ravb_close(ndev); 2315 if (ret < 0) 2316 return ret; 2317 2318 return disable_irq_wake(priv->emac_irq); 2319} 2320 2321static int __maybe_unused ravb_suspend(struct device *dev) 2322{ 2323 struct net_device *ndev = dev_get_drvdata(dev); 2324 struct ravb_private *priv = netdev_priv(ndev); 2325 int ret; 2326 2327 if (!netif_running(ndev)) 2328 return 0; 2329 2330 netif_device_detach(ndev); 2331 2332 if (priv->wol_enabled) 2333 ret = ravb_wol_setup(ndev); 2334 else 2335 ret = ravb_close(ndev); 2336 2337 return ret; 2338} 2339 2340static int __maybe_unused ravb_resume(struct device *dev) 2341{ 2342 struct net_device *ndev = dev_get_drvdata(dev); 2343 struct ravb_private *priv = netdev_priv(ndev); 2344 int ret = 0; 2345 2346 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2347 if (priv->wol_enabled) 2348 ravb_write(ndev, CCC_OPC_RESET, CCC); 2349 2350 /* All register have been reset to default values. 2351 * Restore all registers which where setup at probe time and 2352 * reopen device if it was running before system suspended. 2353 */ 2354 2355 /* Set AVB config mode */ 2356 ravb_set_config_mode(ndev); 2357 2358 /* Set GTI value */ 2359 ret = ravb_set_gti(ndev); 2360 if (ret) 2361 return ret; 2362 2363 /* Request GTI loading */ 2364 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2365 2366 if (priv->chip_id != RCAR_GEN2) 2367 ravb_set_delay_mode(ndev); 2368 2369 /* Restore descriptor base address table */ 2370 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2371 2372 if (netif_running(ndev)) { 2373 if (priv->wol_enabled) { 2374 ret = ravb_wol_restore(ndev); 2375 if (ret) 2376 return ret; 2377 } 2378 ret = ravb_open(ndev); 2379 if (ret < 0) 2380 return ret; 2381 ravb_set_rx_mode(ndev); 2382 netif_device_attach(ndev); 2383 } 2384 2385 return ret; 2386} 2387 2388static int __maybe_unused ravb_runtime_nop(struct device *dev) 2389{ 2390 /* Runtime PM callback shared between ->runtime_suspend() 2391 * and ->runtime_resume(). Simply returns success. 2392 * 2393 * This driver re-initializes all registers after 2394 * pm_runtime_get_sync() anyway so there is no need 2395 * to save and restore registers here. 2396 */ 2397 return 0; 2398} 2399 2400static const struct dev_pm_ops ravb_dev_pm_ops = { 2401 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2402 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2403}; 2404 2405static struct platform_driver ravb_driver = { 2406 .probe = ravb_probe, 2407 .remove = ravb_remove, 2408 .driver = { 2409 .name = "ravb", 2410 .pm = &ravb_dev_pm_ops, 2411 .of_match_table = ravb_match_table, 2412 }, 2413}; 2414 2415module_platform_driver(ravb_driver); 2416 2417MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2418MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2419MODULE_LICENSE("GPL v2"); 2420