1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12#include <linux/module.h> 13#include <linux/pci.h> 14#include <linux/netdevice.h> 15#include <linux/etherdevice.h> 16#include <linux/clk.h> 17#include <linux/delay.h> 18#include <linux/ethtool.h> 19#include <linux/phy.h> 20#include <linux/if_vlan.h> 21#include <linux/in.h> 22#include <linux/io.h> 23#include <linux/ip.h> 24#include <linux/tcp.h> 25#include <linux/interrupt.h> 26#include <linux/dma-mapping.h> 27#include <linux/pm_runtime.h> 28#include <linux/bitfield.h> 29#include <linux/prefetch.h> 30#include <linux/ipv6.h> 31#include <net/ip6_checksum.h> 32 33#include "r8169.h" 34#include "r8169_firmware.h" 35 36#define MODULENAME "r8169" 37 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 60 61/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 63#define MC_FILTER_LIMIT 32 64 65#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 66#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 67 68#define R8169_REGS_SIZE 256 69#define R8169_RX_BUF_SIZE (SZ_16K - 1) 70#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 71#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 72#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 73#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 74 75#define OCP_STD_PHY_BASE 0xa400 76 77#define RTL_CFG_NO_GBIT 1 78 79/* write/read MMIO register */ 80#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92static const struct { 93 const char *name; 94 const char *fw_name; 95} rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 110 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 152}; 153 154static const struct pci_device_id rtl8169_pci_tbl[] = { 155 { PCI_VDEVICE(REALTEK, 0x2502) }, 156 { PCI_VDEVICE(REALTEK, 0x2600) }, 157 { PCI_VDEVICE(REALTEK, 0x8129) }, 158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 159 { PCI_VDEVICE(REALTEK, 0x8161) }, 160 { PCI_VDEVICE(REALTEK, 0x8162) }, 161 { PCI_VDEVICE(REALTEK, 0x8167) }, 162 { PCI_VDEVICE(REALTEK, 0x8168) }, 163 { PCI_VDEVICE(NCUBE, 0x8168) }, 164 { PCI_VDEVICE(REALTEK, 0x8169) }, 165 { PCI_VENDOR_ID_DLINK, 0x4300, 166 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 167 { PCI_VDEVICE(DLINK, 0x4300) }, 168 { PCI_VDEVICE(DLINK, 0x4302) }, 169 { PCI_VDEVICE(AT, 0xc107) }, 170 { PCI_VDEVICE(USR, 0x0116) }, 171 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 172 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 173 { PCI_VDEVICE(REALTEK, 0x8125) }, 174 { PCI_VDEVICE(REALTEK, 0x3000) }, 175 {} 176}; 177 178MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 179 180enum rtl_registers { 181 MAC0 = 0, /* Ethernet hardware address. */ 182 MAC4 = 4, 183 MAR0 = 8, /* Multicast filter. */ 184 CounterAddrLow = 0x10, 185 CounterAddrHigh = 0x14, 186 TxDescStartAddrLow = 0x20, 187 TxDescStartAddrHigh = 0x24, 188 TxHDescStartAddrLow = 0x28, 189 TxHDescStartAddrHigh = 0x2c, 190 FLASH = 0x30, 191 ERSR = 0x36, 192 ChipCmd = 0x37, 193 TxPoll = 0x38, 194 IntrMask = 0x3c, 195 IntrStatus = 0x3e, 196 197 TxConfig = 0x40, 198#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 199#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 200 201 RxConfig = 0x44, 202#define RX128_INT_EN (1 << 15) /* 8111c and later */ 203#define RX_MULTI_EN (1 << 14) /* 8111c only */ 204#define RXCFG_FIFO_SHIFT 13 205 /* No threshold before first PCI xfer */ 206#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 207#define RX_EARLY_OFF (1 << 11) 208#define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 209#define RXCFG_DMA_SHIFT 8 210 /* Unlimited maximum PCI burst. */ 211#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 212 213 Cfg9346 = 0x50, 214 Config0 = 0x51, 215 Config1 = 0x52, 216 Config2 = 0x53, 217#define PME_SIGNAL (1 << 5) /* 8168c and later */ 218 219 Config3 = 0x54, 220 Config4 = 0x55, 221 Config5 = 0x56, 222 PHYAR = 0x60, 223 PHYstatus = 0x6c, 224 RxMaxSize = 0xda, 225 CPlusCmd = 0xe0, 226 IntrMitigate = 0xe2, 227 228#define RTL_COALESCE_TX_USECS GENMASK(15, 12) 229#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 230#define RTL_COALESCE_RX_USECS GENMASK(7, 4) 231#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 232 233#define RTL_COALESCE_T_MAX 0x0fU 234#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 235 236 RxDescAddrLow = 0xe4, 237 RxDescAddrHigh = 0xe8, 238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 239 240#define NoEarlyTx 0x3f /* Max value : no early transmit. */ 241 242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 243 244#define TxPacketMax (8064 >> 7) 245#define EarlySize 0x27 246 247 FuncEvent = 0xf0, 248 FuncEventMask = 0xf4, 249 FuncPresetState = 0xf8, 250 IBCR0 = 0xf8, 251 IBCR2 = 0xf9, 252 IBIMR0 = 0xfa, 253 IBISR0 = 0xfb, 254 FuncForceEvent = 0xfc, 255}; 256 257enum rtl8168_8101_registers { 258 CSIDR = 0x64, 259 CSIAR = 0x68, 260#define CSIAR_FLAG 0x80000000 261#define CSIAR_WRITE_CMD 0x80000000 262#define CSIAR_BYTE_ENABLE 0x0000f000 263#define CSIAR_ADDR_MASK 0x00000fff 264 PMCH = 0x6f, 265 EPHYAR = 0x80, 266#define EPHYAR_FLAG 0x80000000 267#define EPHYAR_WRITE_CMD 0x80000000 268#define EPHYAR_REG_MASK 0x1f 269#define EPHYAR_REG_SHIFT 16 270#define EPHYAR_DATA_MASK 0xffff 271 DLLPR = 0xd0, 272#define PFM_EN (1 << 6) 273#define TX_10M_PS_EN (1 << 7) 274 DBG_REG = 0xd1, 275#define FIX_NAK_1 (1 << 4) 276#define FIX_NAK_2 (1 << 3) 277 TWSI = 0xd2, 278 MCU = 0xd3, 279#define NOW_IS_OOB (1 << 7) 280#define TX_EMPTY (1 << 5) 281#define RX_EMPTY (1 << 4) 282#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 283#define EN_NDP (1 << 3) 284#define EN_OOB_RESET (1 << 2) 285#define LINK_LIST_RDY (1 << 1) 286 EFUSEAR = 0xdc, 287#define EFUSEAR_FLAG 0x80000000 288#define EFUSEAR_WRITE_CMD 0x80000000 289#define EFUSEAR_READ_CMD 0x00000000 290#define EFUSEAR_REG_MASK 0x03ff 291#define EFUSEAR_REG_SHIFT 8 292#define EFUSEAR_DATA_MASK 0xff 293 MISC_1 = 0xf2, 294#define PFM_D3COLD_EN (1 << 6) 295}; 296 297enum rtl8168_registers { 298 LED_FREQ = 0x1a, 299 EEE_LED = 0x1b, 300 ERIDR = 0x70, 301 ERIAR = 0x74, 302#define ERIAR_FLAG 0x80000000 303#define ERIAR_WRITE_CMD 0x80000000 304#define ERIAR_READ_CMD 0x00000000 305#define ERIAR_ADDR_BYTE_ALIGN 4 306#define ERIAR_TYPE_SHIFT 16 307#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 308#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 309#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 310#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 311#define ERIAR_MASK_SHIFT 12 312#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 313#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 314#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 315#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 316#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 317 EPHY_RXER_NUM = 0x7c, 318 OCPDR = 0xb0, /* OCP GPHY access */ 319#define OCPDR_WRITE_CMD 0x80000000 320#define OCPDR_READ_CMD 0x00000000 321#define OCPDR_REG_MASK 0x7f 322#define OCPDR_GPHY_REG_SHIFT 16 323#define OCPDR_DATA_MASK 0xffff 324 OCPAR = 0xb4, 325#define OCPAR_FLAG 0x80000000 326#define OCPAR_GPHY_WRITE_CMD 0x8000f060 327#define OCPAR_GPHY_READ_CMD 0x0000f060 328 GPHY_OCP = 0xb8, 329 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 330 MISC = 0xf0, /* 8168e only. */ 331#define TXPLA_RST (1 << 29) 332#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 333#define PWM_EN (1 << 22) 334#define RXDV_GATED_EN (1 << 19) 335#define EARLY_TALLY_EN (1 << 16) 336}; 337 338enum rtl8125_registers { 339 IntrMask_8125 = 0x38, 340 IntrStatus_8125 = 0x3c, 341 TxPoll_8125 = 0x90, 342 MAC0_BKP = 0x19e0, 343 EEE_TXIDLE_TIMER_8125 = 0x6048, 344}; 345 346#define RX_VLAN_INNER_8125 BIT(22) 347#define RX_VLAN_OUTER_8125 BIT(23) 348#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 349 350#define RX_FETCH_DFLT_8125 (8 << 27) 351 352enum rtl_register_content { 353 /* InterruptStatusBits */ 354 SYSErr = 0x8000, 355 PCSTimeout = 0x4000, 356 SWInt = 0x0100, 357 TxDescUnavail = 0x0080, 358 RxFIFOOver = 0x0040, 359 LinkChg = 0x0020, 360 RxOverflow = 0x0010, 361 TxErr = 0x0008, 362 TxOK = 0x0004, 363 RxErr = 0x0002, 364 RxOK = 0x0001, 365 366 /* RxStatusDesc */ 367 RxRWT = (1 << 22), 368 RxRES = (1 << 21), 369 RxRUNT = (1 << 20), 370 RxCRC = (1 << 19), 371 372 /* ChipCmdBits */ 373 StopReq = 0x80, 374 CmdReset = 0x10, 375 CmdRxEnb = 0x08, 376 CmdTxEnb = 0x04, 377 RxBufEmpty = 0x01, 378 379 /* TXPoll register p.5 */ 380 HPQ = 0x80, /* Poll cmd on the high prio queue */ 381 NPQ = 0x40, /* Poll cmd on the low prio queue */ 382 FSWInt = 0x01, /* Forced software interrupt */ 383 384 /* Cfg9346Bits */ 385 Cfg9346_Lock = 0x00, 386 Cfg9346_Unlock = 0xc0, 387 388 /* rx_mode_bits */ 389 AcceptErr = 0x20, 390 AcceptRunt = 0x10, 391#define RX_CONFIG_ACCEPT_ERR_MASK 0x30 392 AcceptBroadcast = 0x08, 393 AcceptMulticast = 0x04, 394 AcceptMyPhys = 0x02, 395 AcceptAllPhys = 0x01, 396#define RX_CONFIG_ACCEPT_OK_MASK 0x0f 397#define RX_CONFIG_ACCEPT_MASK 0x3f 398 399 /* TxConfigBits */ 400 TxInterFrameGapShift = 24, 401 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 402 403 /* Config1 register p.24 */ 404 LEDS1 = (1 << 7), 405 LEDS0 = (1 << 6), 406 Speed_down = (1 << 4), 407 MEMMAP = (1 << 3), 408 IOMAP = (1 << 2), 409 VPD = (1 << 1), 410 PMEnable = (1 << 0), /* Power Management Enable */ 411 412 /* Config2 register p. 25 */ 413 ClkReqEn = (1 << 7), /* Clock Request Enable */ 414 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 415 PCI_Clock_66MHz = 0x01, 416 PCI_Clock_33MHz = 0x00, 417 418 /* Config3 register p.25 */ 419 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 420 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 421 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 422 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 423 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 424 425 /* Config4 register */ 426 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config5 register p.27 */ 429 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 430 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 431 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 432 Spi_en = (1 << 3), 433 LanWake = (1 << 1), /* LanWake enable/disable */ 434 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 435 ASPM_en = (1 << 0), /* ASPM enable */ 436 437 /* CPlusCmd p.31 */ 438 EnableBist = (1 << 15), // 8168 8101 439 Mac_dbgo_oe = (1 << 14), // 8168 8101 440 EnAnaPLL = (1 << 14), // 8169 441 Normal_mode = (1 << 13), // unused 442 Force_half_dup = (1 << 12), // 8168 8101 443 Force_rxflow_en = (1 << 11), // 8168 8101 444 Force_txflow_en = (1 << 10), // 8168 8101 445 Cxpl_dbg_sel = (1 << 9), // 8168 8101 446 ASF = (1 << 8), // 8168 8101 447 PktCntrDisable = (1 << 7), // 8168 8101 448 Mac_dbgo_sel = 0x001c, // 8168 449 RxVlan = (1 << 6), 450 RxChkSum = (1 << 5), 451 PCIDAC = (1 << 4), 452 PCIMulRW = (1 << 3), 453#define INTT_MASK GENMASK(1, 0) 454#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 455 456 /* rtl8169_PHYstatus */ 457 TBI_Enable = 0x80, 458 TxFlowCtrl = 0x40, 459 RxFlowCtrl = 0x20, 460 _1000bpsF = 0x10, 461 _100bps = 0x08, 462 _10bps = 0x04, 463 LinkStatus = 0x02, 464 FullDup = 0x01, 465 466 /* ResetCounterCommand */ 467 CounterReset = 0x1, 468 469 /* DumpCounterCommand */ 470 CounterDump = 0x8, 471 472 /* magic enable v2 */ 473 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 474}; 475 476enum rtl_desc_bit { 477 /* First doubleword. */ 478 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 479 RingEnd = (1 << 30), /* End of descriptor ring */ 480 FirstFrag = (1 << 29), /* First segment of a packet */ 481 LastFrag = (1 << 28), /* Final segment of a packet */ 482}; 483 484/* Generic case. */ 485enum rtl_tx_desc_bit { 486 /* First doubleword. */ 487 TD_LSO = (1 << 27), /* Large Send Offload */ 488#define TD_MSS_MAX 0x07ffu /* MSS value */ 489 490 /* Second doubleword. */ 491 TxVlanTag = (1 << 17), /* Add VLAN tag */ 492}; 493 494/* 8169, 8168b and 810x except 8102e. */ 495enum rtl_tx_desc_bit_0 { 496 /* First doubleword. */ 497#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 498 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 499 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 500 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 501}; 502 503/* 8102e, 8168c and beyond. */ 504enum rtl_tx_desc_bit_1 { 505 /* First doubleword. */ 506 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 507 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 508#define GTTCPHO_SHIFT 18 509#define GTTCPHO_MAX 0x7f 510 511 /* Second doubleword. */ 512#define TCPHO_SHIFT 18 513#define TCPHO_MAX 0x3ff 514#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 515 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 516 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 517 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 518 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 519}; 520 521enum rtl_rx_desc_bit { 522 /* Rx private */ 523 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 524 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 525 526#define RxProtoUDP (PID1) 527#define RxProtoTCP (PID0) 528#define RxProtoIP (PID1 | PID0) 529#define RxProtoMask RxProtoIP 530 531 IPFail = (1 << 16), /* IP checksum failed */ 532 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 533 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 534 RxVlanTag = (1 << 16), /* VLAN tag available */ 535}; 536 537#define RTL_GSO_MAX_SIZE_V1 32000 538#define RTL_GSO_MAX_SEGS_V1 24 539#define RTL_GSO_MAX_SIZE_V2 64000 540#define RTL_GSO_MAX_SEGS_V2 64 541 542struct TxDesc { 543 __le32 opts1; 544 __le32 opts2; 545 __le64 addr; 546}; 547 548struct RxDesc { 549 __le32 opts1; 550 __le32 opts2; 551 __le64 addr; 552}; 553 554struct ring_info { 555 struct sk_buff *skb; 556 u32 len; 557}; 558 559struct rtl8169_counters { 560 __le64 tx_packets; 561 __le64 rx_packets; 562 __le64 tx_errors; 563 __le32 rx_errors; 564 __le16 rx_missed; 565 __le16 align_errors; 566 __le32 tx_one_collision; 567 __le32 tx_multi_collision; 568 __le64 rx_unicast; 569 __le64 rx_broadcast; 570 __le32 rx_multicast; 571 __le16 tx_aborted; 572 __le16 tx_underun; 573}; 574 575struct rtl8169_tc_offsets { 576 bool inited; 577 __le64 tx_errors; 578 __le32 tx_multi_collision; 579 __le16 tx_aborted; 580 __le16 rx_missed; 581}; 582 583enum rtl_flag { 584 RTL_FLAG_TASK_ENABLED = 0, 585 RTL_FLAG_TASK_RESET_PENDING, 586 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 587 RTL_FLAG_TASK_TX_TIMEOUT, 588 RTL_FLAG_MAX 589}; 590 591struct rtl8169_stats { 592 u64 packets; 593 u64 bytes; 594 struct u64_stats_sync syncp; 595}; 596 597struct rtl8169_private { 598 void __iomem *mmio_addr; /* memory map physical address */ 599 struct pci_dev *pci_dev; 600 struct net_device *dev; 601 struct phy_device *phydev; 602 struct napi_struct napi; 603 enum mac_version mac_version; 604 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 605 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 606 u32 dirty_tx; 607 struct rtl8169_stats rx_stats; 608 struct rtl8169_stats tx_stats; 609 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 610 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 611 dma_addr_t TxPhyAddr; 612 dma_addr_t RxPhyAddr; 613 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 614 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 615 u16 cp_cmd; 616 u32 irq_mask; 617 struct clk *clk; 618 619 struct { 620 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 621 struct work_struct work; 622 } wk; 623 624 unsigned supports_gmii:1; 625 unsigned aspm_manageable:1; 626 dma_addr_t counters_phys_addr; 627 struct rtl8169_counters *counters; 628 struct rtl8169_tc_offsets tc_offset; 629 u32 saved_wolopts; 630 int eee_adv; 631 632 const char *fw_name; 633 struct rtl_fw *rtl_fw; 634 635 u32 ocp_base; 636}; 637 638typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 639 640MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 641MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 642MODULE_SOFTDEP("pre: realtek"); 643MODULE_LICENSE("GPL"); 644MODULE_FIRMWARE(FIRMWARE_8168D_1); 645MODULE_FIRMWARE(FIRMWARE_8168D_2); 646MODULE_FIRMWARE(FIRMWARE_8168E_1); 647MODULE_FIRMWARE(FIRMWARE_8168E_2); 648MODULE_FIRMWARE(FIRMWARE_8168E_3); 649MODULE_FIRMWARE(FIRMWARE_8105E_1); 650MODULE_FIRMWARE(FIRMWARE_8168F_1); 651MODULE_FIRMWARE(FIRMWARE_8168F_2); 652MODULE_FIRMWARE(FIRMWARE_8402_1); 653MODULE_FIRMWARE(FIRMWARE_8411_1); 654MODULE_FIRMWARE(FIRMWARE_8411_2); 655MODULE_FIRMWARE(FIRMWARE_8106E_1); 656MODULE_FIRMWARE(FIRMWARE_8106E_2); 657MODULE_FIRMWARE(FIRMWARE_8168G_2); 658MODULE_FIRMWARE(FIRMWARE_8168G_3); 659MODULE_FIRMWARE(FIRMWARE_8168H_1); 660MODULE_FIRMWARE(FIRMWARE_8168H_2); 661MODULE_FIRMWARE(FIRMWARE_8168FP_3); 662MODULE_FIRMWARE(FIRMWARE_8107E_1); 663MODULE_FIRMWARE(FIRMWARE_8107E_2); 664MODULE_FIRMWARE(FIRMWARE_8125A_3); 665MODULE_FIRMWARE(FIRMWARE_8125B_2); 666 667static inline struct device *tp_to_dev(struct rtl8169_private *tp) 668{ 669 return &tp->pci_dev->dev; 670} 671 672static void rtl_lock_config_regs(struct rtl8169_private *tp) 673{ 674 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 675} 676 677static void rtl_unlock_config_regs(struct rtl8169_private *tp) 678{ 679 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 680} 681 682static void rtl_pci_commit(struct rtl8169_private *tp) 683{ 684 /* Read an arbitrary register to commit a preceding PCI write */ 685 RTL_R8(tp, ChipCmd); 686} 687 688static bool rtl_is_8125(struct rtl8169_private *tp) 689{ 690 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 691} 692 693static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 694{ 695 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 696 tp->mac_version != RTL_GIGA_MAC_VER_39 && 697 tp->mac_version <= RTL_GIGA_MAC_VER_52; 698} 699 700static bool rtl_supports_eee(struct rtl8169_private *tp) 701{ 702 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 703 tp->mac_version != RTL_GIGA_MAC_VER_37 && 704 tp->mac_version != RTL_GIGA_MAC_VER_39; 705} 706 707static void rtl_get_priv_stats(struct rtl8169_stats *stats, 708 u64 *pkts, u64 *bytes) 709{ 710 unsigned int start; 711 712 do { 713 start = u64_stats_fetch_begin_irq(&stats->syncp); 714 *pkts = stats->packets; 715 *bytes = stats->bytes; 716 } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 717} 718 719static void rtl_inc_priv_stats(struct rtl8169_stats *stats, 720 u64 pkts, u64 bytes) 721{ 722 u64_stats_update_begin(&stats->syncp); 723 stats->packets += pkts; 724 stats->bytes += bytes; 725 u64_stats_update_end(&stats->syncp); 726} 727 728static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 729{ 730 int i; 731 732 for (i = 0; i < ETH_ALEN; i++) 733 mac[i] = RTL_R8(tp, reg + i); 734} 735 736struct rtl_cond { 737 bool (*check)(struct rtl8169_private *); 738 const char *msg; 739}; 740 741static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 742 unsigned long usecs, int n, bool high) 743{ 744 int i; 745 746 for (i = 0; i < n; i++) { 747 if (c->check(tp) == high) 748 return true; 749 fsleep(usecs); 750 } 751 752 if (net_ratelimit()) 753 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 754 c->msg, !high, n, usecs); 755 return false; 756} 757 758static bool rtl_loop_wait_high(struct rtl8169_private *tp, 759 const struct rtl_cond *c, 760 unsigned long d, int n) 761{ 762 return rtl_loop_wait(tp, c, d, n, true); 763} 764 765static bool rtl_loop_wait_low(struct rtl8169_private *tp, 766 const struct rtl_cond *c, 767 unsigned long d, int n) 768{ 769 return rtl_loop_wait(tp, c, d, n, false); 770} 771 772#define DECLARE_RTL_COND(name) \ 773static bool name ## _check(struct rtl8169_private *); \ 774 \ 775static const struct rtl_cond name = { \ 776 .check = name ## _check, \ 777 .msg = #name \ 778}; \ 779 \ 780static bool name ## _check(struct rtl8169_private *tp) 781 782static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 783{ 784 if (reg & 0xffff0001) { 785 if (net_ratelimit()) 786 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 787 return true; 788 } 789 return false; 790} 791 792DECLARE_RTL_COND(rtl_ocp_gphy_cond) 793{ 794 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 795} 796 797static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 798{ 799 if (rtl_ocp_reg_failure(tp, reg)) 800 return; 801 802 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 803 804 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 805} 806 807static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 808{ 809 if (rtl_ocp_reg_failure(tp, reg)) 810 return 0; 811 812 RTL_W32(tp, GPHY_OCP, reg << 15); 813 814 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 815 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 816} 817 818static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 819{ 820 if (rtl_ocp_reg_failure(tp, reg)) 821 return; 822 823 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 824} 825 826static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 827{ 828 if (rtl_ocp_reg_failure(tp, reg)) 829 return 0; 830 831 RTL_W32(tp, OCPDR, reg << 15); 832 833 return RTL_R32(tp, OCPDR); 834} 835 836static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 837 u16 set) 838{ 839 u16 data = r8168_mac_ocp_read(tp, reg); 840 841 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 842} 843 844static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 845{ 846 if (reg == 0x1f) { 847 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 848 return; 849 } 850 851 if (tp->ocp_base != OCP_STD_PHY_BASE) 852 reg -= 0x10; 853 854 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 855} 856 857static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 858{ 859 if (reg == 0x1f) 860 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 861 862 if (tp->ocp_base != OCP_STD_PHY_BASE) 863 reg -= 0x10; 864 865 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 866} 867 868static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 869{ 870 if (reg == 0x1f) { 871 tp->ocp_base = value << 4; 872 return; 873 } 874 875 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 876} 877 878static int mac_mcu_read(struct rtl8169_private *tp, int reg) 879{ 880 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 881} 882 883DECLARE_RTL_COND(rtl_phyar_cond) 884{ 885 return RTL_R32(tp, PHYAR) & 0x80000000; 886} 887 888static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 889{ 890 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 891 892 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 893 /* 894 * According to hardware specs a 20us delay is required after write 895 * complete indication, but before sending next command. 896 */ 897 udelay(20); 898} 899 900static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 901{ 902 int value; 903 904 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 905 906 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 907 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 908 909 /* 910 * According to hardware specs a 20us delay is required after read 911 * complete indication, but before sending next command. 912 */ 913 udelay(20); 914 915 return value; 916} 917 918DECLARE_RTL_COND(rtl_ocpar_cond) 919{ 920 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 921} 922 923static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 924{ 925 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 926 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 927 RTL_W32(tp, EPHY_RXER_NUM, 0); 928 929 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 930} 931 932static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 933{ 934 r8168dp_1_mdio_access(tp, reg, 935 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 936} 937 938static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 939{ 940 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 941 942 mdelay(1); 943 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 944 RTL_W32(tp, EPHY_RXER_NUM, 0); 945 946 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 947 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 948} 949 950#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 951 952static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 953{ 954 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 955} 956 957static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 958{ 959 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 960} 961 962static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 963{ 964 r8168dp_2_mdio_start(tp); 965 966 r8169_mdio_write(tp, reg, value); 967 968 r8168dp_2_mdio_stop(tp); 969} 970 971static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 972{ 973 int value; 974 975 /* Work around issue with chip reporting wrong PHY ID */ 976 if (reg == MII_PHYSID2) 977 return 0xc912; 978 979 r8168dp_2_mdio_start(tp); 980 981 value = r8169_mdio_read(tp, reg); 982 983 r8168dp_2_mdio_stop(tp); 984 985 return value; 986} 987 988static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 989{ 990 switch (tp->mac_version) { 991 case RTL_GIGA_MAC_VER_27: 992 r8168dp_1_mdio_write(tp, location, val); 993 break; 994 case RTL_GIGA_MAC_VER_28: 995 case RTL_GIGA_MAC_VER_31: 996 r8168dp_2_mdio_write(tp, location, val); 997 break; 998 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 999 r8168g_mdio_write(tp, location, val); 1000 break; 1001 default: 1002 r8169_mdio_write(tp, location, val); 1003 break; 1004 } 1005} 1006 1007static int rtl_readphy(struct rtl8169_private *tp, int location) 1008{ 1009 switch (tp->mac_version) { 1010 case RTL_GIGA_MAC_VER_27: 1011 return r8168dp_1_mdio_read(tp, location); 1012 case RTL_GIGA_MAC_VER_28: 1013 case RTL_GIGA_MAC_VER_31: 1014 return r8168dp_2_mdio_read(tp, location); 1015 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1016 return r8168g_mdio_read(tp, location); 1017 default: 1018 return r8169_mdio_read(tp, location); 1019 } 1020} 1021 1022DECLARE_RTL_COND(rtl_ephyar_cond) 1023{ 1024 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1025} 1026 1027static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1028{ 1029 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1030 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1031 1032 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1033 1034 udelay(10); 1035} 1036 1037static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1038{ 1039 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1040 1041 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1042 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1043} 1044 1045static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1046{ 1047 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1048 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB) 1049 *cmd |= 0xf70 << 18; 1050} 1051 1052DECLARE_RTL_COND(rtl_eriar_cond) 1053{ 1054 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1055} 1056 1057static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1058 u32 val, int type) 1059{ 1060 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1061 1062 BUG_ON((addr & 3) || (mask == 0)); 1063 RTL_W32(tp, ERIDR, val); 1064 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1065 RTL_W32(tp, ERIAR, cmd); 1066 1067 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1068} 1069 1070static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1071 u32 val) 1072{ 1073 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1074} 1075 1076static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1077{ 1078 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1079 1080 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1081 RTL_W32(tp, ERIAR, cmd); 1082 1083 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1084 RTL_R32(tp, ERIDR) : ~0; 1085} 1086 1087static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1088{ 1089 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1090} 1091 1092static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1093{ 1094 u32 val = rtl_eri_read(tp, addr); 1095 1096 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1097} 1098 1099static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1100{ 1101 rtl_w0w1_eri(tp, addr, p, 0); 1102} 1103 1104static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1105{ 1106 rtl_w0w1_eri(tp, addr, 0, m); 1107} 1108 1109static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1110{ 1111 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1112 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1113 RTL_R32(tp, OCPDR) : ~0; 1114} 1115 1116static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1117{ 1118 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1119} 1120 1121static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1122 u32 data) 1123{ 1124 RTL_W32(tp, OCPDR, data); 1125 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1126 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1127} 1128 1129static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1130 u32 data) 1131{ 1132 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1133 data, ERIAR_OOB); 1134} 1135 1136static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1137{ 1138 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1139 1140 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1141} 1142 1143#define OOB_CMD_RESET 0x00 1144#define OOB_CMD_DRIVER_START 0x05 1145#define OOB_CMD_DRIVER_STOP 0x06 1146 1147static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1148{ 1149 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1150} 1151 1152DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1153{ 1154 u16 reg; 1155 1156 reg = rtl8168_get_ocp_reg(tp); 1157 1158 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1159} 1160 1161DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1162{ 1163 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1164} 1165 1166DECLARE_RTL_COND(rtl_ocp_tx_cond) 1167{ 1168 return RTL_R8(tp, IBISR0) & 0x20; 1169} 1170 1171static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1172{ 1173 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1174 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1175 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1176 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1177} 1178 1179static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1180{ 1181 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1182 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1183} 1184 1185static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1186{ 1187 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1188 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1189 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1190} 1191 1192static void rtl8168_driver_start(struct rtl8169_private *tp) 1193{ 1194 switch (tp->mac_version) { 1195 case RTL_GIGA_MAC_VER_27: 1196 case RTL_GIGA_MAC_VER_28: 1197 case RTL_GIGA_MAC_VER_31: 1198 rtl8168dp_driver_start(tp); 1199 break; 1200 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1201 rtl8168ep_driver_start(tp); 1202 break; 1203 default: 1204 BUG(); 1205 break; 1206 } 1207} 1208 1209static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1210{ 1211 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1212 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1213} 1214 1215static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1216{ 1217 rtl8168ep_stop_cmac(tp); 1218 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1219 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1220 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1221} 1222 1223static void rtl8168_driver_stop(struct rtl8169_private *tp) 1224{ 1225 switch (tp->mac_version) { 1226 case RTL_GIGA_MAC_VER_27: 1227 case RTL_GIGA_MAC_VER_28: 1228 case RTL_GIGA_MAC_VER_31: 1229 rtl8168dp_driver_stop(tp); 1230 break; 1231 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1232 rtl8168ep_driver_stop(tp); 1233 break; 1234 default: 1235 BUG(); 1236 break; 1237 } 1238} 1239 1240static bool r8168dp_check_dash(struct rtl8169_private *tp) 1241{ 1242 u16 reg = rtl8168_get_ocp_reg(tp); 1243 1244 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000); 1245} 1246 1247static bool r8168ep_check_dash(struct rtl8169_private *tp) 1248{ 1249 return r8168ep_ocp_read(tp, 0x128) & 0x00000001; 1250} 1251 1252static bool r8168_check_dash(struct rtl8169_private *tp) 1253{ 1254 switch (tp->mac_version) { 1255 case RTL_GIGA_MAC_VER_27: 1256 case RTL_GIGA_MAC_VER_28: 1257 case RTL_GIGA_MAC_VER_31: 1258 return r8168dp_check_dash(tp); 1259 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1260 return r8168ep_check_dash(tp); 1261 default: 1262 return false; 1263 } 1264} 1265 1266static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1267{ 1268 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1269 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1270} 1271 1272DECLARE_RTL_COND(rtl_efusear_cond) 1273{ 1274 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1275} 1276 1277u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1278{ 1279 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1280 1281 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1282 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1283} 1284 1285static u32 rtl_get_events(struct rtl8169_private *tp) 1286{ 1287 if (rtl_is_8125(tp)) 1288 return RTL_R32(tp, IntrStatus_8125); 1289 else 1290 return RTL_R16(tp, IntrStatus); 1291} 1292 1293static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1294{ 1295 if (rtl_is_8125(tp)) 1296 RTL_W32(tp, IntrStatus_8125, bits); 1297 else 1298 RTL_W16(tp, IntrStatus, bits); 1299} 1300 1301static void rtl_irq_disable(struct rtl8169_private *tp) 1302{ 1303 if (rtl_is_8125(tp)) 1304 RTL_W32(tp, IntrMask_8125, 0); 1305 else 1306 RTL_W16(tp, IntrMask, 0); 1307} 1308 1309static void rtl_irq_enable(struct rtl8169_private *tp) 1310{ 1311 if (rtl_is_8125(tp)) 1312 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1313 else 1314 RTL_W16(tp, IntrMask, tp->irq_mask); 1315} 1316 1317static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1318{ 1319 rtl_irq_disable(tp); 1320 rtl_ack_events(tp, 0xffffffff); 1321 rtl_pci_commit(tp); 1322} 1323 1324static void rtl_link_chg_patch(struct rtl8169_private *tp) 1325{ 1326 struct phy_device *phydev = tp->phydev; 1327 1328 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1329 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1330 if (phydev->speed == SPEED_1000) { 1331 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1333 } else if (phydev->speed == SPEED_100) { 1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1336 } else { 1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1339 } 1340 rtl_reset_packet_filter(tp); 1341 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1342 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1343 if (phydev->speed == SPEED_1000) { 1344 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1345 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1346 } else { 1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1349 } 1350 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1351 if (phydev->speed == SPEED_10) { 1352 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1354 } else { 1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1356 } 1357 } 1358} 1359 1360#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1361 1362static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1363{ 1364 struct rtl8169_private *tp = netdev_priv(dev); 1365 1366 wol->supported = WAKE_ANY; 1367 wol->wolopts = tp->saved_wolopts; 1368} 1369 1370static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1371{ 1372 static const struct { 1373 u32 opt; 1374 u16 reg; 1375 u8 mask; 1376 } cfg[] = { 1377 { WAKE_PHY, Config3, LinkUp }, 1378 { WAKE_UCAST, Config5, UWF }, 1379 { WAKE_BCAST, Config5, BWF }, 1380 { WAKE_MCAST, Config5, MWF }, 1381 { WAKE_ANY, Config5, LanWake }, 1382 { WAKE_MAGIC, Config3, MagicPacket } 1383 }; 1384 unsigned int i, tmp = ARRAY_SIZE(cfg); 1385 u8 options; 1386 1387 rtl_unlock_config_regs(tp); 1388 1389 if (rtl_is_8168evl_up(tp)) { 1390 tmp--; 1391 if (wolopts & WAKE_MAGIC) 1392 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1393 else 1394 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1395 } else if (rtl_is_8125(tp)) { 1396 tmp--; 1397 if (wolopts & WAKE_MAGIC) 1398 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1399 else 1400 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1401 } 1402 1403 for (i = 0; i < tmp; i++) { 1404 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1405 if (wolopts & cfg[i].opt) 1406 options |= cfg[i].mask; 1407 RTL_W8(tp, cfg[i].reg, options); 1408 } 1409 1410 switch (tp->mac_version) { 1411 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1412 options = RTL_R8(tp, Config1) & ~PMEnable; 1413 if (wolopts) 1414 options |= PMEnable; 1415 RTL_W8(tp, Config1, options); 1416 break; 1417 case RTL_GIGA_MAC_VER_34: 1418 case RTL_GIGA_MAC_VER_37: 1419 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1420 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1421 if (wolopts) 1422 options |= PME_SIGNAL; 1423 RTL_W8(tp, Config2, options); 1424 break; 1425 default: 1426 break; 1427 } 1428 1429 rtl_lock_config_regs(tp); 1430 1431 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1432 tp->dev->wol_enabled = wolopts ? 1 : 0; 1433} 1434 1435static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1436{ 1437 struct rtl8169_private *tp = netdev_priv(dev); 1438 1439 if (wol->wolopts & ~WAKE_ANY) 1440 return -EINVAL; 1441 1442 tp->saved_wolopts = wol->wolopts; 1443 __rtl8169_set_wol(tp, tp->saved_wolopts); 1444 1445 return 0; 1446} 1447 1448static void rtl8169_get_drvinfo(struct net_device *dev, 1449 struct ethtool_drvinfo *info) 1450{ 1451 struct rtl8169_private *tp = netdev_priv(dev); 1452 struct rtl_fw *rtl_fw = tp->rtl_fw; 1453 1454 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1455 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1456 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1457 if (rtl_fw) 1458 strlcpy(info->fw_version, rtl_fw->version, 1459 sizeof(info->fw_version)); 1460} 1461 1462static int rtl8169_get_regs_len(struct net_device *dev) 1463{ 1464 return R8169_REGS_SIZE; 1465} 1466 1467static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1468 netdev_features_t features) 1469{ 1470 struct rtl8169_private *tp = netdev_priv(dev); 1471 1472 if (dev->mtu > TD_MSS_MAX) 1473 features &= ~NETIF_F_ALL_TSO; 1474 1475 if (dev->mtu > ETH_DATA_LEN && 1476 tp->mac_version > RTL_GIGA_MAC_VER_06) 1477 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1478 1479 return features; 1480} 1481 1482static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1483 netdev_features_t features) 1484{ 1485 u32 rx_config = RTL_R32(tp, RxConfig); 1486 1487 if (features & NETIF_F_RXALL) 1488 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1489 else 1490 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1491 1492 if (rtl_is_8125(tp)) { 1493 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1494 rx_config |= RX_VLAN_8125; 1495 else 1496 rx_config &= ~RX_VLAN_8125; 1497 } 1498 1499 RTL_W32(tp, RxConfig, rx_config); 1500} 1501 1502static int rtl8169_set_features(struct net_device *dev, 1503 netdev_features_t features) 1504{ 1505 struct rtl8169_private *tp = netdev_priv(dev); 1506 1507 rtl_set_rx_config_features(tp, features); 1508 1509 if (features & NETIF_F_RXCSUM) 1510 tp->cp_cmd |= RxChkSum; 1511 else 1512 tp->cp_cmd &= ~RxChkSum; 1513 1514 if (!rtl_is_8125(tp)) { 1515 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1516 tp->cp_cmd |= RxVlan; 1517 else 1518 tp->cp_cmd &= ~RxVlan; 1519 } 1520 1521 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1522 rtl_pci_commit(tp); 1523 1524 return 0; 1525} 1526 1527static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1528{ 1529 return (skb_vlan_tag_present(skb)) ? 1530 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1531} 1532 1533static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1534{ 1535 u32 opts2 = le32_to_cpu(desc->opts2); 1536 1537 if (opts2 & RxVlanTag) 1538 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1539} 1540 1541static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1542 void *p) 1543{ 1544 struct rtl8169_private *tp = netdev_priv(dev); 1545 u32 __iomem *data = tp->mmio_addr; 1546 u32 *dw = p; 1547 int i; 1548 1549 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1550 memcpy_fromio(dw++, data++, 4); 1551} 1552 1553static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1554 "tx_packets", 1555 "rx_packets", 1556 "tx_errors", 1557 "rx_errors", 1558 "rx_missed", 1559 "align_errors", 1560 "tx_single_collisions", 1561 "tx_multi_collisions", 1562 "unicast", 1563 "broadcast", 1564 "multicast", 1565 "tx_aborted", 1566 "tx_underrun", 1567}; 1568 1569static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1570{ 1571 switch (sset) { 1572 case ETH_SS_STATS: 1573 return ARRAY_SIZE(rtl8169_gstrings); 1574 default: 1575 return -EOPNOTSUPP; 1576 } 1577} 1578 1579DECLARE_RTL_COND(rtl_counters_cond) 1580{ 1581 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1582} 1583 1584static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1585{ 1586 dma_addr_t paddr = tp->counters_phys_addr; 1587 u32 cmd; 1588 1589 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1590 rtl_pci_commit(tp); 1591 cmd = (u64)paddr & DMA_BIT_MASK(32); 1592 RTL_W32(tp, CounterAddrLow, cmd); 1593 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1594 1595 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1596} 1597 1598static void rtl8169_reset_counters(struct rtl8169_private *tp) 1599{ 1600 /* 1601 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1602 * tally counters. 1603 */ 1604 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1605 rtl8169_do_counters(tp, CounterReset); 1606} 1607 1608static void rtl8169_update_counters(struct rtl8169_private *tp) 1609{ 1610 u8 val = RTL_R8(tp, ChipCmd); 1611 1612 /* 1613 * Some chips are unable to dump tally counters when the receiver 1614 * is disabled. If 0xff chip may be in a PCI power-save state. 1615 */ 1616 if (val & CmdRxEnb && val != 0xff) 1617 rtl8169_do_counters(tp, CounterDump); 1618} 1619 1620static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1621{ 1622 struct rtl8169_counters *counters = tp->counters; 1623 1624 /* 1625 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1626 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1627 * reset by a power cycle, while the counter values collected by the 1628 * driver are reset at every driver unload/load cycle. 1629 * 1630 * To make sure the HW values returned by @get_stats64 match the SW 1631 * values, we collect the initial values at first open(*) and use them 1632 * as offsets to normalize the values returned by @get_stats64. 1633 * 1634 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1635 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1636 * set at open time by rtl_hw_start. 1637 */ 1638 1639 if (tp->tc_offset.inited) 1640 return; 1641 1642 rtl8169_reset_counters(tp); 1643 rtl8169_update_counters(tp); 1644 1645 tp->tc_offset.tx_errors = counters->tx_errors; 1646 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1647 tp->tc_offset.tx_aborted = counters->tx_aborted; 1648 tp->tc_offset.rx_missed = counters->rx_missed; 1649 tp->tc_offset.inited = true; 1650} 1651 1652static void rtl8169_get_ethtool_stats(struct net_device *dev, 1653 struct ethtool_stats *stats, u64 *data) 1654{ 1655 struct rtl8169_private *tp = netdev_priv(dev); 1656 struct rtl8169_counters *counters; 1657 1658 counters = tp->counters; 1659 rtl8169_update_counters(tp); 1660 1661 data[0] = le64_to_cpu(counters->tx_packets); 1662 data[1] = le64_to_cpu(counters->rx_packets); 1663 data[2] = le64_to_cpu(counters->tx_errors); 1664 data[3] = le32_to_cpu(counters->rx_errors); 1665 data[4] = le16_to_cpu(counters->rx_missed); 1666 data[5] = le16_to_cpu(counters->align_errors); 1667 data[6] = le32_to_cpu(counters->tx_one_collision); 1668 data[7] = le32_to_cpu(counters->tx_multi_collision); 1669 data[8] = le64_to_cpu(counters->rx_unicast); 1670 data[9] = le64_to_cpu(counters->rx_broadcast); 1671 data[10] = le32_to_cpu(counters->rx_multicast); 1672 data[11] = le16_to_cpu(counters->tx_aborted); 1673 data[12] = le16_to_cpu(counters->tx_underun); 1674} 1675 1676static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1677{ 1678 switch(stringset) { 1679 case ETH_SS_STATS: 1680 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1681 break; 1682 } 1683} 1684 1685/* 1686 * Interrupt coalescing 1687 * 1688 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1689 * > 8169, 8168 and 810x line of chipsets 1690 * 1691 * 8169, 8168, and 8136(810x) serial chipsets support it. 1692 * 1693 * > 2 - the Tx timer unit at gigabit speed 1694 * 1695 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1696 * (0xe0) bit 1 and bit 0. 1697 * 1698 * For 8169 1699 * bit[1:0] \ speed 1000M 100M 10M 1700 * 0 0 320ns 2.56us 40.96us 1701 * 0 1 2.56us 20.48us 327.7us 1702 * 1 0 5.12us 40.96us 655.4us 1703 * 1 1 10.24us 81.92us 1.31ms 1704 * 1705 * For the other 1706 * bit[1:0] \ speed 1000M 100M 10M 1707 * 0 0 5us 2.56us 40.96us 1708 * 0 1 40us 20.48us 327.7us 1709 * 1 0 80us 40.96us 655.4us 1710 * 1 1 160us 81.92us 1.31ms 1711 */ 1712 1713/* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1714struct rtl_coalesce_info { 1715 u32 speed; 1716 u32 scale_nsecs[4]; 1717}; 1718 1719/* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1720#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1721 1722static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1723 { SPEED_1000, COALESCE_DELAY(320) }, 1724 { SPEED_100, COALESCE_DELAY(2560) }, 1725 { SPEED_10, COALESCE_DELAY(40960) }, 1726 { 0 }, 1727}; 1728 1729static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1730 { SPEED_1000, COALESCE_DELAY(5000) }, 1731 { SPEED_100, COALESCE_DELAY(2560) }, 1732 { SPEED_10, COALESCE_DELAY(40960) }, 1733 { 0 }, 1734}; 1735#undef COALESCE_DELAY 1736 1737/* get rx/tx scale vector corresponding to current speed */ 1738static const struct rtl_coalesce_info * 1739rtl_coalesce_info(struct rtl8169_private *tp) 1740{ 1741 const struct rtl_coalesce_info *ci; 1742 1743 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1744 ci = rtl_coalesce_info_8169; 1745 else 1746 ci = rtl_coalesce_info_8168_8136; 1747 1748 /* if speed is unknown assume highest one */ 1749 if (tp->phydev->speed == SPEED_UNKNOWN) 1750 return ci; 1751 1752 for (; ci->speed; ci++) { 1753 if (tp->phydev->speed == ci->speed) 1754 return ci; 1755 } 1756 1757 return ERR_PTR(-ELNRNG); 1758} 1759 1760static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1761{ 1762 struct rtl8169_private *tp = netdev_priv(dev); 1763 const struct rtl_coalesce_info *ci; 1764 u32 scale, c_us, c_fr; 1765 u16 intrmit; 1766 1767 if (rtl_is_8125(tp)) 1768 return -EOPNOTSUPP; 1769 1770 memset(ec, 0, sizeof(*ec)); 1771 1772 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1773 ci = rtl_coalesce_info(tp); 1774 if (IS_ERR(ci)) 1775 return PTR_ERR(ci); 1776 1777 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1778 1779 intrmit = RTL_R16(tp, IntrMitigate); 1780 1781 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1782 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1783 1784 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1785 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1786 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1787 1788 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1789 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1790 1791 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1792 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1793 1794 return 0; 1795} 1796 1797/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1798static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1799 u16 *cp01) 1800{ 1801 const struct rtl_coalesce_info *ci; 1802 u16 i; 1803 1804 ci = rtl_coalesce_info(tp); 1805 if (IS_ERR(ci)) 1806 return PTR_ERR(ci); 1807 1808 for (i = 0; i < 4; i++) { 1809 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1810 *cp01 = i; 1811 return ci->scale_nsecs[i]; 1812 } 1813 } 1814 1815 return -ERANGE; 1816} 1817 1818static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1819{ 1820 struct rtl8169_private *tp = netdev_priv(dev); 1821 u32 tx_fr = ec->tx_max_coalesced_frames; 1822 u32 rx_fr = ec->rx_max_coalesced_frames; 1823 u32 coal_usec_max, units; 1824 u16 w = 0, cp01 = 0; 1825 int scale; 1826 1827 if (rtl_is_8125(tp)) 1828 return -EOPNOTSUPP; 1829 1830 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1831 return -ERANGE; 1832 1833 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1834 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1835 if (scale < 0) 1836 return scale; 1837 1838 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1839 * not only when usecs=0 because of e.g. the following scenario: 1840 * 1841 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1842 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1843 * - then user does `ethtool -C eth0 rx-usecs 100` 1844 * 1845 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1846 * if we want to ignore rx_frames then it has to be set to 0. 1847 */ 1848 if (rx_fr == 1) 1849 rx_fr = 0; 1850 if (tx_fr == 1) 1851 tx_fr = 0; 1852 1853 /* HW requires time limit to be set if frame limit is set */ 1854 if ((tx_fr && !ec->tx_coalesce_usecs) || 1855 (rx_fr && !ec->rx_coalesce_usecs)) 1856 return -EINVAL; 1857 1858 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1859 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1860 1861 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1862 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1863 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1864 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1865 1866 RTL_W16(tp, IntrMitigate, w); 1867 1868 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1869 if (rtl_is_8168evl_up(tp)) { 1870 if (!rx_fr && !tx_fr) 1871 /* disable packet counter */ 1872 tp->cp_cmd |= PktCntrDisable; 1873 else 1874 tp->cp_cmd &= ~PktCntrDisable; 1875 } 1876 1877 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1878 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1879 rtl_pci_commit(tp); 1880 1881 return 0; 1882} 1883 1884static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1885{ 1886 struct rtl8169_private *tp = netdev_priv(dev); 1887 1888 if (!rtl_supports_eee(tp)) 1889 return -EOPNOTSUPP; 1890 1891 return phy_ethtool_get_eee(tp->phydev, data); 1892} 1893 1894static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1895{ 1896 struct rtl8169_private *tp = netdev_priv(dev); 1897 int ret; 1898 1899 if (!rtl_supports_eee(tp)) 1900 return -EOPNOTSUPP; 1901 1902 ret = phy_ethtool_set_eee(tp->phydev, data); 1903 1904 if (!ret) 1905 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1906 MDIO_AN_EEE_ADV); 1907 return ret; 1908} 1909 1910static const struct ethtool_ops rtl8169_ethtool_ops = { 1911 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1912 ETHTOOL_COALESCE_MAX_FRAMES, 1913 .get_drvinfo = rtl8169_get_drvinfo, 1914 .get_regs_len = rtl8169_get_regs_len, 1915 .get_link = ethtool_op_get_link, 1916 .get_coalesce = rtl_get_coalesce, 1917 .set_coalesce = rtl_set_coalesce, 1918 .get_regs = rtl8169_get_regs, 1919 .get_wol = rtl8169_get_wol, 1920 .set_wol = rtl8169_set_wol, 1921 .get_strings = rtl8169_get_strings, 1922 .get_sset_count = rtl8169_get_sset_count, 1923 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1924 .get_ts_info = ethtool_op_get_ts_info, 1925 .nway_reset = phy_ethtool_nway_reset, 1926 .get_eee = rtl8169_get_eee, 1927 .set_eee = rtl8169_set_eee, 1928 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1929 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1930}; 1931 1932static void rtl_enable_eee(struct rtl8169_private *tp) 1933{ 1934 struct phy_device *phydev = tp->phydev; 1935 int adv; 1936 1937 /* respect EEE advertisement the user may have set */ 1938 if (tp->eee_adv >= 0) 1939 adv = tp->eee_adv; 1940 else 1941 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1942 1943 if (adv >= 0) 1944 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1945} 1946 1947static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1948{ 1949 /* 1950 * The driver currently handles the 8168Bf and the 8168Be identically 1951 * but they can be identified more specifically through the test below 1952 * if needed: 1953 * 1954 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1955 * 1956 * Same thing for the 8101Eb and the 8101Ec: 1957 * 1958 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1959 */ 1960 static const struct rtl_mac_info { 1961 u16 mask; 1962 u16 val; 1963 enum mac_version ver; 1964 } mac_info[] = { 1965 /* 8125B family. */ 1966 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1967 1968 /* 8125A family. */ 1969 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1970 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1971 1972 /* RTL8117 */ 1973 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1974 1975 /* 8168EP family. */ 1976 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1977 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1978 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1979 1980 /* 8168H family. */ 1981 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1982 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1983 1984 /* 8168G family. */ 1985 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1986 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1987 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1988 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1989 1990 /* 8168F family. */ 1991 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1992 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1993 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1994 1995 /* 8168E family. */ 1996 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 1997 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 1998 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 1999 2000 /* 8168D family. */ 2001 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2002 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2003 2004 /* 8168DP family. */ 2005 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2006 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2007 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2008 2009 /* 8168C family. */ 2010 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2011 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2012 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2013 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2014 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2015 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2016 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2017 2018 /* 8168B family. */ 2019 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2020 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2021 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2022 2023 /* 8101 family. */ 2024 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2025 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2026 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2027 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2028 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2029 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2030 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2031 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2032 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2033 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2034 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2035 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2036 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2037 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2038 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2039 /* FIXME: where did these entries come from ? -- FR */ 2040 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2041 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2042 2043 /* 8110 family. */ 2044 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2045 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2046 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2047 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2048 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2049 2050 /* Catch-all */ 2051 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2052 }; 2053 const struct rtl_mac_info *p = mac_info; 2054 enum mac_version ver; 2055 2056 while ((xid & p->mask) != p->val) 2057 p++; 2058 ver = p->ver; 2059 2060 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2061 if (ver == RTL_GIGA_MAC_VER_42) 2062 ver = RTL_GIGA_MAC_VER_43; 2063 else if (ver == RTL_GIGA_MAC_VER_45) 2064 ver = RTL_GIGA_MAC_VER_47; 2065 else if (ver == RTL_GIGA_MAC_VER_46) 2066 ver = RTL_GIGA_MAC_VER_48; 2067 } 2068 2069 return ver; 2070} 2071 2072static void rtl_release_firmware(struct rtl8169_private *tp) 2073{ 2074 if (tp->rtl_fw) { 2075 rtl_fw_release_firmware(tp->rtl_fw); 2076 kfree(tp->rtl_fw); 2077 tp->rtl_fw = NULL; 2078 } 2079} 2080 2081void r8169_apply_firmware(struct rtl8169_private *tp) 2082{ 2083 int val; 2084 2085 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2086 if (tp->rtl_fw) { 2087 rtl_fw_write_firmware(tp, tp->rtl_fw); 2088 /* At least one firmware doesn't reset tp->ocp_base. */ 2089 tp->ocp_base = OCP_STD_PHY_BASE; 2090 2091 /* PHY soft reset may still be in progress */ 2092 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2093 !(val & BMCR_RESET), 2094 50000, 600000, true); 2095 } 2096} 2097 2098static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2099{ 2100 /* Adjust EEE LED frequency */ 2101 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2102 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2103 2104 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2105} 2106 2107static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2108{ 2109 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2110 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2111} 2112 2113static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2114{ 2115 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2116} 2117 2118static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2119{ 2120 rtl8125_set_eee_txidle_timer(tp); 2121 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2122} 2123 2124static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2125{ 2126 const u16 w[] = { 2127 addr[0] | (addr[1] << 8), 2128 addr[2] | (addr[3] << 8), 2129 addr[4] | (addr[5] << 8) 2130 }; 2131 2132 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2133 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2134 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2135 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2136} 2137 2138u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2139{ 2140 u16 data1, data2, ioffset; 2141 2142 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2143 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2144 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2145 2146 ioffset = (data2 >> 1) & 0x7ff8; 2147 ioffset |= data2 & 0x0007; 2148 if (data1 & BIT(7)) 2149 ioffset |= BIT(15); 2150 2151 return ioffset; 2152} 2153 2154static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2155{ 2156 set_bit(flag, tp->wk.flags); 2157 schedule_work(&tp->wk.work); 2158} 2159 2160static void rtl8169_init_phy(struct rtl8169_private *tp) 2161{ 2162 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2163 2164 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2165 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2166 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2167 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2168 RTL_W8(tp, 0x82, 0x01); 2169 } 2170 2171 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2172 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2173 tp->pci_dev->subsystem_device == 0xe000) 2174 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2175 2176 /* We may have called phy_speed_down before */ 2177 phy_speed_up(tp->phydev); 2178 2179 if (rtl_supports_eee(tp)) 2180 rtl_enable_eee(tp); 2181 2182 genphy_soft_reset(tp->phydev); 2183} 2184 2185static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2186{ 2187 rtl_unlock_config_regs(tp); 2188 2189 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2190 rtl_pci_commit(tp); 2191 2192 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2193 rtl_pci_commit(tp); 2194 2195 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2196 rtl_rar_exgmac_set(tp, addr); 2197 2198 rtl_lock_config_regs(tp); 2199} 2200 2201static int rtl_set_mac_address(struct net_device *dev, void *p) 2202{ 2203 struct rtl8169_private *tp = netdev_priv(dev); 2204 int ret; 2205 2206 ret = eth_mac_addr(dev, p); 2207 if (ret) 2208 return ret; 2209 2210 rtl_rar_set(tp, dev->dev_addr); 2211 2212 return 0; 2213} 2214 2215static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2216{ 2217 switch (tp->mac_version) { 2218 case RTL_GIGA_MAC_VER_25: 2219 case RTL_GIGA_MAC_VER_26: 2220 case RTL_GIGA_MAC_VER_29: 2221 case RTL_GIGA_MAC_VER_30: 2222 case RTL_GIGA_MAC_VER_32: 2223 case RTL_GIGA_MAC_VER_33: 2224 case RTL_GIGA_MAC_VER_34: 2225 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63: 2226 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2227 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2228 break; 2229 default: 2230 break; 2231 } 2232} 2233 2234static void rtl_pll_power_down(struct rtl8169_private *tp) 2235{ 2236 if (r8168_check_dash(tp)) 2237 return; 2238 2239 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2240 tp->mac_version == RTL_GIGA_MAC_VER_33) 2241 rtl_ephy_write(tp, 0x19, 0xff64); 2242 2243 if (device_may_wakeup(tp_to_dev(tp))) { 2244 phy_speed_down(tp->phydev, false); 2245 rtl_wol_suspend_quirk(tp); 2246 return; 2247 } 2248 2249 switch (tp->mac_version) { 2250 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 2251 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 2252 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33: 2253 case RTL_GIGA_MAC_VER_37: 2254 case RTL_GIGA_MAC_VER_39: 2255 case RTL_GIGA_MAC_VER_43: 2256 case RTL_GIGA_MAC_VER_44: 2257 case RTL_GIGA_MAC_VER_45: 2258 case RTL_GIGA_MAC_VER_46: 2259 case RTL_GIGA_MAC_VER_47: 2260 case RTL_GIGA_MAC_VER_48: 2261 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63: 2262 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2263 break; 2264 case RTL_GIGA_MAC_VER_40: 2265 case RTL_GIGA_MAC_VER_41: 2266 case RTL_GIGA_MAC_VER_49: 2267 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 2268 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2269 break; 2270 default: 2271 break; 2272 } 2273} 2274 2275static void rtl_pll_power_up(struct rtl8169_private *tp) 2276{ 2277 switch (tp->mac_version) { 2278 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 2279 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 2280 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33: 2281 case RTL_GIGA_MAC_VER_37: 2282 case RTL_GIGA_MAC_VER_39: 2283 case RTL_GIGA_MAC_VER_43: 2284 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2285 break; 2286 case RTL_GIGA_MAC_VER_44: 2287 case RTL_GIGA_MAC_VER_45: 2288 case RTL_GIGA_MAC_VER_46: 2289 case RTL_GIGA_MAC_VER_47: 2290 case RTL_GIGA_MAC_VER_48: 2291 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63: 2292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2293 break; 2294 case RTL_GIGA_MAC_VER_40: 2295 case RTL_GIGA_MAC_VER_41: 2296 case RTL_GIGA_MAC_VER_49: 2297 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2298 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 2299 break; 2300 default: 2301 break; 2302 } 2303 2304 phy_resume(tp->phydev); 2305} 2306 2307static void rtl_init_rxcfg(struct rtl8169_private *tp) 2308{ 2309 switch (tp->mac_version) { 2310 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2311 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2312 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2313 break; 2314 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2315 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2316 case RTL_GIGA_MAC_VER_38: 2317 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2318 break; 2319 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2320 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2321 break; 2322 case RTL_GIGA_MAC_VER_61: 2323 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2324 break; 2325 case RTL_GIGA_MAC_VER_63: 2326 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2327 RX_PAUSE_SLOT_ON); 2328 break; 2329 default: 2330 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2331 break; 2332 } 2333} 2334 2335static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2336{ 2337 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2338} 2339 2340static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2341{ 2342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2344} 2345 2346static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2347{ 2348 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2349 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2350} 2351 2352static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2353{ 2354 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2355} 2356 2357static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2358{ 2359 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2360} 2361 2362static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2363{ 2364 RTL_W8(tp, MaxTxPacketSize, 0x24); 2365 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2366 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2367} 2368 2369static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2370{ 2371 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2372 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2373 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2374} 2375 2376static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2377{ 2378 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2379} 2380 2381static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2382{ 2383 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2384} 2385 2386static void rtl_jumbo_config(struct rtl8169_private *tp) 2387{ 2388 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2389 int readrq = 4096; 2390 2391 rtl_unlock_config_regs(tp); 2392 switch (tp->mac_version) { 2393 case RTL_GIGA_MAC_VER_12: 2394 case RTL_GIGA_MAC_VER_17: 2395 if (jumbo) { 2396 readrq = 512; 2397 r8168b_1_hw_jumbo_enable(tp); 2398 } else { 2399 r8168b_1_hw_jumbo_disable(tp); 2400 } 2401 break; 2402 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2403 if (jumbo) { 2404 readrq = 512; 2405 r8168c_hw_jumbo_enable(tp); 2406 } else { 2407 r8168c_hw_jumbo_disable(tp); 2408 } 2409 break; 2410 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2411 if (jumbo) 2412 r8168dp_hw_jumbo_enable(tp); 2413 else 2414 r8168dp_hw_jumbo_disable(tp); 2415 break; 2416 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2417 if (jumbo) { 2418 pcie_set_readrq(tp->pci_dev, 512); 2419 r8168e_hw_jumbo_enable(tp); 2420 } else { 2421 r8168e_hw_jumbo_disable(tp); 2422 } 2423 break; 2424 default: 2425 break; 2426 } 2427 rtl_lock_config_regs(tp); 2428 2429 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2430 pcie_set_readrq(tp->pci_dev, readrq); 2431 2432 /* Chip doesn't support pause in jumbo mode */ 2433 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2434 tp->phydev->advertising, !jumbo); 2435 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2436 tp->phydev->advertising, !jumbo); 2437 phy_start_aneg(tp->phydev); 2438} 2439 2440DECLARE_RTL_COND(rtl_chipcmd_cond) 2441{ 2442 return RTL_R8(tp, ChipCmd) & CmdReset; 2443} 2444 2445static void rtl_hw_reset(struct rtl8169_private *tp) 2446{ 2447 RTL_W8(tp, ChipCmd, CmdReset); 2448 2449 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2450} 2451 2452static void rtl_request_firmware(struct rtl8169_private *tp) 2453{ 2454 struct rtl_fw *rtl_fw; 2455 2456 /* firmware loaded already or no firmware available */ 2457 if (tp->rtl_fw || !tp->fw_name) 2458 return; 2459 2460 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2461 if (!rtl_fw) 2462 return; 2463 2464 rtl_fw->phy_write = rtl_writephy; 2465 rtl_fw->phy_read = rtl_readphy; 2466 rtl_fw->mac_mcu_write = mac_mcu_write; 2467 rtl_fw->mac_mcu_read = mac_mcu_read; 2468 rtl_fw->fw_name = tp->fw_name; 2469 rtl_fw->dev = tp_to_dev(tp); 2470 2471 if (rtl_fw_request_firmware(rtl_fw)) 2472 kfree(rtl_fw); 2473 else 2474 tp->rtl_fw = rtl_fw; 2475} 2476 2477static void rtl_rx_close(struct rtl8169_private *tp) 2478{ 2479 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2480} 2481 2482DECLARE_RTL_COND(rtl_npq_cond) 2483{ 2484 return RTL_R8(tp, TxPoll) & NPQ; 2485} 2486 2487DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2488{ 2489 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2490} 2491 2492DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2493{ 2494 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2495} 2496 2497DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2498{ 2499 /* IntrMitigate has new functionality on RTL8125 */ 2500 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2501} 2502 2503static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2504{ 2505 switch (tp->mac_version) { 2506 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2507 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2508 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2509 break; 2510 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2511 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2512 break; 2513 case RTL_GIGA_MAC_VER_63: 2514 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2515 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2516 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2517 break; 2518 default: 2519 break; 2520 } 2521} 2522 2523static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2524{ 2525 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2526 fsleep(2000); 2527 rtl_wait_txrx_fifo_empty(tp); 2528} 2529 2530static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2531{ 2532 u32 val = TX_DMA_BURST << TxDMAShift | 2533 InterFrameGap << TxInterFrameGapShift; 2534 2535 if (rtl_is_8168evl_up(tp)) 2536 val |= TXCFG_AUTO_FIFO; 2537 2538 RTL_W32(tp, TxConfig, val); 2539} 2540 2541static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2542{ 2543 /* Low hurts. Let's disable the filtering. */ 2544 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2545} 2546 2547static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2548{ 2549 /* 2550 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2551 * register to be written before TxDescAddrLow to work. 2552 * Switching from MMIO to I/O access fixes the issue as well. 2553 */ 2554 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2555 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2556 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2557 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2558} 2559 2560static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2561{ 2562 u32 val; 2563 2564 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2565 val = 0x000fff00; 2566 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2567 val = 0x00ffff00; 2568 else 2569 return; 2570 2571 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2572 val |= 0xff; 2573 2574 RTL_W32(tp, 0x7c, val); 2575} 2576 2577static void rtl_set_rx_mode(struct net_device *dev) 2578{ 2579 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2580 /* Multicast hash filter */ 2581 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2582 struct rtl8169_private *tp = netdev_priv(dev); 2583 u32 tmp; 2584 2585 if (dev->flags & IFF_PROMISC) { 2586 rx_mode |= AcceptAllPhys; 2587 } else if (!(dev->flags & IFF_MULTICAST)) { 2588 rx_mode &= ~AcceptMulticast; 2589 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2590 dev->flags & IFF_ALLMULTI || 2591 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2592 /* accept all multicasts */ 2593 } else if (netdev_mc_empty(dev)) { 2594 rx_mode &= ~AcceptMulticast; 2595 } else { 2596 struct netdev_hw_addr *ha; 2597 2598 mc_filter[1] = mc_filter[0] = 0; 2599 netdev_for_each_mc_addr(ha, dev) { 2600 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2601 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2602 } 2603 2604 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2605 tmp = mc_filter[0]; 2606 mc_filter[0] = swab32(mc_filter[1]); 2607 mc_filter[1] = swab32(tmp); 2608 } 2609 } 2610 2611 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2612 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2613 2614 tmp = RTL_R32(tp, RxConfig); 2615 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2616} 2617 2618DECLARE_RTL_COND(rtl_csiar_cond) 2619{ 2620 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2621} 2622 2623static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2624{ 2625 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2626 2627 RTL_W32(tp, CSIDR, value); 2628 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2629 CSIAR_BYTE_ENABLE | func << 16); 2630 2631 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2632} 2633 2634static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2635{ 2636 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2637 2638 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2639 CSIAR_BYTE_ENABLE); 2640 2641 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2642 RTL_R32(tp, CSIDR) : ~0; 2643} 2644 2645static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2646{ 2647 struct pci_dev *pdev = tp->pci_dev; 2648 u32 csi; 2649 2650 /* According to Realtek the value at config space address 0x070f 2651 * controls the L0s/L1 entrance latency. We try standard ECAM access 2652 * first and if it fails fall back to CSI. 2653 */ 2654 if (pdev->cfg_size > 0x070f && 2655 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2656 return; 2657 2658 netdev_notice_once(tp->dev, 2659 "No native access to PCI extended config space, falling back to CSI\n"); 2660 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2661 rtl_csi_write(tp, 0x070c, csi | val << 24); 2662} 2663 2664static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2665{ 2666 rtl_csi_access_enable(tp, 0x27); 2667} 2668 2669struct ephy_info { 2670 unsigned int offset; 2671 u16 mask; 2672 u16 bits; 2673}; 2674 2675static void __rtl_ephy_init(struct rtl8169_private *tp, 2676 const struct ephy_info *e, int len) 2677{ 2678 u16 w; 2679 2680 while (len-- > 0) { 2681 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2682 rtl_ephy_write(tp, e->offset, w); 2683 e++; 2684 } 2685} 2686 2687#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2688 2689static void rtl_disable_clock_request(struct rtl8169_private *tp) 2690{ 2691 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2692 PCI_EXP_LNKCTL_CLKREQ_EN); 2693} 2694 2695static void rtl_enable_clock_request(struct rtl8169_private *tp) 2696{ 2697 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2698 PCI_EXP_LNKCTL_CLKREQ_EN); 2699} 2700 2701static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2702{ 2703 /* work around an issue when PCI reset occurs during L2/L3 state */ 2704 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2705} 2706 2707static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2708{ 2709 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2710 if (enable && tp->aspm_manageable) { 2711 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2712 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2713 } else { 2714 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2715 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2716 } 2717 2718 udelay(10); 2719} 2720 2721static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2722 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2723{ 2724 /* Usage of dynamic vs. static FIFO is controlled by bit 2725 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2726 */ 2727 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2728 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2729} 2730 2731static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2732 u8 low, u8 high) 2733{ 2734 /* FIFO thresholds for pause flow control */ 2735 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2736 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2737} 2738 2739static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2740{ 2741 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2742} 2743 2744static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2745{ 2746 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2747 2748 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2749 2750 rtl_disable_clock_request(tp); 2751} 2752 2753static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2754{ 2755 static const struct ephy_info e_info_8168cp[] = { 2756 { 0x01, 0, 0x0001 }, 2757 { 0x02, 0x0800, 0x1000 }, 2758 { 0x03, 0, 0x0042 }, 2759 { 0x06, 0x0080, 0x0000 }, 2760 { 0x07, 0, 0x2000 } 2761 }; 2762 2763 rtl_set_def_aspm_entry_latency(tp); 2764 2765 rtl_ephy_init(tp, e_info_8168cp); 2766 2767 __rtl_hw_start_8168cp(tp); 2768} 2769 2770static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2771{ 2772 rtl_set_def_aspm_entry_latency(tp); 2773 2774 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2775} 2776 2777static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2778{ 2779 rtl_set_def_aspm_entry_latency(tp); 2780 2781 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2782 2783 /* Magic. */ 2784 RTL_W8(tp, DBG_REG, 0x20); 2785} 2786 2787static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2788{ 2789 static const struct ephy_info e_info_8168c_1[] = { 2790 { 0x02, 0x0800, 0x1000 }, 2791 { 0x03, 0, 0x0002 }, 2792 { 0x06, 0x0080, 0x0000 } 2793 }; 2794 2795 rtl_set_def_aspm_entry_latency(tp); 2796 2797 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2798 2799 rtl_ephy_init(tp, e_info_8168c_1); 2800 2801 __rtl_hw_start_8168cp(tp); 2802} 2803 2804static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2805{ 2806 static const struct ephy_info e_info_8168c_2[] = { 2807 { 0x01, 0, 0x0001 }, 2808 { 0x03, 0x0400, 0x0020 } 2809 }; 2810 2811 rtl_set_def_aspm_entry_latency(tp); 2812 2813 rtl_ephy_init(tp, e_info_8168c_2); 2814 2815 __rtl_hw_start_8168cp(tp); 2816} 2817 2818static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2819{ 2820 rtl_hw_start_8168c_2(tp); 2821} 2822 2823static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2824{ 2825 rtl_set_def_aspm_entry_latency(tp); 2826 2827 __rtl_hw_start_8168cp(tp); 2828} 2829 2830static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2831{ 2832 rtl_set_def_aspm_entry_latency(tp); 2833 2834 rtl_disable_clock_request(tp); 2835} 2836 2837static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2838{ 2839 static const struct ephy_info e_info_8168d_4[] = { 2840 { 0x0b, 0x0000, 0x0048 }, 2841 { 0x19, 0x0020, 0x0050 }, 2842 { 0x0c, 0x0100, 0x0020 }, 2843 { 0x10, 0x0004, 0x0000 }, 2844 }; 2845 2846 rtl_set_def_aspm_entry_latency(tp); 2847 2848 rtl_ephy_init(tp, e_info_8168d_4); 2849 2850 rtl_enable_clock_request(tp); 2851} 2852 2853static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2854{ 2855 static const struct ephy_info e_info_8168e_1[] = { 2856 { 0x00, 0x0200, 0x0100 }, 2857 { 0x00, 0x0000, 0x0004 }, 2858 { 0x06, 0x0002, 0x0001 }, 2859 { 0x06, 0x0000, 0x0030 }, 2860 { 0x07, 0x0000, 0x2000 }, 2861 { 0x00, 0x0000, 0x0020 }, 2862 { 0x03, 0x5800, 0x2000 }, 2863 { 0x03, 0x0000, 0x0001 }, 2864 { 0x01, 0x0800, 0x1000 }, 2865 { 0x07, 0x0000, 0x4000 }, 2866 { 0x1e, 0x0000, 0x2000 }, 2867 { 0x19, 0xffff, 0xfe6c }, 2868 { 0x0a, 0x0000, 0x0040 } 2869 }; 2870 2871 rtl_set_def_aspm_entry_latency(tp); 2872 2873 rtl_ephy_init(tp, e_info_8168e_1); 2874 2875 rtl_disable_clock_request(tp); 2876 2877 /* Reset tx FIFO pointer */ 2878 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2879 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2880 2881 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2882} 2883 2884static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2885{ 2886 static const struct ephy_info e_info_8168e_2[] = { 2887 { 0x09, 0x0000, 0x0080 }, 2888 { 0x19, 0x0000, 0x0224 }, 2889 { 0x00, 0x0000, 0x0004 }, 2890 { 0x0c, 0x3df0, 0x0200 }, 2891 }; 2892 2893 rtl_set_def_aspm_entry_latency(tp); 2894 2895 rtl_ephy_init(tp, e_info_8168e_2); 2896 2897 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2898 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2899 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2900 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2901 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2902 rtl_reset_packet_filter(tp); 2903 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2904 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2905 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2906 2907 rtl_disable_clock_request(tp); 2908 2909 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2910 2911 rtl8168_config_eee_mac(tp); 2912 2913 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2914 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2915 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2916 2917 rtl_hw_aspm_clkreq_enable(tp, true); 2918} 2919 2920static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2921{ 2922 rtl_set_def_aspm_entry_latency(tp); 2923 2924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2926 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2927 rtl_reset_packet_filter(tp); 2928 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2929 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2930 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2931 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2932 2933 rtl_disable_clock_request(tp); 2934 2935 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2936 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2937 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2938 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2939 2940 rtl8168_config_eee_mac(tp); 2941} 2942 2943static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2944{ 2945 static const struct ephy_info e_info_8168f_1[] = { 2946 { 0x06, 0x00c0, 0x0020 }, 2947 { 0x08, 0x0001, 0x0002 }, 2948 { 0x09, 0x0000, 0x0080 }, 2949 { 0x19, 0x0000, 0x0224 }, 2950 { 0x00, 0x0000, 0x0008 }, 2951 { 0x0c, 0x3df0, 0x0200 }, 2952 }; 2953 2954 rtl_hw_start_8168f(tp); 2955 2956 rtl_ephy_init(tp, e_info_8168f_1); 2957 2958 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2959} 2960 2961static void rtl_hw_start_8411(struct rtl8169_private *tp) 2962{ 2963 static const struct ephy_info e_info_8168f_1[] = { 2964 { 0x06, 0x00c0, 0x0020 }, 2965 { 0x0f, 0xffff, 0x5200 }, 2966 { 0x19, 0x0000, 0x0224 }, 2967 { 0x00, 0x0000, 0x0008 }, 2968 { 0x0c, 0x3df0, 0x0200 }, 2969 }; 2970 2971 rtl_hw_start_8168f(tp); 2972 rtl_pcie_state_l2l3_disable(tp); 2973 2974 rtl_ephy_init(tp, e_info_8168f_1); 2975 2976 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2977} 2978 2979static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2980{ 2981 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2982 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2983 2984 rtl_set_def_aspm_entry_latency(tp); 2985 2986 rtl_reset_packet_filter(tp); 2987 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2988 2989 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2990 2991 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2992 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2993 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2994 2995 rtl8168_config_eee_mac(tp); 2996 2997 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2998 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2999 3000 rtl_pcie_state_l2l3_disable(tp); 3001} 3002 3003static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3004{ 3005 static const struct ephy_info e_info_8168g_1[] = { 3006 { 0x00, 0x0008, 0x0000 }, 3007 { 0x0c, 0x3ff0, 0x0820 }, 3008 { 0x1e, 0x0000, 0x0001 }, 3009 { 0x19, 0x8000, 0x0000 } 3010 }; 3011 3012 rtl_hw_start_8168g(tp); 3013 3014 /* disable aspm and clock request before access ephy */ 3015 rtl_hw_aspm_clkreq_enable(tp, false); 3016 rtl_ephy_init(tp, e_info_8168g_1); 3017 rtl_hw_aspm_clkreq_enable(tp, true); 3018} 3019 3020static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3021{ 3022 static const struct ephy_info e_info_8168g_2[] = { 3023 { 0x00, 0x0008, 0x0000 }, 3024 { 0x0c, 0x3ff0, 0x0820 }, 3025 { 0x19, 0xffff, 0x7c00 }, 3026 { 0x1e, 0xffff, 0x20eb }, 3027 { 0x0d, 0xffff, 0x1666 }, 3028 { 0x00, 0xffff, 0x10a3 }, 3029 { 0x06, 0xffff, 0xf050 }, 3030 { 0x04, 0x0000, 0x0010 }, 3031 { 0x1d, 0x4000, 0x0000 }, 3032 }; 3033 3034 rtl_hw_start_8168g(tp); 3035 3036 /* disable aspm and clock request before access ephy */ 3037 rtl_hw_aspm_clkreq_enable(tp, false); 3038 rtl_ephy_init(tp, e_info_8168g_2); 3039} 3040 3041static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3042{ 3043 static const struct ephy_info e_info_8411_2[] = { 3044 { 0x00, 0x0008, 0x0000 }, 3045 { 0x0c, 0x37d0, 0x0820 }, 3046 { 0x1e, 0x0000, 0x0001 }, 3047 { 0x19, 0x8021, 0x0000 }, 3048 { 0x1e, 0x0000, 0x2000 }, 3049 { 0x0d, 0x0100, 0x0200 }, 3050 { 0x00, 0x0000, 0x0080 }, 3051 { 0x06, 0x0000, 0x0010 }, 3052 { 0x04, 0x0000, 0x0010 }, 3053 { 0x1d, 0x0000, 0x4000 }, 3054 }; 3055 3056 rtl_hw_start_8168g(tp); 3057 3058 /* disable aspm and clock request before access ephy */ 3059 rtl_hw_aspm_clkreq_enable(tp, false); 3060 rtl_ephy_init(tp, e_info_8411_2); 3061 3062 /* The following Realtek-provided magic fixes an issue with the RX unit 3063 * getting confused after the PHY having been powered-down. 3064 */ 3065 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3066 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3067 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3068 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3069 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3070 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3071 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3072 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3073 mdelay(3); 3074 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3075 3076 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3077 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3078 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3079 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3080 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3081 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3082 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3083 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3084 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3085 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3086 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3087 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3088 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3089 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3090 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3091 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3092 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3093 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3094 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3095 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3096 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3097 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3098 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3099 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3100 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3101 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3102 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3103 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3104 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3105 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3106 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3107 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3108 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3109 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3110 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3111 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3112 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3113 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3114 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3115 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3116 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3117 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3118 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3119 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3120 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3121 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3122 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3123 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3124 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3125 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3126 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3127 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3128 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3129 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3130 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3131 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3132 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3133 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3134 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3135 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3136 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3137 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3138 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3139 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3140 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3141 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3142 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3143 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3144 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3145 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3146 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3147 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3148 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3149 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3150 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3151 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3152 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3153 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3154 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3155 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3156 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3157 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3158 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3159 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3160 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3161 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3162 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3163 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3164 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3165 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3166 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3167 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3168 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3169 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3170 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3171 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3172 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3173 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3174 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3175 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3176 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3177 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3178 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3179 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3180 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3181 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3182 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3183 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3184 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3185 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3186 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3187 3188 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3189 3190 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3191 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3192 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3193 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3194 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3195 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3196 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3197 3198 rtl_hw_aspm_clkreq_enable(tp, true); 3199} 3200 3201static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3202{ 3203 static const struct ephy_info e_info_8168h_1[] = { 3204 { 0x1e, 0x0800, 0x0001 }, 3205 { 0x1d, 0x0000, 0x0800 }, 3206 { 0x05, 0xffff, 0x2089 }, 3207 { 0x06, 0xffff, 0x5881 }, 3208 { 0x04, 0xffff, 0x854a }, 3209 { 0x01, 0xffff, 0x068b } 3210 }; 3211 int rg_saw_cnt; 3212 3213 /* disable aspm and clock request before access ephy */ 3214 rtl_hw_aspm_clkreq_enable(tp, false); 3215 rtl_ephy_init(tp, e_info_8168h_1); 3216 3217 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3218 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3219 3220 rtl_set_def_aspm_entry_latency(tp); 3221 3222 rtl_reset_packet_filter(tp); 3223 3224 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3225 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3226 3227 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3228 3229 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3230 3231 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3232 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3233 3234 rtl8168_config_eee_mac(tp); 3235 3236 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3237 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3238 3239 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3240 3241 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3242 3243 rtl_pcie_state_l2l3_disable(tp); 3244 3245 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3246 if (rg_saw_cnt > 0) { 3247 u16 sw_cnt_1ms_ini; 3248 3249 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3250 sw_cnt_1ms_ini &= 0x0fff; 3251 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3252 } 3253 3254 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3255 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3256 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3257 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3258 3259 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3260 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3261 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3262 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3263 3264 rtl_hw_aspm_clkreq_enable(tp, true); 3265} 3266 3267static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3268{ 3269 rtl8168ep_stop_cmac(tp); 3270 3271 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3272 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3273 3274 rtl_set_def_aspm_entry_latency(tp); 3275 3276 rtl_reset_packet_filter(tp); 3277 3278 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3279 3280 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3281 3282 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3283 3284 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3285 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3286 3287 rtl8168_config_eee_mac(tp); 3288 3289 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3290 3291 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3292 3293 rtl_pcie_state_l2l3_disable(tp); 3294} 3295 3296static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3297{ 3298 static const struct ephy_info e_info_8168ep_1[] = { 3299 { 0x00, 0xffff, 0x10ab }, 3300 { 0x06, 0xffff, 0xf030 }, 3301 { 0x08, 0xffff, 0x2006 }, 3302 { 0x0d, 0xffff, 0x1666 }, 3303 { 0x0c, 0x3ff0, 0x0000 } 3304 }; 3305 3306 /* disable aspm and clock request before access ephy */ 3307 rtl_hw_aspm_clkreq_enable(tp, false); 3308 rtl_ephy_init(tp, e_info_8168ep_1); 3309 3310 rtl_hw_start_8168ep(tp); 3311 3312 rtl_hw_aspm_clkreq_enable(tp, true); 3313} 3314 3315static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3316{ 3317 static const struct ephy_info e_info_8168ep_2[] = { 3318 { 0x00, 0xffff, 0x10a3 }, 3319 { 0x19, 0xffff, 0xfc00 }, 3320 { 0x1e, 0xffff, 0x20ea } 3321 }; 3322 3323 /* disable aspm and clock request before access ephy */ 3324 rtl_hw_aspm_clkreq_enable(tp, false); 3325 rtl_ephy_init(tp, e_info_8168ep_2); 3326 3327 rtl_hw_start_8168ep(tp); 3328 3329 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3330 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3331 3332 rtl_hw_aspm_clkreq_enable(tp, true); 3333} 3334 3335static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3336{ 3337 static const struct ephy_info e_info_8168ep_3[] = { 3338 { 0x00, 0x0000, 0x0080 }, 3339 { 0x0d, 0x0100, 0x0200 }, 3340 { 0x19, 0x8021, 0x0000 }, 3341 { 0x1e, 0x0000, 0x2000 }, 3342 }; 3343 3344 /* disable aspm and clock request before access ephy */ 3345 rtl_hw_aspm_clkreq_enable(tp, false); 3346 rtl_ephy_init(tp, e_info_8168ep_3); 3347 3348 rtl_hw_start_8168ep(tp); 3349 3350 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3351 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3352 3353 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3354 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3355 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3356 3357 rtl_hw_aspm_clkreq_enable(tp, true); 3358} 3359 3360static void rtl_hw_start_8117(struct rtl8169_private *tp) 3361{ 3362 static const struct ephy_info e_info_8117[] = { 3363 { 0x19, 0x0040, 0x1100 }, 3364 { 0x59, 0x0040, 0x1100 }, 3365 }; 3366 int rg_saw_cnt; 3367 3368 rtl8168ep_stop_cmac(tp); 3369 3370 /* disable aspm and clock request before access ephy */ 3371 rtl_hw_aspm_clkreq_enable(tp, false); 3372 rtl_ephy_init(tp, e_info_8117); 3373 3374 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3375 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3376 3377 rtl_set_def_aspm_entry_latency(tp); 3378 3379 rtl_reset_packet_filter(tp); 3380 3381 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3382 3383 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3384 3385 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3386 3387 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3388 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3389 3390 rtl8168_config_eee_mac(tp); 3391 3392 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3393 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3394 3395 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3396 3397 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3398 3399 rtl_pcie_state_l2l3_disable(tp); 3400 3401 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3402 if (rg_saw_cnt > 0) { 3403 u16 sw_cnt_1ms_ini; 3404 3405 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3406 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3407 } 3408 3409 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3410 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3411 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3412 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3413 3414 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3415 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3416 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3417 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3418 3419 /* firmware is for MAC only */ 3420 r8169_apply_firmware(tp); 3421 3422 rtl_hw_aspm_clkreq_enable(tp, true); 3423} 3424 3425static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3426{ 3427 static const struct ephy_info e_info_8102e_1[] = { 3428 { 0x01, 0, 0x6e65 }, 3429 { 0x02, 0, 0x091f }, 3430 { 0x03, 0, 0xc2f9 }, 3431 { 0x06, 0, 0xafb5 }, 3432 { 0x07, 0, 0x0e00 }, 3433 { 0x19, 0, 0xec80 }, 3434 { 0x01, 0, 0x2e65 }, 3435 { 0x01, 0, 0x6e65 } 3436 }; 3437 u8 cfg1; 3438 3439 rtl_set_def_aspm_entry_latency(tp); 3440 3441 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3442 3443 RTL_W8(tp, Config1, 3444 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3445 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3446 3447 cfg1 = RTL_R8(tp, Config1); 3448 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3449 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3450 3451 rtl_ephy_init(tp, e_info_8102e_1); 3452} 3453 3454static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3455{ 3456 rtl_set_def_aspm_entry_latency(tp); 3457 3458 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3459 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3460} 3461 3462static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3463{ 3464 rtl_hw_start_8102e_2(tp); 3465 3466 rtl_ephy_write(tp, 0x03, 0xc2f9); 3467} 3468 3469static void rtl_hw_start_8401(struct rtl8169_private *tp) 3470{ 3471 static const struct ephy_info e_info_8401[] = { 3472 { 0x01, 0xffff, 0x6fe5 }, 3473 { 0x03, 0xffff, 0x0599 }, 3474 { 0x06, 0xffff, 0xaf25 }, 3475 { 0x07, 0xffff, 0x8e68 }, 3476 }; 3477 3478 rtl_ephy_init(tp, e_info_8401); 3479 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3480} 3481 3482static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3483{ 3484 static const struct ephy_info e_info_8105e_1[] = { 3485 { 0x07, 0, 0x4000 }, 3486 { 0x19, 0, 0x0200 }, 3487 { 0x19, 0, 0x0020 }, 3488 { 0x1e, 0, 0x2000 }, 3489 { 0x03, 0, 0x0001 }, 3490 { 0x19, 0, 0x0100 }, 3491 { 0x19, 0, 0x0004 }, 3492 { 0x0a, 0, 0x0020 } 3493 }; 3494 3495 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3496 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3497 3498 /* Disable Early Tally Counter */ 3499 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3500 3501 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3502 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3503 3504 rtl_ephy_init(tp, e_info_8105e_1); 3505 3506 rtl_pcie_state_l2l3_disable(tp); 3507} 3508 3509static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3510{ 3511 rtl_hw_start_8105e_1(tp); 3512 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3513} 3514 3515static void rtl_hw_start_8402(struct rtl8169_private *tp) 3516{ 3517 static const struct ephy_info e_info_8402[] = { 3518 { 0x19, 0xffff, 0xff64 }, 3519 { 0x1e, 0, 0x4000 } 3520 }; 3521 3522 rtl_set_def_aspm_entry_latency(tp); 3523 3524 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3525 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3526 3527 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3528 3529 rtl_ephy_init(tp, e_info_8402); 3530 3531 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3532 rtl_reset_packet_filter(tp); 3533 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3534 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3535 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3536 3537 /* disable EEE */ 3538 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3539 3540 rtl_pcie_state_l2l3_disable(tp); 3541} 3542 3543static void rtl_hw_start_8106(struct rtl8169_private *tp) 3544{ 3545 rtl_hw_aspm_clkreq_enable(tp, false); 3546 3547 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3548 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3549 3550 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3551 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3552 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3553 3554 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3555 3556 /* disable EEE */ 3557 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3558 3559 rtl_pcie_state_l2l3_disable(tp); 3560 rtl_hw_aspm_clkreq_enable(tp, true); 3561} 3562 3563DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3564{ 3565 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3566} 3567 3568static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3569{ 3570 rtl_pcie_state_l2l3_disable(tp); 3571 3572 RTL_W16(tp, 0x382, 0x221b); 3573 RTL_W8(tp, 0x4500, 0); 3574 RTL_W16(tp, 0x4800, 0); 3575 3576 /* disable UPS */ 3577 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3578 3579 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3580 3581 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3582 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3583 3584 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3585 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3586 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3587 3588 /* disable new tx descriptor format */ 3589 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3590 3591 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3592 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3593 else 3594 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3595 3596 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3597 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3598 else 3599 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3600 3601 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3602 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3603 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3604 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3605 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3606 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3607 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3608 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3609 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3610 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3611 3612 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3613 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3614 udelay(1); 3615 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3616 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3617 3618 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3619 3620 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3621 3622 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3623 rtl8125b_config_eee_mac(tp); 3624 else 3625 rtl8125a_config_eee_mac(tp); 3626 3627 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3628 udelay(10); 3629} 3630 3631static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3632{ 3633 static const struct ephy_info e_info_8125a_1[] = { 3634 { 0x01, 0xffff, 0xa812 }, 3635 { 0x09, 0xffff, 0x520c }, 3636 { 0x04, 0xffff, 0xd000 }, 3637 { 0x0d, 0xffff, 0xf702 }, 3638 { 0x0a, 0xffff, 0x8653 }, 3639 { 0x06, 0xffff, 0x001e }, 3640 { 0x08, 0xffff, 0x3595 }, 3641 { 0x20, 0xffff, 0x9455 }, 3642 { 0x21, 0xffff, 0x99ff }, 3643 { 0x02, 0xffff, 0x6046 }, 3644 { 0x29, 0xffff, 0xfe00 }, 3645 { 0x23, 0xffff, 0xab62 }, 3646 3647 { 0x41, 0xffff, 0xa80c }, 3648 { 0x49, 0xffff, 0x520c }, 3649 { 0x44, 0xffff, 0xd000 }, 3650 { 0x4d, 0xffff, 0xf702 }, 3651 { 0x4a, 0xffff, 0x8653 }, 3652 { 0x46, 0xffff, 0x001e }, 3653 { 0x48, 0xffff, 0x3595 }, 3654 { 0x60, 0xffff, 0x9455 }, 3655 { 0x61, 0xffff, 0x99ff }, 3656 { 0x42, 0xffff, 0x6046 }, 3657 { 0x69, 0xffff, 0xfe00 }, 3658 { 0x63, 0xffff, 0xab62 }, 3659 }; 3660 3661 rtl_set_def_aspm_entry_latency(tp); 3662 3663 /* disable aspm and clock request before access ephy */ 3664 rtl_hw_aspm_clkreq_enable(tp, false); 3665 rtl_ephy_init(tp, e_info_8125a_1); 3666 3667 rtl_hw_start_8125_common(tp); 3668 rtl_hw_aspm_clkreq_enable(tp, true); 3669} 3670 3671static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3672{ 3673 static const struct ephy_info e_info_8125a_2[] = { 3674 { 0x04, 0xffff, 0xd000 }, 3675 { 0x0a, 0xffff, 0x8653 }, 3676 { 0x23, 0xffff, 0xab66 }, 3677 { 0x20, 0xffff, 0x9455 }, 3678 { 0x21, 0xffff, 0x99ff }, 3679 { 0x29, 0xffff, 0xfe04 }, 3680 3681 { 0x44, 0xffff, 0xd000 }, 3682 { 0x4a, 0xffff, 0x8653 }, 3683 { 0x63, 0xffff, 0xab66 }, 3684 { 0x60, 0xffff, 0x9455 }, 3685 { 0x61, 0xffff, 0x99ff }, 3686 { 0x69, 0xffff, 0xfe04 }, 3687 }; 3688 3689 rtl_set_def_aspm_entry_latency(tp); 3690 3691 /* disable aspm and clock request before access ephy */ 3692 rtl_hw_aspm_clkreq_enable(tp, false); 3693 rtl_ephy_init(tp, e_info_8125a_2); 3694 3695 rtl_hw_start_8125_common(tp); 3696 rtl_hw_aspm_clkreq_enable(tp, true); 3697} 3698 3699static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3700{ 3701 static const struct ephy_info e_info_8125b[] = { 3702 { 0x0b, 0xffff, 0xa908 }, 3703 { 0x1e, 0xffff, 0x20eb }, 3704 { 0x4b, 0xffff, 0xa908 }, 3705 { 0x5e, 0xffff, 0x20eb }, 3706 { 0x22, 0x0030, 0x0020 }, 3707 { 0x62, 0x0030, 0x0020 }, 3708 }; 3709 3710 rtl_set_def_aspm_entry_latency(tp); 3711 rtl_hw_aspm_clkreq_enable(tp, false); 3712 3713 rtl_ephy_init(tp, e_info_8125b); 3714 rtl_hw_start_8125_common(tp); 3715 3716 rtl_hw_aspm_clkreq_enable(tp, true); 3717} 3718 3719static void rtl_hw_config(struct rtl8169_private *tp) 3720{ 3721 static const rtl_generic_fct hw_configs[] = { 3722 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3723 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3724 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3725 [RTL_GIGA_MAC_VER_10] = NULL, 3726 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3727 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3728 [RTL_GIGA_MAC_VER_13] = NULL, 3729 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3730 [RTL_GIGA_MAC_VER_16] = NULL, 3731 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3732 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3733 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3734 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3735 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3736 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3737 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3738 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3739 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3740 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3741 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3742 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3743 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3744 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3745 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3746 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3747 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3748 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3749 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3750 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3751 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3752 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3753 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3754 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3755 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3756 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3757 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3758 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3759 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3760 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3761 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3762 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3763 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3764 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3765 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3766 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3767 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3768 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3769 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3770 }; 3771 3772 if (hw_configs[tp->mac_version]) 3773 hw_configs[tp->mac_version](tp); 3774} 3775 3776static void rtl_hw_start_8125(struct rtl8169_private *tp) 3777{ 3778 int i; 3779 3780 /* disable interrupt coalescing */ 3781 for (i = 0xa00; i < 0xb00; i += 4) 3782 RTL_W32(tp, i, 0); 3783 3784 rtl_hw_config(tp); 3785} 3786 3787static void rtl_hw_start_8168(struct rtl8169_private *tp) 3788{ 3789 if (rtl_is_8168evl_up(tp)) 3790 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3791 else 3792 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3793 3794 rtl_hw_config(tp); 3795 3796 /* disable interrupt coalescing */ 3797 RTL_W16(tp, IntrMitigate, 0x0000); 3798} 3799 3800static void rtl_hw_start_8169(struct rtl8169_private *tp) 3801{ 3802 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3803 3804 tp->cp_cmd |= PCIMulRW; 3805 3806 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3807 tp->mac_version == RTL_GIGA_MAC_VER_03) 3808 tp->cp_cmd |= EnAnaPLL; 3809 3810 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3811 3812 rtl8169_set_magic_reg(tp); 3813 3814 /* disable interrupt coalescing */ 3815 RTL_W16(tp, IntrMitigate, 0x0000); 3816} 3817 3818static void rtl_hw_start(struct rtl8169_private *tp) 3819{ 3820 rtl_unlock_config_regs(tp); 3821 3822 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3823 3824 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3825 rtl_hw_start_8169(tp); 3826 else if (rtl_is_8125(tp)) 3827 rtl_hw_start_8125(tp); 3828 else 3829 rtl_hw_start_8168(tp); 3830 3831 rtl_set_rx_max_size(tp); 3832 rtl_set_rx_tx_desc_registers(tp); 3833 rtl_lock_config_regs(tp); 3834 3835 rtl_jumbo_config(tp); 3836 3837 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3838 rtl_pci_commit(tp); 3839 3840 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3841 rtl_init_rxcfg(tp); 3842 rtl_set_tx_config_registers(tp); 3843 rtl_set_rx_config_features(tp, tp->dev->features); 3844 rtl_set_rx_mode(tp->dev); 3845 rtl_irq_enable(tp); 3846} 3847 3848static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3849{ 3850 struct rtl8169_private *tp = netdev_priv(dev); 3851 3852 dev->mtu = new_mtu; 3853 netdev_update_features(dev); 3854 rtl_jumbo_config(tp); 3855 3856 switch (tp->mac_version) { 3857 case RTL_GIGA_MAC_VER_61: 3858 case RTL_GIGA_MAC_VER_63: 3859 rtl8125_set_eee_txidle_timer(tp); 3860 break; 3861 default: 3862 break; 3863 } 3864 3865 return 0; 3866} 3867 3868static void rtl8169_mark_to_asic(struct RxDesc *desc) 3869{ 3870 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3871 3872 desc->opts2 = 0; 3873 /* Force memory writes to complete before releasing descriptor */ 3874 dma_wmb(); 3875 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3876} 3877 3878static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3879 struct RxDesc *desc) 3880{ 3881 struct device *d = tp_to_dev(tp); 3882 int node = dev_to_node(d); 3883 dma_addr_t mapping; 3884 struct page *data; 3885 3886 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3887 if (!data) 3888 return NULL; 3889 3890 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3891 if (unlikely(dma_mapping_error(d, mapping))) { 3892 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3893 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3894 return NULL; 3895 } 3896 3897 desc->addr = cpu_to_le64(mapping); 3898 rtl8169_mark_to_asic(desc); 3899 3900 return data; 3901} 3902 3903static void rtl8169_rx_clear(struct rtl8169_private *tp) 3904{ 3905 unsigned int i; 3906 3907 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3908 dma_unmap_page(tp_to_dev(tp), 3909 le64_to_cpu(tp->RxDescArray[i].addr), 3910 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3911 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3912 tp->Rx_databuff[i] = NULL; 3913 tp->RxDescArray[i].addr = 0; 3914 tp->RxDescArray[i].opts1 = 0; 3915 } 3916} 3917 3918static int rtl8169_rx_fill(struct rtl8169_private *tp) 3919{ 3920 unsigned int i; 3921 3922 for (i = 0; i < NUM_RX_DESC; i++) { 3923 struct page *data; 3924 3925 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3926 if (!data) { 3927 rtl8169_rx_clear(tp); 3928 return -ENOMEM; 3929 } 3930 tp->Rx_databuff[i] = data; 3931 } 3932 3933 /* mark as last descriptor in the ring */ 3934 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3935 3936 return 0; 3937} 3938 3939static int rtl8169_init_ring(struct rtl8169_private *tp) 3940{ 3941 rtl8169_init_ring_indexes(tp); 3942 3943 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3944 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3945 3946 return rtl8169_rx_fill(tp); 3947} 3948 3949static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3950{ 3951 struct ring_info *tx_skb = tp->tx_skb + entry; 3952 struct TxDesc *desc = tp->TxDescArray + entry; 3953 3954 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3955 DMA_TO_DEVICE); 3956 memset(desc, 0, sizeof(*desc)); 3957 memset(tx_skb, 0, sizeof(*tx_skb)); 3958} 3959 3960static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3961 unsigned int n) 3962{ 3963 unsigned int i; 3964 3965 for (i = 0; i < n; i++) { 3966 unsigned int entry = (start + i) % NUM_TX_DESC; 3967 struct ring_info *tx_skb = tp->tx_skb + entry; 3968 unsigned int len = tx_skb->len; 3969 3970 if (len) { 3971 struct sk_buff *skb = tx_skb->skb; 3972 3973 rtl8169_unmap_tx_skb(tp, entry); 3974 if (skb) 3975 dev_consume_skb_any(skb); 3976 } 3977 } 3978} 3979 3980static void rtl8169_tx_clear(struct rtl8169_private *tp) 3981{ 3982 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3983 netdev_reset_queue(tp->dev); 3984} 3985 3986static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3987{ 3988 napi_disable(&tp->napi); 3989 3990 /* Give a racing hard_start_xmit a few cycles to complete. */ 3991 synchronize_net(); 3992 3993 /* Disable interrupts */ 3994 rtl8169_irq_mask_and_ack(tp); 3995 3996 rtl_rx_close(tp); 3997 3998 if (going_down && tp->dev->wol_enabled) 3999 goto no_reset; 4000 4001 switch (tp->mac_version) { 4002 case RTL_GIGA_MAC_VER_27: 4003 case RTL_GIGA_MAC_VER_28: 4004 case RTL_GIGA_MAC_VER_31: 4005 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4006 break; 4007 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4008 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4009 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4010 break; 4011 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 4012 rtl_enable_rxdvgate(tp); 4013 fsleep(2000); 4014 break; 4015 default: 4016 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4017 fsleep(100); 4018 break; 4019 } 4020 4021 rtl_hw_reset(tp); 4022no_reset: 4023 rtl8169_tx_clear(tp); 4024 rtl8169_init_ring_indexes(tp); 4025} 4026 4027static void rtl_reset_work(struct rtl8169_private *tp) 4028{ 4029 int i; 4030 4031 netif_stop_queue(tp->dev); 4032 4033 rtl8169_cleanup(tp, false); 4034 4035 for (i = 0; i < NUM_RX_DESC; i++) 4036 rtl8169_mark_to_asic(tp->RxDescArray + i); 4037 4038 napi_enable(&tp->napi); 4039 rtl_hw_start(tp); 4040} 4041 4042static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4043{ 4044 struct rtl8169_private *tp = netdev_priv(dev); 4045 4046 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4047} 4048 4049static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4050 void *addr, unsigned int entry, bool desc_own) 4051{ 4052 struct TxDesc *txd = tp->TxDescArray + entry; 4053 struct device *d = tp_to_dev(tp); 4054 dma_addr_t mapping; 4055 u32 opts1; 4056 int ret; 4057 4058 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4059 ret = dma_mapping_error(d, mapping); 4060 if (unlikely(ret)) { 4061 if (net_ratelimit()) 4062 netdev_err(tp->dev, "Failed to map TX data!\n"); 4063 return ret; 4064 } 4065 4066 txd->addr = cpu_to_le64(mapping); 4067 txd->opts2 = cpu_to_le32(opts[1]); 4068 4069 opts1 = opts[0] | len; 4070 if (entry == NUM_TX_DESC - 1) 4071 opts1 |= RingEnd; 4072 if (desc_own) 4073 opts1 |= DescOwn; 4074 txd->opts1 = cpu_to_le32(opts1); 4075 4076 tp->tx_skb[entry].len = len; 4077 4078 return 0; 4079} 4080 4081static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4082 const u32 *opts, unsigned int entry) 4083{ 4084 struct skb_shared_info *info = skb_shinfo(skb); 4085 unsigned int cur_frag; 4086 4087 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4088 const skb_frag_t *frag = info->frags + cur_frag; 4089 void *addr = skb_frag_address(frag); 4090 u32 len = skb_frag_size(frag); 4091 4092 entry = (entry + 1) % NUM_TX_DESC; 4093 4094 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4095 goto err_out; 4096 } 4097 4098 return 0; 4099 4100err_out: 4101 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4102 return -EIO; 4103} 4104 4105static bool rtl_skb_is_udp(struct sk_buff *skb) 4106{ 4107 int no = skb_network_offset(skb); 4108 struct ipv6hdr *i6h, _i6h; 4109 struct iphdr *ih, _ih; 4110 4111 switch (vlan_get_protocol(skb)) { 4112 case htons(ETH_P_IP): 4113 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4114 return ih && ih->protocol == IPPROTO_UDP; 4115 case htons(ETH_P_IPV6): 4116 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4117 return i6h && i6h->nexthdr == IPPROTO_UDP; 4118 default: 4119 return false; 4120 } 4121} 4122 4123#define RTL_MIN_PATCH_LEN 47 4124 4125/* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4126static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4127 struct sk_buff *skb) 4128{ 4129 unsigned int padto = 0, len = skb->len; 4130 4131 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4132 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4133 unsigned int trans_data_len = skb_tail_pointer(skb) - 4134 skb_transport_header(skb); 4135 4136 if (trans_data_len >= offsetof(struct udphdr, len) && 4137 trans_data_len < RTL_MIN_PATCH_LEN) { 4138 u16 dest = ntohs(udp_hdr(skb)->dest); 4139 4140 /* dest is a standard PTP port */ 4141 if (dest == 319 || dest == 320) 4142 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4143 } 4144 4145 if (trans_data_len < sizeof(struct udphdr)) 4146 padto = max_t(unsigned int, padto, 4147 len + sizeof(struct udphdr) - trans_data_len); 4148 } 4149 4150 return padto; 4151} 4152 4153static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4154 struct sk_buff *skb) 4155{ 4156 unsigned int padto; 4157 4158 padto = rtl8125_quirk_udp_padto(tp, skb); 4159 4160 switch (tp->mac_version) { 4161 case RTL_GIGA_MAC_VER_34: 4162 case RTL_GIGA_MAC_VER_60: 4163 case RTL_GIGA_MAC_VER_61: 4164 case RTL_GIGA_MAC_VER_63: 4165 padto = max_t(unsigned int, padto, ETH_ZLEN); 4166 default: 4167 break; 4168 } 4169 4170 return padto; 4171} 4172 4173static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4174{ 4175 u32 mss = skb_shinfo(skb)->gso_size; 4176 4177 if (mss) { 4178 opts[0] |= TD_LSO; 4179 opts[0] |= mss << TD0_MSS_SHIFT; 4180 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4181 const struct iphdr *ip = ip_hdr(skb); 4182 4183 if (ip->protocol == IPPROTO_TCP) 4184 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4185 else if (ip->protocol == IPPROTO_UDP) 4186 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4187 else 4188 WARN_ON_ONCE(1); 4189 } 4190} 4191 4192static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4193 struct sk_buff *skb, u32 *opts) 4194{ 4195 struct skb_shared_info *shinfo = skb_shinfo(skb); 4196 u32 mss = shinfo->gso_size; 4197 4198 if (mss) { 4199 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4200 opts[0] |= TD1_GTSENV4; 4201 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4202 if (skb_cow_head(skb, 0)) 4203 return false; 4204 4205 tcp_v6_gso_csum_prep(skb); 4206 opts[0] |= TD1_GTSENV6; 4207 } else { 4208 WARN_ON_ONCE(1); 4209 } 4210 4211 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4212 opts[1] |= mss << TD1_MSS_SHIFT; 4213 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4214 u8 ip_protocol; 4215 4216 switch (vlan_get_protocol(skb)) { 4217 case htons(ETH_P_IP): 4218 opts[1] |= TD1_IPv4_CS; 4219 ip_protocol = ip_hdr(skb)->protocol; 4220 break; 4221 4222 case htons(ETH_P_IPV6): 4223 opts[1] |= TD1_IPv6_CS; 4224 ip_protocol = ipv6_hdr(skb)->nexthdr; 4225 break; 4226 4227 default: 4228 ip_protocol = IPPROTO_RAW; 4229 break; 4230 } 4231 4232 if (ip_protocol == IPPROTO_TCP) 4233 opts[1] |= TD1_TCP_CS; 4234 else if (ip_protocol == IPPROTO_UDP) 4235 opts[1] |= TD1_UDP_CS; 4236 else 4237 WARN_ON_ONCE(1); 4238 4239 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4240 } else { 4241 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4242 4243 /* skb_padto would free the skb on error */ 4244 return !__skb_put_padto(skb, padto, false); 4245 } 4246 4247 return true; 4248} 4249 4250static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4251 unsigned int nr_frags) 4252{ 4253 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4254 4255 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4256 return slots_avail > nr_frags; 4257} 4258 4259/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4260static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4261{ 4262 switch (tp->mac_version) { 4263 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4264 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4265 return false; 4266 default: 4267 return true; 4268 } 4269} 4270 4271static void rtl8169_doorbell(struct rtl8169_private *tp) 4272{ 4273 if (rtl_is_8125(tp)) 4274 RTL_W16(tp, TxPoll_8125, BIT(0)); 4275 else 4276 RTL_W8(tp, TxPoll, NPQ); 4277} 4278 4279static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4280 struct net_device *dev) 4281{ 4282 unsigned int frags = skb_shinfo(skb)->nr_frags; 4283 struct rtl8169_private *tp = netdev_priv(dev); 4284 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4285 struct TxDesc *txd_first, *txd_last; 4286 bool stop_queue, door_bell; 4287 u32 opts[2]; 4288 4289 txd_first = tp->TxDescArray + entry; 4290 4291 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4292 if (net_ratelimit()) 4293 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4294 goto err_stop_0; 4295 } 4296 4297 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4298 goto err_stop_0; 4299 4300 opts[1] = rtl8169_tx_vlan_tag(skb); 4301 opts[0] = 0; 4302 4303 if (!rtl_chip_supports_csum_v2(tp)) 4304 rtl8169_tso_csum_v1(skb, opts); 4305 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4306 goto err_dma_0; 4307 4308 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4309 entry, false))) 4310 goto err_dma_0; 4311 4312 if (frags) { 4313 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4314 goto err_dma_1; 4315 entry = (entry + frags) % NUM_TX_DESC; 4316 } 4317 4318 txd_last = tp->TxDescArray + entry; 4319 txd_last->opts1 |= cpu_to_le32(LastFrag); 4320 tp->tx_skb[entry].skb = skb; 4321 4322 skb_tx_timestamp(skb); 4323 4324 /* Force memory writes to complete before releasing descriptor */ 4325 dma_wmb(); 4326 4327 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4328 4329 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4330 4331 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4332 smp_wmb(); 4333 4334 tp->cur_tx += frags + 1; 4335 4336 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4337 if (unlikely(stop_queue)) { 4338 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4339 * not miss a ring update when it notices a stopped queue. 4340 */ 4341 smp_wmb(); 4342 netif_stop_queue(dev); 4343 door_bell = true; 4344 } 4345 4346 if (door_bell) 4347 rtl8169_doorbell(tp); 4348 4349 if (unlikely(stop_queue)) { 4350 /* Sync with rtl_tx: 4351 * - publish queue status and cur_tx ring index (write barrier) 4352 * - refresh dirty_tx ring index (read barrier). 4353 * May the current thread have a pessimistic view of the ring 4354 * status and forget to wake up queue, a racing rtl_tx thread 4355 * can't. 4356 */ 4357 smp_mb(); 4358 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4359 netif_start_queue(dev); 4360 } 4361 4362 return NETDEV_TX_OK; 4363 4364err_dma_1: 4365 rtl8169_unmap_tx_skb(tp, entry); 4366err_dma_0: 4367 dev_kfree_skb_any(skb); 4368 dev->stats.tx_dropped++; 4369 return NETDEV_TX_OK; 4370 4371err_stop_0: 4372 netif_stop_queue(dev); 4373 dev->stats.tx_dropped++; 4374 return NETDEV_TX_BUSY; 4375} 4376 4377static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4378{ 4379 struct skb_shared_info *info = skb_shinfo(skb); 4380 unsigned int nr_frags = info->nr_frags; 4381 4382 if (!nr_frags) 4383 return UINT_MAX; 4384 4385 return skb_frag_size(info->frags + nr_frags - 1); 4386} 4387 4388/* Workaround for hw issues with TSO on RTL8168evl */ 4389static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4390 netdev_features_t features) 4391{ 4392 /* IPv4 header has options field */ 4393 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4394 ip_hdrlen(skb) > sizeof(struct iphdr)) 4395 features &= ~NETIF_F_ALL_TSO; 4396 4397 /* IPv4 TCP header has options field */ 4398 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4399 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4400 features &= ~NETIF_F_ALL_TSO; 4401 4402 else if (rtl_last_frag_len(skb) <= 6) 4403 features &= ~NETIF_F_ALL_TSO; 4404 4405 return features; 4406} 4407 4408static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4409 struct net_device *dev, 4410 netdev_features_t features) 4411{ 4412 struct rtl8169_private *tp = netdev_priv(dev); 4413 4414 if (skb_is_gso(skb)) { 4415 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4416 features = rtl8168evl_fix_tso(skb, features); 4417 4418 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4419 rtl_chip_supports_csum_v2(tp)) 4420 features &= ~NETIF_F_ALL_TSO; 4421 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4422 /* work around hw bug on some chip versions */ 4423 if (skb->len < ETH_ZLEN) 4424 features &= ~NETIF_F_CSUM_MASK; 4425 4426 if (rtl_quirk_packet_padto(tp, skb)) 4427 features &= ~NETIF_F_CSUM_MASK; 4428 4429 if (skb_transport_offset(skb) > TCPHO_MAX && 4430 rtl_chip_supports_csum_v2(tp)) 4431 features &= ~NETIF_F_CSUM_MASK; 4432 } 4433 4434 return vlan_features_check(skb, features); 4435} 4436 4437static void rtl8169_pcierr_interrupt(struct net_device *dev) 4438{ 4439 struct rtl8169_private *tp = netdev_priv(dev); 4440 struct pci_dev *pdev = tp->pci_dev; 4441 int pci_status_errs; 4442 u16 pci_cmd; 4443 4444 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4445 4446 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4447 4448 if (net_ratelimit()) 4449 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4450 pci_cmd, pci_status_errs); 4451 /* 4452 * The recovery sequence below admits a very elaborated explanation: 4453 * - it seems to work; 4454 * - I did not see what else could be done; 4455 * - it makes iop3xx happy. 4456 * 4457 * Feel free to adjust to your needs. 4458 */ 4459 if (pdev->broken_parity_status) 4460 pci_cmd &= ~PCI_COMMAND_PARITY; 4461 else 4462 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4463 4464 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4465 4466 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4467} 4468 4469static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4470 int budget) 4471{ 4472 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4473 4474 dirty_tx = tp->dirty_tx; 4475 smp_rmb(); 4476 4477 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4478 unsigned int entry = dirty_tx % NUM_TX_DESC; 4479 struct sk_buff *skb = tp->tx_skb[entry].skb; 4480 u32 status; 4481 4482 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4483 if (status & DescOwn) 4484 break; 4485 4486 rtl8169_unmap_tx_skb(tp, entry); 4487 4488 if (skb) { 4489 pkts_compl++; 4490 bytes_compl += skb->len; 4491 napi_consume_skb(skb, budget); 4492 } 4493 dirty_tx++; 4494 } 4495 4496 if (tp->dirty_tx != dirty_tx) { 4497 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4498 4499 rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl); 4500 4501 tp->dirty_tx = dirty_tx; 4502 /* Sync with rtl8169_start_xmit: 4503 * - publish dirty_tx ring index (write barrier) 4504 * - refresh cur_tx ring index and queue status (read barrier) 4505 * May the current thread miss the stopped queue condition, 4506 * a racing xmit thread can only have a right view of the 4507 * ring status. 4508 */ 4509 smp_mb(); 4510 if (netif_queue_stopped(dev) && 4511 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4512 netif_wake_queue(dev); 4513 } 4514 /* 4515 * 8168 hack: TxPoll requests are lost when the Tx packets are 4516 * too close. Let's kick an extra TxPoll request when a burst 4517 * of start_xmit activity is detected (if it is not detected, 4518 * it is slow enough). -- FR 4519 */ 4520 if (tp->cur_tx != dirty_tx) 4521 rtl8169_doorbell(tp); 4522 } 4523} 4524 4525static inline int rtl8169_fragmented_frame(u32 status) 4526{ 4527 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4528} 4529 4530static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4531{ 4532 u32 status = opts1 & RxProtoMask; 4533 4534 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4535 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4536 skb->ip_summed = CHECKSUM_UNNECESSARY; 4537 else 4538 skb_checksum_none_assert(skb); 4539} 4540 4541static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4542{ 4543 unsigned int cur_rx, rx_left, count; 4544 struct device *d = tp_to_dev(tp); 4545 4546 cur_rx = tp->cur_rx; 4547 4548 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4549 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC; 4550 struct RxDesc *desc = tp->RxDescArray + entry; 4551 struct sk_buff *skb; 4552 const void *rx_buf; 4553 dma_addr_t addr; 4554 u32 status; 4555 4556 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4557 if (status & DescOwn) 4558 break; 4559 4560 /* This barrier is needed to keep us from reading 4561 * any other fields out of the Rx descriptor until 4562 * we know the status of DescOwn 4563 */ 4564 dma_rmb(); 4565 4566 if (unlikely(status & RxRES)) { 4567 if (net_ratelimit()) 4568 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4569 status); 4570 dev->stats.rx_errors++; 4571 if (status & (RxRWT | RxRUNT)) 4572 dev->stats.rx_length_errors++; 4573 if (status & RxCRC) 4574 dev->stats.rx_crc_errors++; 4575 4576 if (!(dev->features & NETIF_F_RXALL)) 4577 goto release_descriptor; 4578 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4579 goto release_descriptor; 4580 } 4581 4582 pkt_size = status & GENMASK(13, 0); 4583 if (likely(!(dev->features & NETIF_F_RXFCS))) 4584 pkt_size -= ETH_FCS_LEN; 4585 4586 /* The driver does not support incoming fragmented frames. 4587 * They are seen as a symptom of over-mtu sized frames. 4588 */ 4589 if (unlikely(rtl8169_fragmented_frame(status))) { 4590 dev->stats.rx_dropped++; 4591 dev->stats.rx_length_errors++; 4592 goto release_descriptor; 4593 } 4594 4595 skb = napi_alloc_skb(&tp->napi, pkt_size); 4596 if (unlikely(!skb)) { 4597 dev->stats.rx_dropped++; 4598 goto release_descriptor; 4599 } 4600 4601 addr = le64_to_cpu(desc->addr); 4602 rx_buf = page_address(tp->Rx_databuff[entry]); 4603 4604 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4605 prefetch(rx_buf); 4606 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4607 skb->tail += pkt_size; 4608 skb->len = pkt_size; 4609 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4610 4611 rtl8169_rx_csum(skb, status); 4612 skb->protocol = eth_type_trans(skb, dev); 4613 4614 rtl8169_rx_vlan_tag(desc, skb); 4615 4616 if (skb->pkt_type == PACKET_MULTICAST) 4617 dev->stats.multicast++; 4618 4619 napi_gro_receive(&tp->napi, skb); 4620 4621 rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size); 4622release_descriptor: 4623 rtl8169_mark_to_asic(desc); 4624 } 4625 4626 count = cur_rx - tp->cur_rx; 4627 tp->cur_rx = cur_rx; 4628 4629 return count; 4630} 4631 4632static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4633{ 4634 struct rtl8169_private *tp = dev_instance; 4635 u32 status = rtl_get_events(tp); 4636 4637 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4638 return IRQ_NONE; 4639 4640 if (unlikely(status & SYSErr)) { 4641 rtl8169_pcierr_interrupt(tp->dev); 4642 goto out; 4643 } 4644 4645 if (status & LinkChg) 4646 phy_mac_interrupt(tp->phydev); 4647 4648 if (unlikely(status & RxFIFOOver && 4649 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4650 netif_stop_queue(tp->dev); 4651 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4652 } 4653 4654 rtl_irq_disable(tp); 4655 napi_schedule(&tp->napi); 4656out: 4657 rtl_ack_events(tp, status); 4658 4659 return IRQ_HANDLED; 4660} 4661 4662static void rtl_task(struct work_struct *work) 4663{ 4664 struct rtl8169_private *tp = 4665 container_of(work, struct rtl8169_private, wk.work); 4666 int ret; 4667 4668 rtnl_lock(); 4669 4670 if (!netif_running(tp->dev) || 4671 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4672 goto out_unlock; 4673 4674 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4675 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4676 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4677 PCIE_LINK_STATE_L0S); 4678 if (!ret) 4679 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4680 goto reset; 4681 } 4682 4683 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4684reset: 4685 rtl_reset_work(tp); 4686 netif_wake_queue(tp->dev); 4687 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4688 rtl_reset_work(tp); 4689 } 4690out_unlock: 4691 rtnl_unlock(); 4692} 4693 4694static int rtl8169_poll(struct napi_struct *napi, int budget) 4695{ 4696 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4697 struct net_device *dev = tp->dev; 4698 int work_done; 4699 4700 work_done = rtl_rx(dev, tp, (u32) budget); 4701 4702 rtl_tx(dev, tp, budget); 4703 4704 if (work_done < budget && napi_complete_done(napi, work_done)) 4705 rtl_irq_enable(tp); 4706 4707 return work_done; 4708} 4709 4710static void r8169_phylink_handler(struct net_device *ndev) 4711{ 4712 struct rtl8169_private *tp = netdev_priv(ndev); 4713 struct device *d = tp_to_dev(tp); 4714 4715 if (netif_carrier_ok(ndev)) { 4716 rtl_link_chg_patch(tp); 4717 pm_request_resume(d); 4718 netif_wake_queue(tp->dev); 4719 } else { 4720 /* In few cases rx is broken after link-down otherwise */ 4721 if (rtl_is_8125(tp)) 4722 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4723 pm_runtime_idle(d); 4724 } 4725 4726 if (net_ratelimit()) 4727 phy_print_status(tp->phydev); 4728} 4729 4730static int r8169_phy_connect(struct rtl8169_private *tp) 4731{ 4732 struct phy_device *phydev = tp->phydev; 4733 phy_interface_t phy_mode; 4734 int ret; 4735 4736 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4737 PHY_INTERFACE_MODE_MII; 4738 4739 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4740 phy_mode); 4741 if (ret) 4742 return ret; 4743 4744 if (!tp->supports_gmii) 4745 phy_set_max_speed(phydev, SPEED_100); 4746 4747 phy_attached_info(phydev); 4748 4749 return 0; 4750} 4751 4752static void rtl8169_down(struct rtl8169_private *tp) 4753{ 4754 /* Clear all task flags */ 4755 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4756 4757 phy_stop(tp->phydev); 4758 4759 rtl8169_update_counters(tp); 4760 4761 pci_clear_master(tp->pci_dev); 4762 rtl_pci_commit(tp); 4763 4764 rtl8169_cleanup(tp, true); 4765 4766 rtl_pll_power_down(tp); 4767} 4768 4769static void rtl8169_up(struct rtl8169_private *tp) 4770{ 4771 pci_set_master(tp->pci_dev); 4772 rtl_pll_power_up(tp); 4773 rtl8169_init_phy(tp); 4774 napi_enable(&tp->napi); 4775 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4776 rtl_reset_work(tp); 4777 4778 phy_start(tp->phydev); 4779} 4780 4781static int rtl8169_close(struct net_device *dev) 4782{ 4783 struct rtl8169_private *tp = netdev_priv(dev); 4784 struct pci_dev *pdev = tp->pci_dev; 4785 4786 pm_runtime_get_sync(&pdev->dev); 4787 4788 netif_stop_queue(dev); 4789 rtl8169_down(tp); 4790 rtl8169_rx_clear(tp); 4791 4792 cancel_work(&tp->wk.work); 4793 4794 free_irq(pci_irq_vector(pdev, 0), tp); 4795 4796 phy_disconnect(tp->phydev); 4797 4798 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4799 tp->RxPhyAddr); 4800 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4801 tp->TxPhyAddr); 4802 tp->TxDescArray = NULL; 4803 tp->RxDescArray = NULL; 4804 4805 pm_runtime_put_sync(&pdev->dev); 4806 4807 return 0; 4808} 4809 4810#ifdef CONFIG_NET_POLL_CONTROLLER 4811static void rtl8169_netpoll(struct net_device *dev) 4812{ 4813 struct rtl8169_private *tp = netdev_priv(dev); 4814 4815 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4816} 4817#endif 4818 4819static int rtl_open(struct net_device *dev) 4820{ 4821 struct rtl8169_private *tp = netdev_priv(dev); 4822 struct pci_dev *pdev = tp->pci_dev; 4823 int retval = -ENOMEM; 4824 4825 pm_runtime_get_sync(&pdev->dev); 4826 4827 /* 4828 * Rx and Tx descriptors needs 256 bytes alignment. 4829 * dma_alloc_coherent provides more. 4830 */ 4831 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4832 &tp->TxPhyAddr, GFP_KERNEL); 4833 if (!tp->TxDescArray) 4834 goto err_pm_runtime_put; 4835 4836 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4837 &tp->RxPhyAddr, GFP_KERNEL); 4838 if (!tp->RxDescArray) 4839 goto err_free_tx_0; 4840 4841 retval = rtl8169_init_ring(tp); 4842 if (retval < 0) 4843 goto err_free_rx_1; 4844 4845 rtl_request_firmware(tp); 4846 4847 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4848 IRQF_SHARED, dev->name, tp); 4849 if (retval < 0) 4850 goto err_release_fw_2; 4851 4852 retval = r8169_phy_connect(tp); 4853 if (retval) 4854 goto err_free_irq; 4855 4856 rtl8169_up(tp); 4857 rtl8169_init_counter_offsets(tp); 4858 netif_start_queue(dev); 4859 4860 pm_runtime_put_sync(&pdev->dev); 4861out: 4862 return retval; 4863 4864err_free_irq: 4865 free_irq(pci_irq_vector(pdev, 0), tp); 4866err_release_fw_2: 4867 rtl_release_firmware(tp); 4868 rtl8169_rx_clear(tp); 4869err_free_rx_1: 4870 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4871 tp->RxPhyAddr); 4872 tp->RxDescArray = NULL; 4873err_free_tx_0: 4874 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4875 tp->TxPhyAddr); 4876 tp->TxDescArray = NULL; 4877err_pm_runtime_put: 4878 pm_runtime_put_noidle(&pdev->dev); 4879 goto out; 4880} 4881 4882static void 4883rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4884{ 4885 struct rtl8169_private *tp = netdev_priv(dev); 4886 struct pci_dev *pdev = tp->pci_dev; 4887 struct rtl8169_counters *counters = tp->counters; 4888 4889 pm_runtime_get_noresume(&pdev->dev); 4890 4891 netdev_stats_to_stats64(stats, &dev->stats); 4892 4893 rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes); 4894 rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes); 4895 4896 /* 4897 * Fetch additional counter values missing in stats collected by driver 4898 * from tally counters. 4899 */ 4900 if (pm_runtime_active(&pdev->dev)) 4901 rtl8169_update_counters(tp); 4902 4903 /* 4904 * Subtract values fetched during initalization. 4905 * See rtl8169_init_counter_offsets for a description why we do that. 4906 */ 4907 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4908 le64_to_cpu(tp->tc_offset.tx_errors); 4909 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4910 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4911 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4912 le16_to_cpu(tp->tc_offset.tx_aborted); 4913 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4914 le16_to_cpu(tp->tc_offset.rx_missed); 4915 4916 pm_runtime_put_noidle(&pdev->dev); 4917} 4918 4919static void rtl8169_net_suspend(struct rtl8169_private *tp) 4920{ 4921 netif_device_detach(tp->dev); 4922 4923 if (netif_running(tp->dev)) 4924 rtl8169_down(tp); 4925} 4926 4927#ifdef CONFIG_PM 4928 4929static int rtl8169_net_resume(struct rtl8169_private *tp) 4930{ 4931 rtl_rar_set(tp, tp->dev->dev_addr); 4932 4933 if (tp->TxDescArray) 4934 rtl8169_up(tp); 4935 4936 netif_device_attach(tp->dev); 4937 4938 return 0; 4939} 4940 4941static int __maybe_unused rtl8169_suspend(struct device *device) 4942{ 4943 struct rtl8169_private *tp = dev_get_drvdata(device); 4944 4945 rtnl_lock(); 4946 rtl8169_net_suspend(tp); 4947 if (!device_may_wakeup(tp_to_dev(tp))) 4948 clk_disable_unprepare(tp->clk); 4949 rtnl_unlock(); 4950 4951 return 0; 4952} 4953 4954static int __maybe_unused rtl8169_resume(struct device *device) 4955{ 4956 struct rtl8169_private *tp = dev_get_drvdata(device); 4957 4958 if (!device_may_wakeup(tp_to_dev(tp))) 4959 clk_prepare_enable(tp->clk); 4960 4961 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4962 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4963 rtl_init_rxcfg(tp); 4964 4965 return rtl8169_net_resume(tp); 4966} 4967 4968static int rtl8169_runtime_suspend(struct device *device) 4969{ 4970 struct rtl8169_private *tp = dev_get_drvdata(device); 4971 4972 if (!tp->TxDescArray) { 4973 netif_device_detach(tp->dev); 4974 return 0; 4975 } 4976 4977 rtnl_lock(); 4978 __rtl8169_set_wol(tp, WAKE_PHY); 4979 rtl8169_net_suspend(tp); 4980 rtnl_unlock(); 4981 4982 return 0; 4983} 4984 4985static int rtl8169_runtime_resume(struct device *device) 4986{ 4987 struct rtl8169_private *tp = dev_get_drvdata(device); 4988 4989 __rtl8169_set_wol(tp, tp->saved_wolopts); 4990 4991 return rtl8169_net_resume(tp); 4992} 4993 4994static int rtl8169_runtime_idle(struct device *device) 4995{ 4996 struct rtl8169_private *tp = dev_get_drvdata(device); 4997 4998 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4999 pm_schedule_suspend(device, 10000); 5000 5001 return -EBUSY; 5002} 5003 5004static const struct dev_pm_ops rtl8169_pm_ops = { 5005 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5006 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5007 rtl8169_runtime_idle) 5008}; 5009 5010#endif /* CONFIG_PM */ 5011 5012static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 5013{ 5014 /* WoL fails with 8168b when the receiver is disabled. */ 5015 switch (tp->mac_version) { 5016 case RTL_GIGA_MAC_VER_11: 5017 case RTL_GIGA_MAC_VER_12: 5018 case RTL_GIGA_MAC_VER_17: 5019 pci_clear_master(tp->pci_dev); 5020 5021 RTL_W8(tp, ChipCmd, CmdRxEnb); 5022 rtl_pci_commit(tp); 5023 break; 5024 default: 5025 break; 5026 } 5027} 5028 5029static void rtl_shutdown(struct pci_dev *pdev) 5030{ 5031 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5032 5033 rtnl_lock(); 5034 rtl8169_net_suspend(tp); 5035 rtnl_unlock(); 5036 5037 /* Restore original MAC address */ 5038 rtl_rar_set(tp, tp->dev->perm_addr); 5039 5040 if (system_state == SYSTEM_POWER_OFF) { 5041 if (tp->saved_wolopts) { 5042 rtl_wol_suspend_quirk(tp); 5043 rtl_wol_shutdown_quirk(tp); 5044 } 5045 5046 pci_wake_from_d3(pdev, true); 5047 pci_set_power_state(pdev, PCI_D3hot); 5048 } 5049} 5050 5051static void rtl_remove_one(struct pci_dev *pdev) 5052{ 5053 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5054 5055 if (pci_dev_run_wake(pdev)) 5056 pm_runtime_get_noresume(&pdev->dev); 5057 5058 cancel_work_sync(&tp->wk.work); 5059 5060 unregister_netdev(tp->dev); 5061 5062 if (r8168_check_dash(tp)) 5063 rtl8168_driver_stop(tp); 5064 5065 rtl_release_firmware(tp); 5066 5067 /* restore original MAC address */ 5068 rtl_rar_set(tp, tp->dev->perm_addr); 5069} 5070 5071static const struct net_device_ops rtl_netdev_ops = { 5072 .ndo_open = rtl_open, 5073 .ndo_stop = rtl8169_close, 5074 .ndo_get_stats64 = rtl8169_get_stats64, 5075 .ndo_start_xmit = rtl8169_start_xmit, 5076 .ndo_features_check = rtl8169_features_check, 5077 .ndo_tx_timeout = rtl8169_tx_timeout, 5078 .ndo_validate_addr = eth_validate_addr, 5079 .ndo_change_mtu = rtl8169_change_mtu, 5080 .ndo_fix_features = rtl8169_fix_features, 5081 .ndo_set_features = rtl8169_set_features, 5082 .ndo_set_mac_address = rtl_set_mac_address, 5083 .ndo_do_ioctl = phy_do_ioctl_running, 5084 .ndo_set_rx_mode = rtl_set_rx_mode, 5085#ifdef CONFIG_NET_POLL_CONTROLLER 5086 .ndo_poll_controller = rtl8169_netpoll, 5087#endif 5088 5089}; 5090 5091static void rtl_set_irq_mask(struct rtl8169_private *tp) 5092{ 5093 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5094 5095 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5096 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5097 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5098 /* special workaround needed */ 5099 tp->irq_mask |= RxFIFOOver; 5100 else 5101 tp->irq_mask |= RxOverflow; 5102} 5103 5104static int rtl_alloc_irq(struct rtl8169_private *tp) 5105{ 5106 unsigned int flags; 5107 5108 switch (tp->mac_version) { 5109 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5110 rtl_unlock_config_regs(tp); 5111 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5112 rtl_lock_config_regs(tp); 5113 fallthrough; 5114 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5115 flags = PCI_IRQ_LEGACY; 5116 break; 5117 default: 5118 flags = PCI_IRQ_ALL_TYPES; 5119 break; 5120 } 5121 5122 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5123} 5124 5125static void rtl_read_mac_address(struct rtl8169_private *tp, 5126 u8 mac_addr[ETH_ALEN]) 5127{ 5128 /* Get MAC address */ 5129 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5130 u32 value = rtl_eri_read(tp, 0xe0); 5131 5132 mac_addr[0] = (value >> 0) & 0xff; 5133 mac_addr[1] = (value >> 8) & 0xff; 5134 mac_addr[2] = (value >> 16) & 0xff; 5135 mac_addr[3] = (value >> 24) & 0xff; 5136 5137 value = rtl_eri_read(tp, 0xe4); 5138 mac_addr[4] = (value >> 0) & 0xff; 5139 mac_addr[5] = (value >> 8) & 0xff; 5140 } else if (rtl_is_8125(tp)) { 5141 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5142 } 5143} 5144 5145DECLARE_RTL_COND(rtl_link_list_ready_cond) 5146{ 5147 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5148} 5149 5150static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5151{ 5152 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5153} 5154 5155static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5156{ 5157 struct rtl8169_private *tp = mii_bus->priv; 5158 5159 if (phyaddr > 0) 5160 return -ENODEV; 5161 5162 return rtl_readphy(tp, phyreg); 5163} 5164 5165static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5166 int phyreg, u16 val) 5167{ 5168 struct rtl8169_private *tp = mii_bus->priv; 5169 5170 if (phyaddr > 0) 5171 return -ENODEV; 5172 5173 rtl_writephy(tp, phyreg, val); 5174 5175 return 0; 5176} 5177 5178static int r8169_mdio_register(struct rtl8169_private *tp) 5179{ 5180 struct pci_dev *pdev = tp->pci_dev; 5181 struct mii_bus *new_bus; 5182 int ret; 5183 5184 new_bus = devm_mdiobus_alloc(&pdev->dev); 5185 if (!new_bus) 5186 return -ENOMEM; 5187 5188 new_bus->name = "r8169"; 5189 new_bus->priv = tp; 5190 new_bus->parent = &pdev->dev; 5191 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5192 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5193 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5194 5195 new_bus->read = r8169_mdio_read_reg; 5196 new_bus->write = r8169_mdio_write_reg; 5197 5198 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5199 if (ret) 5200 return ret; 5201 5202 tp->phydev = mdiobus_get_phy(new_bus, 0); 5203 if (!tp->phydev) { 5204 return -ENODEV; 5205 } else if (!tp->phydev->drv) { 5206 /* Most chip versions fail with the genphy driver. 5207 * Therefore ensure that the dedicated PHY driver is loaded. 5208 */ 5209 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5210 tp->phydev->phy_id); 5211 return -EUNATCH; 5212 } 5213 5214 /* PHY will be woken up in rtl_open() */ 5215 phy_suspend(tp->phydev); 5216 5217 return 0; 5218} 5219 5220static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5221{ 5222 rtl_enable_rxdvgate(tp); 5223 5224 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5225 msleep(1); 5226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5227 5228 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5229 r8168g_wait_ll_share_fifo_ready(tp); 5230 5231 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5232 r8168g_wait_ll_share_fifo_ready(tp); 5233} 5234 5235static void rtl_hw_init_8125(struct rtl8169_private *tp) 5236{ 5237 rtl_enable_rxdvgate(tp); 5238 5239 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5240 msleep(1); 5241 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5242 5243 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5244 r8168g_wait_ll_share_fifo_ready(tp); 5245 5246 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5247 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5248 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5249 r8168g_wait_ll_share_fifo_ready(tp); 5250} 5251 5252static void rtl_hw_initialize(struct rtl8169_private *tp) 5253{ 5254 switch (tp->mac_version) { 5255 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5256 rtl8168ep_stop_cmac(tp); 5257 fallthrough; 5258 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5259 rtl_hw_init_8168g(tp); 5260 break; 5261 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5262 rtl_hw_init_8125(tp); 5263 break; 5264 default: 5265 break; 5266 } 5267} 5268 5269static int rtl_jumbo_max(struct rtl8169_private *tp) 5270{ 5271 /* Non-GBit versions don't support jumbo frames */ 5272 if (!tp->supports_gmii) 5273 return 0; 5274 5275 switch (tp->mac_version) { 5276 /* RTL8169 */ 5277 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5278 return JUMBO_7K; 5279 /* RTL8168b */ 5280 case RTL_GIGA_MAC_VER_11: 5281 case RTL_GIGA_MAC_VER_12: 5282 case RTL_GIGA_MAC_VER_17: 5283 return JUMBO_4K; 5284 /* RTL8168c */ 5285 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5286 return JUMBO_6K; 5287 default: 5288 return JUMBO_9K; 5289 } 5290} 5291 5292static void rtl_disable_clk(void *data) 5293{ 5294 clk_disable_unprepare(data); 5295} 5296 5297static int rtl_get_ether_clk(struct rtl8169_private *tp) 5298{ 5299 struct device *d = tp_to_dev(tp); 5300 struct clk *clk; 5301 int rc; 5302 5303 clk = devm_clk_get(d, "ether_clk"); 5304 if (IS_ERR(clk)) { 5305 rc = PTR_ERR(clk); 5306 if (rc == -ENOENT) 5307 /* clk-core allows NULL (for suspend / resume) */ 5308 rc = 0; 5309 else if (rc != -EPROBE_DEFER) 5310 dev_err(d, "failed to get clk: %d\n", rc); 5311 } else { 5312 tp->clk = clk; 5313 rc = clk_prepare_enable(clk); 5314 if (rc) 5315 dev_err(d, "failed to enable clk: %d\n", rc); 5316 else 5317 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5318 } 5319 5320 return rc; 5321} 5322 5323static void rtl_init_mac_address(struct rtl8169_private *tp) 5324{ 5325 struct net_device *dev = tp->dev; 5326 u8 *mac_addr = dev->dev_addr; 5327 int rc; 5328 5329 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5330 if (!rc) 5331 goto done; 5332 5333 rtl_read_mac_address(tp, mac_addr); 5334 if (is_valid_ether_addr(mac_addr)) 5335 goto done; 5336 5337 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5338 if (is_valid_ether_addr(mac_addr)) 5339 goto done; 5340 5341 eth_hw_addr_random(dev); 5342 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5343done: 5344 rtl_rar_set(tp, mac_addr); 5345} 5346 5347static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5348{ 5349 struct rtl8169_private *tp; 5350 int jumbo_max, region, rc; 5351 enum mac_version chipset; 5352 struct net_device *dev; 5353 u16 xid; 5354 5355 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5356 if (!dev) 5357 return -ENOMEM; 5358 5359 SET_NETDEV_DEV(dev, &pdev->dev); 5360 dev->netdev_ops = &rtl_netdev_ops; 5361 tp = netdev_priv(dev); 5362 tp->dev = dev; 5363 tp->pci_dev = pdev; 5364 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5365 tp->eee_adv = -1; 5366 tp->ocp_base = OCP_STD_PHY_BASE; 5367 5368 /* Get the *optional* external "ether_clk" used on some boards */ 5369 rc = rtl_get_ether_clk(tp); 5370 if (rc) 5371 return rc; 5372 5373 /* Disable ASPM completely as that cause random device stop working 5374 * problems as well as full system hangs for some PCIe devices users. 5375 */ 5376 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5377 PCIE_LINK_STATE_L1); 5378 tp->aspm_manageable = !rc; 5379 5380 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5381 rc = pcim_enable_device(pdev); 5382 if (rc < 0) { 5383 dev_err(&pdev->dev, "enable failure\n"); 5384 return rc; 5385 } 5386 5387 if (pcim_set_mwi(pdev) < 0) 5388 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5389 5390 /* use first MMIO region */ 5391 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5392 if (region < 0) { 5393 dev_err(&pdev->dev, "no MMIO resource found\n"); 5394 return -ENODEV; 5395 } 5396 5397 /* check for weird/broken PCI region reporting */ 5398 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5399 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5400 return -ENODEV; 5401 } 5402 5403 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5404 if (rc < 0) { 5405 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5406 return rc; 5407 } 5408 5409 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5410 5411 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5412 5413 /* Identify chip attached to board */ 5414 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5415 if (chipset == RTL_GIGA_MAC_NONE) { 5416 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5417 return -ENODEV; 5418 } 5419 5420 tp->mac_version = chipset; 5421 5422 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5423 5424 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5425 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5426 dev->features |= NETIF_F_HIGHDMA; 5427 5428 rtl_init_rxcfg(tp); 5429 5430 rtl8169_irq_mask_and_ack(tp); 5431 5432 rtl_hw_initialize(tp); 5433 5434 rtl_hw_reset(tp); 5435 5436 rc = rtl_alloc_irq(tp); 5437 if (rc < 0) { 5438 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5439 return rc; 5440 } 5441 5442 INIT_WORK(&tp->wk.work, rtl_task); 5443 u64_stats_init(&tp->rx_stats.syncp); 5444 u64_stats_init(&tp->tx_stats.syncp); 5445 5446 rtl_init_mac_address(tp); 5447 5448 dev->ethtool_ops = &rtl8169_ethtool_ops; 5449 5450 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5451 5452 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5453 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5454 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5455 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5456 5457 /* 5458 * Pretend we are using VLANs; This bypasses a nasty bug where 5459 * Interrupts stop flowing on high load on 8110SCd controllers. 5460 */ 5461 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5462 /* Disallow toggling */ 5463 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5464 5465 if (rtl_chip_supports_csum_v2(tp)) 5466 dev->hw_features |= NETIF_F_IPV6_CSUM; 5467 5468 dev->features |= dev->hw_features; 5469 5470 /* There has been a number of reports that using SG/TSO results in 5471 * tx timeouts. However for a lot of people SG/TSO works fine. 5472 * Therefore disable both features by default, but allow users to 5473 * enable them. Use at own risk! 5474 */ 5475 if (rtl_chip_supports_csum_v2(tp)) { 5476 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5477 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5478 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5479 } else { 5480 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5481 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5482 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5483 } 5484 5485 dev->hw_features |= NETIF_F_RXALL; 5486 dev->hw_features |= NETIF_F_RXFCS; 5487 5488 /* configure chip for default features */ 5489 rtl8169_set_features(dev, dev->features); 5490 5491 jumbo_max = rtl_jumbo_max(tp); 5492 if (jumbo_max) 5493 dev->max_mtu = jumbo_max; 5494 5495 rtl_set_irq_mask(tp); 5496 5497 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5498 5499 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5500 &tp->counters_phys_addr, 5501 GFP_KERNEL); 5502 if (!tp->counters) 5503 return -ENOMEM; 5504 5505 pci_set_drvdata(pdev, tp); 5506 5507 rc = r8169_mdio_register(tp); 5508 if (rc) 5509 return rc; 5510 5511 /* chip gets powered up in rtl_open() */ 5512 rtl_pll_power_down(tp); 5513 5514 rc = register_netdev(dev); 5515 if (rc) 5516 return rc; 5517 5518 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5519 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5520 pci_irq_vector(pdev, 0)); 5521 5522 if (jumbo_max) 5523 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5524 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5525 "ok" : "ko"); 5526 5527 if (r8168_check_dash(tp)) { 5528 netdev_info(dev, "DASH enabled\n"); 5529 rtl8168_driver_start(tp); 5530 } 5531 5532 if (pci_dev_run_wake(pdev)) 5533 pm_runtime_put_sync(&pdev->dev); 5534 5535 return 0; 5536} 5537 5538static struct pci_driver rtl8169_pci_driver = { 5539 .name = MODULENAME, 5540 .id_table = rtl8169_pci_tbl, 5541 .probe = rtl_init_one, 5542 .remove = rtl_remove_one, 5543 .shutdown = rtl_shutdown, 5544#ifdef CONFIG_PM 5545 .driver.pm = &rtl8169_pm_ops, 5546#endif 5547}; 5548 5549module_pci_driver(rtl8169_pci_driver); 5550