1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * QLogic qlcnic NIC Driver 4 * Copyright (c) 2009-2013 QLogic Corporation 5 */ 6 7#include <linux/slab.h> 8#include <net/ip.h> 9#include <linux/bitops.h> 10 11#include "qlcnic.h" 12#include "qlcnic_hdr.h" 13 14#define MASK(n) ((1ULL<<(n))-1) 15#define OCM_WIN_P3P(addr) (addr & 0xffc0000) 16 17#define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 18 19#define CRB_BLK(off) ((off >> 20) & 0x3f) 20#define CRB_SUBBLK(off) ((off >> 16) & 0xf) 21#define CRB_WINDOW_2M (0x130060) 22#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) 23#define CRB_INDIRECT_2M (0x1e0000UL) 24 25struct qlcnic_ms_reg_ctrl { 26 u32 ocm_window; 27 u32 control; 28 u32 hi; 29 u32 low; 30 u32 rd[4]; 31 u32 wd[4]; 32 u64 off; 33}; 34 35#ifndef readq 36static inline u64 readq(void __iomem *addr) 37{ 38 return readl(addr) | (((u64) readl(addr + 4)) << 32LL); 39} 40#endif 41 42#ifndef writeq 43static inline void writeq(u64 val, void __iomem *addr) 44{ 45 writel(((u32) (val)), (addr)); 46 writel(((u32) (val >> 32)), (addr + 4)); 47} 48#endif 49 50static struct crb_128M_2M_block_map 51crb_128M_2M_map[64] __cacheline_aligned_in_smp = { 52 {{{0, 0, 0, 0} } }, /* 0: PCI */ 53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 54 {1, 0x0110000, 0x0120000, 0x130000}, 55 {1, 0x0120000, 0x0122000, 0x124000}, 56 {1, 0x0130000, 0x0132000, 0x126000}, 57 {1, 0x0140000, 0x0142000, 0x128000}, 58 {1, 0x0150000, 0x0152000, 0x12a000}, 59 {1, 0x0160000, 0x0170000, 0x110000}, 60 {1, 0x0170000, 0x0172000, 0x12e000}, 61 {0, 0x0000000, 0x0000000, 0x000000}, 62 {0, 0x0000000, 0x0000000, 0x000000}, 63 {0, 0x0000000, 0x0000000, 0x000000}, 64 {0, 0x0000000, 0x0000000, 0x000000}, 65 {0, 0x0000000, 0x0000000, 0x000000}, 66 {0, 0x0000000, 0x0000000, 0x000000}, 67 {1, 0x01e0000, 0x01e0800, 0x122000}, 68 {0, 0x0000000, 0x0000000, 0x000000} } }, 69 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 70 {{{0, 0, 0, 0} } }, /* 3: */ 71 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 72 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 73 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 74 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 75 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 76 {0, 0x0000000, 0x0000000, 0x000000}, 77 {0, 0x0000000, 0x0000000, 0x000000}, 78 {0, 0x0000000, 0x0000000, 0x000000}, 79 {0, 0x0000000, 0x0000000, 0x000000}, 80 {0, 0x0000000, 0x0000000, 0x000000}, 81 {0, 0x0000000, 0x0000000, 0x000000}, 82 {0, 0x0000000, 0x0000000, 0x000000}, 83 {0, 0x0000000, 0x0000000, 0x000000}, 84 {0, 0x0000000, 0x0000000, 0x000000}, 85 {0, 0x0000000, 0x0000000, 0x000000}, 86 {0, 0x0000000, 0x0000000, 0x000000}, 87 {0, 0x0000000, 0x0000000, 0x000000}, 88 {0, 0x0000000, 0x0000000, 0x000000}, 89 {0, 0x0000000, 0x0000000, 0x000000}, 90 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 91 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 92 {0, 0x0000000, 0x0000000, 0x000000}, 93 {0, 0x0000000, 0x0000000, 0x000000}, 94 {0, 0x0000000, 0x0000000, 0x000000}, 95 {0, 0x0000000, 0x0000000, 0x000000}, 96 {0, 0x0000000, 0x0000000, 0x000000}, 97 {0, 0x0000000, 0x0000000, 0x000000}, 98 {0, 0x0000000, 0x0000000, 0x000000}, 99 {0, 0x0000000, 0x0000000, 0x000000}, 100 {0, 0x0000000, 0x0000000, 0x000000}, 101 {0, 0x0000000, 0x0000000, 0x000000}, 102 {0, 0x0000000, 0x0000000, 0x000000}, 103 {0, 0x0000000, 0x0000000, 0x000000}, 104 {0, 0x0000000, 0x0000000, 0x000000}, 105 {0, 0x0000000, 0x0000000, 0x000000}, 106 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 107 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 108 {0, 0x0000000, 0x0000000, 0x000000}, 109 {0, 0x0000000, 0x0000000, 0x000000}, 110 {0, 0x0000000, 0x0000000, 0x000000}, 111 {0, 0x0000000, 0x0000000, 0x000000}, 112 {0, 0x0000000, 0x0000000, 0x000000}, 113 {0, 0x0000000, 0x0000000, 0x000000}, 114 {0, 0x0000000, 0x0000000, 0x000000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 123 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {0, 0x0000000, 0x0000000, 0x000000}, 128 {0, 0x0000000, 0x0000000, 0x000000}, 129 {0, 0x0000000, 0x0000000, 0x000000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 139 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 140 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 141 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 142 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 143 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 144 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 145 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 146 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 147 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 148 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 149 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 150 {{{0, 0, 0, 0} } }, /* 23: */ 151 {{{0, 0, 0, 0} } }, /* 24: */ 152 {{{0, 0, 0, 0} } }, /* 25: */ 153 {{{0, 0, 0, 0} } }, /* 26: */ 154 {{{0, 0, 0, 0} } }, /* 27: */ 155 {{{0, 0, 0, 0} } }, /* 28: */ 156 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 157 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 158 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 159 {{{0} } }, /* 32: PCI */ 160 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 161 {1, 0x2110000, 0x2120000, 0x130000}, 162 {1, 0x2120000, 0x2122000, 0x124000}, 163 {1, 0x2130000, 0x2132000, 0x126000}, 164 {1, 0x2140000, 0x2142000, 0x128000}, 165 {1, 0x2150000, 0x2152000, 0x12a000}, 166 {1, 0x2160000, 0x2170000, 0x110000}, 167 {1, 0x2170000, 0x2172000, 0x12e000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000} } }, 176 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 177 {{{0} } }, /* 35: */ 178 {{{0} } }, /* 36: */ 179 {{{0} } }, /* 37: */ 180 {{{0} } }, /* 38: */ 181 {{{0} } }, /* 39: */ 182 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 183 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 184 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 185 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 186 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 187 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 188 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 189 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 190 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 191 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 192 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 193 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 194 {{{0} } }, /* 52: */ 195 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 196 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 197 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 198 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 199 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 200 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 201 {{{0} } }, /* 59: I2C0 */ 202 {{{0} } }, /* 60: I2C1 */ 203 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ 204 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 205 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 206}; 207 208/* 209 * top 12 bits of crb internal address (hub, agent) 210 */ 211static const unsigned crb_hub_agt[64] = { 212 0, 213 QLCNIC_HW_CRB_HUB_AGT_ADR_PS, 214 QLCNIC_HW_CRB_HUB_AGT_ADR_MN, 215 QLCNIC_HW_CRB_HUB_AGT_ADR_MS, 216 0, 217 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE, 218 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU, 219 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN, 220 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0, 221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1, 222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2, 223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3, 224 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q, 225 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR, 226 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB, 227 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4, 228 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA, 229 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0, 230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1, 231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2, 232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3, 233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND, 234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI, 235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0, 236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1, 237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2, 238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3, 239 0, 240 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI, 241 QLCNIC_HW_CRB_HUB_AGT_ADR_SN, 242 0, 243 QLCNIC_HW_CRB_HUB_AGT_ADR_EG, 244 0, 245 QLCNIC_HW_CRB_HUB_AGT_ADR_PS, 246 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM, 247 0, 248 0, 249 0, 250 0, 251 0, 252 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR, 253 0, 254 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1, 255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2, 256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3, 257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4, 258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5, 259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6, 260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7, 261 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA, 262 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q, 263 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB, 264 0, 265 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0, 266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8, 267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9, 268 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0, 269 0, 270 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB, 271 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0, 272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1, 273 0, 274 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC, 275 0, 276}; 277 278/* PCI Windowing for DDR regions. */ 279 280#define QLCNIC_PCIE_SEM_TIMEOUT 10000 281 282static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data) 283{ 284 u32 dest; 285 void __iomem *val; 286 287 dest = addr & 0xFFFF0000; 288 val = bar0 + QLCNIC_FW_DUMP_REG1; 289 writel(dest, val); 290 readl(val); 291 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); 292 *data = readl(val); 293} 294 295static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data) 296{ 297 u32 dest; 298 void __iomem *val; 299 300 dest = addr & 0xFFFF0000; 301 val = bar0 + QLCNIC_FW_DUMP_REG1; 302 writel(dest, val); 303 readl(val); 304 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); 305 writel(data, val); 306 readl(val); 307} 308 309int 310qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg) 311{ 312 int timeout = 0, err = 0, done = 0; 313 314 while (!done) { 315 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)), 316 &err); 317 if (done == 1) 318 break; 319 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) { 320 if (id_reg) { 321 done = QLCRD32(adapter, id_reg, &err); 322 if (done != -1) 323 dev_err(&adapter->pdev->dev, 324 "Failed to acquire sem=%d lock held by=%d\n", 325 sem, done); 326 else 327 dev_err(&adapter->pdev->dev, 328 "Failed to acquire sem=%d lock", 329 sem); 330 } else { 331 dev_err(&adapter->pdev->dev, 332 "Failed to acquire sem=%d lock", sem); 333 } 334 return -EIO; 335 } 336 udelay(1200); 337 } 338 339 if (id_reg) 340 QLCWR32(adapter, id_reg, adapter->portnum); 341 342 return 0; 343} 344 345void 346qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem) 347{ 348 int err = 0; 349 350 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err); 351} 352 353int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr) 354{ 355 int err = 0; 356 u32 data; 357 358 if (qlcnic_82xx_check(adapter)) 359 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data); 360 else { 361 data = QLCRD32(adapter, addr, &err); 362 if (err == -EIO) 363 return err; 364 } 365 return data; 366} 367 368int qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data) 369{ 370 int ret = 0; 371 372 if (qlcnic_82xx_check(adapter)) 373 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data); 374 else 375 ret = qlcnic_83xx_wrt_reg_indirect(adapter, addr, data); 376 377 return ret; 378} 379 380static int 381qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter, 382 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) 383{ 384 u32 i, producer; 385 struct qlcnic_cmd_buffer *pbuf; 386 struct cmd_desc_type0 *cmd_desc; 387 struct qlcnic_host_tx_ring *tx_ring; 388 389 i = 0; 390 391 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 392 return -EIO; 393 394 tx_ring = &adapter->tx_ring[0]; 395 __netif_tx_lock_bh(tx_ring->txq); 396 397 producer = tx_ring->producer; 398 399 if (nr_desc >= qlcnic_tx_avail(tx_ring)) { 400 netif_tx_stop_queue(tx_ring->txq); 401 smp_mb(); 402 if (qlcnic_tx_avail(tx_ring) > nr_desc) { 403 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH) 404 netif_tx_wake_queue(tx_ring->txq); 405 } else { 406 adapter->stats.xmit_off++; 407 __netif_tx_unlock_bh(tx_ring->txq); 408 return -EBUSY; 409 } 410 } 411 412 do { 413 cmd_desc = &cmd_desc_arr[i]; 414 415 pbuf = &tx_ring->cmd_buf_arr[producer]; 416 pbuf->skb = NULL; 417 pbuf->frag_count = 0; 418 419 memcpy(&tx_ring->desc_head[producer], 420 cmd_desc, sizeof(struct cmd_desc_type0)); 421 422 producer = get_next_index(producer, tx_ring->num_desc); 423 i++; 424 425 } while (i != nr_desc); 426 427 tx_ring->producer = producer; 428 429 qlcnic_update_cmd_producer(tx_ring); 430 431 __netif_tx_unlock_bh(tx_ring->txq); 432 433 return 0; 434} 435 436int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, 437 u16 vlan_id, u8 op) 438{ 439 struct qlcnic_nic_req req; 440 struct qlcnic_mac_req *mac_req; 441 struct qlcnic_vlan_req *vlan_req; 442 u64 word; 443 444 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 445 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23); 446 447 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16); 448 req.req_hdr = cpu_to_le64(word); 449 450 mac_req = (struct qlcnic_mac_req *)&req.words[0]; 451 mac_req->op = op; 452 memcpy(mac_req->mac_addr, addr, ETH_ALEN); 453 454 vlan_req = (struct qlcnic_vlan_req *)&req.words[1]; 455 vlan_req->vlan_id = cpu_to_le16(vlan_id); 456 457 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 458} 459 460int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr) 461{ 462 struct qlcnic_mac_vlan_list *cur; 463 struct list_head *head; 464 int err = -EINVAL; 465 466 /* Delete MAC from the existing list */ 467 list_for_each(head, &adapter->mac_list) { 468 cur = list_entry(head, struct qlcnic_mac_vlan_list, list); 469 if (ether_addr_equal(addr, cur->mac_addr)) { 470 err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr, 471 0, QLCNIC_MAC_DEL); 472 if (err) 473 return err; 474 list_del(&cur->list); 475 kfree(cur); 476 return err; 477 } 478 } 479 return err; 480} 481 482int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan, 483 enum qlcnic_mac_type mac_type) 484{ 485 struct qlcnic_mac_vlan_list *cur; 486 struct list_head *head; 487 488 /* look up if already exists */ 489 list_for_each(head, &adapter->mac_list) { 490 cur = list_entry(head, struct qlcnic_mac_vlan_list, list); 491 if (ether_addr_equal(addr, cur->mac_addr) && 492 cur->vlan_id == vlan) 493 return 0; 494 } 495 496 cur = kzalloc(sizeof(*cur), GFP_ATOMIC); 497 if (cur == NULL) 498 return -ENOMEM; 499 500 memcpy(cur->mac_addr, addr, ETH_ALEN); 501 502 if (qlcnic_sre_macaddr_change(adapter, 503 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) { 504 kfree(cur); 505 return -EIO; 506 } 507 508 cur->vlan_id = vlan; 509 cur->mac_type = mac_type; 510 511 list_add_tail(&cur->list, &adapter->mac_list); 512 return 0; 513} 514 515void qlcnic_flush_mcast_mac(struct qlcnic_adapter *adapter) 516{ 517 struct qlcnic_mac_vlan_list *cur; 518 struct list_head *head, *tmp; 519 520 list_for_each_safe(head, tmp, &adapter->mac_list) { 521 cur = list_entry(head, struct qlcnic_mac_vlan_list, list); 522 if (cur->mac_type != QLCNIC_MULTICAST_MAC) 523 continue; 524 525 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, 526 cur->vlan_id, QLCNIC_MAC_DEL); 527 list_del(&cur->list); 528 kfree(cur); 529 } 530} 531 532static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan) 533{ 534 struct qlcnic_adapter *adapter = netdev_priv(netdev); 535 struct qlcnic_hardware_context *ahw = adapter->ahw; 536 struct netdev_hw_addr *ha; 537 static const u8 bcast_addr[ETH_ALEN] = { 538 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 539 }; 540 u32 mode = VPORT_MISS_MODE_DROP; 541 542 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 543 return; 544 545 qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan, 546 QLCNIC_UNICAST_MAC); 547 qlcnic_nic_add_mac(adapter, bcast_addr, vlan, QLCNIC_BROADCAST_MAC); 548 549 if (netdev->flags & IFF_PROMISC) { 550 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED)) 551 mode = VPORT_MISS_MODE_ACCEPT_ALL; 552 } else if ((netdev->flags & IFF_ALLMULTI) || 553 (netdev_mc_count(netdev) > ahw->max_mc_count)) { 554 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 555 } else if (!netdev_mc_empty(netdev)) { 556 qlcnic_flush_mcast_mac(adapter); 557 netdev_for_each_mc_addr(ha, netdev) 558 qlcnic_nic_add_mac(adapter, ha->addr, vlan, 559 QLCNIC_MULTICAST_MAC); 560 } 561 562 /* configure unicast MAC address, if there is not sufficient space 563 * to store all the unicast addresses then enable promiscuous mode 564 */ 565 if (netdev_uc_count(netdev) > ahw->max_uc_count) { 566 mode = VPORT_MISS_MODE_ACCEPT_ALL; 567 } else if (!netdev_uc_empty(netdev)) { 568 netdev_for_each_uc_addr(ha, netdev) 569 qlcnic_nic_add_mac(adapter, ha->addr, vlan, 570 QLCNIC_UNICAST_MAC); 571 } 572 573 if (mode == VPORT_MISS_MODE_ACCEPT_ALL && 574 !adapter->fdb_mac_learn) { 575 qlcnic_alloc_lb_filters_mem(adapter); 576 adapter->drv_mac_learn = 1; 577 if (adapter->flags & QLCNIC_ESWITCH_ENABLED) 578 adapter->rx_mac_learn = true; 579 } else { 580 adapter->drv_mac_learn = 0; 581 adapter->rx_mac_learn = false; 582 } 583 584 qlcnic_nic_set_promisc(adapter, mode); 585} 586 587void qlcnic_set_multi(struct net_device *netdev) 588{ 589 struct qlcnic_adapter *adapter = netdev_priv(netdev); 590 591 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 592 return; 593 594 if (qlcnic_sriov_vf_check(adapter)) 595 qlcnic_sriov_vf_set_multi(netdev); 596 else 597 __qlcnic_set_multi(netdev, 0); 598} 599 600int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) 601{ 602 struct qlcnic_nic_req req; 603 u64 word; 604 605 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 606 607 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 608 609 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE | 610 ((u64)adapter->portnum << 16); 611 req.req_hdr = cpu_to_le64(word); 612 613 req.words[0] = cpu_to_le64(mode); 614 615 return qlcnic_send_cmd_descs(adapter, 616 (struct cmd_desc_type0 *)&req, 1); 617} 618 619void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter) 620{ 621 struct list_head *head = &adapter->mac_list; 622 struct qlcnic_mac_vlan_list *cur; 623 624 while (!list_empty(head)) { 625 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list); 626 qlcnic_sre_macaddr_change(adapter, 627 cur->mac_addr, 0, QLCNIC_MAC_DEL); 628 list_del(&cur->list); 629 kfree(cur); 630 } 631} 632 633void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter) 634{ 635 struct qlcnic_filter *tmp_fil; 636 struct hlist_node *n; 637 struct hlist_head *head; 638 int i; 639 unsigned long expires; 640 u8 cmd; 641 642 for (i = 0; i < adapter->fhash.fbucket_size; i++) { 643 head = &(adapter->fhash.fhead[i]); 644 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) { 645 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL : 646 QLCNIC_MAC_DEL; 647 expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ; 648 if (time_before(expires, jiffies)) { 649 qlcnic_sre_macaddr_change(adapter, 650 tmp_fil->faddr, 651 tmp_fil->vlan_id, 652 cmd); 653 spin_lock_bh(&adapter->mac_learn_lock); 654 adapter->fhash.fnum--; 655 hlist_del(&tmp_fil->fnode); 656 spin_unlock_bh(&adapter->mac_learn_lock); 657 kfree(tmp_fil); 658 } 659 } 660 } 661 for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) { 662 head = &(adapter->rx_fhash.fhead[i]); 663 664 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) 665 { 666 expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ; 667 if (time_before(expires, jiffies)) { 668 spin_lock_bh(&adapter->rx_mac_learn_lock); 669 adapter->rx_fhash.fnum--; 670 hlist_del(&tmp_fil->fnode); 671 spin_unlock_bh(&adapter->rx_mac_learn_lock); 672 kfree(tmp_fil); 673 } 674 } 675 } 676} 677 678void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter) 679{ 680 struct qlcnic_filter *tmp_fil; 681 struct hlist_node *n; 682 struct hlist_head *head; 683 int i; 684 u8 cmd; 685 686 for (i = 0; i < adapter->fhash.fbucket_size; i++) { 687 head = &(adapter->fhash.fhead[i]); 688 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) { 689 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL : 690 QLCNIC_MAC_DEL; 691 qlcnic_sre_macaddr_change(adapter, 692 tmp_fil->faddr, 693 tmp_fil->vlan_id, 694 cmd); 695 spin_lock_bh(&adapter->mac_learn_lock); 696 adapter->fhash.fnum--; 697 hlist_del(&tmp_fil->fnode); 698 spin_unlock_bh(&adapter->mac_learn_lock); 699 kfree(tmp_fil); 700 } 701 } 702} 703 704static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag) 705{ 706 struct qlcnic_nic_req req; 707 int rv; 708 709 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 710 711 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 712 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK | 713 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32)); 714 715 req.words[0] = cpu_to_le64(flag); 716 717 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 718 if (rv != 0) 719 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n", 720 flag ? "Set" : "Reset"); 721 return rv; 722} 723 724int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 725{ 726 if (qlcnic_set_fw_loopback(adapter, mode)) 727 return -EIO; 728 729 if (qlcnic_nic_set_promisc(adapter, 730 VPORT_MISS_MODE_ACCEPT_ALL)) { 731 qlcnic_set_fw_loopback(adapter, 0); 732 return -EIO; 733 } 734 735 msleep(1000); 736 return 0; 737} 738 739int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 740{ 741 struct net_device *netdev = adapter->netdev; 742 743 mode = VPORT_MISS_MODE_DROP; 744 qlcnic_set_fw_loopback(adapter, 0); 745 746 if (netdev->flags & IFF_PROMISC) 747 mode = VPORT_MISS_MODE_ACCEPT_ALL; 748 else if (netdev->flags & IFF_ALLMULTI) 749 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 750 751 qlcnic_nic_set_promisc(adapter, mode); 752 msleep(1000); 753 return 0; 754} 755 756int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter) 757{ 758 u8 mac[ETH_ALEN]; 759 int ret; 760 761 ret = qlcnic_get_mac_address(adapter, mac, 762 adapter->ahw->physical_port); 763 if (ret) 764 return ret; 765 766 memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN); 767 adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID; 768 769 return 0; 770} 771 772int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter) 773{ 774 struct qlcnic_nic_req req; 775 int rv; 776 777 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 778 779 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 780 781 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE | 782 ((u64) adapter->portnum << 16)); 783 784 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32); 785 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets | 786 ((u64) adapter->ahw->coal.rx_time_us) << 16); 787 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out | 788 ((u64) adapter->ahw->coal.type) << 32 | 789 ((u64) adapter->ahw->coal.sts_ring_mask) << 40); 790 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 791 if (rv != 0) 792 dev_err(&adapter->netdev->dev, 793 "Could not send interrupt coalescing parameters\n"); 794 795 return rv; 796} 797 798/* Send the interrupt coalescing parameter set by ethtool to the card. */ 799int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter, 800 struct ethtool_coalesce *ethcoal) 801{ 802 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 803 int rv; 804 805 coal->flag = QLCNIC_INTR_DEFAULT; 806 coal->rx_time_us = ethcoal->rx_coalesce_usecs; 807 coal->rx_packets = ethcoal->rx_max_coalesced_frames; 808 809 rv = qlcnic_82xx_set_rx_coalesce(adapter); 810 811 if (rv) 812 netdev_err(adapter->netdev, 813 "Failed to set Rx coalescing parameters\n"); 814 815 return rv; 816} 817 818#define QLCNIC_ENABLE_IPV4_LRO BIT_0 819#define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9) 820 821int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable) 822{ 823 struct qlcnic_nic_req req; 824 u64 word; 825 int rv; 826 827 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 828 return 0; 829 830 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 831 832 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 833 834 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); 835 req.req_hdr = cpu_to_le64(word); 836 837 word = 0; 838 if (enable) { 839 word = QLCNIC_ENABLE_IPV4_LRO; 840 if (adapter->ahw->extra_capability[0] & 841 QLCNIC_FW_CAP2_HW_LRO_IPV6) 842 word |= QLCNIC_ENABLE_IPV6_LRO; 843 } 844 845 req.words[0] = cpu_to_le64(word); 846 847 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 848 if (rv != 0) 849 dev_err(&adapter->netdev->dev, 850 "Could not send configure hw lro request\n"); 851 852 return rv; 853} 854 855int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable) 856{ 857 struct qlcnic_nic_req req; 858 u64 word; 859 int rv; 860 861 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable) 862 return 0; 863 864 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 865 866 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 867 868 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING | 869 ((u64)adapter->portnum << 16); 870 req.req_hdr = cpu_to_le64(word); 871 872 req.words[0] = cpu_to_le64(enable); 873 874 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 875 if (rv != 0) 876 dev_err(&adapter->netdev->dev, 877 "Could not send configure bridge mode request\n"); 878 879 adapter->flags ^= QLCNIC_BRIDGE_ENABLED; 880 881 return rv; 882} 883 884 885#define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3 886#define QLCNIC_ENABLE_TYPE_C_RSS BIT_10 887#define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63) 888#define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL 889 890int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable) 891{ 892 struct qlcnic_nic_req req; 893 u64 word; 894 int i, rv; 895 896 static const u64 key[] = { 897 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 898 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 899 0x255b0ec26d5a56daULL 900 }; 901 902 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 903 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 904 905 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); 906 req.req_hdr = cpu_to_le64(word); 907 908 /* 909 * RSS request: 910 * bits 3-0: hash_method 911 * 5-4: hash_type_ipv4 912 * 7-6: hash_type_ipv6 913 * 8: enable 914 * 9: use indirection table 915 * 10: type-c rss 916 * 11: udp rss 917 * 47-12: reserved 918 * 62-48: indirection table mask 919 * 63: feature flag 920 */ 921 word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 922 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 923 ((u64)(enable & 0x1) << 8) | 924 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) | 925 (u64)QLCNIC_ENABLE_TYPE_C_RSS | 926 (u64)QLCNIC_RSS_FEATURE_FLAG; 927 928 req.words[0] = cpu_to_le64(word); 929 for (i = 0; i < 5; i++) 930 req.words[i+1] = cpu_to_le64(key[i]); 931 932 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 933 if (rv != 0) 934 dev_err(&adapter->netdev->dev, "could not configure RSS\n"); 935 936 return rv; 937} 938 939void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter, 940 __be32 ip, int cmd) 941{ 942 struct qlcnic_nic_req req; 943 struct qlcnic_ipaddr *ipa; 944 u64 word; 945 int rv; 946 947 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 948 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 949 950 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); 951 req.req_hdr = cpu_to_le64(word); 952 953 req.words[0] = cpu_to_le64(cmd); 954 ipa = (struct qlcnic_ipaddr *)&req.words[1]; 955 ipa->ipv4 = ip; 956 957 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 958 if (rv != 0) 959 dev_err(&adapter->netdev->dev, 960 "could not notify %s IP 0x%x request\n", 961 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip); 962} 963 964int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable) 965{ 966 struct qlcnic_nic_req req; 967 u64 word; 968 int rv; 969 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 970 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 971 972 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); 973 req.req_hdr = cpu_to_le64(word); 974 req.words[0] = cpu_to_le64(enable | (enable << 8)); 975 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 976 if (rv != 0) 977 dev_err(&adapter->netdev->dev, 978 "could not configure link notification\n"); 979 980 return rv; 981} 982 983static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter) 984{ 985 struct qlcnic_nic_req req; 986 u64 word; 987 int rv; 988 989 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 990 return 0; 991 992 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 993 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 994 995 word = QLCNIC_H2C_OPCODE_LRO_REQUEST | 996 ((u64)adapter->portnum << 16) | 997 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ; 998 999 req.req_hdr = cpu_to_le64(word); 1000 1001 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 1002 if (rv != 0) 1003 dev_err(&adapter->netdev->dev, 1004 "could not cleanup lro flows\n"); 1005 1006 return rv; 1007} 1008 1009/* 1010 * qlcnic_change_mtu - Change the Maximum Transfer Unit 1011 * @returns 0 on success, negative on failure 1012 */ 1013 1014int qlcnic_change_mtu(struct net_device *netdev, int mtu) 1015{ 1016 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1017 int rc = 0; 1018 1019 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu); 1020 1021 if (!rc) 1022 netdev->mtu = mtu; 1023 1024 return rc; 1025} 1026 1027static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter, 1028 netdev_features_t features) 1029{ 1030 u32 offload_flags = adapter->offload_flags; 1031 1032 if (offload_flags & BIT_0) { 1033 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 1034 NETIF_F_IPV6_CSUM; 1035 adapter->rx_csum = 1; 1036 if (QLCNIC_IS_TSO_CAPABLE(adapter)) { 1037 if (!(offload_flags & BIT_1)) 1038 features &= ~NETIF_F_TSO; 1039 else 1040 features |= NETIF_F_TSO; 1041 1042 if (!(offload_flags & BIT_2)) 1043 features &= ~NETIF_F_TSO6; 1044 else 1045 features |= NETIF_F_TSO6; 1046 } 1047 } else { 1048 features &= ~(NETIF_F_RXCSUM | 1049 NETIF_F_IP_CSUM | 1050 NETIF_F_IPV6_CSUM); 1051 1052 if (QLCNIC_IS_TSO_CAPABLE(adapter)) 1053 features &= ~(NETIF_F_TSO | NETIF_F_TSO6); 1054 adapter->rx_csum = 0; 1055 } 1056 1057 return features; 1058} 1059 1060netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1061 netdev_features_t features) 1062{ 1063 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1064 netdev_features_t changed; 1065 1066 if (qlcnic_82xx_check(adapter) && 1067 (adapter->flags & QLCNIC_ESWITCH_ENABLED)) { 1068 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) { 1069 features = qlcnic_process_flags(adapter, features); 1070 } else { 1071 changed = features ^ netdev->features; 1072 features ^= changed & (NETIF_F_RXCSUM | 1073 NETIF_F_IP_CSUM | 1074 NETIF_F_IPV6_CSUM | 1075 NETIF_F_TSO | 1076 NETIF_F_TSO6); 1077 } 1078 } 1079 1080 if (!(features & NETIF_F_RXCSUM)) 1081 features &= ~NETIF_F_LRO; 1082 1083 return features; 1084} 1085 1086 1087int qlcnic_set_features(struct net_device *netdev, netdev_features_t features) 1088{ 1089 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1090 netdev_features_t changed = netdev->features ^ features; 1091 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0; 1092 1093 if (!(changed & NETIF_F_LRO)) 1094 return 0; 1095 1096 netdev->features ^= NETIF_F_LRO; 1097 1098 if (qlcnic_config_hw_lro(adapter, hw_lro)) 1099 return -EIO; 1100 1101 if (!hw_lro && qlcnic_82xx_check(adapter)) { 1102 if (qlcnic_send_lro_cleanup(adapter)) 1103 return -EIO; 1104 } 1105 1106 return 0; 1107} 1108 1109/* 1110 * Changes the CRB window to the specified window. 1111 */ 1112 /* Returns < 0 if off is not valid, 1113 * 1 if window access is needed. 'off' is set to offset from 1114 * CRB space in 128M pci map 1115 * 0 if no window access is needed. 'off' is set to 2M addr 1116 * In: 'off' is offset from base in 128M pci map 1117 */ 1118static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw, 1119 ulong off, void __iomem **addr) 1120{ 1121 const struct crb_128M_2M_sub_block_map *m; 1122 1123 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE)) 1124 return -EINVAL; 1125 1126 off -= QLCNIC_PCI_CRBSPACE; 1127 1128 /* 1129 * Try direct map 1130 */ 1131 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; 1132 1133 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { 1134 *addr = ahw->pci_base0 + m->start_2M + 1135 (off - m->start_128M); 1136 return 0; 1137 } 1138 1139 /* 1140 * Not in direct map, use crb window 1141 */ 1142 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16)); 1143 return 1; 1144} 1145 1146/* 1147 * In: 'off' is offset from CRB space in 128M pci map 1148 * Out: 'off' is 2M pci map addr 1149 * side effect: lock crb window 1150 */ 1151static int 1152qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off) 1153{ 1154 u32 window; 1155 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M; 1156 1157 off -= QLCNIC_PCI_CRBSPACE; 1158 1159 window = CRB_HI(off); 1160 if (window == 0) { 1161 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off); 1162 return -EIO; 1163 } 1164 1165 writel(window, addr); 1166 if (readl(addr) != window) { 1167 if (printk_ratelimit()) 1168 dev_warn(&adapter->pdev->dev, 1169 "failed to set CRB window to %d off 0x%lx\n", 1170 window, off); 1171 return -EIO; 1172 } 1173 return 0; 1174} 1175 1176int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, 1177 u32 data) 1178{ 1179 unsigned long flags; 1180 int rv; 1181 void __iomem *addr = NULL; 1182 1183 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr); 1184 1185 if (rv == 0) { 1186 writel(data, addr); 1187 return 0; 1188 } 1189 1190 if (rv > 0) { 1191 /* indirect access */ 1192 write_lock_irqsave(&adapter->ahw->crb_lock, flags); 1193 crb_win_lock(adapter); 1194 rv = qlcnic_pci_set_crbwindow_2M(adapter, off); 1195 if (!rv) 1196 writel(data, addr); 1197 crb_win_unlock(adapter); 1198 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags); 1199 return rv; 1200 } 1201 1202 dev_err(&adapter->pdev->dev, 1203 "%s: invalid offset: 0x%016lx\n", __func__, off); 1204 dump_stack(); 1205 return -EIO; 1206} 1207 1208int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off, 1209 int *err) 1210{ 1211 unsigned long flags; 1212 int rv; 1213 u32 data = -1; 1214 void __iomem *addr = NULL; 1215 1216 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr); 1217 1218 if (rv == 0) 1219 return readl(addr); 1220 1221 if (rv > 0) { 1222 /* indirect access */ 1223 write_lock_irqsave(&adapter->ahw->crb_lock, flags); 1224 crb_win_lock(adapter); 1225 if (!qlcnic_pci_set_crbwindow_2M(adapter, off)) 1226 data = readl(addr); 1227 crb_win_unlock(adapter); 1228 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags); 1229 return data; 1230 } 1231 1232 dev_err(&adapter->pdev->dev, 1233 "%s: invalid offset: 0x%016lx\n", __func__, off); 1234 dump_stack(); 1235 return -1; 1236} 1237 1238void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw, 1239 u32 offset) 1240{ 1241 void __iomem *addr = NULL; 1242 1243 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr)); 1244 1245 return addr; 1246} 1247 1248static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, 1249 u32 window, u64 off, u64 *data, int op) 1250{ 1251 void __iomem *addr; 1252 u32 start; 1253 1254 mutex_lock(&adapter->ahw->mem_lock); 1255 1256 writel(window, adapter->ahw->ocm_win_crb); 1257 /* read back to flush */ 1258 readl(adapter->ahw->ocm_win_crb); 1259 start = QLCNIC_PCI_OCM0_2M + off; 1260 1261 addr = adapter->ahw->pci_base0 + start; 1262 1263 if (op == 0) /* read */ 1264 *data = readq(addr); 1265 else /* write */ 1266 writeq(*data, addr); 1267 1268 /* Set window to 0 */ 1269 writel(0, adapter->ahw->ocm_win_crb); 1270 readl(adapter->ahw->ocm_win_crb); 1271 1272 mutex_unlock(&adapter->ahw->mem_lock); 1273 return 0; 1274} 1275 1276static void 1277qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) 1278{ 1279 void __iomem *addr = adapter->ahw->pci_base0 + 1280 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM); 1281 1282 mutex_lock(&adapter->ahw->mem_lock); 1283 *data = readq(addr); 1284 mutex_unlock(&adapter->ahw->mem_lock); 1285} 1286 1287static void 1288qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data) 1289{ 1290 void __iomem *addr = adapter->ahw->pci_base0 + 1291 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM); 1292 1293 mutex_lock(&adapter->ahw->mem_lock); 1294 writeq(data, addr); 1295 mutex_unlock(&adapter->ahw->mem_lock); 1296} 1297 1298 1299 1300/* Set MS memory control data for different adapters */ 1301static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off, 1302 struct qlcnic_ms_reg_ctrl *ms) 1303{ 1304 ms->control = QLCNIC_MS_CTRL; 1305 ms->low = QLCNIC_MS_ADDR_LO; 1306 ms->hi = QLCNIC_MS_ADDR_HI; 1307 if (off & 0xf) { 1308 ms->wd[0] = QLCNIC_MS_WRTDATA_LO; 1309 ms->rd[0] = QLCNIC_MS_RDDATA_LO; 1310 ms->wd[1] = QLCNIC_MS_WRTDATA_HI; 1311 ms->rd[1] = QLCNIC_MS_RDDATA_HI; 1312 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO; 1313 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI; 1314 ms->rd[2] = QLCNIC_MS_RDDATA_ULO; 1315 ms->rd[3] = QLCNIC_MS_RDDATA_UHI; 1316 } else { 1317 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO; 1318 ms->rd[0] = QLCNIC_MS_RDDATA_ULO; 1319 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI; 1320 ms->rd[1] = QLCNIC_MS_RDDATA_UHI; 1321 ms->wd[2] = QLCNIC_MS_WRTDATA_LO; 1322 ms->wd[3] = QLCNIC_MS_WRTDATA_HI; 1323 ms->rd[2] = QLCNIC_MS_RDDATA_LO; 1324 ms->rd[3] = QLCNIC_MS_RDDATA_HI; 1325 } 1326 1327 ms->ocm_window = OCM_WIN_P3P(off); 1328 ms->off = GET_MEM_OFFS_2M(off); 1329} 1330 1331int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data) 1332{ 1333 int j, ret = 0; 1334 u32 temp, off8; 1335 struct qlcnic_ms_reg_ctrl ms; 1336 1337 /* Only 64-bit aligned access */ 1338 if (off & 7) 1339 return -EIO; 1340 1341 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); 1342 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, 1343 QLCNIC_ADDR_QDR_NET_MAX) || 1344 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, 1345 QLCNIC_ADDR_DDR_NET_MAX))) 1346 return -EIO; 1347 1348 qlcnic_set_ms_controls(adapter, off, &ms); 1349 1350 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) 1351 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window, 1352 ms.off, &data, 1); 1353 1354 off8 = off & ~0xf; 1355 1356 mutex_lock(&adapter->ahw->mem_lock); 1357 1358 qlcnic_ind_wr(adapter, ms.low, off8); 1359 qlcnic_ind_wr(adapter, ms.hi, 0); 1360 1361 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE); 1362 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE); 1363 1364 for (j = 0; j < MAX_CTL_CHECK; j++) { 1365 temp = qlcnic_ind_rd(adapter, ms.control); 1366 if ((temp & TA_CTL_BUSY) == 0) 1367 break; 1368 } 1369 1370 if (j >= MAX_CTL_CHECK) { 1371 ret = -EIO; 1372 goto done; 1373 } 1374 1375 /* This is the modify part of read-modify-write */ 1376 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0])); 1377 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1])); 1378 /* This is the write part of read-modify-write */ 1379 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff); 1380 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff); 1381 1382 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE); 1383 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START); 1384 1385 for (j = 0; j < MAX_CTL_CHECK; j++) { 1386 temp = qlcnic_ind_rd(adapter, ms.control); 1387 if ((temp & TA_CTL_BUSY) == 0) 1388 break; 1389 } 1390 1391 if (j >= MAX_CTL_CHECK) { 1392 if (printk_ratelimit()) 1393 dev_err(&adapter->pdev->dev, 1394 "failed to write through agent\n"); 1395 ret = -EIO; 1396 } else 1397 ret = 0; 1398 1399done: 1400 mutex_unlock(&adapter->ahw->mem_lock); 1401 1402 return ret; 1403} 1404 1405int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) 1406{ 1407 int j, ret; 1408 u32 temp, off8; 1409 u64 val; 1410 struct qlcnic_ms_reg_ctrl ms; 1411 1412 /* Only 64-bit aligned access */ 1413 if (off & 7) 1414 return -EIO; 1415 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, 1416 QLCNIC_ADDR_QDR_NET_MAX) || 1417 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, 1418 QLCNIC_ADDR_DDR_NET_MAX))) 1419 return -EIO; 1420 1421 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); 1422 qlcnic_set_ms_controls(adapter, off, &ms); 1423 1424 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) 1425 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window, 1426 ms.off, data, 0); 1427 1428 mutex_lock(&adapter->ahw->mem_lock); 1429 1430 off8 = off & ~0xf; 1431 1432 qlcnic_ind_wr(adapter, ms.low, off8); 1433 qlcnic_ind_wr(adapter, ms.hi, 0); 1434 1435 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE); 1436 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE); 1437 1438 for (j = 0; j < MAX_CTL_CHECK; j++) { 1439 temp = qlcnic_ind_rd(adapter, ms.control); 1440 if ((temp & TA_CTL_BUSY) == 0) 1441 break; 1442 } 1443 1444 if (j >= MAX_CTL_CHECK) { 1445 if (printk_ratelimit()) 1446 dev_err(&adapter->pdev->dev, 1447 "failed to read through agent\n"); 1448 ret = -EIO; 1449 } else { 1450 1451 temp = qlcnic_ind_rd(adapter, ms.rd[3]); 1452 val = (u64)temp << 32; 1453 val |= qlcnic_ind_rd(adapter, ms.rd[2]); 1454 *data = val; 1455 ret = 0; 1456 } 1457 1458 mutex_unlock(&adapter->ahw->mem_lock); 1459 1460 return ret; 1461} 1462 1463int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter) 1464{ 1465 int offset, board_type, magic, err = 0; 1466 struct pci_dev *pdev = adapter->pdev; 1467 1468 offset = QLCNIC_FW_MAGIC_OFFSET; 1469 if (qlcnic_rom_fast_read(adapter, offset, &magic)) 1470 return -EIO; 1471 1472 if (magic != QLCNIC_BDINFO_MAGIC) { 1473 dev_err(&pdev->dev, "invalid board config, magic=%08x\n", 1474 magic); 1475 return -EIO; 1476 } 1477 1478 offset = QLCNIC_BRDTYPE_OFFSET; 1479 if (qlcnic_rom_fast_read(adapter, offset, &board_type)) 1480 return -EIO; 1481 1482 adapter->ahw->board_type = board_type; 1483 1484 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) { 1485 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err); 1486 if (err == -EIO) 1487 return err; 1488 if ((gpio & 0x8000) == 0) 1489 board_type = QLCNIC_BRDTYPE_P3P_10G_TP; 1490 } 1491 1492 switch (board_type) { 1493 case QLCNIC_BRDTYPE_P3P_HMEZ: 1494 case QLCNIC_BRDTYPE_P3P_XG_LOM: 1495 case QLCNIC_BRDTYPE_P3P_10G_CX4: 1496 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP: 1497 case QLCNIC_BRDTYPE_P3P_IMEZ: 1498 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS: 1499 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT: 1500 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT: 1501 case QLCNIC_BRDTYPE_P3P_10G_XFP: 1502 case QLCNIC_BRDTYPE_P3P_10000_BASE_T: 1503 adapter->ahw->port_type = QLCNIC_XGBE; 1504 break; 1505 case QLCNIC_BRDTYPE_P3P_REF_QG: 1506 case QLCNIC_BRDTYPE_P3P_4_GB: 1507 case QLCNIC_BRDTYPE_P3P_4_GB_MM: 1508 adapter->ahw->port_type = QLCNIC_GBE; 1509 break; 1510 case QLCNIC_BRDTYPE_P3P_10G_TP: 1511 adapter->ahw->port_type = (adapter->portnum < 2) ? 1512 QLCNIC_XGBE : QLCNIC_GBE; 1513 break; 1514 default: 1515 dev_err(&pdev->dev, "unknown board type %x\n", board_type); 1516 adapter->ahw->port_type = QLCNIC_XGBE; 1517 break; 1518 } 1519 1520 return 0; 1521} 1522 1523static int 1524qlcnic_wol_supported(struct qlcnic_adapter *adapter) 1525{ 1526 u32 wol_cfg; 1527 int err = 0; 1528 1529 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err); 1530 if (wol_cfg & (1UL << adapter->portnum)) { 1531 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err); 1532 if (err == -EIO) 1533 return err; 1534 if (wol_cfg & (1 << adapter->portnum)) 1535 return 1; 1536 } 1537 1538 return 0; 1539} 1540 1541int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate) 1542{ 1543 struct qlcnic_nic_req req; 1544 int rv; 1545 u64 word; 1546 1547 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 1548 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 1549 1550 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16); 1551 req.req_hdr = cpu_to_le64(word); 1552 1553 req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum); 1554 req.words[1] = cpu_to_le64(state); 1555 1556 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 1557 if (rv) 1558 dev_err(&adapter->pdev->dev, "LED configuration failed.\n"); 1559 1560 return rv; 1561} 1562 1563void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter) 1564{ 1565 struct qlcnic_hardware_context *ahw = adapter->ahw; 1566 struct qlcnic_cmd_args cmd; 1567 u8 beacon_state; 1568 int err = 0; 1569 1570 if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) { 1571 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1572 QLCNIC_CMD_GET_LED_STATUS); 1573 if (!err) { 1574 err = qlcnic_issue_cmd(adapter, &cmd); 1575 if (err) { 1576 netdev_err(adapter->netdev, 1577 "Failed to get current beacon state, err=%d\n", 1578 err); 1579 } else { 1580 beacon_state = cmd.rsp.arg[1]; 1581 if (beacon_state == QLCNIC_BEACON_DISABLE) 1582 ahw->beacon_state = QLCNIC_BEACON_OFF; 1583 else if (beacon_state == QLCNIC_BEACON_EANBLE) 1584 ahw->beacon_state = QLCNIC_BEACON_ON; 1585 } 1586 } 1587 qlcnic_free_mbx_args(&cmd); 1588 } 1589 1590 return; 1591} 1592 1593void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter) 1594{ 1595 void __iomem *msix_base_addr; 1596 u32 func; 1597 u32 msix_base; 1598 1599 pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func); 1600 msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE; 1601 msix_base = readl(msix_base_addr); 1602 func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE; 1603 adapter->ahw->pci_func = func; 1604} 1605 1606void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf, 1607 loff_t offset, size_t size) 1608{ 1609 int err = 0; 1610 u32 data; 1611 u64 qmdata; 1612 1613 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) { 1614 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata); 1615 memcpy(buf, &qmdata, size); 1616 } else { 1617 data = QLCRD32(adapter, offset, &err); 1618 memcpy(buf, &data, size); 1619 } 1620} 1621 1622void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf, 1623 loff_t offset, size_t size) 1624{ 1625 u32 data; 1626 u64 qmdata; 1627 1628 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) { 1629 memcpy(&qmdata, buf, size); 1630 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata); 1631 } else { 1632 memcpy(&data, buf, size); 1633 QLCWR32(adapter, offset, data); 1634 } 1635} 1636 1637int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter) 1638{ 1639 return qlcnic_pcie_sem_lock(adapter, 5, 0); 1640} 1641 1642void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter) 1643{ 1644 qlcnic_pcie_sem_unlock(adapter, 5); 1645} 1646 1647int qlcnic_82xx_shutdown(struct pci_dev *pdev) 1648{ 1649 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 1650 struct net_device *netdev = adapter->netdev; 1651 1652 netif_device_detach(netdev); 1653 1654 qlcnic_cancel_idc_work(adapter); 1655 1656 if (netif_running(netdev)) 1657 qlcnic_down(adapter, netdev); 1658 1659 qlcnic_clr_all_drv_state(adapter, 0); 1660 1661 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1662 1663 if (qlcnic_wol_supported(adapter)) 1664 device_wakeup_enable(&pdev->dev); 1665 1666 return 0; 1667} 1668 1669int qlcnic_82xx_resume(struct qlcnic_adapter *adapter) 1670{ 1671 struct net_device *netdev = adapter->netdev; 1672 int err; 1673 1674 err = qlcnic_start_firmware(adapter); 1675 if (err) { 1676 dev_err(&adapter->pdev->dev, "failed to start firmware\n"); 1677 return err; 1678 } 1679 1680 if (netif_running(netdev)) { 1681 err = qlcnic_up(adapter, netdev); 1682 if (!err) 1683 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 1684 } 1685 1686 netif_device_attach(netdev); 1687 qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY); 1688 return err; 1689} 1690