1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7#ifndef _QED_MCP_H 8#define _QED_MCP_H 9 10#include <linux/types.h> 11#include <linux/delay.h> 12#include <linux/slab.h> 13#include <linux/spinlock.h> 14#include <linux/qed/qed_fcoe_if.h> 15#include "qed_hsi.h" 16#include "qed_dev_api.h" 17 18struct qed_mcp_link_speed_params { 19 bool autoneg; 20 21 u32 advertised_speeds; 22#define QED_EXT_SPEED_MASK_RES 0x1 23#define QED_EXT_SPEED_MASK_1G 0x2 24#define QED_EXT_SPEED_MASK_10G 0x4 25#define QED_EXT_SPEED_MASK_20G 0x8 26#define QED_EXT_SPEED_MASK_25G 0x10 27#define QED_EXT_SPEED_MASK_40G 0x20 28#define QED_EXT_SPEED_MASK_50G_R 0x40 29#define QED_EXT_SPEED_MASK_50G_R2 0x80 30#define QED_EXT_SPEED_MASK_100G_R2 0x100 31#define QED_EXT_SPEED_MASK_100G_R4 0x200 32#define QED_EXT_SPEED_MASK_100G_P4 0x400 33 34 u32 forced_speed; /* In Mb/s */ 35#define QED_EXT_SPEED_1G 0x1 36#define QED_EXT_SPEED_10G 0x2 37#define QED_EXT_SPEED_20G 0x4 38#define QED_EXT_SPEED_25G 0x8 39#define QED_EXT_SPEED_40G 0x10 40#define QED_EXT_SPEED_50G_R 0x20 41#define QED_EXT_SPEED_50G_R2 0x40 42#define QED_EXT_SPEED_100G_R2 0x80 43#define QED_EXT_SPEED_100G_R4 0x100 44#define QED_EXT_SPEED_100G_P4 0x200 45}; 46 47struct qed_mcp_link_pause_params { 48 bool autoneg; 49 bool forced_rx; 50 bool forced_tx; 51}; 52 53enum qed_mcp_eee_mode { 54 QED_MCP_EEE_DISABLED, 55 QED_MCP_EEE_ENABLED, 56 QED_MCP_EEE_UNSUPPORTED 57}; 58 59struct qed_mcp_link_params { 60 struct qed_mcp_link_speed_params speed; 61 struct qed_mcp_link_pause_params pause; 62 u32 loopback_mode; 63 struct qed_link_eee_params eee; 64 u32 fec; 65 66 struct qed_mcp_link_speed_params ext_speed; 67 u32 ext_fec_mode; 68}; 69 70struct qed_mcp_link_capabilities { 71 u32 speed_capabilities; 72 bool default_speed_autoneg; 73 u32 fec_default; 74 enum qed_mcp_eee_mode default_eee; 75 u32 eee_lpi_timer; 76 u8 eee_speed_caps; 77 78 u32 default_ext_speed_caps; 79 u32 default_ext_autoneg; 80 u32 default_ext_speed; 81 u32 default_ext_fec; 82}; 83 84struct qed_mcp_link_state { 85 bool link_up; 86 u32 min_pf_rate; 87 88 /* Actual link speed in Mb/s */ 89 u32 line_speed; 90 91 /* PF max speed in Mb/s, deduced from line_speed 92 * according to PF max bandwidth configuration. 93 */ 94 u32 speed; 95 96 bool full_duplex; 97 bool an; 98 bool an_complete; 99 bool parallel_detection; 100 bool pfc_enabled; 101 102 u32 partner_adv_speed; 103#define QED_LINK_PARTNER_SPEED_1G_HD BIT(0) 104#define QED_LINK_PARTNER_SPEED_1G_FD BIT(1) 105#define QED_LINK_PARTNER_SPEED_10G BIT(2) 106#define QED_LINK_PARTNER_SPEED_20G BIT(3) 107#define QED_LINK_PARTNER_SPEED_25G BIT(4) 108#define QED_LINK_PARTNER_SPEED_40G BIT(5) 109#define QED_LINK_PARTNER_SPEED_50G BIT(6) 110#define QED_LINK_PARTNER_SPEED_100G BIT(7) 111 112 bool partner_tx_flow_ctrl_en; 113 bool partner_rx_flow_ctrl_en; 114 115 u8 partner_adv_pause; 116#define QED_LINK_PARTNER_SYMMETRIC_PAUSE 0x1 117#define QED_LINK_PARTNER_ASYMMETRIC_PAUSE 0x2 118#define QED_LINK_PARTNER_BOTH_PAUSE 0x3 119 120 bool sfp_tx_fault; 121 bool eee_active; 122 u8 eee_adv_caps; 123 u8 eee_lp_adv_caps; 124 125 u32 fec_active; 126}; 127 128struct qed_mcp_function_info { 129 u8 pause_on_host; 130 131 enum qed_pci_personality protocol; 132 133 u8 bandwidth_min; 134 u8 bandwidth_max; 135 136 u8 mac[ETH_ALEN]; 137 138 u64 wwn_port; 139 u64 wwn_node; 140 141#define QED_MCP_VLAN_UNSET (0xffff) 142 u16 ovlan; 143 144 u16 mtu; 145}; 146 147struct qed_mcp_nvm_common { 148 u32 offset; 149 u32 param; 150 u32 resp; 151 u32 cmd; 152}; 153 154struct qed_mcp_drv_version { 155 u32 version; 156 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 157}; 158 159struct qed_mcp_lan_stats { 160 u64 ucast_rx_pkts; 161 u64 ucast_tx_pkts; 162 u32 fcs_err; 163}; 164 165struct qed_mcp_fcoe_stats { 166 u64 rx_pkts; 167 u64 tx_pkts; 168 u32 fcs_err; 169 u32 login_failure; 170}; 171 172struct qed_mcp_iscsi_stats { 173 u64 rx_pdus; 174 u64 tx_pdus; 175 u64 rx_bytes; 176 u64 tx_bytes; 177}; 178 179struct qed_mcp_rdma_stats { 180 u64 rx_pkts; 181 u64 tx_pkts; 182 u64 rx_bytes; 183 u64 tx_byts; 184}; 185 186enum qed_mcp_protocol_type { 187 QED_MCP_LAN_STATS, 188 QED_MCP_FCOE_STATS, 189 QED_MCP_ISCSI_STATS, 190 QED_MCP_RDMA_STATS 191}; 192 193union qed_mcp_protocol_stats { 194 struct qed_mcp_lan_stats lan_stats; 195 struct qed_mcp_fcoe_stats fcoe_stats; 196 struct qed_mcp_iscsi_stats iscsi_stats; 197 struct qed_mcp_rdma_stats rdma_stats; 198}; 199 200enum qed_ov_eswitch { 201 QED_OV_ESWITCH_NONE, 202 QED_OV_ESWITCH_VEB, 203 QED_OV_ESWITCH_VEPA 204}; 205 206enum qed_ov_client { 207 QED_OV_CLIENT_DRV, 208 QED_OV_CLIENT_USER, 209 QED_OV_CLIENT_VENDOR_SPEC 210}; 211 212enum qed_ov_driver_state { 213 QED_OV_DRIVER_STATE_NOT_LOADED, 214 QED_OV_DRIVER_STATE_DISABLED, 215 QED_OV_DRIVER_STATE_ACTIVE 216}; 217 218enum qed_ov_wol { 219 QED_OV_WOL_DEFAULT, 220 QED_OV_WOL_DISABLED, 221 QED_OV_WOL_ENABLED 222}; 223 224enum qed_mfw_tlv_type { 225 QED_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 226 QED_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 227 QED_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 228 QED_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 229 QED_MFW_TLV_MAX = 0x16, 230}; 231 232struct qed_mfw_tlv_generic { 233#define QED_MFW_TLV_FLAGS_SIZE 2 234 struct { 235 u8 ipv4_csum_offload; 236 u8 lso_supported; 237 bool b_set; 238 } flags; 239 240#define QED_MFW_TLV_MAC_COUNT 3 241 /* First entry for primary MAC, 2 secondary MACs possible */ 242 u8 mac[QED_MFW_TLV_MAC_COUNT][6]; 243 bool mac_set[QED_MFW_TLV_MAC_COUNT]; 244 245 u64 rx_frames; 246 bool rx_frames_set; 247 u64 rx_bytes; 248 bool rx_bytes_set; 249 u64 tx_frames; 250 bool tx_frames_set; 251 u64 tx_bytes; 252 bool tx_bytes_set; 253}; 254 255union qed_mfw_tlv_data { 256 struct qed_mfw_tlv_generic generic; 257 struct qed_mfw_tlv_eth eth; 258 struct qed_mfw_tlv_fcoe fcoe; 259 struct qed_mfw_tlv_iscsi iscsi; 260}; 261 262#define QED_NVM_CFG_OPTION_ALL BIT(0) 263#define QED_NVM_CFG_OPTION_INIT BIT(1) 264#define QED_NVM_CFG_OPTION_COMMIT BIT(2) 265#define QED_NVM_CFG_OPTION_FREE BIT(3) 266#define QED_NVM_CFG_OPTION_ENTITY_SEL BIT(4) 267 268/** 269 * @brief - returns the link params of the hw function 270 * 271 * @param p_hwfn 272 * 273 * @returns pointer to link params 274 */ 275struct qed_mcp_link_params *qed_mcp_get_link_params(struct qed_hwfn *); 276 277/** 278 * @brief - return the link state of the hw function 279 * 280 * @param p_hwfn 281 * 282 * @returns pointer to link state 283 */ 284struct qed_mcp_link_state *qed_mcp_get_link_state(struct qed_hwfn *); 285 286/** 287 * @brief - return the link capabilities of the hw function 288 * 289 * @param p_hwfn 290 * 291 * @returns pointer to link capabilities 292 */ 293struct qed_mcp_link_capabilities 294 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn); 295 296/** 297 * @brief Request the MFW to set the the link according to 'link_input'. 298 * 299 * @param p_hwfn 300 * @param p_ptt 301 * @param b_up - raise link if `true'. Reset link if `false'. 302 * 303 * @return int 304 */ 305int qed_mcp_set_link(struct qed_hwfn *p_hwfn, 306 struct qed_ptt *p_ptt, 307 bool b_up); 308 309/** 310 * @brief Get the management firmware version value 311 * 312 * @param p_hwfn 313 * @param p_ptt 314 * @param p_mfw_ver - mfw version value 315 * @param p_running_bundle_id - image id in nvram; Optional. 316 * 317 * @return int - 0 - operation was successful. 318 */ 319int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 320 struct qed_ptt *p_ptt, 321 u32 *p_mfw_ver, u32 *p_running_bundle_id); 322 323/** 324 * @brief Get the MBI version value 325 * 326 * @param p_hwfn 327 * @param p_ptt 328 * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 329 * 330 * @return int - 0 - operation was successful. 331 */ 332int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 333 struct qed_ptt *p_ptt, u32 *p_mbi_ver); 334 335/** 336 * @brief Get media type value of the port. 337 * 338 * @param cdev - qed dev pointer 339 * @param p_ptt 340 * @param mfw_ver - media type value 341 * 342 * @return int - 343 * 0 - Operation was successul. 344 * -EBUSY - Operation failed 345 */ 346int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 347 struct qed_ptt *p_ptt, u32 *media_type); 348 349/** 350 * @brief Get transceiver data of the port. 351 * 352 * @param cdev - qed dev pointer 353 * @param p_ptt 354 * @param p_transceiver_state - transceiver state. 355 * @param p_transceiver_type - media type value 356 * 357 * @return int - 358 * 0 - Operation was successful. 359 * -EBUSY - Operation failed 360 */ 361int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 362 struct qed_ptt *p_ptt, 363 u32 *p_transceiver_state, 364 u32 *p_tranceiver_type); 365 366/** 367 * @brief Get transceiver supported speed mask. 368 * 369 * @param cdev - qed dev pointer 370 * @param p_ptt 371 * @param p_speed_mask - Bit mask of all supported speeds. 372 * 373 * @return int - 374 * 0 - Operation was successful. 375 * -EBUSY - Operation failed 376 */ 377 378int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 379 struct qed_ptt *p_ptt, u32 *p_speed_mask); 380 381/** 382 * @brief Get board configuration. 383 * 384 * @param cdev - qed dev pointer 385 * @param p_ptt 386 * @param p_board_config - Board config. 387 * 388 * @return int - 389 * 0 - Operation was successful. 390 * -EBUSY - Operation failed 391 */ 392int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 393 struct qed_ptt *p_ptt, u32 *p_board_config); 394 395/** 396 * @brief General function for sending commands to the MCP 397 * mailbox. It acquire mutex lock for the entire 398 * operation, from sending the request until the MCP 399 * response. Waiting for MCP response will be checked up 400 * to 5 seconds every 5ms. 401 * 402 * @param p_hwfn - hw function 403 * @param p_ptt - PTT required for register access 404 * @param cmd - command to be sent to the MCP. 405 * @param param - Optional param 406 * @param o_mcp_resp - The MCP response code (exclude sequence). 407 * @param o_mcp_param- Optional parameter provided by the MCP 408 * response 409 * @return int - 0 - operation 410 * was successul. 411 */ 412int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 413 struct qed_ptt *p_ptt, 414 u32 cmd, 415 u32 param, 416 u32 *o_mcp_resp, 417 u32 *o_mcp_param); 418 419/** 420 * @brief - drains the nig, allowing completion to pass in case of pauses. 421 * (Should be called only from sleepable context) 422 * 423 * @param p_hwfn 424 * @param p_ptt 425 */ 426int qed_mcp_drain(struct qed_hwfn *p_hwfn, 427 struct qed_ptt *p_ptt); 428 429/** 430 * @brief Get the flash size value 431 * 432 * @param p_hwfn 433 * @param p_ptt 434 * @param p_flash_size - flash size in bytes to be filled. 435 * 436 * @return int - 0 - operation was successul. 437 */ 438int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 439 struct qed_ptt *p_ptt, 440 u32 *p_flash_size); 441 442/** 443 * @brief Send driver version to MFW 444 * 445 * @param p_hwfn 446 * @param p_ptt 447 * @param version - Version value 448 * @param name - Protocol driver name 449 * 450 * @return int - 0 - operation was successul. 451 */ 452int 453qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 454 struct qed_ptt *p_ptt, 455 struct qed_mcp_drv_version *p_ver); 456 457/** 458 * @brief Read the MFW process kill counter 459 * 460 * @param p_hwfn 461 * @param p_ptt 462 * 463 * @return u32 464 */ 465u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 466 struct qed_ptt *p_ptt); 467 468/** 469 * @brief Trigger a recovery process 470 * 471 * @param p_hwfn 472 * @param p_ptt 473 * 474 * @return int 475 */ 476int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 477 478/** 479 * @brief A recovery handler must call this function as its first step. 480 * It is assumed that the handler is not run from an interrupt context. 481 * 482 * @param cdev 483 * @param p_ptt 484 * 485 * @return int 486 */ 487int qed_recovery_prolog(struct qed_dev *cdev); 488 489/** 490 * @brief Notify MFW about the change in base device properties 491 * 492 * @param p_hwfn 493 * @param p_ptt 494 * @param client - qed client type 495 * 496 * @return int - 0 - operation was successful. 497 */ 498int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 499 struct qed_ptt *p_ptt, 500 enum qed_ov_client client); 501 502/** 503 * @brief Notify MFW about the driver state 504 * 505 * @param p_hwfn 506 * @param p_ptt 507 * @param drv_state - Driver state 508 * 509 * @return int - 0 - operation was successful. 510 */ 511int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 512 struct qed_ptt *p_ptt, 513 enum qed_ov_driver_state drv_state); 514 515/** 516 * @brief Send MTU size to MFW 517 * 518 * @param p_hwfn 519 * @param p_ptt 520 * @param mtu - MTU size 521 * 522 * @return int - 0 - operation was successful. 523 */ 524int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 525 struct qed_ptt *p_ptt, u16 mtu); 526 527/** 528 * @brief Send MAC address to MFW 529 * 530 * @param p_hwfn 531 * @param p_ptt 532 * @param mac - MAC address 533 * 534 * @return int - 0 - operation was successful. 535 */ 536int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 537 struct qed_ptt *p_ptt, u8 *mac); 538 539/** 540 * @brief Send WOL mode to MFW 541 * 542 * @param p_hwfn 543 * @param p_ptt 544 * @param wol - WOL mode 545 * 546 * @return int - 0 - operation was successful. 547 */ 548int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 549 struct qed_ptt *p_ptt, 550 enum qed_ov_wol wol); 551 552/** 553 * @brief Set LED status 554 * 555 * @param p_hwfn 556 * @param p_ptt 557 * @param mode - LED mode 558 * 559 * @return int - 0 - operation was successful. 560 */ 561int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 562 struct qed_ptt *p_ptt, 563 enum qed_led_mode mode); 564 565/** 566 * @brief Read from nvm 567 * 568 * @param cdev 569 * @param addr - nvm offset 570 * @param p_buf - nvm read buffer 571 * @param len - buffer len 572 * 573 * @return int - 0 - operation was successful. 574 */ 575int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len); 576 577/** 578 * @brief Write to nvm 579 * 580 * @param cdev 581 * @param addr - nvm offset 582 * @param cmd - nvm command 583 * @param p_buf - nvm write buffer 584 * @param len - buffer len 585 * 586 * @return int - 0 - operation was successful. 587 */ 588int qed_mcp_nvm_write(struct qed_dev *cdev, 589 u32 cmd, u32 addr, u8 *p_buf, u32 len); 590 591/** 592 * @brief Check latest response 593 * 594 * @param cdev 595 * @param p_buf - nvm write buffer 596 * 597 * @return int - 0 - operation was successful. 598 */ 599int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf); 600 601struct qed_nvm_image_att { 602 u32 start_addr; 603 u32 length; 604}; 605 606/** 607 * @brief Allows reading a whole nvram image 608 * 609 * @param p_hwfn 610 * @param image_id - image to get attributes for 611 * @param p_image_att - image attributes structure into which to fill data 612 * 613 * @return int - 0 - operation was successful. 614 */ 615int 616qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 617 enum qed_nvm_images image_id, 618 struct qed_nvm_image_att *p_image_att); 619 620/** 621 * @brief Allows reading a whole nvram image 622 * 623 * @param p_hwfn 624 * @param image_id - image requested for reading 625 * @param p_buffer - allocated buffer into which to fill data 626 * @param buffer_len - length of the allocated buffer. 627 * 628 * @return 0 iff p_buffer now contains the nvram image. 629 */ 630int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 631 enum qed_nvm_images image_id, 632 u8 *p_buffer, u32 buffer_len); 633 634/** 635 * @brief Bist register test 636 * 637 * @param p_hwfn - hw function 638 * @param p_ptt - PTT required for register access 639 * 640 * @return int - 0 - operation was successful. 641 */ 642int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, 643 struct qed_ptt *p_ptt); 644 645/** 646 * @brief Bist clock test 647 * 648 * @param p_hwfn - hw function 649 * @param p_ptt - PTT required for register access 650 * 651 * @return int - 0 - operation was successful. 652 */ 653int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, 654 struct qed_ptt *p_ptt); 655 656/** 657 * @brief Bist nvm test - get number of images 658 * 659 * @param p_hwfn - hw function 660 * @param p_ptt - PTT required for register access 661 * @param num_images - number of images if operation was 662 * successful. 0 if not. 663 * 664 * @return int - 0 - operation was successful. 665 */ 666int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 667 struct qed_ptt *p_ptt, 668 u32 *num_images); 669 670/** 671 * @brief Bist nvm test - get image attributes by index 672 * 673 * @param p_hwfn - hw function 674 * @param p_ptt - PTT required for register access 675 * @param p_image_att - Attributes of image 676 * @param image_index - Index of image to get information for 677 * 678 * @return int - 0 - operation was successful. 679 */ 680int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 681 struct qed_ptt *p_ptt, 682 struct bist_nvm_image_att *p_image_att, 683 u32 image_index); 684 685/** 686 * @brief - Processes the TLV request from MFW i.e., get the required TLV info 687 * from the qed client and send it to the MFW. 688 * 689 * @param p_hwfn 690 * @param p_ptt 691 * 692 * @param return 0 upon success. 693 */ 694int qed_mfw_process_tlv_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 695 696/** 697 * @brief Send raw debug data to the MFW 698 * 699 * @param p_hwfn 700 * @param p_ptt 701 * @param p_buf - raw debug data buffer 702 * @param size - buffer size 703 */ 704int 705qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, 706 struct qed_ptt *p_ptt, u8 *p_buf, u32 size); 707 708/* Using hwfn number (and not pf_num) is required since in CMT mode, 709 * same pf_num may be used by two different hwfn 710 * TODO - this shouldn't really be in .h file, but until all fields 711 * required during hw-init will be placed in their correct place in shmem 712 * we need it in qed_dev.c [for readin the nvram reflection in shmem]. 713 */ 714#define MCP_PF_ID_BY_REL(p_hwfn, rel_pfid) (QED_IS_BB((p_hwfn)->cdev) ? \ 715 ((rel_pfid) | \ 716 ((p_hwfn)->abs_pf_id & 1) << 3) : \ 717 rel_pfid) 718#define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id) 719 720struct qed_mcp_info { 721 /* List for mailbox commands which were sent and wait for a response */ 722 struct list_head cmd_list; 723 724 /* Spinlock used for protecting the access to the mailbox commands list 725 * and the sending of the commands. 726 */ 727 spinlock_t cmd_lock; 728 729 /* Flag to indicate whether sending a MFW mailbox command is blocked */ 730 bool b_block_cmd; 731 732 /* Spinlock used for syncing SW link-changes and link-changes 733 * originating from attention context. 734 */ 735 spinlock_t link_lock; 736 737 u32 public_base; 738 u32 drv_mb_addr; 739 u32 mfw_mb_addr; 740 u32 port_addr; 741 u16 drv_mb_seq; 742 u16 drv_pulse_seq; 743 struct qed_mcp_link_params link_input; 744 struct qed_mcp_link_state link_output; 745 struct qed_mcp_link_capabilities link_capabilities; 746 struct qed_mcp_function_info func_info; 747 u8 *mfw_mb_cur; 748 u8 *mfw_mb_shadow; 749 u16 mfw_mb_length; 750 u32 mcp_hist; 751 752 /* Capabilties negotiated with the MFW */ 753 u32 capabilities; 754 755 /* S/N for debug data mailbox commands */ 756 atomic_t dbg_data_seq; 757}; 758 759struct qed_mcp_mb_params { 760 u32 cmd; 761 u32 param; 762 void *p_data_src; 763 void *p_data_dst; 764 u8 data_src_size; 765 u8 data_dst_size; 766 u32 mcp_resp; 767 u32 mcp_param; 768 u32 flags; 769#define QED_MB_FLAG_CAN_SLEEP (0x1 << 0) 770#define QED_MB_FLAG_AVOID_BLOCK (0x1 << 1) 771#define QED_MB_FLAGS_IS_SET(params, flag) \ 772 ({ typeof(params) __params = (params); \ 773 (__params && (__params->flags & QED_MB_FLAG_ ## flag)); }) 774}; 775 776struct qed_drv_tlv_hdr { 777 u8 tlv_type; 778 u8 tlv_length; /* In dwords - not including this header */ 779 u8 tlv_reserved; 780#define QED_DRV_TLV_FLAGS_CHANGED 0x01 781 u8 tlv_flags; 782}; 783 784/** 785 * qed_mcp_is_ext_speed_supported() - Check if management firmware supports 786 * extended speeds. 787 * @p_hwfn: HW device data. 788 * 789 * Return: true if supported, false otherwise. 790 */ 791static inline bool 792qed_mcp_is_ext_speed_supported(const struct qed_hwfn *p_hwfn) 793{ 794 return !!(p_hwfn->mcp_info->capabilities & 795 FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL); 796} 797 798/** 799 * @brief Initialize the interface with the MCP 800 * 801 * @param p_hwfn - HW func 802 * @param p_ptt - PTT required for register access 803 * 804 * @return int 805 */ 806int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, 807 struct qed_ptt *p_ptt); 808 809/** 810 * @brief Initialize the port interface with the MCP 811 * 812 * @param p_hwfn 813 * @param p_ptt 814 * Can only be called after `num_ports_in_engines' is set 815 */ 816void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, 817 struct qed_ptt *p_ptt); 818/** 819 * @brief Releases resources allocated during the init process. 820 * 821 * @param p_hwfn - HW func 822 * @param p_ptt - PTT required for register access 823 * 824 * @return int 825 */ 826 827int qed_mcp_free(struct qed_hwfn *p_hwfn); 828 829/** 830 * @brief This function is called from the DPC context. After 831 * pointing PTT to the mfw mb, check for events sent by the MCP 832 * to the driver and ack them. In case a critical event 833 * detected, it will be handled here, otherwise the work will be 834 * queued to a sleepable work-queue. 835 * 836 * @param p_hwfn - HW function 837 * @param p_ptt - PTT required for register access 838 * @return int - 0 - operation 839 * was successul. 840 */ 841int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 842 struct qed_ptt *p_ptt); 843 844enum qed_drv_role { 845 QED_DRV_ROLE_OS, 846 QED_DRV_ROLE_KDUMP, 847}; 848 849struct qed_load_req_params { 850 /* Input params */ 851 enum qed_drv_role drv_role; 852 u8 timeout_val; 853 bool avoid_eng_reset; 854 enum qed_override_force_load override_force_load; 855 856 /* Output params */ 857 u32 load_code; 858}; 859 860/** 861 * @brief Sends a LOAD_REQ to the MFW, and in case the operation succeeds, 862 * returns whether this PF is the first on the engine/port or function. 863 * 864 * @param p_hwfn 865 * @param p_ptt 866 * @param p_params 867 * 868 * @return int - 0 - Operation was successful. 869 */ 870int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 871 struct qed_ptt *p_ptt, 872 struct qed_load_req_params *p_params); 873 874/** 875 * @brief Sends a LOAD_DONE message to the MFW 876 * 877 * @param p_hwfn 878 * @param p_ptt 879 * 880 * @return int - 0 - Operation was successful. 881 */ 882int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 883 884/** 885 * @brief Sends a UNLOAD_REQ message to the MFW 886 * 887 * @param p_hwfn 888 * @param p_ptt 889 * 890 * @return int - 0 - Operation was successful. 891 */ 892int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 893 894/** 895 * @brief Sends a UNLOAD_DONE message to the MFW 896 * 897 * @param p_hwfn 898 * @param p_ptt 899 * 900 * @return int - 0 - Operation was successful. 901 */ 902int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 903 904/** 905 * @brief Read the MFW mailbox into Current buffer. 906 * 907 * @param p_hwfn 908 * @param p_ptt 909 */ 910void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, 911 struct qed_ptt *p_ptt); 912 913/** 914 * @brief Ack to mfw that driver finished FLR process for VFs 915 * 916 * @param p_hwfn 917 * @param p_ptt 918 * @param vfs_to_ack - bit mask of all engine VFs for which the PF acks. 919 * 920 * @param return int - 0 upon success. 921 */ 922int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 923 struct qed_ptt *p_ptt, u32 *vfs_to_ack); 924 925/** 926 * @brief - calls during init to read shmem of all function-related info. 927 * 928 * @param p_hwfn 929 * 930 * @param return 0 upon success. 931 */ 932int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 933 struct qed_ptt *p_ptt); 934 935/** 936 * @brief - Reset the MCP using mailbox command. 937 * 938 * @param p_hwfn 939 * @param p_ptt 940 * 941 * @param return 0 upon success. 942 */ 943int qed_mcp_reset(struct qed_hwfn *p_hwfn, 944 struct qed_ptt *p_ptt); 945 946/** 947 * @brief - Sends an NVM read command request to the MFW to get 948 * a buffer. 949 * 950 * @param p_hwfn 951 * @param p_ptt 952 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 953 * DRV_MSG_CODE_NVM_READ_NVRAM commands 954 * @param param - [0:23] - Offset [24:31] - Size 955 * @param o_mcp_resp - MCP response 956 * @param o_mcp_param - MCP response param 957 * @param o_txn_size - Buffer size output 958 * @param o_buf - Pointer to the buffer returned by the MFW. 959 * 960 * @param return 0 upon success. 961 */ 962int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 963 struct qed_ptt *p_ptt, 964 u32 cmd, 965 u32 param, 966 u32 *o_mcp_resp, 967 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf); 968 969/** 970 * @brief Read from sfp 971 * 972 * @param p_hwfn - hw function 973 * @param p_ptt - PTT required for register access 974 * @param port - transceiver port 975 * @param addr - I2C address 976 * @param offset - offset in sfp 977 * @param len - buffer length 978 * @param p_buf - buffer to read into 979 * 980 * @return int - 0 - operation was successful. 981 */ 982int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 983 u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf); 984 985/** 986 * @brief indicates whether the MFW objects [under mcp_info] are accessible 987 * 988 * @param p_hwfn 989 * 990 * @return true iff MFW is running and mcp_info is initialized 991 */ 992bool qed_mcp_is_init(struct qed_hwfn *p_hwfn); 993 994/** 995 * @brief request MFW to configure MSI-X for a VF 996 * 997 * @param p_hwfn 998 * @param p_ptt 999 * @param vf_id - absolute inside engine 1000 * @param num_sbs - number of entries to request 1001 * 1002 * @return int 1003 */ 1004int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 1005 struct qed_ptt *p_ptt, u8 vf_id, u8 num); 1006 1007/** 1008 * @brief - Halt the MCP. 1009 * 1010 * @param p_hwfn 1011 * @param p_ptt 1012 * 1013 * @param return 0 upon success. 1014 */ 1015int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1016 1017/** 1018 * @brief - Wake up the MCP. 1019 * 1020 * @param p_hwfn 1021 * @param p_ptt 1022 * 1023 * @param return 0 upon success. 1024 */ 1025int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1026 1027int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw); 1028int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw); 1029int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 1030 struct qed_ptt *p_ptt, 1031 struct qed_mcp_link_state *p_link, 1032 u8 max_bw); 1033int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 1034 struct qed_ptt *p_ptt, 1035 struct qed_mcp_link_state *p_link, 1036 u8 min_bw); 1037 1038int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 1039 struct qed_ptt *p_ptt, u32 mask_parities); 1040 1041/* @brief - Gets the mdump retained data from the MFW. 1042 * 1043 * @param p_hwfn 1044 * @param p_ptt 1045 * @param p_mdump_retain 1046 * 1047 * @param return 0 upon success. 1048 */ 1049int 1050qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, 1051 struct qed_ptt *p_ptt, 1052 struct mdump_retain_data_stc *p_mdump_retain); 1053 1054/** 1055 * @brief - Sets the MFW's max value for the given resource 1056 * 1057 * @param p_hwfn 1058 * @param p_ptt 1059 * @param res_id 1060 * @param resc_max_val 1061 * @param p_mcp_resp 1062 * 1063 * @return int - 0 - operation was successful. 1064 */ 1065int 1066qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 1067 struct qed_ptt *p_ptt, 1068 enum qed_resources res_id, 1069 u32 resc_max_val, u32 *p_mcp_resp); 1070 1071/** 1072 * @brief - Gets the MFW allocation info for the given resource 1073 * 1074 * @param p_hwfn 1075 * @param p_ptt 1076 * @param res_id 1077 * @param p_mcp_resp 1078 * @param p_resc_num 1079 * @param p_resc_start 1080 * 1081 * @return int - 0 - operation was successful. 1082 */ 1083int 1084qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 1085 struct qed_ptt *p_ptt, 1086 enum qed_resources res_id, 1087 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start); 1088 1089/** 1090 * @brief Send eswitch mode to MFW 1091 * 1092 * @param p_hwfn 1093 * @param p_ptt 1094 * @param eswitch - eswitch mode 1095 * 1096 * @return int - 0 - operation was successful. 1097 */ 1098int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 1099 struct qed_ptt *p_ptt, 1100 enum qed_ov_eswitch eswitch); 1101 1102#define QED_MCP_RESC_LOCK_MIN_VAL RESOURCE_DUMP 1103#define QED_MCP_RESC_LOCK_MAX_VAL 31 1104 1105enum qed_resc_lock { 1106 QED_RESC_LOCK_DBG_DUMP = QED_MCP_RESC_LOCK_MIN_VAL, 1107 QED_RESC_LOCK_PTP_PORT0, 1108 QED_RESC_LOCK_PTP_PORT1, 1109 QED_RESC_LOCK_PTP_PORT2, 1110 QED_RESC_LOCK_PTP_PORT3, 1111 QED_RESC_LOCK_RESC_ALLOC = QED_MCP_RESC_LOCK_MAX_VAL, 1112 QED_RESC_LOCK_RESC_INVALID 1113}; 1114 1115/** 1116 * @brief - Initiates PF FLR 1117 * 1118 * @param p_hwfn 1119 * @param p_ptt 1120 * 1121 * @return int - 0 - operation was successful. 1122 */ 1123int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1124struct qed_resc_lock_params { 1125 /* Resource number [valid values are 0..31] */ 1126 u8 resource; 1127 1128 /* Lock timeout value in seconds [default, none or 1..254] */ 1129 u8 timeout; 1130#define QED_MCP_RESC_LOCK_TO_DEFAULT 0 1131#define QED_MCP_RESC_LOCK_TO_NONE 255 1132 1133 /* Number of times to retry locking */ 1134 u8 retry_num; 1135#define QED_MCP_RESC_LOCK_RETRY_CNT_DFLT 10 1136 1137 /* The interval in usec between retries */ 1138 u16 retry_interval; 1139#define QED_MCP_RESC_LOCK_RETRY_VAL_DFLT 10000 1140 1141 /* Use sleep or delay between retries */ 1142 bool sleep_b4_retry; 1143 1144 /* Will be set as true if the resource is free and granted */ 1145 bool b_granted; 1146 1147 /* Will be filled with the resource owner. 1148 * [0..15 = PF0-15, 16 = MFW] 1149 */ 1150 u8 owner; 1151}; 1152 1153/** 1154 * @brief Acquires MFW generic resource lock 1155 * 1156 * @param p_hwfn 1157 * @param p_ptt 1158 * @param p_params 1159 * 1160 * @return int - 0 - operation was successful. 1161 */ 1162int 1163qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 1164 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params); 1165 1166struct qed_resc_unlock_params { 1167 /* Resource number [valid values are 0..31] */ 1168 u8 resource; 1169 1170 /* Allow to release a resource even if belongs to another PF */ 1171 bool b_force; 1172 1173 /* Will be set as true if the resource is released */ 1174 bool b_released; 1175}; 1176 1177/** 1178 * @brief Releases MFW generic resource lock 1179 * 1180 * @param p_hwfn 1181 * @param p_ptt 1182 * @param p_params 1183 * 1184 * @return int - 0 - operation was successful. 1185 */ 1186int 1187qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 1188 struct qed_ptt *p_ptt, 1189 struct qed_resc_unlock_params *p_params); 1190 1191/** 1192 * @brief - default initialization for lock/unlock resource structs 1193 * 1194 * @param p_lock - lock params struct to be initialized; Can be NULL 1195 * @param p_unlock - unlock params struct to be initialized; Can be NULL 1196 * @param resource - the requested resource 1197 * @paral b_is_permanent - disable retries & aging when set 1198 */ 1199void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 1200 struct qed_resc_unlock_params *p_unlock, 1201 enum qed_resc_lock 1202 resource, bool b_is_permanent); 1203 1204/** 1205 * @brief - Return whether management firmware support smart AN 1206 * 1207 * @param p_hwfn 1208 * 1209 * @return bool - true if feature is supported. 1210 */ 1211bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn); 1212 1213/** 1214 * @brief Learn of supported MFW features; To be done during early init 1215 * 1216 * @param p_hwfn 1217 * @param p_ptt 1218 */ 1219int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1220 1221/** 1222 * @brief Inform MFW of set of features supported by driver. Should be done 1223 * inside the content of the LOAD_REQ. 1224 * 1225 * @param p_hwfn 1226 * @param p_ptt 1227 */ 1228int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1229 1230/** 1231 * @brief Read ufp config from the shared memory. 1232 * 1233 * @param p_hwfn 1234 * @param p_ptt 1235 */ 1236void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1237 1238/** 1239 * @brief Populate the nvm info shadow in the given hardware function 1240 * 1241 * @param p_hwfn 1242 */ 1243int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn); 1244 1245/** 1246 * @brief Delete nvm info shadow in the given hardware function 1247 * 1248 * @param p_hwfn 1249 */ 1250void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn); 1251 1252/** 1253 * @brief Get the engine affinity configuration. 1254 * 1255 * @param p_hwfn 1256 * @param p_ptt 1257 */ 1258int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1259 1260/** 1261 * @brief Get the PPFID bitmap. 1262 * 1263 * @param p_hwfn 1264 * @param p_ptt 1265 */ 1266int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1267 1268/** 1269 * @brief Get NVM config attribute value. 1270 * 1271 * @param p_hwfn 1272 * @param p_ptt 1273 * @param option_id 1274 * @param entity_id 1275 * @param flags 1276 * @param p_buf 1277 * @param p_len 1278 */ 1279int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1280 u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 1281 u32 *p_len); 1282 1283/** 1284 * @brief Set NVM config attribute value. 1285 * 1286 * @param p_hwfn 1287 * @param p_ptt 1288 * @param option_id 1289 * @param entity_id 1290 * @param flags 1291 * @param p_buf 1292 * @param len 1293 */ 1294int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1295 u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 1296 u32 len); 1297#endif 1298