1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7#include <linux/types.h> 8#include <linux/bitops.h> 9#include <linux/dma-mapping.h> 10#include <linux/errno.h> 11#include <linux/kernel.h> 12#include <linux/list.h> 13#include <linux/log2.h> 14#include <linux/pci.h> 15#include <linux/slab.h> 16#include <linux/string.h> 17#include "qed.h" 18#include "qed_cxt.h" 19#include "qed_dev_api.h" 20#include "qed_hsi.h" 21#include "qed_hw.h" 22#include "qed_init_ops.h" 23#include "qed_rdma.h" 24#include "qed_reg_addr.h" 25#include "qed_sriov.h" 26 27/* QM constants */ 28#define QM_PQ_ELEMENT_SIZE 4 /* in bytes */ 29 30/* Doorbell-Queue constants */ 31#define DQ_RANGE_SHIFT 4 32#define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) 33 34/* Searcher constants */ 35#define SRC_MIN_NUM_ELEMS 256 36 37/* Timers constants */ 38#define TM_SHIFT 7 39#define TM_ALIGN BIT(TM_SHIFT) 40#define TM_ELEM_SIZE 4 41 42#define ILT_DEFAULT_HW_P_SIZE 4 43 44#define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 45#define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET 46 47/* ILT entry structure */ 48#define ILT_ENTRY_PHY_ADDR_MASK (~0ULL >> 12) 49#define ILT_ENTRY_PHY_ADDR_SHIFT 0 50#define ILT_ENTRY_VALID_MASK 0x1ULL 51#define ILT_ENTRY_VALID_SHIFT 52 52#define ILT_ENTRY_IN_REGS 2 53#define ILT_REG_SIZE_IN_BYTES 4 54 55/* connection context union */ 56union conn_context { 57 struct e4_core_conn_context core_ctx; 58 struct e4_eth_conn_context eth_ctx; 59 struct e4_iscsi_conn_context iscsi_ctx; 60 struct e4_fcoe_conn_context fcoe_ctx; 61 struct e4_roce_conn_context roce_ctx; 62}; 63 64/* TYPE-0 task context - iSCSI, FCOE */ 65union type0_task_context { 66 struct e4_iscsi_task_context iscsi_ctx; 67 struct e4_fcoe_task_context fcoe_ctx; 68}; 69 70/* TYPE-1 task context - ROCE */ 71union type1_task_context { 72 struct e4_rdma_task_context roce_ctx; 73}; 74 75struct src_ent { 76 __u8 opaque[56]; 77 __be64 next; 78}; 79 80#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 81#define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12) 82 83#define CONN_CXT_SIZE(p_hwfn) \ 84 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 85 86#define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 87#define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context)) 88 89#define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 90 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 91 92/* Alignment is inherent to the type1_task_context structure */ 93#define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 94 95static bool src_proto(enum protocol_type type) 96{ 97 return type == PROTOCOLID_ISCSI || 98 type == PROTOCOLID_FCOE || 99 type == PROTOCOLID_IWARP; 100} 101 102static bool tm_cid_proto(enum protocol_type type) 103{ 104 return type == PROTOCOLID_ISCSI || 105 type == PROTOCOLID_FCOE || 106 type == PROTOCOLID_ROCE || 107 type == PROTOCOLID_IWARP; 108} 109 110static bool tm_tid_proto(enum protocol_type type) 111{ 112 return type == PROTOCOLID_FCOE; 113} 114 115/* counts the iids for the CDU/CDUC ILT client configuration */ 116struct qed_cdu_iids { 117 u32 pf_cids; 118 u32 per_vf_cids; 119}; 120 121static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr, 122 struct qed_cdu_iids *iids) 123{ 124 u32 type; 125 126 for (type = 0; type < MAX_CONN_TYPES; type++) { 127 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 128 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 129 } 130} 131 132/* counts the iids for the Searcher block configuration */ 133struct qed_src_iids { 134 u32 pf_cids; 135 u32 per_vf_cids; 136}; 137 138static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr, 139 struct qed_src_iids *iids) 140{ 141 u32 i; 142 143 for (i = 0; i < MAX_CONN_TYPES; i++) { 144 if (!src_proto(i)) 145 continue; 146 147 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 148 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 149 } 150 151 /* Add L2 filtering filters in addition */ 152 iids->pf_cids += p_mngr->arfs_count; 153} 154 155/* counts the iids for the Timers block configuration */ 156struct qed_tm_iids { 157 u32 pf_cids; 158 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 159 u32 pf_tids_total; 160 u32 per_vf_cids; 161 u32 per_vf_tids; 162}; 163 164static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn, 165 struct qed_cxt_mngr *p_mngr, 166 struct qed_tm_iids *iids) 167{ 168 bool tm_vf_required = false; 169 bool tm_required = false; 170 int i, j; 171 172 /* Timers is a special case -> we don't count how many cids require 173 * timers but what's the max cid that will be used by the timer block. 174 * therefore we traverse in reverse order, and once we hit a protocol 175 * that requires the timers memory, we'll sum all the protocols up 176 * to that one. 177 */ 178 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 179 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 180 181 if (tm_cid_proto(i) || tm_required) { 182 if (p_cfg->cid_count) 183 tm_required = true; 184 185 iids->pf_cids += p_cfg->cid_count; 186 } 187 188 if (tm_cid_proto(i) || tm_vf_required) { 189 if (p_cfg->cids_per_vf) 190 tm_vf_required = true; 191 192 iids->per_vf_cids += p_cfg->cids_per_vf; 193 } 194 195 if (tm_tid_proto(i)) { 196 struct qed_tid_seg *segs = p_cfg->tid_seg; 197 198 /* for each segment there is at most one 199 * protocol for which count is not 0. 200 */ 201 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 202 iids->pf_tids[j] += segs[j].count; 203 204 /* The last array elelment is for the VFs. As for PF 205 * segments there can be only one protocol for 206 * which this value is not 0. 207 */ 208 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 209 } 210 } 211 212 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN); 213 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN); 214 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN); 215 216 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 217 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN); 218 iids->pf_tids_total += iids->pf_tids[j]; 219 } 220} 221 222static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn, 223 struct qed_qm_iids *iids) 224{ 225 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 226 struct qed_tid_seg *segs; 227 u32 vf_cids = 0, type, j; 228 u32 vf_tids = 0; 229 230 for (type = 0; type < MAX_CONN_TYPES; type++) { 231 iids->cids += p_mngr->conn_cfg[type].cid_count; 232 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 233 234 segs = p_mngr->conn_cfg[type].tid_seg; 235 /* for each segment there is at most one 236 * protocol for which count is not 0. 237 */ 238 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 239 iids->tids += segs[j].count; 240 241 /* The last array elelment is for the VFs. As for PF 242 * segments there can be only one protocol for 243 * which this value is not 0. 244 */ 245 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 246 } 247 248 iids->vf_cids = vf_cids; 249 iids->tids += vf_tids * p_mngr->vf_count; 250 251 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 252 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 253 iids->cids, iids->vf_cids, iids->tids, vf_tids); 254} 255 256static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn, 257 u32 seg) 258{ 259 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 260 u32 i; 261 262 /* Find the protocol with tid count > 0 for this segment. 263 * Note: there can only be one and this is already validated. 264 */ 265 for (i = 0; i < MAX_CONN_TYPES; i++) 266 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 267 return &p_cfg->conn_cfg[i].tid_seg[seg]; 268 return NULL; 269} 270 271static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, 272 u32 num_srqs, u32 num_xrc_srqs) 273{ 274 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 275 276 p_mgr->srq_count = num_srqs; 277 p_mgr->xrc_srq_count = num_xrc_srqs; 278} 279 280u32 qed_cxt_get_ilt_page_size(struct qed_hwfn *p_hwfn, 281 enum ilt_clients ilt_client) 282{ 283 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 284 struct qed_ilt_client_cfg *p_cli = &p_mngr->clients[ilt_client]; 285 286 return ILT_PAGE_IN_BYTES(p_cli->p_size.val); 287} 288 289static u32 qed_cxt_xrc_srqs_per_page(struct qed_hwfn *p_hwfn) 290{ 291 u32 page_size; 292 293 page_size = qed_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 294 return page_size / XRC_SRQ_CXT_SIZE; 295} 296 297u32 qed_cxt_get_total_srq_count(struct qed_hwfn *p_hwfn) 298{ 299 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 300 u32 total_srqs; 301 302 total_srqs = p_mgr->srq_count + p_mgr->xrc_srq_count; 303 304 return total_srqs; 305} 306 307/* set the iids count per protocol */ 308static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, 309 enum protocol_type type, 310 u32 cid_count, u32 vf_cid_cnt) 311{ 312 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 313 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 314 315 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN); 316 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN); 317 318 if (type == PROTOCOLID_ROCE) { 319 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 320 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 321 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 322 u32 align = elems_per_page * DQ_RANGE_ALIGN; 323 324 p_conn->cid_count = roundup(p_conn->cid_count, align); 325 } 326} 327 328u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn, 329 enum protocol_type type, u32 *vf_cid) 330{ 331 if (vf_cid) 332 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 333 334 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 335} 336 337u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn, 338 enum protocol_type type) 339{ 340 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 341} 342 343u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, 344 enum protocol_type type) 345{ 346 u32 cnt = 0; 347 int i; 348 349 for (i = 0; i < TASK_SEGMENTS; i++) 350 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 351 352 return cnt; 353} 354 355static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, 356 enum protocol_type proto, 357 u8 seg, 358 u8 seg_type, u32 count, bool has_fl) 359{ 360 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 361 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 362 363 p_seg->count = count; 364 p_seg->has_fl_mem = has_fl; 365 p_seg->type = seg_type; 366} 367 368static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli, 369 struct qed_ilt_cli_blk *p_blk, 370 u32 start_line, u32 total_size, u32 elem_size) 371{ 372 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 373 374 /* verify thatits called only once for each block */ 375 if (p_blk->total_size) 376 return; 377 378 p_blk->total_size = total_size; 379 p_blk->real_size_in_page = 0; 380 if (elem_size) 381 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 382 p_blk->start_line = start_line; 383} 384 385static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, 386 struct qed_ilt_client_cfg *p_cli, 387 struct qed_ilt_cli_blk *p_blk, 388 u32 *p_line, enum ilt_clients client_id) 389{ 390 if (!p_blk->total_size) 391 return; 392 393 if (!p_cli->active) 394 p_cli->first.val = *p_line; 395 396 p_cli->active = true; 397 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 398 p_cli->last.val = *p_line - 1; 399 400 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 401 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 402 client_id, p_cli->first.val, 403 p_cli->last.val, p_blk->total_size, 404 p_blk->real_size_in_page, p_blk->start_line); 405} 406 407static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn, 408 enum ilt_clients ilt_client) 409{ 410 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 411 struct qed_ilt_client_cfg *p_cli; 412 u32 lines_to_skip = 0; 413 u32 cxts_per_p; 414 415 if (ilt_client == ILT_CLI_CDUC) { 416 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 417 418 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 419 (u32) CONN_CXT_SIZE(p_hwfn); 420 421 lines_to_skip = cid_count / cxts_per_p; 422 } 423 424 return lines_to_skip; 425} 426 427static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg 428 *p_cli) 429{ 430 p_cli->active = false; 431 p_cli->first.val = 0; 432 p_cli->last.val = 0; 433 return p_cli; 434} 435 436static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk) 437{ 438 p_blk->total_size = 0; 439 return p_blk; 440} 441 442static void qed_cxt_ilt_blk_reset(struct qed_hwfn *p_hwfn) 443{ 444 struct qed_ilt_client_cfg *clients = p_hwfn->p_cxt_mngr->clients; 445 u32 cli_idx, blk_idx; 446 447 for (cli_idx = 0; cli_idx < MAX_ILT_CLIENTS; cli_idx++) { 448 for (blk_idx = 0; blk_idx < ILT_CLI_PF_BLOCKS; blk_idx++) 449 clients[cli_idx].pf_blks[blk_idx].total_size = 0; 450 451 for (blk_idx = 0; blk_idx < ILT_CLI_VF_BLOCKS; blk_idx++) 452 clients[cli_idx].vf_blks[blk_idx].total_size = 0; 453 } 454} 455 456int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count) 457{ 458 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 459 u32 curr_line, total, i, task_size, line; 460 struct qed_ilt_client_cfg *p_cli; 461 struct qed_ilt_cli_blk *p_blk; 462 struct qed_cdu_iids cdu_iids; 463 struct qed_src_iids src_iids; 464 struct qed_qm_iids qm_iids; 465 struct qed_tm_iids tm_iids; 466 struct qed_tid_seg *p_seg; 467 468 memset(&qm_iids, 0, sizeof(qm_iids)); 469 memset(&cdu_iids, 0, sizeof(cdu_iids)); 470 memset(&src_iids, 0, sizeof(src_iids)); 471 memset(&tm_iids, 0, sizeof(tm_iids)); 472 473 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT); 474 475 /* Reset all ILT blocks at the beginning of ILT computing in order 476 * to prevent memory allocation for irrelevant blocks afterwards. 477 */ 478 qed_cxt_ilt_blk_reset(p_hwfn); 479 480 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 481 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 482 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 483 484 /* CDUC */ 485 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 486 487 curr_line = p_mngr->pf_start_line; 488 489 /* CDUC PF */ 490 p_cli->pf_total_lines = 0; 491 492 /* get the counters for the CDUC and QM clients */ 493 qed_cxt_cdu_iids(p_mngr, &cdu_iids); 494 495 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 496 497 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 498 499 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 500 total, CONN_CXT_SIZE(p_hwfn)); 501 502 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 503 p_cli->pf_total_lines = curr_line - p_blk->start_line; 504 505 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn, 506 ILT_CLI_CDUC); 507 508 /* CDUC VF */ 509 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 510 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 511 512 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 513 total, CONN_CXT_SIZE(p_hwfn)); 514 515 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 516 p_cli->vf_total_lines = curr_line - p_blk->start_line; 517 518 for (i = 1; i < p_mngr->vf_count; i++) 519 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 520 ILT_CLI_CDUC); 521 522 /* CDUT PF */ 523 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 524 p_cli->first.val = curr_line; 525 526 /* first the 'working' task memory */ 527 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 528 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 529 if (!p_seg || p_seg->count == 0) 530 continue; 531 532 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 533 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 534 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 535 p_mngr->task_type_size[p_seg->type]); 536 537 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 538 ILT_CLI_CDUT); 539 } 540 541 /* next the 'init' task memory (forced load memory) */ 542 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 543 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 544 if (!p_seg || p_seg->count == 0) 545 continue; 546 547 p_blk = 548 qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 549 550 if (!p_seg->has_fl_mem) { 551 /* The segment is active (total size pf 'working' 552 * memory is > 0) but has no FL (forced-load, Init) 553 * memory. Thus: 554 * 555 * 1. The total-size in the corrsponding FL block of 556 * the ILT client is set to 0 - No ILT line are 557 * provisioned and no ILT memory allocated. 558 * 559 * 2. The start-line of said block is set to the 560 * start line of the matching working memory 561 * block in the ILT client. This is later used to 562 * configure the CDU segment offset registers and 563 * results in an FL command for TIDs of this 564 * segement behaves as regular load commands 565 * (loading TIDs from the working memory). 566 */ 567 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 568 569 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 570 continue; 571 } 572 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 573 574 qed_ilt_cli_blk_fill(p_cli, p_blk, 575 curr_line, total, 576 p_mngr->task_type_size[p_seg->type]); 577 578 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 579 ILT_CLI_CDUT); 580 } 581 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 582 583 /* CDUT VF */ 584 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 585 if (p_seg && p_seg->count) { 586 /* Stricly speaking we need to iterate over all VF 587 * task segment types, but a VF has only 1 segment 588 */ 589 590 /* 'working' memory */ 591 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 592 593 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 594 qed_ilt_cli_blk_fill(p_cli, p_blk, 595 curr_line, total, 596 p_mngr->task_type_size[p_seg->type]); 597 598 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 599 ILT_CLI_CDUT); 600 601 /* 'init' memory */ 602 p_blk = 603 qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 604 if (!p_seg->has_fl_mem) { 605 /* see comment above */ 606 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 607 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 608 } else { 609 task_size = p_mngr->task_type_size[p_seg->type]; 610 qed_ilt_cli_blk_fill(p_cli, p_blk, 611 curr_line, total, task_size); 612 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 613 ILT_CLI_CDUT); 614 } 615 p_cli->vf_total_lines = curr_line - 616 p_cli->vf_blks[0].start_line; 617 618 /* Now for the rest of the VFs */ 619 for (i = 1; i < p_mngr->vf_count; i++) { 620 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 621 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 622 ILT_CLI_CDUT); 623 624 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 625 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 626 ILT_CLI_CDUT); 627 } 628 } 629 630 /* QM */ 631 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 632 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 633 634 qed_cxt_qm_iids(p_hwfn, &qm_iids); 635 total = qed_qm_pf_mem_size(qm_iids.cids, 636 qm_iids.vf_cids, qm_iids.tids, 637 p_hwfn->qm_info.num_pqs, 638 p_hwfn->qm_info.num_vf_pqs); 639 640 DP_VERBOSE(p_hwfn, 641 QED_MSG_ILT, 642 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 643 qm_iids.cids, 644 qm_iids.vf_cids, 645 qm_iids.tids, 646 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 647 648 qed_ilt_cli_blk_fill(p_cli, p_blk, 649 curr_line, total * 0x1000, 650 QM_PQ_ELEMENT_SIZE); 651 652 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 653 p_cli->pf_total_lines = curr_line - p_blk->start_line; 654 655 /* SRC */ 656 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 657 qed_cxt_src_iids(p_mngr, &src_iids); 658 659 /* Both the PF and VFs searcher connections are stored in the per PF 660 * database. Thus sum the PF searcher cids and all the VFs searcher 661 * cids. 662 */ 663 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 664 if (total) { 665 u32 local_max = max_t(u32, total, 666 SRC_MIN_NUM_ELEMS); 667 668 total = roundup_pow_of_two(local_max); 669 670 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 671 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 672 total * sizeof(struct src_ent), 673 sizeof(struct src_ent)); 674 675 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 676 ILT_CLI_SRC); 677 p_cli->pf_total_lines = curr_line - p_blk->start_line; 678 } 679 680 /* TM PF */ 681 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 682 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 683 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 684 if (total) { 685 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 686 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 687 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 688 689 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 690 ILT_CLI_TM); 691 p_cli->pf_total_lines = curr_line - p_blk->start_line; 692 } 693 694 /* TM VF */ 695 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 696 if (total) { 697 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]); 698 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 699 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 700 701 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 702 ILT_CLI_TM); 703 704 p_cli->vf_total_lines = curr_line - p_blk->start_line; 705 for (i = 1; i < p_mngr->vf_count; i++) 706 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 707 ILT_CLI_TM); 708 } 709 710 /* TSDM (SRQ CONTEXT) */ 711 total = qed_cxt_get_total_srq_count(p_hwfn); 712 713 if (total) { 714 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 715 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 716 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 717 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 718 719 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 720 ILT_CLI_TSDM); 721 p_cli->pf_total_lines = curr_line - p_blk->start_line; 722 } 723 724 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 725 726 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 727 RESC_NUM(p_hwfn, QED_ILT)) 728 return -EINVAL; 729 730 return 0; 731} 732 733u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines) 734{ 735 struct qed_ilt_client_cfg *p_cli; 736 u32 excess_lines, available_lines; 737 struct qed_cxt_mngr *p_mngr; 738 u32 ilt_page_size, elem_size; 739 struct qed_tid_seg *p_seg; 740 int i; 741 742 available_lines = RESC_NUM(p_hwfn, QED_ILT); 743 excess_lines = used_lines - available_lines; 744 745 if (!excess_lines) 746 return 0; 747 748 if (!QED_IS_RDMA_PERSONALITY(p_hwfn)) 749 return 0; 750 751 p_mngr = p_hwfn->p_cxt_mngr; 752 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 753 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 754 755 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 756 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 757 if (!p_seg || p_seg->count == 0) 758 continue; 759 760 elem_size = p_mngr->task_type_size[p_seg->type]; 761 if (!elem_size) 762 continue; 763 764 return (ilt_page_size / elem_size) * excess_lines; 765 } 766 767 DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n"); 768 return 0; 769} 770 771static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn) 772{ 773 struct qed_src_t2 *p_t2 = &p_hwfn->p_cxt_mngr->src_t2; 774 u32 i; 775 776 if (!p_t2 || !p_t2->dma_mem) 777 return; 778 779 for (i = 0; i < p_t2->num_pages; i++) 780 if (p_t2->dma_mem[i].virt_addr) 781 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 782 p_t2->dma_mem[i].size, 783 p_t2->dma_mem[i].virt_addr, 784 p_t2->dma_mem[i].phys_addr); 785 786 kfree(p_t2->dma_mem); 787 p_t2->dma_mem = NULL; 788} 789 790static int 791qed_cxt_t2_alloc_pages(struct qed_hwfn *p_hwfn, 792 struct qed_src_t2 *p_t2, u32 total_size, u32 page_size) 793{ 794 void **p_virt; 795 u32 size, i; 796 797 if (!p_t2 || !p_t2->dma_mem) 798 return -EINVAL; 799 800 for (i = 0; i < p_t2->num_pages; i++) { 801 size = min_t(u32, total_size, page_size); 802 p_virt = &p_t2->dma_mem[i].virt_addr; 803 804 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 805 size, 806 &p_t2->dma_mem[i].phys_addr, 807 GFP_KERNEL); 808 if (!p_t2->dma_mem[i].virt_addr) 809 return -ENOMEM; 810 811 memset(*p_virt, 0, size); 812 p_t2->dma_mem[i].size = size; 813 total_size -= size; 814 } 815 816 return 0; 817} 818 819static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn) 820{ 821 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 822 u32 conn_num, total_size, ent_per_page, psz, i; 823 struct phys_mem_desc *p_t2_last_page; 824 struct qed_ilt_client_cfg *p_src; 825 struct qed_src_iids src_iids; 826 struct qed_src_t2 *p_t2; 827 int rc; 828 829 memset(&src_iids, 0, sizeof(src_iids)); 830 831 /* if the SRC ILT client is inactive - there are no connection 832 * requiring the searcer, leave. 833 */ 834 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 835 if (!p_src->active) 836 return 0; 837 838 qed_cxt_src_iids(p_mngr, &src_iids); 839 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 840 total_size = conn_num * sizeof(struct src_ent); 841 842 /* use the same page size as the SRC ILT client */ 843 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 844 p_t2 = &p_mngr->src_t2; 845 p_t2->num_pages = DIV_ROUND_UP(total_size, psz); 846 847 /* allocate t2 */ 848 p_t2->dma_mem = kcalloc(p_t2->num_pages, sizeof(struct phys_mem_desc), 849 GFP_KERNEL); 850 if (!p_t2->dma_mem) { 851 DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n"); 852 rc = -ENOMEM; 853 goto t2_fail; 854 } 855 856 rc = qed_cxt_t2_alloc_pages(p_hwfn, p_t2, total_size, psz); 857 if (rc) 858 goto t2_fail; 859 860 /* Set the t2 pointers */ 861 862 /* entries per page - must be a power of two */ 863 ent_per_page = psz / sizeof(struct src_ent); 864 865 p_t2->first_free = (u64)p_t2->dma_mem[0].phys_addr; 866 867 p_t2_last_page = &p_t2->dma_mem[(conn_num - 1) / ent_per_page]; 868 p_t2->last_free = (u64)p_t2_last_page->phys_addr + 869 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent); 870 871 for (i = 0; i < p_t2->num_pages; i++) { 872 u32 ent_num = min_t(u32, 873 ent_per_page, 874 conn_num); 875 struct src_ent *entries = p_t2->dma_mem[i].virt_addr; 876 u64 p_ent_phys = (u64)p_t2->dma_mem[i].phys_addr, val; 877 u32 j; 878 879 for (j = 0; j < ent_num - 1; j++) { 880 val = p_ent_phys + (j + 1) * sizeof(struct src_ent); 881 entries[j].next = cpu_to_be64(val); 882 } 883 884 if (i < p_t2->num_pages - 1) 885 val = (u64)p_t2->dma_mem[i + 1].phys_addr; 886 else 887 val = 0; 888 entries[j].next = cpu_to_be64(val); 889 890 conn_num -= ent_num; 891 } 892 893 return 0; 894 895t2_fail: 896 qed_cxt_src_t2_free(p_hwfn); 897 return rc; 898} 899 900#define for_each_ilt_valid_client(pos, clients) \ 901 for (pos = 0; pos < MAX_ILT_CLIENTS; pos++) \ 902 if (!clients[pos].active) { \ 903 continue; \ 904 } else \ 905 906/* Total number of ILT lines used by this PF */ 907static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients) 908{ 909 u32 size = 0; 910 u32 i; 911 912 for_each_ilt_valid_client(i, ilt_clients) 913 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); 914 915 return size; 916} 917 918static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn) 919{ 920 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 921 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 922 u32 ilt_size, i; 923 924 ilt_size = qed_cxt_ilt_shadow_size(p_cli); 925 926 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 927 struct phys_mem_desc *p_dma = &p_mngr->ilt_shadow[i]; 928 929 if (p_dma->virt_addr) 930 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 931 p_dma->size, p_dma->virt_addr, 932 p_dma->phys_addr); 933 p_dma->virt_addr = NULL; 934 } 935 kfree(p_mngr->ilt_shadow); 936 p_mngr->ilt_shadow = NULL; 937} 938 939static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, 940 struct qed_ilt_cli_blk *p_blk, 941 enum ilt_clients ilt_client, 942 u32 start_line_offset) 943{ 944 struct phys_mem_desc *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 945 u32 lines, line, sz_left, lines_to_skip = 0; 946 947 /* Special handling for RoCE that supports dynamic allocation */ 948 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && 949 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 950 return 0; 951 952 lines_to_skip = p_blk->dynamic_line_cnt; 953 954 if (!p_blk->total_size) 955 return 0; 956 957 sz_left = p_blk->total_size; 958 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip; 959 line = p_blk->start_line + start_line_offset - 960 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 961 962 for (; lines; lines--) { 963 dma_addr_t p_phys; 964 void *p_virt; 965 u32 size; 966 967 size = min_t(u32, sz_left, p_blk->real_size_in_page); 968 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, size, 969 &p_phys, GFP_KERNEL); 970 if (!p_virt) 971 return -ENOMEM; 972 973 ilt_shadow[line].phys_addr = p_phys; 974 ilt_shadow[line].virt_addr = p_virt; 975 ilt_shadow[line].size = size; 976 977 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 978 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 979 line, (u64)p_phys, p_virt, size); 980 981 sz_left -= size; 982 line++; 983 } 984 985 return 0; 986} 987 988static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 989{ 990 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 991 struct qed_ilt_client_cfg *clients = p_mngr->clients; 992 struct qed_ilt_cli_blk *p_blk; 993 u32 size, i, j, k; 994 int rc; 995 996 size = qed_cxt_ilt_shadow_size(clients); 997 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct phys_mem_desc), 998 GFP_KERNEL); 999 if (!p_mngr->ilt_shadow) { 1000 rc = -ENOMEM; 1001 goto ilt_shadow_fail; 1002 } 1003 1004 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1005 "Allocated 0x%x bytes for ilt shadow\n", 1006 (u32)(size * sizeof(struct phys_mem_desc))); 1007 1008 for_each_ilt_valid_client(i, clients) { 1009 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 1010 p_blk = &clients[i].pf_blks[j]; 1011 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 1012 if (rc) 1013 goto ilt_shadow_fail; 1014 } 1015 for (k = 0; k < p_mngr->vf_count; k++) { 1016 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1017 u32 lines = clients[i].vf_total_lines * k; 1018 1019 p_blk = &clients[i].vf_blks[j]; 1020 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines); 1021 if (rc) 1022 goto ilt_shadow_fail; 1023 } 1024 } 1025 } 1026 1027 return 0; 1028 1029ilt_shadow_fail: 1030 qed_ilt_shadow_free(p_hwfn); 1031 return rc; 1032} 1033 1034static void qed_cid_map_free(struct qed_hwfn *p_hwfn) 1035{ 1036 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1037 u32 type, vf; 1038 1039 for (type = 0; type < MAX_CONN_TYPES; type++) { 1040 kfree(p_mngr->acquired[type].cid_map); 1041 p_mngr->acquired[type].max_count = 0; 1042 p_mngr->acquired[type].start_cid = 0; 1043 1044 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1045 kfree(p_mngr->acquired_vf[type][vf].cid_map); 1046 p_mngr->acquired_vf[type][vf].max_count = 0; 1047 p_mngr->acquired_vf[type][vf].start_cid = 0; 1048 } 1049 } 1050} 1051 1052static int 1053qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn, 1054 u32 type, 1055 u32 cid_start, 1056 u32 cid_count, struct qed_cid_acquired_map *p_map) 1057{ 1058 u32 size; 1059 1060 if (!cid_count) 1061 return 0; 1062 1063 size = DIV_ROUND_UP(cid_count, 1064 sizeof(unsigned long) * BITS_PER_BYTE) * 1065 sizeof(unsigned long); 1066 p_map->cid_map = kzalloc(size, GFP_KERNEL); 1067 if (!p_map->cid_map) 1068 return -ENOMEM; 1069 1070 p_map->max_count = cid_count; 1071 p_map->start_cid = cid_start; 1072 1073 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1074 "Type %08x start: %08x count %08x\n", 1075 type, p_map->start_cid, p_map->max_count); 1076 1077 return 0; 1078} 1079 1080static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn) 1081{ 1082 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1083 u32 start_cid = 0, vf_start_cid = 0; 1084 u32 type, vf; 1085 1086 for (type = 0; type < MAX_CONN_TYPES; type++) { 1087 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1088 struct qed_cid_acquired_map *p_map; 1089 1090 /* Handle PF maps */ 1091 p_map = &p_mngr->acquired[type]; 1092 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid, 1093 p_cfg->cid_count, p_map)) 1094 goto cid_map_fail; 1095 1096 /* Handle VF maps */ 1097 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1098 p_map = &p_mngr->acquired_vf[type][vf]; 1099 if (qed_cid_map_alloc_single(p_hwfn, type, 1100 vf_start_cid, 1101 p_cfg->cids_per_vf, p_map)) 1102 goto cid_map_fail; 1103 } 1104 1105 start_cid += p_cfg->cid_count; 1106 vf_start_cid += p_cfg->cids_per_vf; 1107 } 1108 1109 return 0; 1110 1111cid_map_fail: 1112 qed_cid_map_free(p_hwfn); 1113 return -ENOMEM; 1114} 1115 1116int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) 1117{ 1118 struct qed_ilt_client_cfg *clients; 1119 struct qed_cxt_mngr *p_mngr; 1120 u32 i; 1121 1122 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL); 1123 if (!p_mngr) 1124 return -ENOMEM; 1125 1126 /* Initialize ILT client registers */ 1127 clients = p_mngr->clients; 1128 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1129 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1130 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1131 1132 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1133 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1134 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1135 1136 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1137 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1138 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1139 1140 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1141 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1142 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1143 1144 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1145 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1146 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1147 1148 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1149 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1150 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1151 /* default ILT page size for all clients is 64K */ 1152 for (i = 0; i < MAX_ILT_CLIENTS; i++) 1153 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; 1154 1155 p_mngr->conn_ctx_size = CONN_CXT_SIZE(p_hwfn); 1156 1157 /* Initialize task sizes */ 1158 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1159 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1160 1161 if (p_hwfn->cdev->p_iov_info) { 1162 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs; 1163 p_mngr->first_vf_in_pf = 1164 p_hwfn->cdev->p_iov_info->first_vf_in_pf; 1165 } 1166 /* Initialize the dynamic ILT allocation mutex */ 1167 mutex_init(&p_mngr->mutex); 1168 1169 /* Set the cxt mangr pointer priori to further allocations */ 1170 p_hwfn->p_cxt_mngr = p_mngr; 1171 1172 return 0; 1173} 1174 1175int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn) 1176{ 1177 int rc; 1178 1179 /* Allocate the ILT shadow table */ 1180 rc = qed_ilt_shadow_alloc(p_hwfn); 1181 if (rc) 1182 goto tables_alloc_fail; 1183 1184 /* Allocate the T2 table */ 1185 rc = qed_cxt_src_t2_alloc(p_hwfn); 1186 if (rc) 1187 goto tables_alloc_fail; 1188 1189 /* Allocate and initialize the acquired cids bitmaps */ 1190 rc = qed_cid_map_alloc(p_hwfn); 1191 if (rc) 1192 goto tables_alloc_fail; 1193 1194 return 0; 1195 1196tables_alloc_fail: 1197 qed_cxt_mngr_free(p_hwfn); 1198 return rc; 1199} 1200 1201void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn) 1202{ 1203 if (!p_hwfn->p_cxt_mngr) 1204 return; 1205 1206 qed_cid_map_free(p_hwfn); 1207 qed_cxt_src_t2_free(p_hwfn); 1208 qed_ilt_shadow_free(p_hwfn); 1209 kfree(p_hwfn->p_cxt_mngr); 1210 1211 p_hwfn->p_cxt_mngr = NULL; 1212} 1213 1214void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn) 1215{ 1216 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1217 struct qed_cid_acquired_map *p_map; 1218 struct qed_conn_type_cfg *p_cfg; 1219 int type; 1220 u32 len; 1221 1222 /* Reset acquired cids */ 1223 for (type = 0; type < MAX_CONN_TYPES; type++) { 1224 u32 vf; 1225 1226 p_cfg = &p_mngr->conn_cfg[type]; 1227 if (p_cfg->cid_count) { 1228 p_map = &p_mngr->acquired[type]; 1229 len = DIV_ROUND_UP(p_map->max_count, 1230 sizeof(unsigned long) * 1231 BITS_PER_BYTE) * 1232 sizeof(unsigned long); 1233 memset(p_map->cid_map, 0, len); 1234 } 1235 1236 if (!p_cfg->cids_per_vf) 1237 continue; 1238 1239 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1240 p_map = &p_mngr->acquired_vf[type][vf]; 1241 len = DIV_ROUND_UP(p_map->max_count, 1242 sizeof(unsigned long) * 1243 BITS_PER_BYTE) * 1244 sizeof(unsigned long); 1245 memset(p_map->cid_map, 0, len); 1246 } 1247 } 1248} 1249 1250/* CDU Common */ 1251#define CDUC_CXT_SIZE_SHIFT \ 1252 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1253 1254#define CDUC_CXT_SIZE_MASK \ 1255 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1256 1257#define CDUC_BLOCK_WASTE_SHIFT \ 1258 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1259 1260#define CDUC_BLOCK_WASTE_MASK \ 1261 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1262 1263#define CDUC_NCIB_SHIFT \ 1264 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1265 1266#define CDUC_NCIB_MASK \ 1267 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1268 1269#define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1270 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1271 1272#define CDUT_TYPE0_CXT_SIZE_MASK \ 1273 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1274 CDUT_TYPE0_CXT_SIZE_SHIFT) 1275 1276#define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1277 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1278 1279#define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1280 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1281 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1282 1283#define CDUT_TYPE0_NCIB_SHIFT \ 1284 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1285 1286#define CDUT_TYPE0_NCIB_MASK \ 1287 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1288 CDUT_TYPE0_NCIB_SHIFT) 1289 1290#define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1291 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1292 1293#define CDUT_TYPE1_CXT_SIZE_MASK \ 1294 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1295 CDUT_TYPE1_CXT_SIZE_SHIFT) 1296 1297#define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1298 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1299 1300#define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1301 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1302 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1303 1304#define CDUT_TYPE1_NCIB_SHIFT \ 1305 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1306 1307#define CDUT_TYPE1_NCIB_MASK \ 1308 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1309 CDUT_TYPE1_NCIB_SHIFT) 1310 1311static void qed_cdu_init_common(struct qed_hwfn *p_hwfn) 1312{ 1313 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1314 1315 /* CDUC - connection configuration */ 1316 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1317 cxt_size = CONN_CXT_SIZE(p_hwfn); 1318 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1319 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1320 1321 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1322 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1323 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); 1324 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1325 1326 /* CDUT - type-0 tasks configuration */ 1327 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1328 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1329 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1330 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1331 1332 /* cxt size and block-waste are multipes of 8 */ 1333 cdu_params = 0; 1334 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1335 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1336 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1337 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1338 1339 /* CDUT - type-1 tasks configuration */ 1340 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1341 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1342 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1343 1344 /* cxt size and block-waste are multipes of 8 */ 1345 cdu_params = 0; 1346 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1347 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1348 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1349 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1350} 1351 1352/* CDU PF */ 1353#define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1354#define CDU_SEG_REG_TYPE_MASK 0x1 1355#define CDU_SEG_REG_OFFSET_SHIFT 0 1356#define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1357 1358static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) 1359{ 1360 struct qed_ilt_client_cfg *p_cli; 1361 struct qed_tid_seg *p_seg; 1362 u32 cdu_seg_params, offset; 1363 int i; 1364 1365 static const u32 rt_type_offset_arr[] = { 1366 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1367 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1368 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1369 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1370 }; 1371 1372 static const u32 rt_type_offset_fl_arr[] = { 1373 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1374 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1375 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1376 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1377 }; 1378 1379 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1380 1381 /* There are initializations only for CDUT during pf Phase */ 1382 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1383 /* Segment 0 */ 1384 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 1385 if (!p_seg) 1386 continue; 1387 1388 /* Note: start_line is already adjusted for the CDU 1389 * segment register granularity, so we just need to 1390 * divide. Adjustment is implicit as we assume ILT 1391 * Page size is larger than 32K! 1392 */ 1393 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1394 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1395 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1396 1397 cdu_seg_params = 0; 1398 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1399 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1400 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); 1401 1402 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1403 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1404 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1405 1406 cdu_seg_params = 0; 1407 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1408 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1409 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); 1410 } 1411} 1412 1413void qed_qm_init_pf(struct qed_hwfn *p_hwfn, 1414 struct qed_ptt *p_ptt, bool is_pf_loading) 1415{ 1416 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1417 struct qed_qm_pf_rt_init_params params; 1418 struct qed_qm_iids iids; 1419 1420 memset(&iids, 0, sizeof(iids)); 1421 qed_cxt_qm_iids(p_hwfn, &iids); 1422 1423 memset(¶ms, 0, sizeof(params)); 1424 params.port_id = p_hwfn->port_id; 1425 params.pf_id = p_hwfn->rel_pf_id; 1426 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1427 params.is_pf_loading = is_pf_loading; 1428 params.num_pf_cids = iids.cids; 1429 params.num_vf_cids = iids.vf_cids; 1430 params.num_tids = iids.tids; 1431 params.start_pq = qm_info->start_pq; 1432 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs; 1433 params.num_vf_pqs = qm_info->num_vf_pqs; 1434 params.start_vport = qm_info->start_vport; 1435 params.num_vports = qm_info->num_vports; 1436 params.pf_wfq = qm_info->pf_wfq; 1437 params.pf_rl = qm_info->pf_rl; 1438 params.pq_params = qm_info->qm_pq_params; 1439 params.vport_params = qm_info->qm_vport_params; 1440 1441 qed_qm_pf_rt_init(p_hwfn, p_ptt, ¶ms); 1442} 1443 1444/* CM PF */ 1445static void qed_cm_init_pf(struct qed_hwfn *p_hwfn) 1446{ 1447 /* XCM pure-LB queue */ 1448 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, 1449 qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1450} 1451 1452/* DQ PF */ 1453static void qed_dq_init_pf(struct qed_hwfn *p_hwfn) 1454{ 1455 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1456 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1457 1458 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1459 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1460 1461 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1462 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1463 1464 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1465 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1466 1467 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1468 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1469 1470 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1471 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1472 1473 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1474 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1475 1476 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1477 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1478 1479 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1480 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1481 1482 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1483 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1484 1485 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1486 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1487 1488 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1489 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1490 1491 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1492 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1493 1494 /* Connection types 6 & 7 are not in use, yet they must be configured 1495 * as the highest possible connection. Not configuring them means the 1496 * defaults will be used, and with a large number of cids a bug may 1497 * occur, if the defaults will be smaller than dq_pf_max_cid / 1498 * dq_vf_max_cid. 1499 */ 1500 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1501 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1502 1503 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1504 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1505} 1506 1507static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) 1508{ 1509 struct qed_ilt_client_cfg *ilt_clients; 1510 int i; 1511 1512 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1513 for_each_ilt_valid_client(i, ilt_clients) { 1514 STORE_RT_REG(p_hwfn, 1515 ilt_clients[i].first.reg, 1516 ilt_clients[i].first.val); 1517 STORE_RT_REG(p_hwfn, 1518 ilt_clients[i].last.reg, ilt_clients[i].last.val); 1519 STORE_RT_REG(p_hwfn, 1520 ilt_clients[i].p_size.reg, 1521 ilt_clients[i].p_size.val); 1522 } 1523} 1524 1525static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn) 1526{ 1527 struct qed_ilt_client_cfg *p_cli; 1528 u32 blk_factor; 1529 1530 /* For simplicty we set the 'block' to be an ILT page */ 1531 if (p_hwfn->cdev->p_iov_info) { 1532 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 1533 1534 STORE_RT_REG(p_hwfn, 1535 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1536 p_iov->first_vf_in_pf); 1537 STORE_RT_REG(p_hwfn, 1538 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1539 p_iov->first_vf_in_pf + p_iov->total_vfs); 1540 } 1541 1542 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1543 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1544 if (p_cli->active) { 1545 STORE_RT_REG(p_hwfn, 1546 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1547 blk_factor); 1548 STORE_RT_REG(p_hwfn, 1549 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1550 p_cli->pf_total_lines); 1551 STORE_RT_REG(p_hwfn, 1552 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1553 p_cli->vf_total_lines); 1554 } 1555 1556 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1557 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1558 if (p_cli->active) { 1559 STORE_RT_REG(p_hwfn, 1560 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1561 blk_factor); 1562 STORE_RT_REG(p_hwfn, 1563 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1564 p_cli->pf_total_lines); 1565 STORE_RT_REG(p_hwfn, 1566 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1567 p_cli->vf_total_lines); 1568 } 1569 1570 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1571 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1572 if (p_cli->active) { 1573 STORE_RT_REG(p_hwfn, 1574 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor); 1575 STORE_RT_REG(p_hwfn, 1576 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1577 p_cli->pf_total_lines); 1578 STORE_RT_REG(p_hwfn, 1579 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1580 p_cli->vf_total_lines); 1581 } 1582} 1583 1584/* ILT (PSWRQ2) PF */ 1585static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) 1586{ 1587 struct qed_ilt_client_cfg *clients; 1588 struct qed_cxt_mngr *p_mngr; 1589 struct phys_mem_desc *p_shdw; 1590 u32 line, rt_offst, i; 1591 1592 qed_ilt_bounds_init(p_hwfn); 1593 qed_ilt_vf_bounds_init(p_hwfn); 1594 1595 p_mngr = p_hwfn->p_cxt_mngr; 1596 p_shdw = p_mngr->ilt_shadow; 1597 clients = p_hwfn->p_cxt_mngr->clients; 1598 1599 for_each_ilt_valid_client(i, clients) { 1600 /** Client's 1st val and RT array are absolute, ILT shadows' 1601 * lines are relative. 1602 */ 1603 line = clients[i].first.val - p_mngr->pf_start_line; 1604 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1605 clients[i].first.val * ILT_ENTRY_IN_REGS; 1606 1607 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1608 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1609 u64 ilt_hw_entry = 0; 1610 1611 /** p_virt could be NULL incase of dynamic 1612 * allocation 1613 */ 1614 if (p_shdw[line].virt_addr) { 1615 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1616 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1617 (p_shdw[line].phys_addr >> 12)); 1618 1619 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1620 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1621 rt_offst, line, i, 1622 (u64)(p_shdw[line].phys_addr >> 12)); 1623 } 1624 1625 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1626 } 1627 } 1628} 1629 1630/* SRC (Searcher) PF */ 1631static void qed_src_init_pf(struct qed_hwfn *p_hwfn) 1632{ 1633 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1634 u32 rounded_conn_num, conn_num, conn_max; 1635 struct qed_src_iids src_iids; 1636 1637 memset(&src_iids, 0, sizeof(src_iids)); 1638 qed_cxt_src_iids(p_mngr, &src_iids); 1639 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1640 if (!conn_num) 1641 return; 1642 1643 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS); 1644 rounded_conn_num = roundup_pow_of_two(conn_max); 1645 1646 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1647 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1648 ilog2(rounded_conn_num)); 1649 1650 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1651 p_hwfn->p_cxt_mngr->src_t2.first_free); 1652 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1653 p_hwfn->p_cxt_mngr->src_t2.last_free); 1654} 1655 1656/* Timers PF */ 1657#define TM_CFG_NUM_IDS_SHIFT 0 1658#define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1659#define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1660#define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1661#define TM_CFG_PARENT_PF_SHIFT 25 1662#define TM_CFG_PARENT_PF_MASK 0x7ULL 1663 1664#define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1665#define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1666 1667#define TM_CFG_TID_OFFSET_SHIFT 30 1668#define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1669#define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1670#define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1671 1672static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) 1673{ 1674 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1675 u32 active_seg_mask = 0, tm_offset, rt_reg; 1676 struct qed_tm_iids tm_iids; 1677 u64 cfg_word; 1678 u8 i; 1679 1680 memset(&tm_iids, 0, sizeof(tm_iids)); 1681 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 1682 1683 /* @@@TBD No pre-scan for now */ 1684 1685 /* Note: We assume consecutive VFs for a PF */ 1686 for (i = 0; i < p_mngr->vf_count; i++) { 1687 cfg_word = 0; 1688 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1689 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1690 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1691 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); 1692 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1693 (sizeof(cfg_word) / sizeof(u32)) * 1694 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1695 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1696 } 1697 1698 cfg_word = 0; 1699 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1700 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1701 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1702 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1703 1704 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1705 (sizeof(cfg_word) / sizeof(u32)) * 1706 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id); 1707 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1708 1709 /* enale scan */ 1710 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1711 tm_iids.pf_cids ? 0x1 : 0x0); 1712 1713 /* @@@TBD how to enable the scan for the VFs */ 1714 1715 tm_offset = tm_iids.per_vf_cids; 1716 1717 /* Note: We assume consecutive VFs for a PF */ 1718 for (i = 0; i < p_mngr->vf_count; i++) { 1719 cfg_word = 0; 1720 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1721 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1722 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1723 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1724 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1725 1726 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1727 (sizeof(cfg_word) / sizeof(u32)) * 1728 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1729 1730 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1731 } 1732 1733 tm_offset = tm_iids.pf_cids; 1734 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1735 cfg_word = 0; 1736 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1737 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1738 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1739 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1740 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1741 1742 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1743 (sizeof(cfg_word) / sizeof(u32)) * 1744 (NUM_OF_VFS(p_hwfn->cdev) + 1745 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1746 1747 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1748 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0); 1749 1750 tm_offset += tm_iids.pf_tids[i]; 1751 } 1752 1753 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) 1754 active_seg_mask = 0; 1755 1756 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1757 1758 /* @@@TBD how to enable the scan for the VFs */ 1759} 1760 1761static void qed_prs_init_common(struct qed_hwfn *p_hwfn) 1762{ 1763 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) && 1764 p_hwfn->pf_params.fcoe_pf_params.is_target) 1765 STORE_RT_REG(p_hwfn, 1766 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1767} 1768 1769static void qed_prs_init_pf(struct qed_hwfn *p_hwfn) 1770{ 1771 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1772 struct qed_conn_type_cfg *p_fcoe; 1773 struct qed_tid_seg *p_tid; 1774 1775 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1776 1777 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1778 if (!p_fcoe->cid_count) 1779 return; 1780 1781 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG]; 1782 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1783 STORE_RT_REG_AGG(p_hwfn, 1784 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1785 p_tid->count); 1786 } else { 1787 STORE_RT_REG_AGG(p_hwfn, 1788 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1789 p_tid->count); 1790 } 1791} 1792 1793void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) 1794{ 1795 qed_cdu_init_common(p_hwfn); 1796 qed_prs_init_common(p_hwfn); 1797} 1798 1799void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1800{ 1801 qed_qm_init_pf(p_hwfn, p_ptt, true); 1802 qed_cm_init_pf(p_hwfn); 1803 qed_dq_init_pf(p_hwfn); 1804 qed_cdu_init_pf(p_hwfn); 1805 qed_ilt_init_pf(p_hwfn); 1806 qed_src_init_pf(p_hwfn); 1807 qed_tm_init_pf(p_hwfn); 1808 qed_prs_init_pf(p_hwfn); 1809} 1810 1811int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1812 enum protocol_type type, u32 *p_cid, u8 vfid) 1813{ 1814 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1815 struct qed_cid_acquired_map *p_map; 1816 u32 rel_cid; 1817 1818 if (type >= MAX_CONN_TYPES) { 1819 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1820 return -EINVAL; 1821 } 1822 1823 if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) { 1824 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid); 1825 return -EINVAL; 1826 } 1827 1828 /* Determine the right map to take this CID from */ 1829 if (vfid == QED_CXT_PF_CID) 1830 p_map = &p_mngr->acquired[type]; 1831 else 1832 p_map = &p_mngr->acquired_vf[type][vfid]; 1833 1834 if (!p_map->cid_map) { 1835 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1836 return -EINVAL; 1837 } 1838 1839 rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count); 1840 1841 if (rel_cid >= p_map->max_count) { 1842 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type); 1843 return -EINVAL; 1844 } 1845 1846 __set_bit(rel_cid, p_map->cid_map); 1847 1848 *p_cid = rel_cid + p_map->start_cid; 1849 1850 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1851 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 1852 *p_cid, rel_cid, vfid, type); 1853 1854 return 0; 1855} 1856 1857int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1858 enum protocol_type type, u32 *p_cid) 1859{ 1860 return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID); 1861} 1862 1863static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, 1864 u32 cid, 1865 u8 vfid, 1866 enum protocol_type *p_type, 1867 struct qed_cid_acquired_map **pp_map) 1868{ 1869 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1870 u32 rel_cid; 1871 1872 /* Iterate over protocols and find matching cid range */ 1873 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 1874 if (vfid == QED_CXT_PF_CID) 1875 *pp_map = &p_mngr->acquired[*p_type]; 1876 else 1877 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 1878 1879 if (!((*pp_map)->cid_map)) 1880 continue; 1881 if (cid >= (*pp_map)->start_cid && 1882 cid < (*pp_map)->start_cid + (*pp_map)->max_count) 1883 break; 1884 } 1885 1886 if (*p_type == MAX_CONN_TYPES) { 1887 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid); 1888 goto fail; 1889 } 1890 1891 rel_cid = cid - (*pp_map)->start_cid; 1892 if (!test_bit(rel_cid, (*pp_map)->cid_map)) { 1893 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired", 1894 cid, vfid); 1895 goto fail; 1896 } 1897 1898 return true; 1899fail: 1900 *p_type = MAX_CONN_TYPES; 1901 *pp_map = NULL; 1902 return false; 1903} 1904 1905void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid) 1906{ 1907 struct qed_cid_acquired_map *p_map = NULL; 1908 enum protocol_type type; 1909 bool b_acquired; 1910 u32 rel_cid; 1911 1912 if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) { 1913 DP_NOTICE(p_hwfn, 1914 "Trying to return incorrect CID belonging to VF %02x\n", 1915 vfid); 1916 return; 1917 } 1918 1919 /* Test acquired and find matching per-protocol map */ 1920 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid, 1921 &type, &p_map); 1922 1923 if (!b_acquired) 1924 return; 1925 1926 rel_cid = cid - p_map->start_cid; 1927 clear_bit(rel_cid, p_map->cid_map); 1928 1929 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1930 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 1931 cid, rel_cid, vfid, type); 1932} 1933 1934void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid) 1935{ 1936 _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID); 1937} 1938 1939int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info) 1940{ 1941 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1942 struct qed_cid_acquired_map *p_map = NULL; 1943 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 1944 enum protocol_type type; 1945 bool b_acquired; 1946 1947 /* Test acquired and find matching per-protocol map */ 1948 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, 1949 QED_CXT_PF_CID, &type, &p_map); 1950 1951 if (!b_acquired) 1952 return -EINVAL; 1953 1954 /* set the protocl type */ 1955 p_info->type = type; 1956 1957 /* compute context virtual pointer */ 1958 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1959 1960 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 1961 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 1962 line = p_info->iid / cxts_per_p; 1963 1964 /* Make sure context is allocated (dynamic allocation) */ 1965 if (!p_mngr->ilt_shadow[line].virt_addr) 1966 return -EINVAL; 1967 1968 p_info->p_cxt = p_mngr->ilt_shadow[line].virt_addr + 1969 p_info->iid % cxts_per_p * conn_cxt_size; 1970 1971 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT), 1972 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 1973 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid); 1974 1975 return 0; 1976} 1977 1978static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn, 1979 struct qed_rdma_pf_params *p_params, 1980 u32 num_tasks) 1981{ 1982 u32 num_cons, num_qps; 1983 enum protocol_type proto; 1984 1985 if (p_hwfn->mcp_info->func_info.protocol == QED_PCI_ETH_RDMA) { 1986 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1987 "Current day drivers don't support RoCE & iWARP simultaneously on the same PF. Default to RoCE-only\n"); 1988 p_hwfn->hw_info.personality = QED_PCI_ETH_ROCE; 1989 } 1990 1991 switch (p_hwfn->hw_info.personality) { 1992 case QED_PCI_ETH_IWARP: 1993 /* Each QP requires one connection */ 1994 num_cons = min_t(u32, IWARP_MAX_QPS, p_params->num_qps); 1995 proto = PROTOCOLID_IWARP; 1996 break; 1997 case QED_PCI_ETH_ROCE: 1998 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps); 1999 num_cons = num_qps * 2; /* each QP requires two connections */ 2000 proto = PROTOCOLID_ROCE; 2001 break; 2002 default: 2003 return; 2004 } 2005 2006 if (num_cons && num_tasks) { 2007 u32 num_srqs, num_xrc_srqs; 2008 2009 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0); 2010 2011 /* Deliberatly passing ROCE for tasks id. This is because 2012 * iWARP / RoCE share the task id. 2013 */ 2014 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 2015 QED_CXT_ROCE_TID_SEG, 1, 2016 num_tasks, false); 2017 2018 num_srqs = min_t(u32, QED_RDMA_MAX_SRQS, p_params->num_srqs); 2019 2020 /* XRC SRQs populate a single ILT page */ 2021 num_xrc_srqs = qed_cxt_xrc_srqs_per_page(p_hwfn); 2022 2023 qed_cxt_set_srq_count(p_hwfn, num_srqs, num_xrc_srqs); 2024 } else { 2025 DP_INFO(p_hwfn->cdev, 2026 "RDMA personality used without setting params!\n"); 2027 } 2028} 2029 2030int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks) 2031{ 2032 /* Set the number of required CORE connections */ 2033 u32 core_cids = 1; /* SPQ */ 2034 2035 if (p_hwfn->using_ll2) 2036 core_cids += 4; 2037 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2038 2039 switch (p_hwfn->hw_info.personality) { 2040 case QED_PCI_ETH_RDMA: 2041 case QED_PCI_ETH_IWARP: 2042 case QED_PCI_ETH_ROCE: 2043 { 2044 qed_rdma_set_pf_params(p_hwfn, 2045 &p_hwfn-> 2046 pf_params.rdma_pf_params, 2047 rdma_tasks); 2048 /* no need for break since RoCE coexist with Ethernet */ 2049 } 2050 fallthrough; 2051 case QED_PCI_ETH: 2052 { 2053 struct qed_eth_pf_params *p_params = 2054 &p_hwfn->pf_params.eth_pf_params; 2055 2056 if (!p_params->num_vf_cons) 2057 p_params->num_vf_cons = 2058 ETH_PF_PARAMS_VF_CONS_DEFAULT; 2059 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2060 p_params->num_cons, 2061 p_params->num_vf_cons); 2062 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters; 2063 break; 2064 } 2065 case QED_PCI_FCOE: 2066 { 2067 struct qed_fcoe_pf_params *p_params; 2068 2069 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2070 2071 if (p_params->num_cons && p_params->num_tasks) { 2072 qed_cxt_set_proto_cid_count(p_hwfn, 2073 PROTOCOLID_FCOE, 2074 p_params->num_cons, 2075 0); 2076 2077 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2078 QED_CXT_FCOE_TID_SEG, 0, 2079 p_params->num_tasks, true); 2080 } else { 2081 DP_INFO(p_hwfn->cdev, 2082 "Fcoe personality used without setting params!\n"); 2083 } 2084 break; 2085 } 2086 case QED_PCI_ISCSI: 2087 { 2088 struct qed_iscsi_pf_params *p_params; 2089 2090 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2091 2092 if (p_params->num_cons && p_params->num_tasks) { 2093 qed_cxt_set_proto_cid_count(p_hwfn, 2094 PROTOCOLID_ISCSI, 2095 p_params->num_cons, 2096 0); 2097 2098 qed_cxt_set_proto_tid_count(p_hwfn, 2099 PROTOCOLID_ISCSI, 2100 QED_CXT_ISCSI_TID_SEG, 2101 0, 2102 p_params->num_tasks, 2103 true); 2104 } else { 2105 DP_INFO(p_hwfn->cdev, 2106 "Iscsi personality used without setting params!\n"); 2107 } 2108 break; 2109 } 2110 default: 2111 return -EINVAL; 2112 } 2113 2114 return 0; 2115} 2116 2117int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn, 2118 struct qed_tid_mem *p_info) 2119{ 2120 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2121 u32 proto, seg, total_lines, i, shadow_line; 2122 struct qed_ilt_client_cfg *p_cli; 2123 struct qed_ilt_cli_blk *p_fl_seg; 2124 struct qed_tid_seg *p_seg_info; 2125 2126 /* Verify the personality */ 2127 switch (p_hwfn->hw_info.personality) { 2128 case QED_PCI_FCOE: 2129 proto = PROTOCOLID_FCOE; 2130 seg = QED_CXT_FCOE_TID_SEG; 2131 break; 2132 case QED_PCI_ISCSI: 2133 proto = PROTOCOLID_ISCSI; 2134 seg = QED_CXT_ISCSI_TID_SEG; 2135 break; 2136 default: 2137 return -EINVAL; 2138 } 2139 2140 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2141 if (!p_cli->active) 2142 return -EINVAL; 2143 2144 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2145 if (!p_seg_info->has_fl_mem) 2146 return -EINVAL; 2147 2148 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2149 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2150 p_fl_seg->real_size_in_page); 2151 2152 for (i = 0; i < total_lines; i++) { 2153 shadow_line = i + p_fl_seg->start_line - 2154 p_hwfn->p_cxt_mngr->pf_start_line; 2155 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].virt_addr; 2156 } 2157 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2158 p_fl_seg->real_size_in_page; 2159 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2160 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2161 p_info->tid_size; 2162 2163 return 0; 2164} 2165 2166/* This function is very RoCE oriented, if another protocol in the future 2167 * will want this feature we'll need to modify the function to be more generic 2168 */ 2169int 2170qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 2171 enum qed_cxt_elem_type elem_type, u32 iid) 2172{ 2173 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2174 struct tdif_task_context *tdif_context; 2175 struct qed_ilt_client_cfg *p_cli; 2176 struct qed_ilt_cli_blk *p_blk; 2177 struct qed_ptt *p_ptt; 2178 dma_addr_t p_phys; 2179 u64 ilt_hw_entry; 2180 void *p_virt; 2181 u32 flags1; 2182 int rc = 0; 2183 2184 switch (elem_type) { 2185 case QED_ELEM_CXT: 2186 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2187 elem_size = CONN_CXT_SIZE(p_hwfn); 2188 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2189 break; 2190 case QED_ELEM_SRQ: 2191 /* The first ILT page is not used for regular SRQs. Skip it. */ 2192 iid += p_hwfn->p_cxt_mngr->xrc_srq_count; 2193 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2194 elem_size = SRQ_CXT_SIZE; 2195 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2196 break; 2197 case QED_ELEM_XRC_SRQ: 2198 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2199 elem_size = XRC_SRQ_CXT_SIZE; 2200 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2201 break; 2202 case QED_ELEM_TASK: 2203 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2204 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2205 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2206 break; 2207 default: 2208 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2209 return -EINVAL; 2210 } 2211 2212 /* Calculate line in ilt */ 2213 hw_p_size = p_cli->p_size.val; 2214 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2215 line = p_blk->start_line + (iid / elems_per_p); 2216 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2217 2218 /* If line is already allocated, do nothing, otherwise allocate it and 2219 * write it to the PSWRQ2 registers. 2220 * This section can be run in parallel from different contexts and thus 2221 * a mutex protection is needed. 2222 */ 2223 2224 mutex_lock(&p_hwfn->p_cxt_mngr->mutex); 2225 2226 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr) 2227 goto out0; 2228 2229 p_ptt = qed_ptt_acquire(p_hwfn); 2230 if (!p_ptt) { 2231 DP_NOTICE(p_hwfn, 2232 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2233 rc = -EBUSY; 2234 goto out0; 2235 } 2236 2237 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2238 p_blk->real_size_in_page, &p_phys, 2239 GFP_KERNEL); 2240 if (!p_virt) { 2241 rc = -ENOMEM; 2242 goto out1; 2243 } 2244 2245 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2246 * to compensate for a HW bug, but it is configured even if DIF is not 2247 * enabled. This is harmless and allows us to avoid a dedicated API. We 2248 * configure the field for all of the contexts on the newly allocated 2249 * page. 2250 */ 2251 if (elem_type == QED_ELEM_TASK) { 2252 u32 elem_i; 2253 u8 *elem_start = (u8 *)p_virt; 2254 union type1_task_context *elem; 2255 2256 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2257 elem = (union type1_task_context *)elem_start; 2258 tdif_context = &elem->roce_ctx.tdif_context; 2259 2260 flags1 = le32_to_cpu(tdif_context->flags1); 2261 SET_FIELD(flags1, TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf); 2262 tdif_context->flags1 = cpu_to_le32(flags1); 2263 2264 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2265 } 2266 } 2267 2268 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt; 2269 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys; 2270 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2271 p_blk->real_size_in_page; 2272 2273 /* compute absolute offset */ 2274 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2275 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2276 2277 ilt_hw_entry = 0; 2278 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2279 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 2280 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr 2281 >> 12)); 2282 2283 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2284 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry, 2285 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 2286 NULL); 2287 2288 if (elem_type == QED_ELEM_CXT) { 2289 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2290 elems_per_p; 2291 2292 /* Update the relevant register in the parser */ 2293 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2294 last_cid_allocated - 1); 2295 2296 if (!p_hwfn->b_rdma_enabled_in_prs) { 2297 /* Enable RDMA search */ 2298 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2299 p_hwfn->b_rdma_enabled_in_prs = true; 2300 } 2301 } 2302 2303out1: 2304 qed_ptt_release(p_hwfn, p_ptt); 2305out0: 2306 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex); 2307 2308 return rc; 2309} 2310 2311/* This function is very RoCE oriented, if another protocol in the future 2312 * will want this feature we'll need to modify the function to be more generic 2313 */ 2314static int 2315qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn, 2316 enum qed_cxt_elem_type elem_type, 2317 u32 start_iid, u32 count) 2318{ 2319 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2320 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2321 struct qed_ilt_client_cfg *p_cli; 2322 struct qed_ilt_cli_blk *p_blk; 2323 u32 end_iid = start_iid + count; 2324 struct qed_ptt *p_ptt; 2325 u64 ilt_hw_entry = 0; 2326 u32 i; 2327 2328 switch (elem_type) { 2329 case QED_ELEM_CXT: 2330 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2331 elem_size = CONN_CXT_SIZE(p_hwfn); 2332 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2333 break; 2334 case QED_ELEM_SRQ: 2335 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2336 elem_size = SRQ_CXT_SIZE; 2337 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2338 break; 2339 case QED_ELEM_XRC_SRQ: 2340 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2341 elem_size = XRC_SRQ_CXT_SIZE; 2342 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2343 break; 2344 case QED_ELEM_TASK: 2345 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2346 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2347 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2348 break; 2349 default: 2350 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2351 return -EINVAL; 2352 } 2353 2354 /* Calculate line in ilt */ 2355 hw_p_size = p_cli->p_size.val; 2356 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2357 start_line = p_blk->start_line + (start_iid / elems_per_p); 2358 end_line = p_blk->start_line + (end_iid / elems_per_p); 2359 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2360 end_line--; 2361 2362 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2363 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2364 2365 p_ptt = qed_ptt_acquire(p_hwfn); 2366 if (!p_ptt) { 2367 DP_NOTICE(p_hwfn, 2368 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2369 return -EBUSY; 2370 } 2371 2372 for (i = shadow_start_line; i < shadow_end_line; i++) { 2373 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr) 2374 continue; 2375 2376 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2377 p_hwfn->p_cxt_mngr->ilt_shadow[i].size, 2378 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr, 2379 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr); 2380 2381 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr = NULL; 2382 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr = 0; 2383 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2384 2385 /* compute absolute offset */ 2386 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2387 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2388 ILT_ENTRY_IN_REGS); 2389 2390 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2391 * wide-bus. 2392 */ 2393 qed_dmae_host2grc(p_hwfn, p_ptt, 2394 (u64) (uintptr_t) &ilt_hw_entry, 2395 reg_offset, 2396 sizeof(ilt_hw_entry) / sizeof(u32), 2397 NULL); 2398 } 2399 2400 qed_ptt_release(p_hwfn, p_ptt); 2401 2402 return 0; 2403} 2404 2405int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto) 2406{ 2407 int rc; 2408 u32 cid; 2409 2410 /* Free Connection CXT */ 2411 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT, 2412 qed_cxt_get_proto_cid_start(p_hwfn, 2413 proto), 2414 qed_cxt_get_proto_cid_count(p_hwfn, 2415 proto, &cid)); 2416 2417 if (rc) 2418 return rc; 2419 2420 /* Free Task CXT ( Intentionally RoCE as task-id is shared between 2421 * RoCE and iWARP ) 2422 */ 2423 proto = PROTOCOLID_ROCE; 2424 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0, 2425 qed_cxt_get_proto_tid_count(p_hwfn, proto)); 2426 if (rc) 2427 return rc; 2428 2429 /* Free TSDM CXT */ 2430 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_XRC_SRQ, 0, 2431 p_hwfn->p_cxt_mngr->xrc_srq_count); 2432 2433 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 2434 p_hwfn->p_cxt_mngr->xrc_srq_count, 2435 p_hwfn->p_cxt_mngr->srq_count); 2436 2437 return rc; 2438} 2439 2440int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn, 2441 u32 tid, u8 ctx_type, void **pp_task_ctx) 2442{ 2443 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2444 struct qed_ilt_client_cfg *p_cli; 2445 struct qed_tid_seg *p_seg_info; 2446 struct qed_ilt_cli_blk *p_seg; 2447 u32 num_tids_per_block; 2448 u32 tid_size, ilt_idx; 2449 u32 total_lines; 2450 u32 proto, seg; 2451 2452 /* Verify the personality */ 2453 switch (p_hwfn->hw_info.personality) { 2454 case QED_PCI_FCOE: 2455 proto = PROTOCOLID_FCOE; 2456 seg = QED_CXT_FCOE_TID_SEG; 2457 break; 2458 case QED_PCI_ISCSI: 2459 proto = PROTOCOLID_ISCSI; 2460 seg = QED_CXT_ISCSI_TID_SEG; 2461 break; 2462 default: 2463 return -EINVAL; 2464 } 2465 2466 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2467 if (!p_cli->active) 2468 return -EINVAL; 2469 2470 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2471 2472 if (ctx_type == QED_CTX_WORKING_MEM) { 2473 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2474 } else if (ctx_type == QED_CTX_FL_MEM) { 2475 if (!p_seg_info->has_fl_mem) 2476 return -EINVAL; 2477 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2478 } else { 2479 return -EINVAL; 2480 } 2481 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page); 2482 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2483 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2484 2485 if (total_lines < tid / num_tids_per_block) 2486 return -EINVAL; 2487 2488 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2489 p_mngr->pf_start_line; 2490 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].virt_addr + 2491 (tid % num_tids_per_block) * tid_size; 2492 2493 return 0; 2494} 2495 2496static u16 qed_blk_calculate_pages(struct qed_ilt_cli_blk *p_blk) 2497{ 2498 if (p_blk->real_size_in_page == 0) 2499 return 0; 2500 2501 return DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 2502} 2503 2504u16 qed_get_cdut_num_pf_init_pages(struct qed_hwfn *p_hwfn) 2505{ 2506 struct qed_ilt_client_cfg *p_cli; 2507 struct qed_ilt_cli_blk *p_blk; 2508 u16 i, pages = 0; 2509 2510 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2511 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2512 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]; 2513 pages += qed_blk_calculate_pages(p_blk); 2514 } 2515 2516 return pages; 2517} 2518 2519u16 qed_get_cdut_num_vf_init_pages(struct qed_hwfn *p_hwfn) 2520{ 2521 struct qed_ilt_client_cfg *p_cli; 2522 struct qed_ilt_cli_blk *p_blk; 2523 u16 i, pages = 0; 2524 2525 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2526 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2527 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)]; 2528 pages += qed_blk_calculate_pages(p_blk); 2529 } 2530 2531 return pages; 2532} 2533 2534u16 qed_get_cdut_num_pf_work_pages(struct qed_hwfn *p_hwfn) 2535{ 2536 struct qed_ilt_client_cfg *p_cli; 2537 struct qed_ilt_cli_blk *p_blk; 2538 u16 i, pages = 0; 2539 2540 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2541 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2542 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)]; 2543 pages += qed_blk_calculate_pages(p_blk); 2544 } 2545 2546 return pages; 2547} 2548 2549u16 qed_get_cdut_num_vf_work_pages(struct qed_hwfn *p_hwfn) 2550{ 2551 struct qed_ilt_client_cfg *p_cli; 2552 struct qed_ilt_cli_blk *p_blk; 2553 u16 pages = 0, i; 2554 2555 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2556 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2557 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)]; 2558 pages += qed_blk_calculate_pages(p_blk); 2559 } 2560 2561 return pages; 2562} 2563