1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4#ifndef _IONIC_LIF_H_ 5#define _IONIC_LIF_H_ 6 7#include <linux/dim.h> 8#include <linux/pci.h> 9#include "ionic_rx_filter.h" 10 11#define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 12#define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 13 14#define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1) 15#define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1) 16#define IONIC_RX_COPYBREAK_DEFAULT 256 17#define IONIC_TX_BUDGET_DEFAULT 256 18 19struct ionic_tx_stats { 20 u64 pkts; 21 u64 bytes; 22 u64 csum_none; 23 u64 csum; 24 u64 tso; 25 u64 tso_bytes; 26 u64 frags; 27 u64 vlan_inserted; 28 u64 clean; 29 u64 linearize; 30 u64 crc32_csum; 31 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; 32 u64 dma_map_err; 33}; 34 35struct ionic_rx_stats { 36 u64 pkts; 37 u64 bytes; 38 u64 csum_none; 39 u64 csum_complete; 40 u64 buffers_posted; 41 u64 dropped; 42 u64 vlan_stripped; 43 u64 csum_error; 44 u64 dma_map_err; 45 u64 alloc_err; 46}; 47 48#define IONIC_QCQ_F_INITED BIT(0) 49#define IONIC_QCQ_F_SG BIT(1) 50#define IONIC_QCQ_F_INTR BIT(2) 51#define IONIC_QCQ_F_TX_STATS BIT(3) 52#define IONIC_QCQ_F_RX_STATS BIT(4) 53#define IONIC_QCQ_F_NOTIFYQ BIT(5) 54 55struct ionic_napi_stats { 56 u64 poll_count; 57 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR]; 58}; 59 60struct ionic_qcq { 61 void *q_base; 62 dma_addr_t q_base_pa; 63 u32 q_size; 64 void *cq_base; 65 dma_addr_t cq_base_pa; 66 u32 cq_size; 67 void *sg_base; 68 dma_addr_t sg_base_pa; 69 u32 sg_size; 70 struct dim dim; 71 struct ionic_queue q; 72 struct ionic_cq cq; 73 struct ionic_intr_info intr; 74 struct napi_struct napi; 75 struct ionic_napi_stats napi_stats; 76 unsigned int flags; 77 struct dentry *dentry; 78}; 79 80#define q_to_qcq(q) container_of(q, struct ionic_qcq, q) 81#define q_to_tx_stats(q) (&(q)->lif->txqstats[(q)->index]) 82#define q_to_rx_stats(q) (&(q)->lif->rxqstats[(q)->index]) 83#define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi) 84#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq) 85 86enum ionic_deferred_work_type { 87 IONIC_DW_TYPE_RX_MODE, 88 IONIC_DW_TYPE_RX_ADDR_ADD, 89 IONIC_DW_TYPE_RX_ADDR_DEL, 90 IONIC_DW_TYPE_LINK_STATUS, 91 IONIC_DW_TYPE_LIF_RESET, 92}; 93 94struct ionic_deferred_work { 95 struct list_head list; 96 enum ionic_deferred_work_type type; 97 union { 98 unsigned int rx_mode; 99 u8 addr[ETH_ALEN]; 100 u8 fw_status; 101 }; 102}; 103 104struct ionic_deferred { 105 spinlock_t lock; /* lock for deferred work list */ 106 struct list_head list; 107 struct work_struct work; 108}; 109 110struct ionic_lif_sw_stats { 111 u64 tx_packets; 112 u64 tx_bytes; 113 u64 rx_packets; 114 u64 rx_bytes; 115 u64 tx_tso; 116 u64 tx_tso_bytes; 117 u64 tx_csum_none; 118 u64 tx_csum; 119 u64 rx_csum_none; 120 u64 rx_csum_complete; 121 u64 rx_csum_error; 122 u64 hw_tx_dropped; 123 u64 hw_rx_dropped; 124 u64 hw_rx_over_errors; 125 u64 hw_rx_missed_errors; 126 u64 hw_tx_aborted_errors; 127}; 128 129enum ionic_lif_state_flags { 130 IONIC_LIF_F_INITED, 131 IONIC_LIF_F_SW_DEBUG_STATS, 132 IONIC_LIF_F_UP, 133 IONIC_LIF_F_LINK_CHECK_REQUESTED, 134 IONIC_LIF_F_FW_RESET, 135 IONIC_LIF_F_SPLIT_INTR, 136 IONIC_LIF_F_TX_DIM_INTR, 137 IONIC_LIF_F_RX_DIM_INTR, 138 139 /* leave this as last */ 140 IONIC_LIF_F_STATE_SIZE 141}; 142 143struct ionic_qtype_info { 144 u8 version; 145 u8 supported; 146 u64 features; 147 u16 desc_sz; 148 u16 comp_sz; 149 u16 sg_desc_sz; 150 u16 max_sg_elems; 151 u16 sg_desc_stride; 152}; 153 154#define IONIC_LIF_NAME_MAX_SZ 32 155struct ionic_lif { 156 char name[IONIC_LIF_NAME_MAX_SZ]; 157 struct list_head list; 158 struct net_device *netdev; 159 DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE); 160 struct ionic *ionic; 161 bool registered; 162 unsigned int index; 163 unsigned int hw_index; 164 unsigned int kern_pid; 165 u64 __iomem *kern_dbpage; 166 struct mutex queue_lock; /* lock for queue structures */ 167 spinlock_t adminq_lock; /* lock for AdminQ operations */ 168 struct ionic_qcq *adminqcq; 169 struct ionic_qcq *notifyqcq; 170 struct ionic_qcq **txqcqs; 171 struct ionic_tx_stats *txqstats; 172 struct ionic_qcq **rxqcqs; 173 struct ionic_rx_stats *rxqstats; 174 u64 last_eid; 175 unsigned int neqs; 176 unsigned int nxqs; 177 unsigned int ntxq_descs; 178 unsigned int nrxq_descs; 179 u32 rx_copybreak; 180 u32 tx_budget; 181 unsigned int rx_mode; 182 u64 hw_features; 183 bool mc_overflow; 184 unsigned int nmcast; 185 bool uc_overflow; 186 u16 lif_type; 187 unsigned int nucast; 188 189 union ionic_lif_identity *identity; 190 struct ionic_lif_info *info; 191 dma_addr_t info_pa; 192 u32 info_sz; 193 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; 194 195 u16 rss_types; 196 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 197 u8 *rss_ind_tbl; 198 dma_addr_t rss_ind_tbl_pa; 199 u32 rss_ind_tbl_sz; 200 201 struct ionic_rx_filters rx_filters; 202 struct ionic_deferred deferred; 203 unsigned long *dbid_inuse; 204 unsigned int dbid_count; 205 struct dentry *dentry; 206 u32 rx_coalesce_usecs; /* what the user asked for */ 207 u32 rx_coalesce_hw; /* what the hw is using */ 208 u32 tx_coalesce_usecs; /* what the user asked for */ 209 u32 tx_coalesce_hw; /* what the hw is using */ 210 211 struct work_struct tx_timeout_work; 212}; 213 214struct ionic_queue_params { 215 unsigned int nxqs; 216 unsigned int ntxq_descs; 217 unsigned int nrxq_descs; 218 unsigned int intr_split; 219}; 220 221static inline void ionic_init_queue_params(struct ionic_lif *lif, 222 struct ionic_queue_params *qparam) 223{ 224 qparam->nxqs = lif->nxqs; 225 qparam->ntxq_descs = lif->ntxq_descs; 226 qparam->nrxq_descs = lif->nrxq_descs; 227 qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 228} 229 230static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) 231{ 232 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); 233 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); 234 235 /* Div-by-zero should never be an issue, but check anyway */ 236 if (!div || !mult) 237 return 0; 238 239 /* Round up in case usecs is close to the next hw unit */ 240 usecs += (div / mult) >> 1; 241 242 /* Convert from usecs to device units */ 243 return (usecs * mult) / div; 244} 245 246typedef void (*ionic_reset_cb)(struct ionic_lif *lif, void *arg); 247 248void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep); 249void ionic_get_stats64(struct net_device *netdev, 250 struct rtnl_link_stats64 *ns); 251void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 252 struct ionic_deferred_work *work); 253int ionic_lif_alloc(struct ionic *ionic); 254int ionic_lif_init(struct ionic_lif *lif); 255void ionic_lif_free(struct ionic_lif *lif); 256void ionic_lif_deinit(struct ionic_lif *lif); 257int ionic_lif_register(struct ionic_lif *lif); 258void ionic_lif_unregister(struct ionic_lif *lif); 259int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 260 union ionic_lif_identity *lif_ident); 261int ionic_lif_size(struct ionic *ionic); 262int ionic_lif_rss_config(struct ionic_lif *lif, u16 types, 263 const u8 *key, const u32 *indir); 264int ionic_reconfigure_queues(struct ionic_lif *lif, 265 struct ionic_queue_params *qparam); 266 267static inline void debug_stats_txq_post(struct ionic_queue *q, bool dbell) 268{ 269 struct ionic_txq_desc *desc = &q->txq[q->head_idx]; 270 u8 num_sg_elems; 271 272 q->dbell_count += dbell; 273 274 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT) 275 & IONIC_TXQ_DESC_NSGE_MASK); 276 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1)) 277 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1; 278 279 q->lif->txqstats[q->index].sg_cntr[num_sg_elems]++; 280} 281 282static inline void debug_stats_napi_poll(struct ionic_qcq *qcq, 283 unsigned int work_done) 284{ 285 qcq->napi_stats.poll_count++; 286 287 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1)) 288 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1; 289 290 qcq->napi_stats.work_done_cntr[work_done]++; 291} 292 293#define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++) 294#define DEBUG_STATS_RX_BUFF_CNT(q) ((q)->lif->rxqstats[q->index].buffers_posted++) 295#define DEBUG_STATS_TXQ_POST(q, dbell) debug_stats_txq_post(q, dbell) 296#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \ 297 debug_stats_napi_poll(qcq, work_done) 298 299#endif /* _IONIC_LIF_H_ */ 300