1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4#include <linux/printk.h> 5#include <linux/dynamic_debug.h> 6#include <linux/netdevice.h> 7#include <linux/etherdevice.h> 8#include <linux/if_vlan.h> 9#include <linux/rtnetlink.h> 10#include <linux/interrupt.h> 11#include <linux/pci.h> 12#include <linux/cpumask.h> 13 14#include "ionic.h" 15#include "ionic_bus.h" 16#include "ionic_lif.h" 17#include "ionic_txrx.h" 18#include "ionic_ethtool.h" 19#include "ionic_debugfs.h" 20 21/* queuetype support level */ 22static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 23 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 24 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 25 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 26 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 27 * 1 = ... with Tx SG version 1 28 */ 29}; 30 31static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); 32static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); 33static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); 34static void ionic_link_status_check(struct ionic_lif *lif); 35static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39static void ionic_txrx_deinit(struct ionic_lif *lif); 40static int ionic_txrx_init(struct ionic_lif *lif); 41static int ionic_start_queues(struct ionic_lif *lif); 42static void ionic_stop_queues(struct ionic_lif *lif); 43static void ionic_lif_queue_identify(struct ionic_lif *lif); 44 45static void ionic_dim_work(struct work_struct *work) 46{ 47 struct dim *dim = container_of(work, struct dim, work); 48 struct ionic_intr_info *intr; 49 struct dim_cq_moder cur_moder; 50 struct ionic_qcq *qcq; 51 struct ionic_lif *lif; 52 u32 new_coal; 53 54 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 55 qcq = container_of(dim, struct ionic_qcq, dim); 56 lif = qcq->q.lif; 57 new_coal = ionic_coal_usec_to_hw(lif->ionic, cur_moder.usec); 58 new_coal = new_coal ? new_coal : 1; 59 60 intr = &qcq->intr; 61 if (intr->dim_coal_hw != new_coal) { 62 intr->dim_coal_hw = new_coal; 63 64 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 65 intr->index, intr->dim_coal_hw); 66 } 67 68 dim->state = DIM_START_MEASURE; 69} 70 71static void ionic_lif_deferred_work(struct work_struct *work) 72{ 73 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 74 struct ionic_deferred *def = &lif->deferred; 75 struct ionic_deferred_work *w = NULL; 76 77 do { 78 spin_lock_bh(&def->lock); 79 if (!list_empty(&def->list)) { 80 w = list_first_entry(&def->list, 81 struct ionic_deferred_work, list); 82 list_del(&w->list); 83 } 84 spin_unlock_bh(&def->lock); 85 86 if (!w) 87 break; 88 89 switch (w->type) { 90 case IONIC_DW_TYPE_RX_MODE: 91 ionic_lif_rx_mode(lif, w->rx_mode); 92 break; 93 case IONIC_DW_TYPE_RX_ADDR_ADD: 94 ionic_lif_addr_add(lif, w->addr); 95 break; 96 case IONIC_DW_TYPE_RX_ADDR_DEL: 97 ionic_lif_addr_del(lif, w->addr); 98 break; 99 case IONIC_DW_TYPE_LINK_STATUS: 100 ionic_link_status_check(lif); 101 break; 102 case IONIC_DW_TYPE_LIF_RESET: 103 if (w->fw_status) 104 ionic_lif_handle_fw_up(lif); 105 else 106 ionic_lif_handle_fw_down(lif); 107 break; 108 default: 109 break; 110 } 111 kfree(w); 112 w = NULL; 113 } while (true); 114} 115 116void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 117 struct ionic_deferred_work *work) 118{ 119 spin_lock_bh(&def->lock); 120 list_add_tail(&work->list, &def->list); 121 spin_unlock_bh(&def->lock); 122 schedule_work(&def->work); 123} 124 125static void ionic_link_status_check(struct ionic_lif *lif) 126{ 127 struct net_device *netdev = lif->netdev; 128 u16 link_status; 129 bool link_up; 130 131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 132 return; 133 134 link_status = le16_to_cpu(lif->info->status.link_status); 135 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 136 137 if (link_up) { 138 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 139 mutex_lock(&lif->queue_lock); 140 ionic_start_queues(lif); 141 mutex_unlock(&lif->queue_lock); 142 } 143 144 if (!netif_carrier_ok(netdev)) { 145 u32 link_speed; 146 147 ionic_port_identify(lif->ionic); 148 link_speed = le32_to_cpu(lif->info->status.link_speed); 149 netdev_info(netdev, "Link up - %d Gbps\n", 150 link_speed / 1000); 151 netif_carrier_on(netdev); 152 } 153 } else { 154 if (netif_carrier_ok(netdev)) { 155 netdev_info(netdev, "Link down\n"); 156 netif_carrier_off(netdev); 157 } 158 159 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 160 mutex_lock(&lif->queue_lock); 161 ionic_stop_queues(lif); 162 mutex_unlock(&lif->queue_lock); 163 } 164 } 165 166 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 167} 168 169void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 170{ 171 struct ionic_deferred_work *work; 172 173 /* we only need one request outstanding at a time */ 174 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 175 return; 176 177 if (!can_sleep) { 178 work = kzalloc(sizeof(*work), GFP_ATOMIC); 179 if (!work) { 180 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 181 return; 182 } 183 184 work->type = IONIC_DW_TYPE_LINK_STATUS; 185 ionic_lif_deferred_enqueue(&lif->deferred, work); 186 } else { 187 ionic_link_status_check(lif); 188 } 189} 190 191static irqreturn_t ionic_isr(int irq, void *data) 192{ 193 struct napi_struct *napi = data; 194 195 napi_schedule_irqoff(napi); 196 197 return IRQ_HANDLED; 198} 199 200static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 201{ 202 struct ionic_intr_info *intr = &qcq->intr; 203 struct device *dev = lif->ionic->dev; 204 struct ionic_queue *q = &qcq->q; 205 const char *name; 206 207 if (lif->registered) 208 name = lif->netdev->name; 209 else 210 name = dev_name(dev); 211 212 snprintf(intr->name, sizeof(intr->name), 213 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 214 215 return devm_request_irq(dev, intr->vector, ionic_isr, 216 0, intr->name, &qcq->napi); 217} 218 219static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 220{ 221 struct ionic *ionic = lif->ionic; 222 int index; 223 224 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 225 if (index == ionic->nintrs) { 226 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 227 __func__, index, ionic->nintrs); 228 return -ENOSPC; 229 } 230 231 set_bit(index, ionic->intrs); 232 ionic_intr_init(&ionic->idev, intr, index); 233 234 return 0; 235} 236 237static void ionic_intr_free(struct ionic *ionic, int index) 238{ 239 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 240 clear_bit(index, ionic->intrs); 241} 242 243static int ionic_qcq_enable(struct ionic_qcq *qcq) 244{ 245 struct ionic_queue *q = &qcq->q; 246 struct ionic_lif *lif = q->lif; 247 struct ionic_dev *idev; 248 struct device *dev; 249 250 struct ionic_admin_ctx ctx = { 251 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 252 .cmd.q_control = { 253 .opcode = IONIC_CMD_Q_CONTROL, 254 .lif_index = cpu_to_le16(lif->index), 255 .type = q->type, 256 .index = cpu_to_le32(q->index), 257 .oper = IONIC_Q_ENABLE, 258 }, 259 }; 260 int ret; 261 262 idev = &lif->ionic->idev; 263 dev = lif->ionic->dev; 264 265 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 266 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 267 268 if (qcq->flags & IONIC_QCQ_F_INTR) 269 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 270 271 ret = ionic_adminq_post_wait(lif, &ctx); 272 if (ret) 273 return ret; 274 275 if (qcq->napi.poll) 276 napi_enable(&qcq->napi); 277 278 if (qcq->flags & IONIC_QCQ_F_INTR) { 279 irq_set_affinity_hint(qcq->intr.vector, 280 &qcq->intr.affinity_mask); 281 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 282 IONIC_INTR_MASK_CLEAR); 283 } 284 285 return 0; 286} 287 288static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw) 289{ 290 struct ionic_queue *q; 291 struct ionic_lif *lif; 292 int err = 0; 293 294 struct ionic_admin_ctx ctx = { 295 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 296 .cmd.q_control = { 297 .opcode = IONIC_CMD_Q_CONTROL, 298 .oper = IONIC_Q_DISABLE, 299 }, 300 }; 301 302 if (!qcq) 303 return -ENXIO; 304 305 q = &qcq->q; 306 lif = q->lif; 307 308 if (qcq->flags & IONIC_QCQ_F_INTR) { 309 struct ionic_dev *idev = &lif->ionic->idev; 310 311 cancel_work_sync(&qcq->dim.work); 312 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 313 IONIC_INTR_MASK_SET); 314 synchronize_irq(qcq->intr.vector); 315 irq_set_affinity_hint(qcq->intr.vector, NULL); 316 napi_disable(&qcq->napi); 317 } 318 319 if (send_to_hw) { 320 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 321 ctx.cmd.q_control.type = q->type; 322 ctx.cmd.q_control.index = cpu_to_le32(q->index); 323 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 324 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 325 326 err = ionic_adminq_post_wait(lif, &ctx); 327 } 328 329 return err; 330} 331 332static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 333{ 334 struct ionic_dev *idev = &lif->ionic->idev; 335 336 if (!qcq) 337 return; 338 339 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 340 return; 341 342 if (qcq->flags & IONIC_QCQ_F_INTR) { 343 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 344 IONIC_INTR_MASK_SET); 345 netif_napi_del(&qcq->napi); 346 } 347 348 qcq->flags &= ~IONIC_QCQ_F_INITED; 349} 350 351static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 352{ 353 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 354 return; 355 356 irq_set_affinity_hint(qcq->intr.vector, NULL); 357 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 358 qcq->intr.vector = 0; 359 ionic_intr_free(lif->ionic, qcq->intr.index); 360 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 361} 362 363static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 364{ 365 struct device *dev = lif->ionic->dev; 366 367 if (!qcq) 368 return; 369 370 ionic_debugfs_del_qcq(qcq); 371 372 if (qcq->q_base) { 373 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 374 qcq->q_base = NULL; 375 qcq->q_base_pa = 0; 376 } 377 378 if (qcq->cq_base) { 379 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 380 qcq->cq_base = NULL; 381 qcq->cq_base_pa = 0; 382 } 383 384 if (qcq->sg_base) { 385 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 386 qcq->sg_base = NULL; 387 qcq->sg_base_pa = 0; 388 } 389 390 ionic_qcq_intr_free(lif, qcq); 391 392 if (qcq->cq.info) { 393 devm_kfree(dev, qcq->cq.info); 394 qcq->cq.info = NULL; 395 } 396 if (qcq->q.info) { 397 devm_kfree(dev, qcq->q.info); 398 qcq->q.info = NULL; 399 } 400} 401 402static void ionic_qcqs_free(struct ionic_lif *lif) 403{ 404 struct device *dev = lif->ionic->dev; 405 406 if (lif->notifyqcq) { 407 ionic_qcq_free(lif, lif->notifyqcq); 408 devm_kfree(dev, lif->notifyqcq); 409 lif->notifyqcq = NULL; 410 } 411 412 if (lif->adminqcq) { 413 ionic_qcq_free(lif, lif->adminqcq); 414 devm_kfree(dev, lif->adminqcq); 415 lif->adminqcq = NULL; 416 } 417 418 if (lif->rxqcqs) { 419 devm_kfree(dev, lif->rxqstats); 420 lif->rxqstats = NULL; 421 devm_kfree(dev, lif->rxqcqs); 422 lif->rxqcqs = NULL; 423 } 424 425 if (lif->txqcqs) { 426 devm_kfree(dev, lif->txqstats); 427 lif->txqstats = NULL; 428 devm_kfree(dev, lif->txqcqs); 429 lif->txqcqs = NULL; 430 } 431} 432 433static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 434 struct ionic_qcq *n_qcq) 435{ 436 n_qcq->intr.vector = src_qcq->intr.vector; 437 n_qcq->intr.index = src_qcq->intr.index; 438} 439 440static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 441{ 442 int err; 443 444 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 445 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 446 return 0; 447 } 448 449 err = ionic_intr_alloc(lif, &qcq->intr); 450 if (err) { 451 netdev_warn(lif->netdev, "no intr for %s: %d\n", 452 qcq->q.name, err); 453 goto err_out; 454 } 455 456 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 457 if (err < 0) { 458 netdev_warn(lif->netdev, "no vector for %s: %d\n", 459 qcq->q.name, err); 460 goto err_out_free_intr; 461 } 462 qcq->intr.vector = err; 463 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 464 IONIC_INTR_MASK_SET); 465 466 err = ionic_request_irq(lif, qcq); 467 if (err) { 468 netdev_warn(lif->netdev, "irq request failed %d\n", err); 469 goto err_out_free_intr; 470 } 471 472 /* try to get the irq on the local numa node first */ 473 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 474 dev_to_node(lif->ionic->dev)); 475 if (qcq->intr.cpu != -1) 476 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 477 478 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 479 return 0; 480 481err_out_free_intr: 482 ionic_intr_free(lif->ionic, qcq->intr.index); 483err_out: 484 return err; 485} 486 487static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 488 unsigned int index, 489 const char *name, unsigned int flags, 490 unsigned int num_descs, unsigned int desc_size, 491 unsigned int cq_desc_size, 492 unsigned int sg_desc_size, 493 unsigned int pid, struct ionic_qcq **qcq) 494{ 495 struct ionic_dev *idev = &lif->ionic->idev; 496 struct device *dev = lif->ionic->dev; 497 void *q_base, *cq_base, *sg_base; 498 dma_addr_t cq_base_pa = 0; 499 dma_addr_t sg_base_pa = 0; 500 dma_addr_t q_base_pa = 0; 501 struct ionic_qcq *new; 502 int err; 503 504 *qcq = NULL; 505 506 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 507 if (!new) { 508 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 509 err = -ENOMEM; 510 goto err_out; 511 } 512 513 new->flags = flags; 514 515 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 516 GFP_KERNEL); 517 if (!new->q.info) { 518 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 519 err = -ENOMEM; 520 goto err_out_free_qcq; 521 } 522 523 new->q.type = type; 524 525 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 526 desc_size, sg_desc_size, pid); 527 if (err) { 528 netdev_err(lif->netdev, "Cannot initialize queue\n"); 529 goto err_out_free_q_info; 530 } 531 532 err = ionic_alloc_qcq_interrupt(lif, new); 533 if (err) 534 goto err_out; 535 536 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 537 GFP_KERNEL); 538 if (!new->cq.info) { 539 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 540 err = -ENOMEM; 541 goto err_out_free_irq; 542 } 543 544 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 545 if (err) { 546 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 547 goto err_out_free_cq_info; 548 } 549 550 if (flags & IONIC_QCQ_F_NOTIFYQ) { 551 int q_size, cq_size; 552 553 /* q & cq need to be contiguous in case of notifyq */ 554 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 555 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 556 557 new->q_size = PAGE_SIZE + q_size + cq_size; 558 new->q_base = dma_alloc_coherent(dev, new->q_size, 559 &new->q_base_pa, GFP_KERNEL); 560 if (!new->q_base) { 561 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 562 err = -ENOMEM; 563 goto err_out_free_cq_info; 564 } 565 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 566 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 567 ionic_q_map(&new->q, q_base, q_base_pa); 568 569 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 570 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 571 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 572 ionic_cq_bind(&new->cq, &new->q); 573 } else { 574 new->q_size = PAGE_SIZE + (num_descs * desc_size); 575 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 576 GFP_KERNEL); 577 if (!new->q_base) { 578 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 579 err = -ENOMEM; 580 goto err_out_free_cq_info; 581 } 582 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 583 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 584 ionic_q_map(&new->q, q_base, q_base_pa); 585 586 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 587 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 588 GFP_KERNEL); 589 if (!new->cq_base) { 590 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 591 err = -ENOMEM; 592 goto err_out_free_q; 593 } 594 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 595 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 596 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 597 ionic_cq_bind(&new->cq, &new->q); 598 } 599 600 if (flags & IONIC_QCQ_F_SG) { 601 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 602 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 603 GFP_KERNEL); 604 if (!new->sg_base) { 605 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 606 err = -ENOMEM; 607 goto err_out_free_cq; 608 } 609 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 610 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 611 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 612 } 613 614 INIT_WORK(&new->dim.work, ionic_dim_work); 615 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 616 617 *qcq = new; 618 619 return 0; 620 621err_out_free_cq: 622 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 623err_out_free_q: 624 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 625err_out_free_cq_info: 626 devm_kfree(dev, new->cq.info); 627err_out_free_irq: 628 if (flags & IONIC_QCQ_F_INTR) { 629 devm_free_irq(dev, new->intr.vector, &new->napi); 630 ionic_intr_free(lif->ionic, new->intr.index); 631 } 632err_out_free_q_info: 633 devm_kfree(dev, new->q.info); 634err_out_free_qcq: 635 devm_kfree(dev, new); 636err_out: 637 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 638 return err; 639} 640 641static int ionic_qcqs_alloc(struct ionic_lif *lif) 642{ 643 struct device *dev = lif->ionic->dev; 644 unsigned int flags; 645 int err; 646 647 flags = IONIC_QCQ_F_INTR; 648 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 649 IONIC_ADMINQ_LENGTH, 650 sizeof(struct ionic_admin_cmd), 651 sizeof(struct ionic_admin_comp), 652 0, lif->kern_pid, &lif->adminqcq); 653 if (err) 654 return err; 655 ionic_debugfs_add_qcq(lif, lif->adminqcq); 656 657 if (lif->ionic->nnqs_per_lif) { 658 flags = IONIC_QCQ_F_NOTIFYQ; 659 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 660 flags, IONIC_NOTIFYQ_LENGTH, 661 sizeof(struct ionic_notifyq_cmd), 662 sizeof(union ionic_notifyq_comp), 663 0, lif->kern_pid, &lif->notifyqcq); 664 if (err) 665 goto err_out; 666 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 667 668 /* Let the notifyq ride on the adminq interrupt */ 669 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 670 } 671 672 err = -ENOMEM; 673 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 674 sizeof(struct ionic_qcq *), GFP_KERNEL); 675 if (!lif->txqcqs) 676 goto err_out; 677 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 678 sizeof(struct ionic_qcq *), GFP_KERNEL); 679 if (!lif->rxqcqs) 680 goto err_out; 681 682 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 683 sizeof(struct ionic_tx_stats), GFP_KERNEL); 684 if (!lif->txqstats) 685 goto err_out; 686 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 687 sizeof(struct ionic_rx_stats), GFP_KERNEL); 688 if (!lif->rxqstats) 689 goto err_out; 690 691 return 0; 692 693err_out: 694 ionic_qcqs_free(lif); 695 return err; 696} 697 698static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 699{ 700 qcq->q.tail_idx = 0; 701 qcq->q.head_idx = 0; 702 qcq->cq.tail_idx = 0; 703 qcq->cq.done_color = 1; 704 memset(qcq->q_base, 0, qcq->q_size); 705 memset(qcq->cq_base, 0, qcq->cq_size); 706 memset(qcq->sg_base, 0, qcq->sg_size); 707} 708 709static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 710{ 711 struct device *dev = lif->ionic->dev; 712 struct ionic_queue *q = &qcq->q; 713 struct ionic_cq *cq = &qcq->cq; 714 struct ionic_admin_ctx ctx = { 715 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 716 .cmd.q_init = { 717 .opcode = IONIC_CMD_Q_INIT, 718 .lif_index = cpu_to_le16(lif->index), 719 .type = q->type, 720 .ver = lif->qtype_info[q->type].version, 721 .index = cpu_to_le32(q->index), 722 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 723 IONIC_QINIT_F_SG), 724 .pid = cpu_to_le16(q->pid), 725 .ring_size = ilog2(q->num_descs), 726 .ring_base = cpu_to_le64(q->base_pa), 727 .cq_ring_base = cpu_to_le64(cq->base_pa), 728 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 729 }, 730 }; 731 unsigned int intr_index; 732 int err; 733 734 if (qcq->flags & IONIC_QCQ_F_INTR) 735 intr_index = qcq->intr.index; 736 else 737 intr_index = lif->rxqcqs[q->index]->intr.index; 738 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 739 740 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 741 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 742 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 743 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 744 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 745 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 746 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 747 748 ionic_qcq_sanitize(qcq); 749 750 err = ionic_adminq_post_wait(lif, &ctx); 751 if (err) 752 return err; 753 754 q->hw_type = ctx.comp.q_init.hw_type; 755 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 756 q->dbval = IONIC_DBELL_QID(q->hw_index); 757 758 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 759 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 760 761 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 762 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 763 NAPI_POLL_WEIGHT); 764 765 qcq->flags |= IONIC_QCQ_F_INITED; 766 767 return 0; 768} 769 770static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 771{ 772 struct device *dev = lif->ionic->dev; 773 struct ionic_queue *q = &qcq->q; 774 struct ionic_cq *cq = &qcq->cq; 775 struct ionic_admin_ctx ctx = { 776 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 777 .cmd.q_init = { 778 .opcode = IONIC_CMD_Q_INIT, 779 .lif_index = cpu_to_le16(lif->index), 780 .type = q->type, 781 .ver = lif->qtype_info[q->type].version, 782 .index = cpu_to_le32(q->index), 783 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 784 IONIC_QINIT_F_SG), 785 .intr_index = cpu_to_le16(cq->bound_intr->index), 786 .pid = cpu_to_le16(q->pid), 787 .ring_size = ilog2(q->num_descs), 788 .ring_base = cpu_to_le64(q->base_pa), 789 .cq_ring_base = cpu_to_le64(cq->base_pa), 790 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 791 }, 792 }; 793 int err; 794 795 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 796 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 797 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 798 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 799 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 800 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 801 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 802 803 ionic_qcq_sanitize(qcq); 804 805 err = ionic_adminq_post_wait(lif, &ctx); 806 if (err) 807 return err; 808 809 q->hw_type = ctx.comp.q_init.hw_type; 810 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 811 q->dbval = IONIC_DBELL_QID(q->hw_index); 812 813 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 814 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 815 816 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 817 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 818 NAPI_POLL_WEIGHT); 819 else 820 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 821 NAPI_POLL_WEIGHT); 822 823 qcq->flags |= IONIC_QCQ_F_INITED; 824 825 return 0; 826} 827 828static bool ionic_notifyq_service(struct ionic_cq *cq, 829 struct ionic_cq_info *cq_info) 830{ 831 union ionic_notifyq_comp *comp = cq_info->cq_desc; 832 struct ionic_deferred_work *work; 833 struct net_device *netdev; 834 struct ionic_queue *q; 835 struct ionic_lif *lif; 836 u64 eid; 837 838 q = cq->bound_q; 839 lif = q->info[0].cb_arg; 840 netdev = lif->netdev; 841 eid = le64_to_cpu(comp->event.eid); 842 843 /* Have we run out of new completions to process? */ 844 if ((s64)(eid - lif->last_eid) <= 0) 845 return false; 846 847 lif->last_eid = eid; 848 849 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 850 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 851 comp, sizeof(*comp), true); 852 853 switch (le16_to_cpu(comp->event.ecode)) { 854 case IONIC_EVENT_LINK_CHANGE: 855 ionic_link_status_check_request(lif, false); 856 break; 857 case IONIC_EVENT_RESET: 858 work = kzalloc(sizeof(*work), GFP_ATOMIC); 859 if (!work) { 860 netdev_err(lif->netdev, "%s OOM\n", __func__); 861 } else { 862 work->type = IONIC_DW_TYPE_LIF_RESET; 863 ionic_lif_deferred_enqueue(&lif->deferred, work); 864 } 865 break; 866 default: 867 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 868 comp->event.ecode, eid); 869 break; 870 } 871 872 return true; 873} 874 875static bool ionic_adminq_service(struct ionic_cq *cq, 876 struct ionic_cq_info *cq_info) 877{ 878 struct ionic_admin_comp *comp = cq_info->cq_desc; 879 880 if (!color_match(comp->color, cq->done_color)) 881 return false; 882 883 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 884 885 return true; 886} 887 888static int ionic_adminq_napi(struct napi_struct *napi, int budget) 889{ 890 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 891 struct ionic_lif *lif = napi_to_cq(napi)->lif; 892 struct ionic_dev *idev = &lif->ionic->idev; 893 unsigned int flags = 0; 894 int n_work = 0; 895 int a_work = 0; 896 int work_done; 897 898 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 899 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 900 ionic_notifyq_service, NULL, NULL); 901 902 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 903 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 904 ionic_adminq_service, NULL, NULL); 905 906 work_done = max(n_work, a_work); 907 if (work_done < budget && napi_complete_done(napi, work_done)) { 908 flags |= IONIC_INTR_CRED_UNMASK; 909 lif->adminqcq->cq.bound_intr->rearm_count++; 910 } 911 912 if (work_done || flags) { 913 flags |= IONIC_INTR_CRED_RESET_COALESCE; 914 ionic_intr_credits(idev->intr_ctrl, 915 intr->index, 916 n_work + a_work, flags); 917 } 918 919 return work_done; 920} 921 922void ionic_get_stats64(struct net_device *netdev, 923 struct rtnl_link_stats64 *ns) 924{ 925 struct ionic_lif *lif = netdev_priv(netdev); 926 struct ionic_lif_stats *ls; 927 928 memset(ns, 0, sizeof(*ns)); 929 ls = &lif->info->stats; 930 931 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 932 le64_to_cpu(ls->rx_mcast_packets) + 933 le64_to_cpu(ls->rx_bcast_packets); 934 935 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 936 le64_to_cpu(ls->tx_mcast_packets) + 937 le64_to_cpu(ls->tx_bcast_packets); 938 939 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 940 le64_to_cpu(ls->rx_mcast_bytes) + 941 le64_to_cpu(ls->rx_bcast_bytes); 942 943 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 944 le64_to_cpu(ls->tx_mcast_bytes) + 945 le64_to_cpu(ls->tx_bcast_bytes); 946 947 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 948 le64_to_cpu(ls->rx_mcast_drop_packets) + 949 le64_to_cpu(ls->rx_bcast_drop_packets); 950 951 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 952 le64_to_cpu(ls->tx_mcast_drop_packets) + 953 le64_to_cpu(ls->tx_bcast_drop_packets); 954 955 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 956 957 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 958 959 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 960 le64_to_cpu(ls->rx_queue_disabled) + 961 le64_to_cpu(ls->rx_desc_fetch_error) + 962 le64_to_cpu(ls->rx_desc_data_error); 963 964 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 965 le64_to_cpu(ls->tx_queue_disabled) + 966 le64_to_cpu(ls->tx_desc_fetch_error) + 967 le64_to_cpu(ls->tx_desc_data_error); 968 969 ns->rx_errors = ns->rx_over_errors + 970 ns->rx_missed_errors; 971 972 ns->tx_errors = ns->tx_aborted_errors; 973} 974 975static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 976{ 977 struct ionic_admin_ctx ctx = { 978 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 979 .cmd.rx_filter_add = { 980 .opcode = IONIC_CMD_RX_FILTER_ADD, 981 .lif_index = cpu_to_le16(lif->index), 982 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 983 }, 984 }; 985 struct ionic_rx_filter *f; 986 int err; 987 988 /* don't bother if we already have it */ 989 spin_lock_bh(&lif->rx_filters.lock); 990 f = ionic_rx_filter_by_addr(lif, addr); 991 spin_unlock_bh(&lif->rx_filters.lock); 992 if (f) 993 return 0; 994 995 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 996 997 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 998 err = ionic_adminq_post_wait(lif, &ctx); 999 if (err && err != -EEXIST) 1000 return err; 1001 1002 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1003} 1004 1005static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 1006{ 1007 struct ionic_admin_ctx ctx = { 1008 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1009 .cmd.rx_filter_del = { 1010 .opcode = IONIC_CMD_RX_FILTER_DEL, 1011 .lif_index = cpu_to_le16(lif->index), 1012 }, 1013 }; 1014 struct ionic_rx_filter *f; 1015 int err; 1016 1017 spin_lock_bh(&lif->rx_filters.lock); 1018 f = ionic_rx_filter_by_addr(lif, addr); 1019 if (!f) { 1020 spin_unlock_bh(&lif->rx_filters.lock); 1021 return -ENOENT; 1022 } 1023 1024 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 1025 addr, f->filter_id); 1026 1027 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1028 ionic_rx_filter_free(lif, f); 1029 spin_unlock_bh(&lif->rx_filters.lock); 1030 1031 err = ionic_adminq_post_wait(lif, &ctx); 1032 if (err && err != -EEXIST) 1033 return err; 1034 1035 return 0; 1036} 1037 1038static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add, 1039 bool can_sleep) 1040{ 1041 struct ionic_deferred_work *work; 1042 unsigned int nmfilters; 1043 unsigned int nufilters; 1044 1045 if (add) { 1046 /* Do we have space for this filter? We test the counters 1047 * here before checking the need for deferral so that we 1048 * can return an overflow error to the stack. 1049 */ 1050 nmfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters); 1051 nufilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1052 1053 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters)) 1054 lif->nmcast++; 1055 else if (!is_multicast_ether_addr(addr) && 1056 lif->nucast < nufilters) 1057 lif->nucast++; 1058 else 1059 return -ENOSPC; 1060 } else { 1061 if (is_multicast_ether_addr(addr) && lif->nmcast) 1062 lif->nmcast--; 1063 else if (!is_multicast_ether_addr(addr) && lif->nucast) 1064 lif->nucast--; 1065 } 1066 1067 if (!can_sleep) { 1068 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1069 if (!work) { 1070 netdev_err(lif->netdev, "%s OOM\n", __func__); 1071 return -ENOMEM; 1072 } 1073 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD : 1074 IONIC_DW_TYPE_RX_ADDR_DEL; 1075 memcpy(work->addr, addr, ETH_ALEN); 1076 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n", 1077 add ? "add" : "del", addr); 1078 ionic_lif_deferred_enqueue(&lif->deferred, work); 1079 } else { 1080 netdev_dbg(lif->netdev, "rx_filter %s %pM\n", 1081 add ? "add" : "del", addr); 1082 if (add) 1083 return ionic_lif_addr_add(lif, addr); 1084 else 1085 return ionic_lif_addr_del(lif, addr); 1086 } 1087 1088 return 0; 1089} 1090 1091static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1092{ 1093 return ionic_lif_addr(netdev_priv(netdev), addr, true, true); 1094} 1095 1096static int ionic_ndo_addr_add(struct net_device *netdev, const u8 *addr) 1097{ 1098 return ionic_lif_addr(netdev_priv(netdev), addr, true, false); 1099} 1100 1101static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1102{ 1103 /* Don't delete our own address from the uc list */ 1104 if (ether_addr_equal(addr, netdev->dev_addr)) 1105 return 0; 1106 1107 return ionic_lif_addr(netdev_priv(netdev), addr, false, true); 1108} 1109 1110static int ionic_ndo_addr_del(struct net_device *netdev, const u8 *addr) 1111{ 1112 return ionic_lif_addr(netdev_priv(netdev), addr, false, false); 1113} 1114 1115static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1116{ 1117 struct ionic_admin_ctx ctx = { 1118 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1119 .cmd.rx_mode_set = { 1120 .opcode = IONIC_CMD_RX_MODE_SET, 1121 .lif_index = cpu_to_le16(lif->index), 1122 .rx_mode = cpu_to_le16(rx_mode), 1123 }, 1124 }; 1125 char buf[128]; 1126 int err; 1127 int i; 1128#define REMAIN(__x) (sizeof(buf) - (__x)) 1129 1130 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1131 lif->rx_mode, rx_mode); 1132 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1133 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1134 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1135 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1136 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1137 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1138 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1139 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1140 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1141 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1142 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf); 1143 1144 err = ionic_adminq_post_wait(lif, &ctx); 1145 if (err) 1146 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n", 1147 rx_mode, err); 1148 else 1149 lif->rx_mode = rx_mode; 1150} 1151 1152static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep) 1153{ 1154 struct ionic_lif *lif = netdev_priv(netdev); 1155 struct ionic_deferred_work *work; 1156 unsigned int nfilters; 1157 unsigned int rx_mode; 1158 1159 rx_mode = IONIC_RX_MODE_F_UNICAST; 1160 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1161 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1162 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1163 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1164 1165 /* sync unicast addresses 1166 * next check to see if we're in an overflow state 1167 * if so, we track that we overflowed and enable NIC PROMISC 1168 * else if the overflow is set and not needed 1169 * we remove our overflow flag and check the netdev flags 1170 * to see if we can disable NIC PROMISC 1171 */ 1172 if (can_sleep) 1173 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1174 else 1175 __dev_uc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del); 1176 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1177 if (netdev_uc_count(netdev) + 1 > nfilters) { 1178 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1179 lif->uc_overflow = true; 1180 } else if (lif->uc_overflow) { 1181 lif->uc_overflow = false; 1182 if (!(netdev->flags & IFF_PROMISC)) 1183 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1184 } 1185 1186 /* same for multicast */ 1187 if (can_sleep) 1188 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1189 else 1190 __dev_mc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del); 1191 nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters); 1192 if (netdev_mc_count(netdev) > nfilters) { 1193 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1194 lif->mc_overflow = true; 1195 } else if (lif->mc_overflow) { 1196 lif->mc_overflow = false; 1197 if (!(netdev->flags & IFF_ALLMULTI)) 1198 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1199 } 1200 1201 if (lif->rx_mode != rx_mode) { 1202 if (!can_sleep) { 1203 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1204 if (!work) { 1205 netdev_err(lif->netdev, "%s OOM\n", __func__); 1206 return; 1207 } 1208 work->type = IONIC_DW_TYPE_RX_MODE; 1209 work->rx_mode = rx_mode; 1210 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1211 ionic_lif_deferred_enqueue(&lif->deferred, work); 1212 } else { 1213 ionic_lif_rx_mode(lif, rx_mode); 1214 } 1215 } 1216} 1217 1218static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1219{ 1220 ionic_set_rx_mode(netdev, false); 1221} 1222 1223static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1224{ 1225 u64 wanted = 0; 1226 1227 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1228 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1229 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1230 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1231 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1232 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1233 if (features & NETIF_F_RXHASH) 1234 wanted |= IONIC_ETH_HW_RX_HASH; 1235 if (features & NETIF_F_RXCSUM) 1236 wanted |= IONIC_ETH_HW_RX_CSUM; 1237 if (features & NETIF_F_SG) 1238 wanted |= IONIC_ETH_HW_TX_SG; 1239 if (features & NETIF_F_HW_CSUM) 1240 wanted |= IONIC_ETH_HW_TX_CSUM; 1241 if (features & NETIF_F_TSO) 1242 wanted |= IONIC_ETH_HW_TSO; 1243 if (features & NETIF_F_TSO6) 1244 wanted |= IONIC_ETH_HW_TSO_IPV6; 1245 if (features & NETIF_F_TSO_ECN) 1246 wanted |= IONIC_ETH_HW_TSO_ECN; 1247 if (features & NETIF_F_GSO_GRE) 1248 wanted |= IONIC_ETH_HW_TSO_GRE; 1249 if (features & NETIF_F_GSO_GRE_CSUM) 1250 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1251 if (features & NETIF_F_GSO_IPXIP4) 1252 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1253 if (features & NETIF_F_GSO_IPXIP6) 1254 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1255 if (features & NETIF_F_GSO_UDP_TUNNEL) 1256 wanted |= IONIC_ETH_HW_TSO_UDP; 1257 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1258 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1259 1260 return cpu_to_le64(wanted); 1261} 1262 1263static int ionic_set_nic_features(struct ionic_lif *lif, 1264 netdev_features_t features) 1265{ 1266 struct device *dev = lif->ionic->dev; 1267 struct ionic_admin_ctx ctx = { 1268 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1269 .cmd.lif_setattr = { 1270 .opcode = IONIC_CMD_LIF_SETATTR, 1271 .index = cpu_to_le16(lif->index), 1272 .attr = IONIC_LIF_ATTR_FEATURES, 1273 }, 1274 }; 1275 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1276 IONIC_ETH_HW_VLAN_RX_STRIP | 1277 IONIC_ETH_HW_VLAN_RX_FILTER; 1278 u64 old_hw_features; 1279 int err; 1280 1281 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1282 err = ionic_adminq_post_wait(lif, &ctx); 1283 if (err) 1284 return err; 1285 1286 old_hw_features = lif->hw_features; 1287 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1288 ctx.comp.lif_setattr.features); 1289 1290 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1291 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1292 1293 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) && 1294 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1295 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1296 1297 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1298 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1299 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1300 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1301 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1302 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1303 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1304 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1305 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1306 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1307 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1308 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1309 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1310 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1311 if (lif->hw_features & IONIC_ETH_HW_TSO) 1312 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1313 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1314 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1315 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1316 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1317 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1318 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1319 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1320 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1321 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1322 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1323 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1324 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1325 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1326 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1327 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1328 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1329 1330 return 0; 1331} 1332 1333static int ionic_init_nic_features(struct ionic_lif *lif) 1334{ 1335 struct net_device *netdev = lif->netdev; 1336 netdev_features_t features; 1337 int err; 1338 1339 /* set up what we expect to support by default */ 1340 features = NETIF_F_HW_VLAN_CTAG_TX | 1341 NETIF_F_HW_VLAN_CTAG_RX | 1342 NETIF_F_HW_VLAN_CTAG_FILTER | 1343 NETIF_F_RXHASH | 1344 NETIF_F_SG | 1345 NETIF_F_HW_CSUM | 1346 NETIF_F_RXCSUM | 1347 NETIF_F_TSO | 1348 NETIF_F_TSO6 | 1349 NETIF_F_TSO_ECN; 1350 1351 err = ionic_set_nic_features(lif, features); 1352 if (err) 1353 return err; 1354 1355 /* tell the netdev what we actually can support */ 1356 netdev->features |= NETIF_F_HIGHDMA; 1357 1358 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1359 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1360 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1361 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1362 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1363 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1364 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1365 netdev->hw_features |= NETIF_F_RXHASH; 1366 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1367 netdev->hw_features |= NETIF_F_SG; 1368 1369 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1370 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1371 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1372 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1373 if (lif->hw_features & IONIC_ETH_HW_TSO) 1374 netdev->hw_enc_features |= NETIF_F_TSO; 1375 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1376 netdev->hw_enc_features |= NETIF_F_TSO6; 1377 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1378 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1379 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1380 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1381 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1382 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1383 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1384 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1385 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1386 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1387 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1388 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1389 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1390 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1391 1392 netdev->hw_features |= netdev->hw_enc_features; 1393 netdev->features |= netdev->hw_features; 1394 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1395 1396 netdev->priv_flags |= IFF_UNICAST_FLT | 1397 IFF_LIVE_ADDR_CHANGE; 1398 1399 return 0; 1400} 1401 1402static int ionic_set_features(struct net_device *netdev, 1403 netdev_features_t features) 1404{ 1405 struct ionic_lif *lif = netdev_priv(netdev); 1406 int err; 1407 1408 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1409 __func__, (u64)lif->netdev->features, (u64)features); 1410 1411 err = ionic_set_nic_features(lif, features); 1412 1413 return err; 1414} 1415 1416static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1417{ 1418 struct sockaddr *addr = sa; 1419 u8 *mac; 1420 int err; 1421 1422 mac = (u8 *)addr->sa_data; 1423 if (ether_addr_equal(netdev->dev_addr, mac)) 1424 return 0; 1425 1426 err = eth_prepare_mac_addr_change(netdev, addr); 1427 if (err) 1428 return err; 1429 1430 if (!is_zero_ether_addr(netdev->dev_addr)) { 1431 netdev_info(netdev, "deleting mac addr %pM\n", 1432 netdev->dev_addr); 1433 ionic_addr_del(netdev, netdev->dev_addr); 1434 } 1435 1436 eth_commit_mac_addr_change(netdev, addr); 1437 netdev_info(netdev, "updating mac addr %pM\n", mac); 1438 1439 return ionic_addr_add(netdev, mac); 1440} 1441 1442static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1443{ 1444 /* Stop and clean the queues before reconfiguration */ 1445 mutex_lock(&lif->queue_lock); 1446 netif_device_detach(lif->netdev); 1447 ionic_stop_queues(lif); 1448 ionic_txrx_deinit(lif); 1449} 1450 1451static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1452{ 1453 int err; 1454 1455 /* Re-init the queues after reconfiguration */ 1456 1457 /* The only way txrx_init can fail here is if communication 1458 * with FW is suddenly broken. There's not much we can do 1459 * at this point - error messages have already been printed, 1460 * so we can continue on and the user can eventually do a 1461 * DOWN and UP to try to reset and clear the issue. 1462 */ 1463 err = ionic_txrx_init(lif); 1464 mutex_unlock(&lif->queue_lock); 1465 ionic_link_status_check_request(lif, true); 1466 netif_device_attach(lif->netdev); 1467 1468 return err; 1469} 1470 1471static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1472{ 1473 struct ionic_lif *lif = netdev_priv(netdev); 1474 struct ionic_admin_ctx ctx = { 1475 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1476 .cmd.lif_setattr = { 1477 .opcode = IONIC_CMD_LIF_SETATTR, 1478 .index = cpu_to_le16(lif->index), 1479 .attr = IONIC_LIF_ATTR_MTU, 1480 .mtu = cpu_to_le32(new_mtu), 1481 }, 1482 }; 1483 int err; 1484 1485 err = ionic_adminq_post_wait(lif, &ctx); 1486 if (err) 1487 return err; 1488 1489 netdev->mtu = new_mtu; 1490 /* if we're not running, nothing more to do */ 1491 if (!netif_running(netdev)) 1492 return 0; 1493 1494 ionic_stop_queues_reconfig(lif); 1495 return ionic_start_queues_reconfig(lif); 1496} 1497 1498static void ionic_tx_timeout_work(struct work_struct *ws) 1499{ 1500 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1501 1502 netdev_info(lif->netdev, "Tx Timeout recovery\n"); 1503 1504 /* if we were stopped before this scheduled job was launched, 1505 * don't bother the queues as they are already stopped. 1506 */ 1507 if (!netif_running(lif->netdev)) 1508 return; 1509 1510 ionic_stop_queues_reconfig(lif); 1511 ionic_start_queues_reconfig(lif); 1512} 1513 1514static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1515{ 1516 struct ionic_lif *lif = netdev_priv(netdev); 1517 1518 schedule_work(&lif->tx_timeout_work); 1519} 1520 1521static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1522 u16 vid) 1523{ 1524 struct ionic_lif *lif = netdev_priv(netdev); 1525 struct ionic_admin_ctx ctx = { 1526 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1527 .cmd.rx_filter_add = { 1528 .opcode = IONIC_CMD_RX_FILTER_ADD, 1529 .lif_index = cpu_to_le16(lif->index), 1530 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1531 .vlan.vlan = cpu_to_le16(vid), 1532 }, 1533 }; 1534 int err; 1535 1536 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1537 err = ionic_adminq_post_wait(lif, &ctx); 1538 if (err) 1539 return err; 1540 1541 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1542} 1543 1544static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1545 u16 vid) 1546{ 1547 struct ionic_lif *lif = netdev_priv(netdev); 1548 struct ionic_admin_ctx ctx = { 1549 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1550 .cmd.rx_filter_del = { 1551 .opcode = IONIC_CMD_RX_FILTER_DEL, 1552 .lif_index = cpu_to_le16(lif->index), 1553 }, 1554 }; 1555 struct ionic_rx_filter *f; 1556 1557 spin_lock_bh(&lif->rx_filters.lock); 1558 1559 f = ionic_rx_filter_by_vlan(lif, vid); 1560 if (!f) { 1561 spin_unlock_bh(&lif->rx_filters.lock); 1562 return -ENOENT; 1563 } 1564 1565 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1566 vid, f->filter_id); 1567 1568 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1569 ionic_rx_filter_free(lif, f); 1570 spin_unlock_bh(&lif->rx_filters.lock); 1571 1572 return ionic_adminq_post_wait(lif, &ctx); 1573} 1574 1575int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1576 const u8 *key, const u32 *indir) 1577{ 1578 struct ionic_admin_ctx ctx = { 1579 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1580 .cmd.lif_setattr = { 1581 .opcode = IONIC_CMD_LIF_SETATTR, 1582 .attr = IONIC_LIF_ATTR_RSS, 1583 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1584 }, 1585 }; 1586 unsigned int i, tbl_sz; 1587 1588 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1589 lif->rss_types = types; 1590 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1591 } 1592 1593 if (key) 1594 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1595 1596 if (indir) { 1597 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1598 for (i = 0; i < tbl_sz; i++) 1599 lif->rss_ind_tbl[i] = indir[i]; 1600 } 1601 1602 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1603 IONIC_RSS_HASH_KEY_SIZE); 1604 1605 return ionic_adminq_post_wait(lif, &ctx); 1606} 1607 1608static int ionic_lif_rss_init(struct ionic_lif *lif) 1609{ 1610 unsigned int tbl_sz; 1611 unsigned int i; 1612 1613 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1614 IONIC_RSS_TYPE_IPV4_TCP | 1615 IONIC_RSS_TYPE_IPV4_UDP | 1616 IONIC_RSS_TYPE_IPV6 | 1617 IONIC_RSS_TYPE_IPV6_TCP | 1618 IONIC_RSS_TYPE_IPV6_UDP; 1619 1620 /* Fill indirection table with 'default' values */ 1621 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1622 for (i = 0; i < tbl_sz; i++) 1623 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1624 1625 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1626} 1627 1628static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1629{ 1630 int tbl_sz; 1631 1632 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1633 memset(lif->rss_ind_tbl, 0, tbl_sz); 1634 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1635 1636 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1637} 1638 1639static void ionic_txrx_disable(struct ionic_lif *lif) 1640{ 1641 unsigned int i; 1642 int err = 0; 1643 1644 if (lif->txqcqs) { 1645 for (i = 0; i < lif->nxqs; i++) 1646 err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT)); 1647 } 1648 1649 if (lif->rxqcqs) { 1650 for (i = 0; i < lif->nxqs; i++) 1651 err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 1652 } 1653} 1654 1655static void ionic_txrx_deinit(struct ionic_lif *lif) 1656{ 1657 unsigned int i; 1658 1659 if (lif->txqcqs) { 1660 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1661 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1662 ionic_tx_flush(&lif->txqcqs[i]->cq); 1663 ionic_tx_empty(&lif->txqcqs[i]->q); 1664 } 1665 } 1666 1667 if (lif->rxqcqs) { 1668 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1669 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1670 ionic_rx_empty(&lif->rxqcqs[i]->q); 1671 } 1672 } 1673 lif->rx_mode = 0; 1674} 1675 1676static void ionic_txrx_free(struct ionic_lif *lif) 1677{ 1678 unsigned int i; 1679 1680 if (lif->txqcqs) { 1681 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1682 ionic_qcq_free(lif, lif->txqcqs[i]); 1683 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1684 lif->txqcqs[i] = NULL; 1685 } 1686 } 1687 1688 if (lif->rxqcqs) { 1689 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1690 ionic_qcq_free(lif, lif->rxqcqs[i]); 1691 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1692 lif->rxqcqs[i] = NULL; 1693 } 1694 } 1695} 1696 1697static int ionic_txrx_alloc(struct ionic_lif *lif) 1698{ 1699 unsigned int sg_desc_sz; 1700 unsigned int flags; 1701 unsigned int i; 1702 int err = 0; 1703 1704 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1705 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1706 sizeof(struct ionic_txq_sg_desc_v1)) 1707 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1708 else 1709 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1710 1711 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1712 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1713 flags |= IONIC_QCQ_F_INTR; 1714 for (i = 0; i < lif->nxqs; i++) { 1715 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1716 lif->ntxq_descs, 1717 sizeof(struct ionic_txq_desc), 1718 sizeof(struct ionic_txq_comp), 1719 sg_desc_sz, 1720 lif->kern_pid, &lif->txqcqs[i]); 1721 if (err) 1722 goto err_out; 1723 1724 if (flags & IONIC_QCQ_F_INTR) { 1725 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1726 lif->txqcqs[i]->intr.index, 1727 lif->tx_coalesce_hw); 1728 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 1729 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 1730 } 1731 1732 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1733 } 1734 1735 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1736 for (i = 0; i < lif->nxqs; i++) { 1737 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1738 lif->nrxq_descs, 1739 sizeof(struct ionic_rxq_desc), 1740 sizeof(struct ionic_rxq_comp), 1741 sizeof(struct ionic_rxq_sg_desc), 1742 lif->kern_pid, &lif->rxqcqs[i]); 1743 if (err) 1744 goto err_out; 1745 1746 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1747 lif->rxqcqs[i]->intr.index, 1748 lif->rx_coalesce_hw); 1749 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 1750 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 1751 1752 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1753 ionic_link_qcq_interrupts(lif->rxqcqs[i], 1754 lif->txqcqs[i]); 1755 1756 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 1757 } 1758 1759 return 0; 1760 1761err_out: 1762 ionic_txrx_free(lif); 1763 1764 return err; 1765} 1766 1767static int ionic_txrx_init(struct ionic_lif *lif) 1768{ 1769 unsigned int i; 1770 int err; 1771 1772 for (i = 0; i < lif->nxqs; i++) { 1773 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 1774 if (err) 1775 goto err_out; 1776 1777 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 1778 if (err) { 1779 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1780 goto err_out; 1781 } 1782 } 1783 1784 if (lif->netdev->features & NETIF_F_RXHASH) 1785 ionic_lif_rss_init(lif); 1786 1787 ionic_set_rx_mode(lif->netdev, true); 1788 1789 return 0; 1790 1791err_out: 1792 while (i--) { 1793 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1794 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1795 } 1796 1797 return err; 1798} 1799 1800static int ionic_txrx_enable(struct ionic_lif *lif) 1801{ 1802 int derr = 0; 1803 int i, err; 1804 1805 for (i = 0; i < lif->nxqs; i++) { 1806 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 1807 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 1808 err = -ENXIO; 1809 goto err_out; 1810 } 1811 1812 ionic_rx_fill(&lif->rxqcqs[i]->q); 1813 err = ionic_qcq_enable(lif->rxqcqs[i]); 1814 if (err) 1815 goto err_out; 1816 1817 err = ionic_qcq_enable(lif->txqcqs[i]); 1818 if (err) { 1819 derr = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 1820 goto err_out; 1821 } 1822 } 1823 1824 return 0; 1825 1826err_out: 1827 while (i--) { 1828 derr = ionic_qcq_disable(lif->txqcqs[i], (derr != -ETIMEDOUT)); 1829 derr = ionic_qcq_disable(lif->rxqcqs[i], (derr != -ETIMEDOUT)); 1830 } 1831 1832 return err; 1833} 1834 1835static int ionic_start_queues(struct ionic_lif *lif) 1836{ 1837 int err; 1838 1839 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 1840 return 0; 1841 1842 err = ionic_txrx_enable(lif); 1843 if (err) { 1844 clear_bit(IONIC_LIF_F_UP, lif->state); 1845 return err; 1846 } 1847 netif_tx_wake_all_queues(lif->netdev); 1848 1849 return 0; 1850} 1851 1852static int ionic_open(struct net_device *netdev) 1853{ 1854 struct ionic_lif *lif = netdev_priv(netdev); 1855 int err; 1856 1857 err = ionic_txrx_alloc(lif); 1858 if (err) 1859 return err; 1860 1861 err = ionic_txrx_init(lif); 1862 if (err) 1863 goto err_out; 1864 1865 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 1866 if (err) 1867 goto err_txrx_deinit; 1868 1869 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 1870 if (err) 1871 goto err_txrx_deinit; 1872 1873 /* don't start the queues until we have link */ 1874 if (netif_carrier_ok(netdev)) { 1875 err = ionic_start_queues(lif); 1876 if (err) 1877 goto err_txrx_deinit; 1878 } 1879 1880 return 0; 1881 1882err_txrx_deinit: 1883 ionic_txrx_deinit(lif); 1884err_out: 1885 ionic_txrx_free(lif); 1886 return err; 1887} 1888 1889static void ionic_stop_queues(struct ionic_lif *lif) 1890{ 1891 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 1892 return; 1893 1894 netif_tx_disable(lif->netdev); 1895 ionic_txrx_disable(lif); 1896} 1897 1898static int ionic_stop(struct net_device *netdev) 1899{ 1900 struct ionic_lif *lif = netdev_priv(netdev); 1901 1902 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1903 return 0; 1904 1905 ionic_stop_queues(lif); 1906 ionic_txrx_deinit(lif); 1907 ionic_txrx_free(lif); 1908 1909 return 0; 1910} 1911 1912static int ionic_get_vf_config(struct net_device *netdev, 1913 int vf, struct ifla_vf_info *ivf) 1914{ 1915 struct ionic_lif *lif = netdev_priv(netdev); 1916 struct ionic *ionic = lif->ionic; 1917 int ret = 0; 1918 1919 if (!netif_device_present(netdev)) 1920 return -EBUSY; 1921 1922 down_read(&ionic->vf_op_lock); 1923 1924 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1925 ret = -EINVAL; 1926 } else { 1927 ivf->vf = vf; 1928 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 1929 ivf->qos = 0; 1930 ivf->spoofchk = ionic->vfs[vf].spoofchk; 1931 ivf->linkstate = ionic->vfs[vf].linkstate; 1932 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 1933 ivf->trusted = ionic->vfs[vf].trusted; 1934 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 1935 } 1936 1937 up_read(&ionic->vf_op_lock); 1938 return ret; 1939} 1940 1941static int ionic_get_vf_stats(struct net_device *netdev, int vf, 1942 struct ifla_vf_stats *vf_stats) 1943{ 1944 struct ionic_lif *lif = netdev_priv(netdev); 1945 struct ionic *ionic = lif->ionic; 1946 struct ionic_lif_stats *vs; 1947 int ret = 0; 1948 1949 if (!netif_device_present(netdev)) 1950 return -EBUSY; 1951 1952 down_read(&ionic->vf_op_lock); 1953 1954 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1955 ret = -EINVAL; 1956 } else { 1957 memset(vf_stats, 0, sizeof(*vf_stats)); 1958 vs = &ionic->vfs[vf].stats; 1959 1960 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 1961 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 1962 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 1963 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 1964 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 1965 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 1966 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 1967 le64_to_cpu(vs->rx_mcast_drop_packets) + 1968 le64_to_cpu(vs->rx_bcast_drop_packets); 1969 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 1970 le64_to_cpu(vs->tx_mcast_drop_packets) + 1971 le64_to_cpu(vs->tx_bcast_drop_packets); 1972 } 1973 1974 up_read(&ionic->vf_op_lock); 1975 return ret; 1976} 1977 1978static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1979{ 1980 struct ionic_lif *lif = netdev_priv(netdev); 1981 struct ionic *ionic = lif->ionic; 1982 int ret; 1983 1984 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 1985 return -EINVAL; 1986 1987 if (!netif_device_present(netdev)) 1988 return -EBUSY; 1989 1990 down_write(&ionic->vf_op_lock); 1991 1992 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1993 ret = -EINVAL; 1994 } else { 1995 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 1996 if (!ret) 1997 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 1998 } 1999 2000 up_write(&ionic->vf_op_lock); 2001 return ret; 2002} 2003 2004static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2005 u8 qos, __be16 proto) 2006{ 2007 struct ionic_lif *lif = netdev_priv(netdev); 2008 struct ionic *ionic = lif->ionic; 2009 int ret; 2010 2011 /* until someday when we support qos */ 2012 if (qos) 2013 return -EINVAL; 2014 2015 if (vlan > 4095) 2016 return -EINVAL; 2017 2018 if (proto != htons(ETH_P_8021Q)) 2019 return -EPROTONOSUPPORT; 2020 2021 if (!netif_device_present(netdev)) 2022 return -EBUSY; 2023 2024 down_write(&ionic->vf_op_lock); 2025 2026 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2027 ret = -EINVAL; 2028 } else { 2029 ret = ionic_set_vf_config(ionic, vf, 2030 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2031 if (!ret) 2032 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2033 } 2034 2035 up_write(&ionic->vf_op_lock); 2036 return ret; 2037} 2038 2039static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2040 int tx_min, int tx_max) 2041{ 2042 struct ionic_lif *lif = netdev_priv(netdev); 2043 struct ionic *ionic = lif->ionic; 2044 int ret; 2045 2046 /* setting the min just seems silly */ 2047 if (tx_min) 2048 return -EINVAL; 2049 2050 if (!netif_device_present(netdev)) 2051 return -EBUSY; 2052 2053 down_write(&ionic->vf_op_lock); 2054 2055 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2056 ret = -EINVAL; 2057 } else { 2058 ret = ionic_set_vf_config(ionic, vf, 2059 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2060 if (!ret) 2061 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2062 } 2063 2064 up_write(&ionic->vf_op_lock); 2065 return ret; 2066} 2067 2068static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2069{ 2070 struct ionic_lif *lif = netdev_priv(netdev); 2071 struct ionic *ionic = lif->ionic; 2072 u8 data = set; /* convert to u8 for config */ 2073 int ret; 2074 2075 if (!netif_device_present(netdev)) 2076 return -EBUSY; 2077 2078 down_write(&ionic->vf_op_lock); 2079 2080 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2081 ret = -EINVAL; 2082 } else { 2083 ret = ionic_set_vf_config(ionic, vf, 2084 IONIC_VF_ATTR_SPOOFCHK, &data); 2085 if (!ret) 2086 ionic->vfs[vf].spoofchk = data; 2087 } 2088 2089 up_write(&ionic->vf_op_lock); 2090 return ret; 2091} 2092 2093static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2094{ 2095 struct ionic_lif *lif = netdev_priv(netdev); 2096 struct ionic *ionic = lif->ionic; 2097 u8 data = set; /* convert to u8 for config */ 2098 int ret; 2099 2100 if (!netif_device_present(netdev)) 2101 return -EBUSY; 2102 2103 down_write(&ionic->vf_op_lock); 2104 2105 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2106 ret = -EINVAL; 2107 } else { 2108 ret = ionic_set_vf_config(ionic, vf, 2109 IONIC_VF_ATTR_TRUST, &data); 2110 if (!ret) 2111 ionic->vfs[vf].trusted = data; 2112 } 2113 2114 up_write(&ionic->vf_op_lock); 2115 return ret; 2116} 2117 2118static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2119{ 2120 struct ionic_lif *lif = netdev_priv(netdev); 2121 struct ionic *ionic = lif->ionic; 2122 u8 data; 2123 int ret; 2124 2125 switch (set) { 2126 case IFLA_VF_LINK_STATE_ENABLE: 2127 data = IONIC_VF_LINK_STATUS_UP; 2128 break; 2129 case IFLA_VF_LINK_STATE_DISABLE: 2130 data = IONIC_VF_LINK_STATUS_DOWN; 2131 break; 2132 case IFLA_VF_LINK_STATE_AUTO: 2133 data = IONIC_VF_LINK_STATUS_AUTO; 2134 break; 2135 default: 2136 return -EINVAL; 2137 } 2138 2139 if (!netif_device_present(netdev)) 2140 return -EBUSY; 2141 2142 down_write(&ionic->vf_op_lock); 2143 2144 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2145 ret = -EINVAL; 2146 } else { 2147 ret = ionic_set_vf_config(ionic, vf, 2148 IONIC_VF_ATTR_LINKSTATE, &data); 2149 if (!ret) 2150 ionic->vfs[vf].linkstate = set; 2151 } 2152 2153 up_write(&ionic->vf_op_lock); 2154 return ret; 2155} 2156 2157static const struct net_device_ops ionic_netdev_ops = { 2158 .ndo_open = ionic_open, 2159 .ndo_stop = ionic_stop, 2160 .ndo_start_xmit = ionic_start_xmit, 2161 .ndo_get_stats64 = ionic_get_stats64, 2162 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2163 .ndo_set_features = ionic_set_features, 2164 .ndo_set_mac_address = ionic_set_mac_address, 2165 .ndo_validate_addr = eth_validate_addr, 2166 .ndo_tx_timeout = ionic_tx_timeout, 2167 .ndo_change_mtu = ionic_change_mtu, 2168 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2169 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2170 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2171 .ndo_set_vf_trust = ionic_set_vf_trust, 2172 .ndo_set_vf_mac = ionic_set_vf_mac, 2173 .ndo_set_vf_rate = ionic_set_vf_rate, 2174 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2175 .ndo_get_vf_config = ionic_get_vf_config, 2176 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2177 .ndo_get_vf_stats = ionic_get_vf_stats, 2178}; 2179 2180static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2181{ 2182 /* only swapping the queues, not the napi, flags, or other stuff */ 2183 swap(a->q.num_descs, b->q.num_descs); 2184 swap(a->q.base, b->q.base); 2185 swap(a->q.base_pa, b->q.base_pa); 2186 swap(a->q.info, b->q.info); 2187 swap(a->q_base, b->q_base); 2188 swap(a->q_base_pa, b->q_base_pa); 2189 swap(a->q_size, b->q_size); 2190 2191 swap(a->q.sg_base, b->q.sg_base); 2192 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2193 swap(a->sg_base, b->sg_base); 2194 swap(a->sg_base_pa, b->sg_base_pa); 2195 swap(a->sg_size, b->sg_size); 2196 2197 swap(a->cq.num_descs, b->cq.num_descs); 2198 swap(a->cq.base, b->cq.base); 2199 swap(a->cq.base_pa, b->cq.base_pa); 2200 swap(a->cq.info, b->cq.info); 2201 swap(a->cq_base, b->cq_base); 2202 swap(a->cq_base_pa, b->cq_base_pa); 2203 swap(a->cq_size, b->cq_size); 2204} 2205 2206int ionic_reconfigure_queues(struct ionic_lif *lif, 2207 struct ionic_queue_params *qparam) 2208{ 2209 struct ionic_qcq **tx_qcqs = NULL; 2210 struct ionic_qcq **rx_qcqs = NULL; 2211 unsigned int sg_desc_sz; 2212 unsigned int flags; 2213 int err = -ENOMEM; 2214 unsigned int i; 2215 2216 /* allocate temporary qcq arrays to hold new queue structs */ 2217 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2218 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2219 sizeof(struct ionic_qcq *), GFP_KERNEL); 2220 if (!tx_qcqs) 2221 goto err_out; 2222 } 2223 if (qparam->nxqs != lif->nxqs || qparam->nrxq_descs != lif->nrxq_descs) { 2224 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2225 sizeof(struct ionic_qcq *), GFP_KERNEL); 2226 if (!rx_qcqs) 2227 goto err_out; 2228 } 2229 2230 /* allocate new desc_info and rings, but leave the interrupt setup 2231 * until later so as to not mess with the still-running queues 2232 */ 2233 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2234 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2235 sizeof(struct ionic_txq_sg_desc_v1)) 2236 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2237 else 2238 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2239 2240 if (tx_qcqs) { 2241 for (i = 0; i < qparam->nxqs; i++) { 2242 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2243 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2244 qparam->ntxq_descs, 2245 sizeof(struct ionic_txq_desc), 2246 sizeof(struct ionic_txq_comp), 2247 sg_desc_sz, 2248 lif->kern_pid, &tx_qcqs[i]); 2249 if (err) 2250 goto err_out; 2251 } 2252 } 2253 2254 if (rx_qcqs) { 2255 for (i = 0; i < qparam->nxqs; i++) { 2256 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2257 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2258 qparam->nrxq_descs, 2259 sizeof(struct ionic_rxq_desc), 2260 sizeof(struct ionic_rxq_comp), 2261 sizeof(struct ionic_rxq_sg_desc), 2262 lif->kern_pid, &rx_qcqs[i]); 2263 if (err) 2264 goto err_out; 2265 } 2266 } 2267 2268 /* stop and clean the queues */ 2269 ionic_stop_queues_reconfig(lif); 2270 2271 if (qparam->nxqs != lif->nxqs) { 2272 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2273 if (err) 2274 goto err_out_reinit_unlock; 2275 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2276 if (err) { 2277 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2278 goto err_out_reinit_unlock; 2279 } 2280 } 2281 2282 /* swap new desc_info and rings, keeping existing interrupt config */ 2283 if (tx_qcqs) { 2284 lif->ntxq_descs = qparam->ntxq_descs; 2285 for (i = 0; i < qparam->nxqs; i++) 2286 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2287 } 2288 2289 if (rx_qcqs) { 2290 lif->nrxq_descs = qparam->nrxq_descs; 2291 for (i = 0; i < qparam->nxqs; i++) 2292 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2293 } 2294 2295 /* if we need to change the interrupt layout, this is the time */ 2296 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2297 qparam->nxqs != lif->nxqs) { 2298 if (qparam->intr_split) { 2299 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2300 } else { 2301 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2302 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2303 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2304 } 2305 2306 /* clear existing interrupt assignments */ 2307 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2308 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2309 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2310 } 2311 2312 /* re-assign the interrupts */ 2313 for (i = 0; i < qparam->nxqs; i++) { 2314 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2315 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2316 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2317 lif->rxqcqs[i]->intr.index, 2318 lif->rx_coalesce_hw); 2319 2320 if (qparam->intr_split) { 2321 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2322 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2323 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2324 lif->txqcqs[i]->intr.index, 2325 lif->tx_coalesce_hw); 2326 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2327 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2328 } else { 2329 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2330 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2331 } 2332 } 2333 } 2334 2335 /* now we can rework the debugfs mappings */ 2336 if (tx_qcqs) { 2337 for (i = 0; i < qparam->nxqs; i++) { 2338 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2339 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2340 } 2341 } 2342 2343 if (rx_qcqs) { 2344 for (i = 0; i < qparam->nxqs; i++) { 2345 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2346 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2347 } 2348 } 2349 2350 swap(lif->nxqs, qparam->nxqs); 2351 2352err_out_reinit_unlock: 2353 /* re-init the queues, but don't loose an error code */ 2354 if (err) 2355 ionic_start_queues_reconfig(lif); 2356 else 2357 err = ionic_start_queues_reconfig(lif); 2358 2359err_out: 2360 /* free old allocs without cleaning intr */ 2361 for (i = 0; i < qparam->nxqs; i++) { 2362 if (tx_qcqs && tx_qcqs[i]) { 2363 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2364 ionic_qcq_free(lif, tx_qcqs[i]); 2365 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2366 tx_qcqs[i] = NULL; 2367 } 2368 if (rx_qcqs && rx_qcqs[i]) { 2369 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2370 ionic_qcq_free(lif, rx_qcqs[i]); 2371 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2372 rx_qcqs[i] = NULL; 2373 } 2374 } 2375 2376 /* free q array */ 2377 if (rx_qcqs) { 2378 devm_kfree(lif->ionic->dev, rx_qcqs); 2379 rx_qcqs = NULL; 2380 } 2381 if (tx_qcqs) { 2382 devm_kfree(lif->ionic->dev, tx_qcqs); 2383 tx_qcqs = NULL; 2384 } 2385 2386 /* clean the unused dma and info allocations when new set is smaller 2387 * than the full array, but leave the qcq shells in place 2388 */ 2389 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2390 if (lif->txqcqs && lif->txqcqs[i]) { 2391 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2392 ionic_qcq_free(lif, lif->txqcqs[i]); 2393 } 2394 2395 if (lif->rxqcqs && lif->rxqcqs[i]) { 2396 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2397 ionic_qcq_free(lif, lif->rxqcqs[i]); 2398 } 2399 } 2400 2401 return err; 2402} 2403 2404int ionic_lif_alloc(struct ionic *ionic) 2405{ 2406 struct device *dev = ionic->dev; 2407 union ionic_lif_identity *lid; 2408 struct net_device *netdev; 2409 struct ionic_lif *lif; 2410 int tbl_sz; 2411 int err; 2412 2413 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2414 if (!lid) 2415 return -ENOMEM; 2416 2417 netdev = alloc_etherdev_mqs(sizeof(*lif), 2418 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2419 if (!netdev) { 2420 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2421 err = -ENOMEM; 2422 goto err_out_free_lid; 2423 } 2424 2425 SET_NETDEV_DEV(netdev, dev); 2426 2427 lif = netdev_priv(netdev); 2428 lif->netdev = netdev; 2429 ionic->lif = lif; 2430 netdev->netdev_ops = &ionic_netdev_ops; 2431 ionic_ethtool_set_ops(netdev); 2432 2433 netdev->watchdog_timeo = 2 * HZ; 2434 netif_carrier_off(netdev); 2435 2436 lif->identity = lid; 2437 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2438 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2439 if (err) { 2440 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2441 lif->lif_type, err); 2442 goto err_out_free_netdev; 2443 } 2444 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2445 le32_to_cpu(lif->identity->eth.min_frame_size)); 2446 lif->netdev->max_mtu = 2447 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2448 2449 lif->neqs = ionic->neqs_per_lif; 2450 lif->nxqs = ionic->ntxqs_per_lif; 2451 2452 lif->ionic = ionic; 2453 lif->index = 0; 2454 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2455 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2456 lif->tx_budget = IONIC_TX_BUDGET_DEFAULT; 2457 2458 /* Convert the default coalesce value to actual hw resolution */ 2459 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2460 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2461 lif->rx_coalesce_usecs); 2462 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2463 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2464 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2465 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2466 2467 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2468 2469 spin_lock_init(&lif->adminq_lock); 2470 2471 spin_lock_init(&lif->deferred.lock); 2472 INIT_LIST_HEAD(&lif->deferred.list); 2473 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2474 2475 /* allocate lif info */ 2476 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2477 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2478 &lif->info_pa, GFP_KERNEL); 2479 if (!lif->info) { 2480 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2481 err = -ENOMEM; 2482 goto err_out_free_netdev; 2483 } 2484 2485 ionic_debugfs_add_lif(lif); 2486 2487 /* allocate control queues and txrx queue arrays */ 2488 ionic_lif_queue_identify(lif); 2489 err = ionic_qcqs_alloc(lif); 2490 if (err) 2491 goto err_out_free_lif_info; 2492 2493 /* allocate rss indirection table */ 2494 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2495 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2496 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2497 &lif->rss_ind_tbl_pa, 2498 GFP_KERNEL); 2499 2500 if (!lif->rss_ind_tbl) { 2501 err = -ENOMEM; 2502 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2503 goto err_out_free_qcqs; 2504 } 2505 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2506 2507 return 0; 2508 2509err_out_free_qcqs: 2510 ionic_qcqs_free(lif); 2511err_out_free_lif_info: 2512 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2513 lif->info = NULL; 2514 lif->info_pa = 0; 2515err_out_free_netdev: 2516 free_netdev(lif->netdev); 2517 lif = NULL; 2518err_out_free_lid: 2519 kfree(lid); 2520 2521 return err; 2522} 2523 2524static void ionic_lif_reset(struct ionic_lif *lif) 2525{ 2526 struct ionic_dev *idev = &lif->ionic->idev; 2527 2528 mutex_lock(&lif->ionic->dev_cmd_lock); 2529 ionic_dev_cmd_lif_reset(idev, lif->index); 2530 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2531 mutex_unlock(&lif->ionic->dev_cmd_lock); 2532} 2533 2534static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2535{ 2536 struct ionic *ionic = lif->ionic; 2537 2538 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2539 return; 2540 2541 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2542 2543 netif_device_detach(lif->netdev); 2544 2545 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2546 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2547 mutex_lock(&lif->queue_lock); 2548 ionic_stop_queues(lif); 2549 mutex_unlock(&lif->queue_lock); 2550 } 2551 2552 if (netif_running(lif->netdev)) { 2553 ionic_txrx_deinit(lif); 2554 ionic_txrx_free(lif); 2555 } 2556 ionic_lif_deinit(lif); 2557 ionic_reset(ionic); 2558 ionic_qcqs_free(lif); 2559 2560 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2561} 2562 2563static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2564{ 2565 struct ionic *ionic = lif->ionic; 2566 int err; 2567 2568 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2569 return; 2570 2571 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2572 2573 ionic_init_devinfo(ionic); 2574 err = ionic_identify(ionic); 2575 if (err) 2576 goto err_out; 2577 err = ionic_port_identify(ionic); 2578 if (err) 2579 goto err_out; 2580 err = ionic_port_init(ionic); 2581 if (err) 2582 goto err_out; 2583 err = ionic_qcqs_alloc(lif); 2584 if (err) 2585 goto err_out; 2586 2587 err = ionic_lif_init(lif); 2588 if (err) 2589 goto err_qcqs_free; 2590 2591 if (lif->registered) 2592 ionic_lif_set_netdev_info(lif); 2593 2594 ionic_rx_filter_replay(lif); 2595 2596 if (netif_running(lif->netdev)) { 2597 err = ionic_txrx_alloc(lif); 2598 if (err) 2599 goto err_lifs_deinit; 2600 2601 err = ionic_txrx_init(lif); 2602 if (err) 2603 goto err_txrx_free; 2604 } 2605 2606 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2607 ionic_link_status_check_request(lif, true); 2608 netif_device_attach(lif->netdev); 2609 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2610 2611 return; 2612 2613err_txrx_free: 2614 ionic_txrx_free(lif); 2615err_lifs_deinit: 2616 ionic_lif_deinit(lif); 2617err_qcqs_free: 2618 ionic_qcqs_free(lif); 2619err_out: 2620 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2621} 2622 2623void ionic_lif_free(struct ionic_lif *lif) 2624{ 2625 struct device *dev = lif->ionic->dev; 2626 2627 /* free rss indirection table */ 2628 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2629 lif->rss_ind_tbl_pa); 2630 lif->rss_ind_tbl = NULL; 2631 lif->rss_ind_tbl_pa = 0; 2632 2633 /* free queues */ 2634 ionic_qcqs_free(lif); 2635 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2636 ionic_lif_reset(lif); 2637 2638 /* free lif info */ 2639 kfree(lif->identity); 2640 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2641 lif->info = NULL; 2642 lif->info_pa = 0; 2643 2644 /* unmap doorbell page */ 2645 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2646 lif->kern_dbpage = NULL; 2647 kfree(lif->dbid_inuse); 2648 lif->dbid_inuse = NULL; 2649 2650 /* free netdev & lif */ 2651 ionic_debugfs_del_lif(lif); 2652 free_netdev(lif->netdev); 2653} 2654 2655void ionic_lif_deinit(struct ionic_lif *lif) 2656{ 2657 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2658 return; 2659 2660 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2661 cancel_work_sync(&lif->deferred.work); 2662 cancel_work_sync(&lif->tx_timeout_work); 2663 ionic_rx_filters_deinit(lif); 2664 if (lif->netdev->features & NETIF_F_RXHASH) 2665 ionic_lif_rss_deinit(lif); 2666 } 2667 2668 napi_disable(&lif->adminqcq->napi); 2669 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2670 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2671 2672 mutex_destroy(&lif->queue_lock); 2673 ionic_lif_reset(lif); 2674} 2675 2676static int ionic_lif_adminq_init(struct ionic_lif *lif) 2677{ 2678 struct device *dev = lif->ionic->dev; 2679 struct ionic_q_init_comp comp; 2680 struct ionic_dev *idev; 2681 struct ionic_qcq *qcq; 2682 struct ionic_queue *q; 2683 int err; 2684 2685 idev = &lif->ionic->idev; 2686 qcq = lif->adminqcq; 2687 q = &qcq->q; 2688 2689 mutex_lock(&lif->ionic->dev_cmd_lock); 2690 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2691 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2692 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2693 mutex_unlock(&lif->ionic->dev_cmd_lock); 2694 if (err) { 2695 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2696 return err; 2697 } 2698 2699 q->hw_type = comp.hw_type; 2700 q->hw_index = le32_to_cpu(comp.hw_index); 2701 q->dbval = IONIC_DBELL_QID(q->hw_index); 2702 2703 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2704 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2705 2706 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2707 NAPI_POLL_WEIGHT); 2708 2709 napi_enable(&qcq->napi); 2710 2711 if (qcq->flags & IONIC_QCQ_F_INTR) 2712 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 2713 IONIC_INTR_MASK_CLEAR); 2714 2715 qcq->flags |= IONIC_QCQ_F_INITED; 2716 2717 return 0; 2718} 2719 2720static int ionic_lif_notifyq_init(struct ionic_lif *lif) 2721{ 2722 struct ionic_qcq *qcq = lif->notifyqcq; 2723 struct device *dev = lif->ionic->dev; 2724 struct ionic_queue *q = &qcq->q; 2725 int err; 2726 2727 struct ionic_admin_ctx ctx = { 2728 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2729 .cmd.q_init = { 2730 .opcode = IONIC_CMD_Q_INIT, 2731 .lif_index = cpu_to_le16(lif->index), 2732 .type = q->type, 2733 .ver = lif->qtype_info[q->type].version, 2734 .index = cpu_to_le32(q->index), 2735 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 2736 IONIC_QINIT_F_ENA), 2737 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 2738 .pid = cpu_to_le16(q->pid), 2739 .ring_size = ilog2(q->num_descs), 2740 .ring_base = cpu_to_le64(q->base_pa), 2741 } 2742 }; 2743 2744 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 2745 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 2746 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 2747 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 2748 2749 err = ionic_adminq_post_wait(lif, &ctx); 2750 if (err) 2751 return err; 2752 2753 lif->last_eid = 0; 2754 q->hw_type = ctx.comp.q_init.hw_type; 2755 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 2756 q->dbval = IONIC_DBELL_QID(q->hw_index); 2757 2758 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 2759 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 2760 2761 /* preset the callback info */ 2762 q->info[0].cb_arg = lif; 2763 2764 qcq->flags |= IONIC_QCQ_F_INITED; 2765 2766 return 0; 2767} 2768 2769static int ionic_station_set(struct ionic_lif *lif) 2770{ 2771 struct net_device *netdev = lif->netdev; 2772 struct ionic_admin_ctx ctx = { 2773 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2774 .cmd.lif_getattr = { 2775 .opcode = IONIC_CMD_LIF_GETATTR, 2776 .index = cpu_to_le16(lif->index), 2777 .attr = IONIC_LIF_ATTR_MAC, 2778 }, 2779 }; 2780 struct sockaddr addr; 2781 int err; 2782 2783 err = ionic_adminq_post_wait(lif, &ctx); 2784 if (err) 2785 return err; 2786 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 2787 ctx.comp.lif_getattr.mac); 2788 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 2789 return 0; 2790 2791 if (!is_zero_ether_addr(netdev->dev_addr)) { 2792 /* If the netdev mac is non-zero and doesn't match the default 2793 * device address, it was set by something earlier and we're 2794 * likely here again after a fw-upgrade reset. We need to be 2795 * sure the netdev mac is in our filter list. 2796 */ 2797 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 2798 netdev->dev_addr)) 2799 ionic_lif_addr(lif, netdev->dev_addr, true, true); 2800 } else { 2801 /* Update the netdev mac with the device's mac */ 2802 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 2803 addr.sa_family = AF_INET; 2804 err = eth_prepare_mac_addr_change(netdev, &addr); 2805 if (err) { 2806 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 2807 addr.sa_data, err); 2808 return 0; 2809 } 2810 2811 eth_commit_mac_addr_change(netdev, &addr); 2812 } 2813 2814 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 2815 netdev->dev_addr); 2816 ionic_lif_addr(lif, netdev->dev_addr, true, true); 2817 2818 return 0; 2819} 2820 2821int ionic_lif_init(struct ionic_lif *lif) 2822{ 2823 struct ionic_dev *idev = &lif->ionic->idev; 2824 struct device *dev = lif->ionic->dev; 2825 struct ionic_lif_init_comp comp; 2826 int dbpage_num; 2827 int err; 2828 2829 mutex_lock(&lif->ionic->dev_cmd_lock); 2830 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 2831 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2832 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2833 mutex_unlock(&lif->ionic->dev_cmd_lock); 2834 if (err) 2835 return err; 2836 2837 lif->hw_index = le16_to_cpu(comp.hw_index); 2838 mutex_init(&lif->queue_lock); 2839 2840 /* now that we have the hw_index we can figure out our doorbell page */ 2841 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 2842 if (!lif->dbid_count) { 2843 dev_err(dev, "No doorbell pages, aborting\n"); 2844 return -EINVAL; 2845 } 2846 2847 lif->dbid_inuse = bitmap_zalloc(lif->dbid_count, GFP_KERNEL); 2848 if (!lif->dbid_inuse) { 2849 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 2850 return -ENOMEM; 2851 } 2852 2853 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 2854 set_bit(0, lif->dbid_inuse); 2855 lif->kern_pid = 0; 2856 2857 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 2858 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 2859 if (!lif->kern_dbpage) { 2860 dev_err(dev, "Cannot map dbpage, aborting\n"); 2861 err = -ENOMEM; 2862 goto err_out_free_dbid; 2863 } 2864 2865 err = ionic_lif_adminq_init(lif); 2866 if (err) 2867 goto err_out_adminq_deinit; 2868 2869 if (lif->ionic->nnqs_per_lif) { 2870 err = ionic_lif_notifyq_init(lif); 2871 if (err) 2872 goto err_out_notifyq_deinit; 2873 } 2874 2875 err = ionic_init_nic_features(lif); 2876 if (err) 2877 goto err_out_notifyq_deinit; 2878 2879 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2880 err = ionic_rx_filters_init(lif); 2881 if (err) 2882 goto err_out_notifyq_deinit; 2883 } 2884 2885 err = ionic_station_set(lif); 2886 if (err) 2887 goto err_out_notifyq_deinit; 2888 2889 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 2890 2891 set_bit(IONIC_LIF_F_INITED, lif->state); 2892 2893 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 2894 2895 return 0; 2896 2897err_out_notifyq_deinit: 2898 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2899err_out_adminq_deinit: 2900 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2901 ionic_lif_reset(lif); 2902 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2903 lif->kern_dbpage = NULL; 2904err_out_free_dbid: 2905 kfree(lif->dbid_inuse); 2906 lif->dbid_inuse = NULL; 2907 2908 return err; 2909} 2910 2911static void ionic_lif_notify_work(struct work_struct *ws) 2912{ 2913} 2914 2915static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 2916{ 2917 struct ionic_admin_ctx ctx = { 2918 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2919 .cmd.lif_setattr = { 2920 .opcode = IONIC_CMD_LIF_SETATTR, 2921 .index = cpu_to_le16(lif->index), 2922 .attr = IONIC_LIF_ATTR_NAME, 2923 }, 2924 }; 2925 2926 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 2927 sizeof(ctx.cmd.lif_setattr.name)); 2928 2929 ionic_adminq_post_wait(lif, &ctx); 2930} 2931 2932static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 2933{ 2934 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 2935 return NULL; 2936 2937 return netdev_priv(netdev); 2938} 2939 2940static int ionic_lif_notify(struct notifier_block *nb, 2941 unsigned long event, void *info) 2942{ 2943 struct net_device *ndev = netdev_notifier_info_to_dev(info); 2944 struct ionic *ionic = container_of(nb, struct ionic, nb); 2945 struct ionic_lif *lif = ionic_netdev_lif(ndev); 2946 2947 if (!lif || lif->ionic != ionic) 2948 return NOTIFY_DONE; 2949 2950 switch (event) { 2951 case NETDEV_CHANGENAME: 2952 ionic_lif_set_netdev_info(lif); 2953 break; 2954 } 2955 2956 return NOTIFY_DONE; 2957} 2958 2959int ionic_lif_register(struct ionic_lif *lif) 2960{ 2961 int err; 2962 2963 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 2964 2965 lif->ionic->nb.notifier_call = ionic_lif_notify; 2966 2967 err = register_netdevice_notifier(&lif->ionic->nb); 2968 if (err) 2969 lif->ionic->nb.notifier_call = NULL; 2970 2971 /* only register LIF0 for now */ 2972 err = register_netdev(lif->netdev); 2973 if (err) { 2974 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 2975 return err; 2976 } 2977 lif->registered = true; 2978 ionic_lif_set_netdev_info(lif); 2979 2980 return 0; 2981} 2982 2983void ionic_lif_unregister(struct ionic_lif *lif) 2984{ 2985 if (lif->ionic->nb.notifier_call) { 2986 unregister_netdevice_notifier(&lif->ionic->nb); 2987 cancel_work_sync(&lif->ionic->nb_work); 2988 lif->ionic->nb.notifier_call = NULL; 2989 } 2990 2991 if (lif->netdev->reg_state == NETREG_REGISTERED) 2992 unregister_netdev(lif->netdev); 2993 lif->registered = false; 2994} 2995 2996static void ionic_lif_queue_identify(struct ionic_lif *lif) 2997{ 2998 union ionic_q_identity __iomem *q_ident; 2999 struct ionic *ionic = lif->ionic; 3000 struct ionic_dev *idev; 3001 int qtype; 3002 int err; 3003 3004 idev = &lif->ionic->idev; 3005 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3006 3007 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3008 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3009 3010 /* filter out the ones we know about */ 3011 switch (qtype) { 3012 case IONIC_QTYPE_ADMINQ: 3013 case IONIC_QTYPE_NOTIFYQ: 3014 case IONIC_QTYPE_RXQ: 3015 case IONIC_QTYPE_TXQ: 3016 break; 3017 default: 3018 continue; 3019 } 3020 3021 memset(qti, 0, sizeof(*qti)); 3022 3023 mutex_lock(&ionic->dev_cmd_lock); 3024 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3025 ionic_qtype_versions[qtype]); 3026 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3027 if (!err) { 3028 qti->version = readb(&q_ident->version); 3029 qti->supported = readb(&q_ident->supported); 3030 qti->features = readq(&q_ident->features); 3031 qti->desc_sz = readw(&q_ident->desc_sz); 3032 qti->comp_sz = readw(&q_ident->comp_sz); 3033 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3034 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3035 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3036 } 3037 mutex_unlock(&ionic->dev_cmd_lock); 3038 3039 if (err == -EINVAL) { 3040 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3041 continue; 3042 } else if (err == -EIO) { 3043 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3044 return; 3045 } else if (err) { 3046 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3047 qtype, err); 3048 return; 3049 } 3050 3051 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3052 qtype, qti->version); 3053 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3054 qtype, qti->supported); 3055 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3056 qtype, qti->features); 3057 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3058 qtype, qti->desc_sz); 3059 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3060 qtype, qti->comp_sz); 3061 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3062 qtype, qti->sg_desc_sz); 3063 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3064 qtype, qti->max_sg_elems); 3065 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3066 qtype, qti->sg_desc_stride); 3067 } 3068} 3069 3070int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3071 union ionic_lif_identity *lid) 3072{ 3073 struct ionic_dev *idev = &ionic->idev; 3074 size_t sz; 3075 int err; 3076 3077 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3078 3079 mutex_lock(&ionic->dev_cmd_lock); 3080 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3081 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3082 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3083 mutex_unlock(&ionic->dev_cmd_lock); 3084 if (err) 3085 return (err); 3086 3087 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3088 le64_to_cpu(lid->capabilities)); 3089 3090 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3091 le32_to_cpu(lid->eth.max_ucast_filters)); 3092 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3093 le32_to_cpu(lid->eth.max_mcast_filters)); 3094 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3095 le64_to_cpu(lid->eth.config.features)); 3096 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3097 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3098 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3099 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3100 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3101 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3102 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3103 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3104 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3105 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3106 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3107 le32_to_cpu(lid->eth.config.mtu)); 3108 3109 return 0; 3110} 3111 3112int ionic_lif_size(struct ionic *ionic) 3113{ 3114 struct ionic_identity *ident = &ionic->ident; 3115 unsigned int nintrs, dev_nintrs; 3116 union ionic_lif_config *lc; 3117 unsigned int ntxqs_per_lif; 3118 unsigned int nrxqs_per_lif; 3119 unsigned int neqs_per_lif; 3120 unsigned int nnqs_per_lif; 3121 unsigned int nxqs, neqs; 3122 unsigned int min_intrs; 3123 int err; 3124 3125 lc = &ident->lif.eth.config; 3126 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3127 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3128 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3129 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3130 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3131 3132 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3133 nxqs = min(nxqs, num_online_cpus()); 3134 neqs = min(neqs_per_lif, num_online_cpus()); 3135 3136try_again: 3137 /* interrupt usage: 3138 * 1 for master lif adminq/notifyq 3139 * 1 for each CPU for master lif TxRx queue pairs 3140 * whatever's left is for RDMA queues 3141 */ 3142 nintrs = 1 + nxqs + neqs; 3143 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3144 3145 if (nintrs > dev_nintrs) 3146 goto try_fewer; 3147 3148 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3149 if (err < 0 && err != -ENOSPC) { 3150 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3151 return err; 3152 } 3153 if (err == -ENOSPC) 3154 goto try_fewer; 3155 3156 if (err != nintrs) { 3157 ionic_bus_free_irq_vectors(ionic); 3158 goto try_fewer; 3159 } 3160 3161 ionic->nnqs_per_lif = nnqs_per_lif; 3162 ionic->neqs_per_lif = neqs; 3163 ionic->ntxqs_per_lif = nxqs; 3164 ionic->nrxqs_per_lif = nxqs; 3165 ionic->nintrs = nintrs; 3166 3167 ionic_debugfs_add_sizes(ionic); 3168 3169 return 0; 3170 3171try_fewer: 3172 if (nnqs_per_lif > 1) { 3173 nnqs_per_lif >>= 1; 3174 goto try_again; 3175 } 3176 if (neqs > 1) { 3177 neqs >>= 1; 3178 goto try_again; 3179 } 3180 if (nxqs > 1) { 3181 nxqs >>= 1; 3182 goto try_again; 3183 } 3184 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3185 return -ENOSPC; 3186} 3187