1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4#ifndef _IONIC_DEV_H_ 5#define _IONIC_DEV_H_ 6 7#include <linux/mutex.h> 8#include <linux/workqueue.h> 9 10#include "ionic_if.h" 11#include "ionic_regs.h" 12 13#define IONIC_MAX_TX_DESC 8192 14#define IONIC_MAX_RX_DESC 16384 15#define IONIC_MIN_TXRX_DESC 16 16#define IONIC_DEF_TXRX_DESC 4096 17#define IONIC_LIFS_MAX 1024 18#define IONIC_WATCHDOG_SECS 5 19#define IONIC_ITR_COAL_USEC_DEFAULT 64 20 21#define IONIC_DEV_CMD_REG_VERSION 1 22#define IONIC_DEV_INFO_REG_COUNT 32 23#define IONIC_DEV_CMD_REG_COUNT 32 24 25struct ionic_dev_bar { 26 void __iomem *vaddr; 27 phys_addr_t bus_addr; 28 unsigned long len; 29 int res_index; 30}; 31 32#ifndef __CHECKER__ 33/* Registers */ 34static_assert(sizeof(struct ionic_intr) == 32); 35 36static_assert(sizeof(struct ionic_doorbell) == 8); 37static_assert(sizeof(struct ionic_intr_status) == 8); 38static_assert(sizeof(union ionic_dev_regs) == 4096); 39static_assert(sizeof(union ionic_dev_info_regs) == 2048); 40static_assert(sizeof(union ionic_dev_cmd_regs) == 2048); 41static_assert(sizeof(struct ionic_lif_stats) == 1024); 42 43static_assert(sizeof(struct ionic_admin_cmd) == 64); 44static_assert(sizeof(struct ionic_admin_comp) == 16); 45static_assert(sizeof(struct ionic_nop_cmd) == 64); 46static_assert(sizeof(struct ionic_nop_comp) == 16); 47 48/* Device commands */ 49static_assert(sizeof(struct ionic_dev_identify_cmd) == 64); 50static_assert(sizeof(struct ionic_dev_identify_comp) == 16); 51static_assert(sizeof(struct ionic_dev_init_cmd) == 64); 52static_assert(sizeof(struct ionic_dev_init_comp) == 16); 53static_assert(sizeof(struct ionic_dev_reset_cmd) == 64); 54static_assert(sizeof(struct ionic_dev_reset_comp) == 16); 55static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64); 56static_assert(sizeof(struct ionic_dev_getattr_comp) == 16); 57static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64); 58static_assert(sizeof(struct ionic_dev_setattr_comp) == 16); 59 60/* Port commands */ 61static_assert(sizeof(struct ionic_port_identify_cmd) == 64); 62static_assert(sizeof(struct ionic_port_identify_comp) == 16); 63static_assert(sizeof(struct ionic_port_init_cmd) == 64); 64static_assert(sizeof(struct ionic_port_init_comp) == 16); 65static_assert(sizeof(struct ionic_port_reset_cmd) == 64); 66static_assert(sizeof(struct ionic_port_reset_comp) == 16); 67static_assert(sizeof(struct ionic_port_getattr_cmd) == 64); 68static_assert(sizeof(struct ionic_port_getattr_comp) == 16); 69static_assert(sizeof(struct ionic_port_setattr_cmd) == 64); 70static_assert(sizeof(struct ionic_port_setattr_comp) == 16); 71 72/* LIF commands */ 73static_assert(sizeof(struct ionic_lif_init_cmd) == 64); 74static_assert(sizeof(struct ionic_lif_init_comp) == 16); 75static_assert(sizeof(struct ionic_lif_reset_cmd) == 64); 76static_assert(sizeof(ionic_lif_reset_comp) == 16); 77static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64); 78static_assert(sizeof(struct ionic_lif_getattr_comp) == 16); 79static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64); 80static_assert(sizeof(struct ionic_lif_setattr_comp) == 16); 81 82static_assert(sizeof(struct ionic_q_init_cmd) == 64); 83static_assert(sizeof(struct ionic_q_init_comp) == 16); 84static_assert(sizeof(struct ionic_q_control_cmd) == 64); 85static_assert(sizeof(ionic_q_control_comp) == 16); 86static_assert(sizeof(struct ionic_q_identify_cmd) == 64); 87static_assert(sizeof(struct ionic_q_identify_comp) == 16); 88 89static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64); 90static_assert(sizeof(ionic_rx_mode_set_comp) == 16); 91static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64); 92static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16); 93static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64); 94static_assert(sizeof(ionic_rx_filter_del_comp) == 16); 95 96/* RDMA commands */ 97static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64); 98static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64); 99 100/* Events */ 101static_assert(sizeof(struct ionic_notifyq_cmd) == 4); 102static_assert(sizeof(union ionic_notifyq_comp) == 64); 103static_assert(sizeof(struct ionic_notifyq_event) == 64); 104static_assert(sizeof(struct ionic_link_change_event) == 64); 105static_assert(sizeof(struct ionic_reset_event) == 64); 106static_assert(sizeof(struct ionic_heartbeat_event) == 64); 107static_assert(sizeof(struct ionic_log_event) == 64); 108 109/* I/O */ 110static_assert(sizeof(struct ionic_txq_desc) == 16); 111static_assert(sizeof(struct ionic_txq_sg_desc) == 128); 112static_assert(sizeof(struct ionic_txq_comp) == 16); 113 114static_assert(sizeof(struct ionic_rxq_desc) == 16); 115static_assert(sizeof(struct ionic_rxq_sg_desc) == 128); 116static_assert(sizeof(struct ionic_rxq_comp) == 16); 117 118/* SR/IOV */ 119static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64); 120static_assert(sizeof(struct ionic_vf_setattr_comp) == 16); 121static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64); 122static_assert(sizeof(struct ionic_vf_getattr_comp) == 16); 123#endif /* __CHECKER__ */ 124 125struct ionic_devinfo { 126 u8 asic_type; 127 u8 asic_rev; 128 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1]; 129 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1]; 130}; 131 132struct ionic_dev { 133 union ionic_dev_info_regs __iomem *dev_info_regs; 134 union ionic_dev_cmd_regs __iomem *dev_cmd_regs; 135 136 unsigned long last_hb_time; 137 u32 last_hb; 138 u8 last_fw_status; 139 u8 opcode; 140 141 u64 __iomem *db_pages; 142 dma_addr_t phy_db_pages; 143 144 struct ionic_intr __iomem *intr_ctrl; 145 u64 __iomem *intr_status; 146 147 u32 port_info_sz; 148 struct ionic_port_info *port_info; 149 dma_addr_t port_info_pa; 150 151 struct ionic_devinfo dev_info; 152}; 153 154struct ionic_cq_info { 155 union { 156 void *cq_desc; 157 struct ionic_txq_comp *txcq; 158 struct ionic_rxq_comp *rxcq; 159 struct ionic_admin_comp *admincq; 160 struct ionic_notifyq_event *notifyq; 161 }; 162}; 163 164struct ionic_queue; 165struct ionic_qcq; 166struct ionic_desc_info; 167 168typedef void (*ionic_desc_cb)(struct ionic_queue *q, 169 struct ionic_desc_info *desc_info, 170 struct ionic_cq_info *cq_info, void *cb_arg); 171 172struct ionic_page_info { 173 struct page *page; 174 dma_addr_t dma_addr; 175}; 176 177struct ionic_desc_info { 178 union { 179 void *desc; 180 struct ionic_txq_desc *txq_desc; 181 struct ionic_rxq_desc *rxq_desc; 182 struct ionic_admin_cmd *adminq_desc; 183 }; 184 union { 185 void *sg_desc; 186 struct ionic_txq_sg_desc *txq_sg_desc; 187 struct ionic_rxq_sg_desc *rxq_sgl_desc; 188 }; 189 unsigned int npages; 190 struct ionic_page_info pages[IONIC_RX_MAX_SG_ELEMS + 1]; 191 ionic_desc_cb cb; 192 void *cb_arg; 193}; 194 195#define IONIC_QUEUE_NAME_MAX_SZ 16 196 197struct ionic_queue { 198 struct device *dev; 199 struct ionic_lif *lif; 200 struct ionic_desc_info *info; 201 u16 head_idx; 202 u16 tail_idx; 203 unsigned int index; 204 unsigned int num_descs; 205 u64 dbell_count; 206 u64 stop; 207 u64 wake; 208 u64 drop; 209 struct ionic_dev *idev; 210 unsigned int type; 211 unsigned int hw_index; 212 unsigned int hw_type; 213 u64 dbval; 214 union { 215 void *base; 216 struct ionic_txq_desc *txq; 217 struct ionic_rxq_desc *rxq; 218 struct ionic_admin_cmd *adminq; 219 }; 220 union { 221 void *sg_base; 222 struct ionic_txq_sg_desc *txq_sgl; 223 struct ionic_rxq_sg_desc *rxq_sgl; 224 }; 225 dma_addr_t base_pa; 226 dma_addr_t sg_base_pa; 227 unsigned int desc_size; 228 unsigned int sg_desc_size; 229 unsigned int pid; 230 char name[IONIC_QUEUE_NAME_MAX_SZ]; 231}; 232 233#define IONIC_INTR_INDEX_NOT_ASSIGNED -1 234#define IONIC_INTR_NAME_MAX_SZ 32 235 236struct ionic_intr_info { 237 char name[IONIC_INTR_NAME_MAX_SZ]; 238 unsigned int index; 239 unsigned int vector; 240 u64 rearm_count; 241 unsigned int cpu; 242 cpumask_t affinity_mask; 243 u32 dim_coal_hw; 244}; 245 246struct ionic_cq { 247 struct ionic_lif *lif; 248 struct ionic_cq_info *info; 249 struct ionic_queue *bound_q; 250 struct ionic_intr_info *bound_intr; 251 u16 tail_idx; 252 bool done_color; 253 unsigned int num_descs; 254 unsigned int desc_size; 255 u64 compl_count; 256 void *base; 257 dma_addr_t base_pa; 258}; 259 260struct ionic; 261 262static inline void ionic_intr_init(struct ionic_dev *idev, 263 struct ionic_intr_info *intr, 264 unsigned long index) 265{ 266 ionic_intr_clean(idev->intr_ctrl, index); 267 intr->index = index; 268} 269 270static inline unsigned int ionic_q_space_avail(struct ionic_queue *q) 271{ 272 unsigned int avail = q->tail_idx; 273 274 if (q->head_idx >= avail) 275 avail += q->num_descs - q->head_idx - 1; 276 else 277 avail -= q->head_idx + 1; 278 279 return avail; 280} 281 282static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want) 283{ 284 return ionic_q_space_avail(q) >= want; 285} 286 287void ionic_init_devinfo(struct ionic *ionic); 288int ionic_dev_setup(struct ionic *ionic); 289 290void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 291u8 ionic_dev_cmd_status(struct ionic_dev *idev); 292bool ionic_dev_cmd_done(struct ionic_dev *idev); 293void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp); 294 295void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver); 296void ionic_dev_cmd_init(struct ionic_dev *idev); 297void ionic_dev_cmd_reset(struct ionic_dev *idev); 298 299void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 300void ionic_dev_cmd_port_init(struct ionic_dev *idev); 301void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 302void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state); 303void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed); 304void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable); 305void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type); 306void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type); 307 308int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data); 309void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 310 u16 lif_type, u8 qtype, u8 qver); 311void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver); 312void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 313 dma_addr_t addr); 314void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index); 315void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 316 u16 lif_index, u16 intr_index); 317 318int ionic_db_page_num(struct ionic_lif *lif, int pid); 319 320int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 321 struct ionic_intr_info *intr, 322 unsigned int num_descs, size_t desc_size); 323void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa); 324void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q); 325typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 326typedef void (*ionic_cq_done_cb)(void *done_arg); 327unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 328 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 329 void *done_arg); 330 331int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 332 struct ionic_queue *q, unsigned int index, const char *name, 333 unsigned int num_descs, size_t desc_size, 334 size_t sg_desc_size, unsigned int pid); 335void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); 336void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); 337void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 338 void *cb_arg); 339void ionic_q_rewind(struct ionic_queue *q, struct ionic_desc_info *start); 340void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 341 unsigned int stop_index); 342int ionic_heartbeat_check(struct ionic *ionic); 343 344#endif /* _IONIC_DEV_H_ */ 345