1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4#include <linux/kernel.h> 5#include <linux/types.h> 6#include <linux/errno.h> 7#include <linux/io.h> 8#include <linux/slab.h> 9#include <linux/etherdevice.h> 10#include "ionic.h" 11#include "ionic_dev.h" 12#include "ionic_lif.h" 13 14static void ionic_watchdog_cb(struct timer_list *t) 15{ 16 struct ionic *ionic = from_timer(ionic, t, watchdog_timer); 17 int hb; 18 19 mod_timer(&ionic->watchdog_timer, 20 round_jiffies(jiffies + ionic->watchdog_period)); 21 22 if (!ionic->lif) 23 return; 24 25 hb = ionic_heartbeat_check(ionic); 26 27 if (hb >= 0) 28 ionic_link_status_check_request(ionic->lif, false); 29} 30 31void ionic_init_devinfo(struct ionic *ionic) 32{ 33 struct ionic_dev *idev = &ionic->idev; 34 35 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); 36 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); 37 38 memcpy_fromio(idev->dev_info.fw_version, 39 idev->dev_info_regs->fw_version, 40 IONIC_DEVINFO_FWVERS_BUFLEN); 41 42 memcpy_fromio(idev->dev_info.serial_num, 43 idev->dev_info_regs->serial_num, 44 IONIC_DEVINFO_SERIAL_BUFLEN); 45 46 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; 47 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; 48 49 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); 50} 51 52int ionic_dev_setup(struct ionic *ionic) 53{ 54 struct ionic_dev_bar *bar = ionic->bars; 55 unsigned int num_bars = ionic->num_bars; 56 struct ionic_dev *idev = &ionic->idev; 57 struct device *dev = ionic->dev; 58 u32 sig; 59 60 /* BAR0: dev_cmd and interrupts */ 61 if (num_bars < 1) { 62 dev_err(dev, "No bars found, aborting\n"); 63 return -EFAULT; 64 } 65 66 if (bar->len < IONIC_BAR0_SIZE) { 67 dev_err(dev, "Resource bar size %lu too small, aborting\n", 68 bar->len); 69 return -EFAULT; 70 } 71 72 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; 73 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; 74 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; 75 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; 76 77 sig = ioread32(&idev->dev_info_regs->signature); 78 if (sig != IONIC_DEV_INFO_SIGNATURE) { 79 dev_err(dev, "Incompatible firmware signature %x", sig); 80 return -EFAULT; 81 } 82 83 ionic_init_devinfo(ionic); 84 85 /* BAR1: doorbells */ 86 bar++; 87 if (num_bars < 2) { 88 dev_err(dev, "Doorbell bar missing, aborting\n"); 89 return -EFAULT; 90 } 91 92 idev->last_fw_status = 0xff; 93 timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); 94 ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; 95 mod_timer(&ionic->watchdog_timer, 96 round_jiffies(jiffies + ionic->watchdog_period)); 97 98 idev->db_pages = bar->vaddr; 99 idev->phy_db_pages = bar->bus_addr; 100 101 return 0; 102} 103 104/* Devcmd Interface */ 105int ionic_heartbeat_check(struct ionic *ionic) 106{ 107 struct ionic_dev *idev = &ionic->idev; 108 unsigned long hb_time; 109 u8 fw_status; 110 u32 hb; 111 112 /* wait a little more than one second before testing again */ 113 hb_time = jiffies; 114 if (time_before(hb_time, (idev->last_hb_time + ionic->watchdog_period))) 115 return 0; 116 117 /* firmware is useful only if the running bit is set and 118 * fw_status != 0xff (bad PCI read) 119 */ 120 fw_status = ioread8(&idev->dev_info_regs->fw_status); 121 if (fw_status != 0xff) 122 fw_status &= IONIC_FW_STS_F_RUNNING; /* use only the run bit */ 123 124 /* is this a transition? */ 125 if (fw_status != idev->last_fw_status && 126 idev->last_fw_status != 0xff) { 127 struct ionic_lif *lif = ionic->lif; 128 bool trigger = false; 129 130 if (!fw_status || fw_status == 0xff) { 131 dev_info(ionic->dev, "FW stopped %u\n", fw_status); 132 if (lif && !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 133 trigger = true; 134 } else { 135 dev_info(ionic->dev, "FW running %u\n", fw_status); 136 if (lif && test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 137 trigger = true; 138 } 139 140 if (trigger) { 141 struct ionic_deferred_work *work; 142 143 work = kzalloc(sizeof(*work), GFP_ATOMIC); 144 if (!work) { 145 dev_err(ionic->dev, "%s OOM\n", __func__); 146 } else { 147 work->type = IONIC_DW_TYPE_LIF_RESET; 148 if (fw_status & IONIC_FW_STS_F_RUNNING && 149 fw_status != 0xff) 150 work->fw_status = 1; 151 ionic_lif_deferred_enqueue(&lif->deferred, work); 152 } 153 } 154 } 155 idev->last_fw_status = fw_status; 156 157 if (!fw_status || fw_status == 0xff) 158 return -ENXIO; 159 160 /* early FW has no heartbeat, else FW will return non-zero */ 161 hb = ioread32(&idev->dev_info_regs->fw_heartbeat); 162 if (!hb) 163 return 0; 164 165 /* are we stalled? */ 166 if (hb == idev->last_hb) { 167 /* only complain once for each stall seen */ 168 if (idev->last_hb_time != 1) { 169 dev_info(ionic->dev, "FW heartbeat stalled at %d\n", 170 idev->last_hb); 171 idev->last_hb_time = 1; 172 } 173 174 return -ENXIO; 175 } 176 177 if (idev->last_hb_time == 1) 178 dev_info(ionic->dev, "FW heartbeat restored at %d\n", hb); 179 180 idev->last_hb = hb; 181 idev->last_hb_time = hb_time; 182 183 return 0; 184} 185 186u8 ionic_dev_cmd_status(struct ionic_dev *idev) 187{ 188 return ioread8(&idev->dev_cmd_regs->comp.comp.status); 189} 190 191bool ionic_dev_cmd_done(struct ionic_dev *idev) 192{ 193 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; 194} 195 196void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) 197{ 198 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); 199} 200 201void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 202{ 203 idev->opcode = cmd->cmd.opcode; 204 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); 205 iowrite32(0, &idev->dev_cmd_regs->done); 206 iowrite32(1, &idev->dev_cmd_regs->doorbell); 207} 208 209/* Device commands */ 210void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) 211{ 212 union ionic_dev_cmd cmd = { 213 .identify.opcode = IONIC_CMD_IDENTIFY, 214 .identify.ver = ver, 215 }; 216 217 ionic_dev_cmd_go(idev, &cmd); 218} 219 220void ionic_dev_cmd_init(struct ionic_dev *idev) 221{ 222 union ionic_dev_cmd cmd = { 223 .init.opcode = IONIC_CMD_INIT, 224 .init.type = 0, 225 }; 226 227 ionic_dev_cmd_go(idev, &cmd); 228} 229 230void ionic_dev_cmd_reset(struct ionic_dev *idev) 231{ 232 union ionic_dev_cmd cmd = { 233 .reset.opcode = IONIC_CMD_RESET, 234 }; 235 236 ionic_dev_cmd_go(idev, &cmd); 237} 238 239/* Port commands */ 240void ionic_dev_cmd_port_identify(struct ionic_dev *idev) 241{ 242 union ionic_dev_cmd cmd = { 243 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 244 .port_init.index = 0, 245 }; 246 247 ionic_dev_cmd_go(idev, &cmd); 248} 249 250void ionic_dev_cmd_port_init(struct ionic_dev *idev) 251{ 252 union ionic_dev_cmd cmd = { 253 .port_init.opcode = IONIC_CMD_PORT_INIT, 254 .port_init.index = 0, 255 .port_init.info_pa = cpu_to_le64(idev->port_info_pa), 256 }; 257 258 ionic_dev_cmd_go(idev, &cmd); 259} 260 261void ionic_dev_cmd_port_reset(struct ionic_dev *idev) 262{ 263 union ionic_dev_cmd cmd = { 264 .port_reset.opcode = IONIC_CMD_PORT_RESET, 265 .port_reset.index = 0, 266 }; 267 268 ionic_dev_cmd_go(idev, &cmd); 269} 270 271void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) 272{ 273 union ionic_dev_cmd cmd = { 274 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 275 .port_setattr.index = 0, 276 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 277 .port_setattr.state = state, 278 }; 279 280 ionic_dev_cmd_go(idev, &cmd); 281} 282 283void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) 284{ 285 union ionic_dev_cmd cmd = { 286 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 287 .port_setattr.index = 0, 288 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 289 .port_setattr.speed = cpu_to_le32(speed), 290 }; 291 292 ionic_dev_cmd_go(idev, &cmd); 293} 294 295void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) 296{ 297 union ionic_dev_cmd cmd = { 298 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 299 .port_setattr.index = 0, 300 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 301 .port_setattr.an_enable = an_enable, 302 }; 303 304 ionic_dev_cmd_go(idev, &cmd); 305} 306 307void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) 308{ 309 union ionic_dev_cmd cmd = { 310 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 311 .port_setattr.index = 0, 312 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 313 .port_setattr.fec_type = fec_type, 314 }; 315 316 ionic_dev_cmd_go(idev, &cmd); 317} 318 319void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) 320{ 321 union ionic_dev_cmd cmd = { 322 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 323 .port_setattr.index = 0, 324 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 325 .port_setattr.pause_type = pause_type, 326 }; 327 328 ionic_dev_cmd_go(idev, &cmd); 329} 330 331/* VF commands */ 332int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data) 333{ 334 union ionic_dev_cmd cmd = { 335 .vf_setattr.opcode = IONIC_CMD_VF_SETATTR, 336 .vf_setattr.attr = attr, 337 .vf_setattr.vf_index = cpu_to_le16(vf), 338 }; 339 int err; 340 341 switch (attr) { 342 case IONIC_VF_ATTR_SPOOFCHK: 343 cmd.vf_setattr.spoofchk = *data; 344 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 345 __func__, vf, *data); 346 break; 347 case IONIC_VF_ATTR_TRUST: 348 cmd.vf_setattr.trust = *data; 349 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 350 __func__, vf, *data); 351 break; 352 case IONIC_VF_ATTR_LINKSTATE: 353 cmd.vf_setattr.linkstate = *data; 354 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 355 __func__, vf, *data); 356 break; 357 case IONIC_VF_ATTR_MAC: 358 ether_addr_copy(cmd.vf_setattr.macaddr, data); 359 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 360 __func__, vf, data); 361 break; 362 case IONIC_VF_ATTR_VLAN: 363 cmd.vf_setattr.vlanid = cpu_to_le16(*(u16 *)data); 364 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 365 __func__, vf, *(u16 *)data); 366 break; 367 case IONIC_VF_ATTR_RATE: 368 cmd.vf_setattr.maxrate = cpu_to_le32(*(u32 *)data); 369 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 370 __func__, vf, *(u32 *)data); 371 break; 372 case IONIC_VF_ATTR_STATSADDR: 373 cmd.vf_setattr.stats_pa = cpu_to_le64(*(u64 *)data); 374 dev_dbg(ionic->dev, "%s: vf %d stats_pa 0x%08llx\n", 375 __func__, vf, *(u64 *)data); 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 mutex_lock(&ionic->dev_cmd_lock); 382 ionic_dev_cmd_go(&ionic->idev, &cmd); 383 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 384 mutex_unlock(&ionic->dev_cmd_lock); 385 386 return err; 387} 388 389/* LIF commands */ 390void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 391 u16 lif_type, u8 qtype, u8 qver) 392{ 393 union ionic_dev_cmd cmd = { 394 .q_identify.opcode = IONIC_CMD_Q_IDENTIFY, 395 .q_identify.lif_type = cpu_to_le16(lif_type), 396 .q_identify.type = qtype, 397 .q_identify.ver = qver, 398 }; 399 400 ionic_dev_cmd_go(idev, &cmd); 401} 402 403void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) 404{ 405 union ionic_dev_cmd cmd = { 406 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 407 .lif_identify.type = type, 408 .lif_identify.ver = ver, 409 }; 410 411 ionic_dev_cmd_go(idev, &cmd); 412} 413 414void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 415 dma_addr_t info_pa) 416{ 417 union ionic_dev_cmd cmd = { 418 .lif_init.opcode = IONIC_CMD_LIF_INIT, 419 .lif_init.index = cpu_to_le16(lif_index), 420 .lif_init.info_pa = cpu_to_le64(info_pa), 421 }; 422 423 ionic_dev_cmd_go(idev, &cmd); 424} 425 426void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) 427{ 428 union ionic_dev_cmd cmd = { 429 .lif_init.opcode = IONIC_CMD_LIF_RESET, 430 .lif_init.index = cpu_to_le16(lif_index), 431 }; 432 433 ionic_dev_cmd_go(idev, &cmd); 434} 435 436void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 437 u16 lif_index, u16 intr_index) 438{ 439 struct ionic_queue *q = &qcq->q; 440 struct ionic_cq *cq = &qcq->cq; 441 442 union ionic_dev_cmd cmd = { 443 .q_init.opcode = IONIC_CMD_Q_INIT, 444 .q_init.lif_index = cpu_to_le16(lif_index), 445 .q_init.type = q->type, 446 .q_init.ver = qcq->q.lif->qtype_info[q->type].version, 447 .q_init.index = cpu_to_le32(q->index), 448 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 449 IONIC_QINIT_F_ENA), 450 .q_init.pid = cpu_to_le16(q->pid), 451 .q_init.intr_index = cpu_to_le16(intr_index), 452 .q_init.ring_size = ilog2(q->num_descs), 453 .q_init.ring_base = cpu_to_le64(q->base_pa), 454 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa), 455 }; 456 457 ionic_dev_cmd_go(idev, &cmd); 458} 459 460int ionic_db_page_num(struct ionic_lif *lif, int pid) 461{ 462 return (lif->hw_index * lif->dbid_count) + pid; 463} 464 465int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 466 struct ionic_intr_info *intr, 467 unsigned int num_descs, size_t desc_size) 468{ 469 unsigned int ring_size; 470 471 if (desc_size == 0 || !is_power_of_2(num_descs)) 472 return -EINVAL; 473 474 ring_size = ilog2(num_descs); 475 if (ring_size < 2 || ring_size > 16) 476 return -EINVAL; 477 478 cq->lif = lif; 479 cq->bound_intr = intr; 480 cq->num_descs = num_descs; 481 cq->desc_size = desc_size; 482 cq->tail_idx = 0; 483 cq->done_color = 1; 484 485 return 0; 486} 487 488void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) 489{ 490 struct ionic_cq_info *cur; 491 unsigned int i; 492 493 cq->base = base; 494 cq->base_pa = base_pa; 495 496 for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++) 497 cur->cq_desc = base + (i * cq->desc_size); 498} 499 500void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 501{ 502 cq->bound_q = q; 503} 504 505unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 506 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 507 void *done_arg) 508{ 509 struct ionic_cq_info *cq_info; 510 unsigned int work_done = 0; 511 512 if (work_to_do == 0) 513 return 0; 514 515 cq_info = &cq->info[cq->tail_idx]; 516 while (cb(cq, cq_info)) { 517 if (cq->tail_idx == cq->num_descs - 1) 518 cq->done_color = !cq->done_color; 519 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 520 cq_info = &cq->info[cq->tail_idx]; 521 DEBUG_STATS_CQE_CNT(cq); 522 523 if (++work_done >= work_to_do) 524 break; 525 } 526 527 if (work_done && done_cb) 528 done_cb(done_arg); 529 530 return work_done; 531} 532 533int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 534 struct ionic_queue *q, unsigned int index, const char *name, 535 unsigned int num_descs, size_t desc_size, 536 size_t sg_desc_size, unsigned int pid) 537{ 538 unsigned int ring_size; 539 540 if (desc_size == 0 || !is_power_of_2(num_descs)) 541 return -EINVAL; 542 543 ring_size = ilog2(num_descs); 544 if (ring_size < 2 || ring_size > 16) 545 return -EINVAL; 546 547 q->lif = lif; 548 q->idev = idev; 549 q->index = index; 550 q->num_descs = num_descs; 551 q->desc_size = desc_size; 552 q->sg_desc_size = sg_desc_size; 553 q->tail_idx = 0; 554 q->head_idx = 0; 555 q->pid = pid; 556 557 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); 558 559 return 0; 560} 561 562void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 563{ 564 struct ionic_desc_info *cur; 565 unsigned int i; 566 567 q->base = base; 568 q->base_pa = base_pa; 569 570 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 571 cur->desc = base + (i * q->desc_size); 572} 573 574void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 575{ 576 struct ionic_desc_info *cur; 577 unsigned int i; 578 579 q->sg_base = base; 580 q->sg_base_pa = base_pa; 581 582 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 583 cur->sg_desc = base + (i * q->sg_desc_size); 584} 585 586void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 587 void *cb_arg) 588{ 589 struct device *dev = q->lif->ionic->dev; 590 struct ionic_desc_info *desc_info; 591 struct ionic_lif *lif = q->lif; 592 593 desc_info = &q->info[q->head_idx]; 594 desc_info->cb = cb; 595 desc_info->cb_arg = cb_arg; 596 597 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); 598 599 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", 600 q->lif->index, q->name, q->hw_type, q->hw_index, 601 q->head_idx, ring_doorbell); 602 603 if (ring_doorbell) 604 ionic_dbell_ring(lif->kern_dbpage, q->hw_type, 605 q->dbval | q->head_idx); 606} 607 608static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) 609{ 610 unsigned int mask, tail, head; 611 612 mask = q->num_descs - 1; 613 tail = q->tail_idx; 614 head = q->head_idx; 615 616 return ((pos - tail) & mask) < ((head - tail) & mask); 617} 618 619void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 620 unsigned int stop_index) 621{ 622 struct ionic_desc_info *desc_info; 623 ionic_desc_cb cb; 624 void *cb_arg; 625 u16 index; 626 627 /* check for empty queue */ 628 if (q->tail_idx == q->head_idx) 629 return; 630 631 /* stop index must be for a descriptor that is not yet completed */ 632 if (unlikely(!ionic_q_is_posted(q, stop_index))) 633 dev_err(q->lif->ionic->dev, 634 "ionic stop is not posted %s stop %u tail %u head %u\n", 635 q->name, stop_index, q->tail_idx, q->head_idx); 636 637 do { 638 desc_info = &q->info[q->tail_idx]; 639 index = q->tail_idx; 640 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 641 642 cb = desc_info->cb; 643 cb_arg = desc_info->cb_arg; 644 645 desc_info->cb = NULL; 646 desc_info->cb_arg = NULL; 647 648 if (cb) 649 cb(q, desc_info, cq_info, cb_arg); 650 } while (index != stop_index); 651} 652