1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7#include <linux/interrupt.h> 8#include <linux/module.h> 9#include <linux/of_net.h> 10#include <linux/netdevice.h> 11#include <linux/of_mdio.h> 12#include <linux/of_platform.h> 13#include <linux/mfd/syscon.h> 14#include <linux/skbuff.h> 15#include <net/switchdev.h> 16 17#include <soc/mscc/ocelot_vcap.h> 18#include <soc/mscc/ocelot_hsio.h> 19#include "ocelot.h" 20 21#define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0)) 22 23static const u32 ocelot_ana_regmap[] = { 24 REG(ANA_ADVLEARN, 0x009000), 25 REG(ANA_VLANMASK, 0x009004), 26 REG(ANA_PORT_B_DOMAIN, 0x009008), 27 REG(ANA_ANAGEFIL, 0x00900c), 28 REG(ANA_ANEVENTS, 0x009010), 29 REG(ANA_STORMLIMIT_BURST, 0x009014), 30 REG(ANA_STORMLIMIT_CFG, 0x009018), 31 REG(ANA_ISOLATED_PORTS, 0x009028), 32 REG(ANA_COMMUNITY_PORTS, 0x00902c), 33 REG(ANA_AUTOAGE, 0x009030), 34 REG(ANA_MACTOPTIONS, 0x009034), 35 REG(ANA_LEARNDISC, 0x009038), 36 REG(ANA_AGENCTRL, 0x00903c), 37 REG(ANA_MIRRORPORTS, 0x009040), 38 REG(ANA_EMIRRORPORTS, 0x009044), 39 REG(ANA_FLOODING, 0x009048), 40 REG(ANA_FLOODING_IPMC, 0x00904c), 41 REG(ANA_SFLOW_CFG, 0x009050), 42 REG(ANA_PORT_MODE, 0x009080), 43 REG(ANA_PGID_PGID, 0x008c00), 44 REG(ANA_TABLES_ANMOVED, 0x008b30), 45 REG(ANA_TABLES_MACHDATA, 0x008b34), 46 REG(ANA_TABLES_MACLDATA, 0x008b38), 47 REG(ANA_TABLES_MACACCESS, 0x008b3c), 48 REG(ANA_TABLES_MACTINDX, 0x008b40), 49 REG(ANA_TABLES_VLANACCESS, 0x008b44), 50 REG(ANA_TABLES_VLANTIDX, 0x008b48), 51 REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 52 REG(ANA_TABLES_ISDXTIDX, 0x008b50), 53 REG(ANA_TABLES_ENTRYLIM, 0x008b00), 54 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 55 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 56 REG(ANA_MSTI_STATE, 0x008e00), 57 REG(ANA_PORT_VLAN_CFG, 0x007000), 58 REG(ANA_PORT_DROP_CFG, 0x007004), 59 REG(ANA_PORT_QOS_CFG, 0x007008), 60 REG(ANA_PORT_VCAP_CFG, 0x00700c), 61 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 62 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 63 REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 64 REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 65 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 66 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 67 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 68 REG(ANA_PORT_PORT_CFG, 0x007070), 69 REG(ANA_PORT_POL_CFG, 0x007074), 70 REG(ANA_PORT_PTP_CFG, 0x007078), 71 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 72 REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 73 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 74 REG(ANA_PFC_PFC_CFG, 0x008800), 75 REG(ANA_PFC_PFC_TIMER, 0x008804), 76 REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 77 REG(ANA_IPT_IPT, 0x008004), 78 REG(ANA_PPT_PPT, 0x008ac0), 79 REG(ANA_FID_MAP_FID_MAP, 0x000000), 80 REG(ANA_AGGR_CFG, 0x0090b4), 81 REG(ANA_CPUQ_CFG, 0x0090b8), 82 REG(ANA_CPUQ_CFG2, 0x0090bc), 83 REG(ANA_CPUQ_8021_CFG, 0x0090c0), 84 REG(ANA_DSCP_CFG, 0x009100), 85 REG(ANA_DSCP_REWR_CFG, 0x009200), 86 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 87 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 88 REG(ANA_VRAP_CFG, 0x009280), 89 REG(ANA_VRAP_HDR_DATA, 0x009284), 90 REG(ANA_VRAP_HDR_MASK, 0x009288), 91 REG(ANA_DISCARD_CFG, 0x00928c), 92 REG(ANA_FID_CFG, 0x009290), 93 REG(ANA_POL_PIR_CFG, 0x004000), 94 REG(ANA_POL_CIR_CFG, 0x004004), 95 REG(ANA_POL_MODE_CFG, 0x004008), 96 REG(ANA_POL_PIR_STATE, 0x00400c), 97 REG(ANA_POL_CIR_STATE, 0x004010), 98 REG(ANA_POL_STATE, 0x004014), 99 REG(ANA_POL_FLOWC, 0x008b80), 100 REG(ANA_POL_HYST, 0x008bec), 101 REG(ANA_POL_MISC_CFG, 0x008bf0), 102}; 103 104static const u32 ocelot_qs_regmap[] = { 105 REG(QS_XTR_GRP_CFG, 0x000000), 106 REG(QS_XTR_RD, 0x000008), 107 REG(QS_XTR_FRM_PRUNING, 0x000010), 108 REG(QS_XTR_FLUSH, 0x000018), 109 REG(QS_XTR_DATA_PRESENT, 0x00001c), 110 REG(QS_XTR_CFG, 0x000020), 111 REG(QS_INJ_GRP_CFG, 0x000024), 112 REG(QS_INJ_WR, 0x00002c), 113 REG(QS_INJ_CTRL, 0x000034), 114 REG(QS_INJ_STATUS, 0x00003c), 115 REG(QS_INJ_ERR, 0x000040), 116 REG(QS_INH_DBG, 0x000048), 117}; 118 119static const u32 ocelot_qsys_regmap[] = { 120 REG(QSYS_PORT_MODE, 0x011200), 121 REG(QSYS_SWITCH_PORT_MODE, 0x011234), 122 REG(QSYS_STAT_CNT_CFG, 0x011264), 123 REG(QSYS_EEE_CFG, 0x011268), 124 REG(QSYS_EEE_THRES, 0x011294), 125 REG(QSYS_IGR_NO_SHARING, 0x011298), 126 REG(QSYS_EGR_NO_SHARING, 0x01129c), 127 REG(QSYS_SW_STATUS, 0x0112a0), 128 REG(QSYS_EXT_CPU_CFG, 0x0112d0), 129 REG(QSYS_PAD_CFG, 0x0112d4), 130 REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 131 REG(QSYS_QMAP, 0x0112dc), 132 REG(QSYS_ISDX_SGRP, 0x011400), 133 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 134 REG(QSYS_TFRM_MISC, 0x011310), 135 REG(QSYS_TFRM_PORT_DLY, 0x011314), 136 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 137 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 138 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 139 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 140 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 141 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 142 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 143 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 144 REG(QSYS_RED_PROFILE, 0x011338), 145 REG(QSYS_RES_QOS_MODE, 0x011378), 146 REG(QSYS_RES_CFG, 0x012000), 147 REG(QSYS_RES_STAT, 0x012004), 148 REG(QSYS_EGR_DROP_MODE, 0x01137c), 149 REG(QSYS_EQ_CTRL, 0x011380), 150 REG(QSYS_EVENTS_CORE, 0x011384), 151 REG(QSYS_CIR_CFG, 0x000000), 152 REG(QSYS_EIR_CFG, 0x000004), 153 REG(QSYS_SE_CFG, 0x000008), 154 REG(QSYS_SE_DWRR_CFG, 0x00000c), 155 REG(QSYS_SE_CONNECT, 0x00003c), 156 REG(QSYS_SE_DLB_SENSE, 0x000040), 157 REG(QSYS_CIR_STATE, 0x000044), 158 REG(QSYS_EIR_STATE, 0x000048), 159 REG(QSYS_SE_STATE, 0x00004c), 160 REG(QSYS_HSCH_MISC_CFG, 0x011388), 161}; 162 163static const u32 ocelot_rew_regmap[] = { 164 REG(REW_PORT_VLAN_CFG, 0x000000), 165 REG(REW_TAG_CFG, 0x000004), 166 REG(REW_PORT_CFG, 0x000008), 167 REG(REW_DSCP_CFG, 0x00000c), 168 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 169 REG(REW_PTP_CFG, 0x000050), 170 REG(REW_PTP_DLY1_CFG, 0x000054), 171 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 172 REG(REW_DSCP_REMAP_CFG, 0x000790), 173 REG(REW_STAT_CFG, 0x000890), 174 REG(REW_PPT, 0x000680), 175}; 176 177static const u32 ocelot_sys_regmap[] = { 178 REG(SYS_COUNT_RX_OCTETS, 0x000000), 179 REG(SYS_COUNT_RX_UNICAST, 0x000004), 180 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 181 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 182 REG(SYS_COUNT_RX_SHORTS, 0x000010), 183 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 184 REG(SYS_COUNT_RX_JABBERS, 0x000018), 185 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 186 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 187 REG(SYS_COUNT_RX_64, 0x000024), 188 REG(SYS_COUNT_RX_65_127, 0x000028), 189 REG(SYS_COUNT_RX_128_255, 0x00002c), 190 REG(SYS_COUNT_RX_256_1023, 0x000030), 191 REG(SYS_COUNT_RX_1024_1526, 0x000034), 192 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 193 REG(SYS_COUNT_RX_PAUSE, 0x00003c), 194 REG(SYS_COUNT_RX_CONTROL, 0x000040), 195 REG(SYS_COUNT_RX_LONGS, 0x000044), 196 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 197 REG(SYS_COUNT_TX_OCTETS, 0x000100), 198 REG(SYS_COUNT_TX_UNICAST, 0x000104), 199 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 200 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 201 REG(SYS_COUNT_TX_COLLISION, 0x000110), 202 REG(SYS_COUNT_TX_DROPS, 0x000114), 203 REG(SYS_COUNT_TX_PAUSE, 0x000118), 204 REG(SYS_COUNT_TX_64, 0x00011c), 205 REG(SYS_COUNT_TX_65_127, 0x000120), 206 REG(SYS_COUNT_TX_128_511, 0x000124), 207 REG(SYS_COUNT_TX_512_1023, 0x000128), 208 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 209 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 210 REG(SYS_COUNT_TX_AGING, 0x000170), 211 REG(SYS_RESET_CFG, 0x000508), 212 REG(SYS_CMID, 0x00050c), 213 REG(SYS_VLAN_ETYPE_CFG, 0x000510), 214 REG(SYS_PORT_MODE, 0x000514), 215 REG(SYS_FRONT_PORT_MODE, 0x000548), 216 REG(SYS_FRM_AGING, 0x000574), 217 REG(SYS_STAT_CFG, 0x000578), 218 REG(SYS_SW_STATUS, 0x00057c), 219 REG(SYS_MISC_CFG, 0x0005ac), 220 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 221 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 222 REG(SYS_CM_ADDR, 0x000500), 223 REG(SYS_CM_DATA, 0x000504), 224 REG(SYS_PAUSE_CFG, 0x000608), 225 REG(SYS_PAUSE_TOT_CFG, 0x000638), 226 REG(SYS_ATOP, 0x00063c), 227 REG(SYS_ATOP_TOT_CFG, 0x00066c), 228 REG(SYS_MAC_FC_CFG, 0x000670), 229 REG(SYS_MMGT, 0x00069c), 230 REG(SYS_MMGT_FAST, 0x0006a0), 231 REG(SYS_EVENTS_DIF, 0x0006a4), 232 REG(SYS_EVENTS_CORE, 0x0006b4), 233 REG(SYS_CNT, 0x000000), 234 REG(SYS_PTP_STATUS, 0x0006b8), 235 REG(SYS_PTP_TXSTAMP, 0x0006bc), 236 REG(SYS_PTP_NXT, 0x0006c0), 237 REG(SYS_PTP_CFG, 0x0006c4), 238}; 239 240static const u32 ocelot_vcap_regmap[] = { 241 /* VCAP_CORE_CFG */ 242 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 243 REG(VCAP_CORE_MV_CFG, 0x000004), 244 /* VCAP_CORE_CACHE */ 245 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 246 REG(VCAP_CACHE_MASK_DAT, 0x000108), 247 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 248 REG(VCAP_CACHE_CNT_DAT, 0x000308), 249 REG(VCAP_CACHE_TG_DAT, 0x000388), 250 /* VCAP_CONST */ 251 REG(VCAP_CONST_VCAP_VER, 0x000398), 252 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 253 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 254 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 255 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 256 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 257 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 258 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 259 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 260 REG(VCAP_CONST_IF_CNT, 0x0003bc), 261}; 262 263static const u32 ocelot_ptp_regmap[] = { 264 REG(PTP_PIN_CFG, 0x000000), 265 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 266 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 267 REG(PTP_PIN_TOD_NSEC, 0x00000c), 268 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 269 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 270 REG(PTP_CFG_MISC, 0x0000a0), 271 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 272 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 273}; 274 275static const u32 ocelot_dev_gmii_regmap[] = { 276 REG(DEV_CLOCK_CFG, 0x0), 277 REG(DEV_PORT_MISC, 0x4), 278 REG(DEV_EVENTS, 0x8), 279 REG(DEV_EEE_CFG, 0xc), 280 REG(DEV_RX_PATH_DELAY, 0x10), 281 REG(DEV_TX_PATH_DELAY, 0x14), 282 REG(DEV_PTP_PREDICT_CFG, 0x18), 283 REG(DEV_MAC_ENA_CFG, 0x1c), 284 REG(DEV_MAC_MODE_CFG, 0x20), 285 REG(DEV_MAC_MAXLEN_CFG, 0x24), 286 REG(DEV_MAC_TAGS_CFG, 0x28), 287 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 288 REG(DEV_MAC_IFG_CFG, 0x30), 289 REG(DEV_MAC_HDX_CFG, 0x34), 290 REG(DEV_MAC_DBG_CFG, 0x38), 291 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 292 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 293 REG(DEV_MAC_STICKY, 0x44), 294 REG(PCS1G_CFG, 0x48), 295 REG(PCS1G_MODE_CFG, 0x4c), 296 REG(PCS1G_SD_CFG, 0x50), 297 REG(PCS1G_ANEG_CFG, 0x54), 298 REG(PCS1G_ANEG_NP_CFG, 0x58), 299 REG(PCS1G_LB_CFG, 0x5c), 300 REG(PCS1G_DBG_CFG, 0x60), 301 REG(PCS1G_CDET_CFG, 0x64), 302 REG(PCS1G_ANEG_STATUS, 0x68), 303 REG(PCS1G_ANEG_NP_STATUS, 0x6c), 304 REG(PCS1G_LINK_STATUS, 0x70), 305 REG(PCS1G_LINK_DOWN_CNT, 0x74), 306 REG(PCS1G_STICKY, 0x78), 307 REG(PCS1G_DEBUG_STATUS, 0x7c), 308 REG(PCS1G_LPI_CFG, 0x80), 309 REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 310 REG(PCS1G_LPI_STATUS, 0x88), 311 REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 312 REG(PCS1G_TSTPAT_STATUS, 0x90), 313 REG(DEV_PCS_FX100_CFG, 0x94), 314 REG(DEV_PCS_FX100_STATUS, 0x98), 315}; 316 317static const u32 *ocelot_regmap[TARGET_MAX] = { 318 [ANA] = ocelot_ana_regmap, 319 [QS] = ocelot_qs_regmap, 320 [QSYS] = ocelot_qsys_regmap, 321 [REW] = ocelot_rew_regmap, 322 [SYS] = ocelot_sys_regmap, 323 [S0] = ocelot_vcap_regmap, 324 [S1] = ocelot_vcap_regmap, 325 [S2] = ocelot_vcap_regmap, 326 [PTP] = ocelot_ptp_regmap, 327 [DEV_GMII] = ocelot_dev_gmii_regmap, 328}; 329 330static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { 331 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 332 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 333 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 334 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 335 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 336 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 337 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 338 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 339 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 340 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 341 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 342 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 343 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 344 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 345 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 346 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 347 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 348 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 349 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 350 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 351 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 352 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 353 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 354 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 355 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 356 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 357 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 358 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 359 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 360 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 361 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 362 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 363 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 364 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 365 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 366 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 367 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 368 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 369 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 370 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 371 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 372 /* Replicated per number of ports (12), register size 4 per port */ 373 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), 374 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), 375 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), 376 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), 377 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), 378 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), 379 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), 380 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), 381 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), 382 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), 383 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), 384 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), 385 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), 386}; 387 388static const struct ocelot_stat_layout ocelot_stats_layout[] = { 389 { .name = "rx_octets", .offset = 0x00, }, 390 { .name = "rx_unicast", .offset = 0x01, }, 391 { .name = "rx_multicast", .offset = 0x02, }, 392 { .name = "rx_broadcast", .offset = 0x03, }, 393 { .name = "rx_shorts", .offset = 0x04, }, 394 { .name = "rx_fragments", .offset = 0x05, }, 395 { .name = "rx_jabbers", .offset = 0x06, }, 396 { .name = "rx_crc_align_errs", .offset = 0x07, }, 397 { .name = "rx_sym_errs", .offset = 0x08, }, 398 { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 399 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 400 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 401 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 402 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 403 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 404 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 405 { .name = "rx_pause", .offset = 0x10, }, 406 { .name = "rx_control", .offset = 0x11, }, 407 { .name = "rx_longs", .offset = 0x12, }, 408 { .name = "rx_classified_drops", .offset = 0x13, }, 409 { .name = "rx_red_prio_0", .offset = 0x14, }, 410 { .name = "rx_red_prio_1", .offset = 0x15, }, 411 { .name = "rx_red_prio_2", .offset = 0x16, }, 412 { .name = "rx_red_prio_3", .offset = 0x17, }, 413 { .name = "rx_red_prio_4", .offset = 0x18, }, 414 { .name = "rx_red_prio_5", .offset = 0x19, }, 415 { .name = "rx_red_prio_6", .offset = 0x1A, }, 416 { .name = "rx_red_prio_7", .offset = 0x1B, }, 417 { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 418 { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 419 { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 420 { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 421 { .name = "rx_yellow_prio_4", .offset = 0x20, }, 422 { .name = "rx_yellow_prio_5", .offset = 0x21, }, 423 { .name = "rx_yellow_prio_6", .offset = 0x22, }, 424 { .name = "rx_yellow_prio_7", .offset = 0x23, }, 425 { .name = "rx_green_prio_0", .offset = 0x24, }, 426 { .name = "rx_green_prio_1", .offset = 0x25, }, 427 { .name = "rx_green_prio_2", .offset = 0x26, }, 428 { .name = "rx_green_prio_3", .offset = 0x27, }, 429 { .name = "rx_green_prio_4", .offset = 0x28, }, 430 { .name = "rx_green_prio_5", .offset = 0x29, }, 431 { .name = "rx_green_prio_6", .offset = 0x2A, }, 432 { .name = "rx_green_prio_7", .offset = 0x2B, }, 433 { .name = "tx_octets", .offset = 0x40, }, 434 { .name = "tx_unicast", .offset = 0x41, }, 435 { .name = "tx_multicast", .offset = 0x42, }, 436 { .name = "tx_broadcast", .offset = 0x43, }, 437 { .name = "tx_collision", .offset = 0x44, }, 438 { .name = "tx_drops", .offset = 0x45, }, 439 { .name = "tx_pause", .offset = 0x46, }, 440 { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 441 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 442 { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 443 { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 444 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 445 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 446 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 447 { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 448 { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 449 { .name = "tx_yellow_prio_2", .offset = 0x50, }, 450 { .name = "tx_yellow_prio_3", .offset = 0x51, }, 451 { .name = "tx_yellow_prio_4", .offset = 0x52, }, 452 { .name = "tx_yellow_prio_5", .offset = 0x53, }, 453 { .name = "tx_yellow_prio_6", .offset = 0x54, }, 454 { .name = "tx_yellow_prio_7", .offset = 0x55, }, 455 { .name = "tx_green_prio_0", .offset = 0x56, }, 456 { .name = "tx_green_prio_1", .offset = 0x57, }, 457 { .name = "tx_green_prio_2", .offset = 0x58, }, 458 { .name = "tx_green_prio_3", .offset = 0x59, }, 459 { .name = "tx_green_prio_4", .offset = 0x5A, }, 460 { .name = "tx_green_prio_5", .offset = 0x5B, }, 461 { .name = "tx_green_prio_6", .offset = 0x5C, }, 462 { .name = "tx_green_prio_7", .offset = 0x5D, }, 463 { .name = "tx_aged", .offset = 0x5E, }, 464 { .name = "drop_local", .offset = 0x80, }, 465 { .name = "drop_tail", .offset = 0x81, }, 466 { .name = "drop_yellow_prio_0", .offset = 0x82, }, 467 { .name = "drop_yellow_prio_1", .offset = 0x83, }, 468 { .name = "drop_yellow_prio_2", .offset = 0x84, }, 469 { .name = "drop_yellow_prio_3", .offset = 0x85, }, 470 { .name = "drop_yellow_prio_4", .offset = 0x86, }, 471 { .name = "drop_yellow_prio_5", .offset = 0x87, }, 472 { .name = "drop_yellow_prio_6", .offset = 0x88, }, 473 { .name = "drop_yellow_prio_7", .offset = 0x89, }, 474 { .name = "drop_green_prio_0", .offset = 0x8A, }, 475 { .name = "drop_green_prio_1", .offset = 0x8B, }, 476 { .name = "drop_green_prio_2", .offset = 0x8C, }, 477 { .name = "drop_green_prio_3", .offset = 0x8D, }, 478 { .name = "drop_green_prio_4", .offset = 0x8E, }, 479 { .name = "drop_green_prio_5", .offset = 0x8F, }, 480 { .name = "drop_green_prio_6", .offset = 0x90, }, 481 { .name = "drop_green_prio_7", .offset = 0x91, }, 482}; 483 484static void ocelot_pll5_init(struct ocelot *ocelot) 485{ 486 /* Configure PLL5. This will need a proper CCF driver 487 * The values are coming from the VTSS API for Ocelot 488 */ 489 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 490 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 491 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 492 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 493 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 494 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 495 HSIO_PLL5G_CFG0_ENA_BIAS | 496 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 497 HSIO_PLL5G_CFG0_ENA_CP1 | 498 HSIO_PLL5G_CFG0_SELCPI(2) | 499 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 500 HSIO_PLL5G_CFG0_SELBGV820(4) | 501 HSIO_PLL5G_CFG0_DIV4 | 502 HSIO_PLL5G_CFG0_ENA_CLKTREE | 503 HSIO_PLL5G_CFG0_ENA_LANE); 504 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 505 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 506 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 507 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 508 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 509 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 510 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 511} 512 513static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 514{ 515 int ret; 516 517 ocelot->map = ocelot_regmap; 518 ocelot->stats_layout = ocelot_stats_layout; 519 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 520 ocelot->shared_queue_sz = 224 * 1024; 521 ocelot->num_mact_rows = 1024; 522 ocelot->ops = ops; 523 524 ret = ocelot_regfields_init(ocelot, ocelot_regfields); 525 if (ret) 526 return ret; 527 528 ocelot_pll5_init(ocelot); 529 530 eth_random_addr(ocelot->base_mac); 531 ocelot->base_mac[5] &= 0xf0; 532 533 return 0; 534} 535 536static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info) 537{ 538 u8 llen, wlen; 539 u64 ifh[2]; 540 541 ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]); 542 ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]); 543 544 wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7, 8); 545 llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15, 6); 546 547 info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80; 548 549 info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32); 550 551 info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4); 552 553 info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16, 1); 554 info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0, 12); 555 556 return 0; 557} 558 559static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 560 u32 *rval) 561{ 562 u32 val; 563 u32 bytes_valid; 564 565 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 566 if (val == XTR_NOT_READY) { 567 if (ifh) 568 return -EIO; 569 570 do { 571 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 572 } while (val == XTR_NOT_READY); 573 } 574 575 switch (val) { 576 case XTR_ABORT: 577 return -EIO; 578 case XTR_EOF_0: 579 case XTR_EOF_1: 580 case XTR_EOF_2: 581 case XTR_EOF_3: 582 case XTR_PRUNED: 583 bytes_valid = XTR_VALID_BYTES(val); 584 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 585 if (val == XTR_ESCAPE) 586 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 587 else 588 *rval = val; 589 590 return bytes_valid; 591 case XTR_ESCAPE: 592 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 593 594 return 4; 595 default: 596 *rval = val; 597 598 return 4; 599 } 600} 601 602static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 603{ 604 struct ocelot *ocelot = arg; 605 int i = 0, grp = 0; 606 int err = 0; 607 608 if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))) 609 return IRQ_NONE; 610 611 do { 612 struct skb_shared_hwtstamps *shhwtstamps; 613 struct ocelot_port_private *priv; 614 struct ocelot_port *ocelot_port; 615 u64 tod_in_ns, full_ts_in_ns; 616 struct frame_info info = {}; 617 struct net_device *dev; 618 u32 ifh[4], val, *buf; 619 struct timespec64 ts; 620 int sz, len, buf_len; 621 struct sk_buff *skb; 622 623 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 624 err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]); 625 if (err != 4) 626 break; 627 } 628 629 if (err != 4) 630 break; 631 632 /* At this point the IFH was read correctly, so it is safe to 633 * presume that there is no error. The err needs to be reset 634 * otherwise a frame could come in CPU queue between the while 635 * condition and the check for error later on. And in that case 636 * the new frame is just removed and not processed. 637 */ 638 err = 0; 639 640 ocelot_parse_ifh(ifh, &info); 641 642 ocelot_port = ocelot->ports[info.port]; 643 priv = container_of(ocelot_port, struct ocelot_port_private, 644 port); 645 dev = priv->dev; 646 647 skb = netdev_alloc_skb(dev, info.len); 648 649 if (unlikely(!skb)) { 650 netdev_err(dev, "Unable to allocate sk_buff\n"); 651 err = -ENOMEM; 652 break; 653 } 654 buf_len = info.len - ETH_FCS_LEN; 655 buf = (u32 *)skb_put(skb, buf_len); 656 657 len = 0; 658 do { 659 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 660 *buf++ = val; 661 len += sz; 662 } while (len < buf_len); 663 664 /* Read the FCS */ 665 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 666 /* Update the statistics if part of the FCS was read before */ 667 len -= ETH_FCS_LEN - sz; 668 669 if (unlikely(dev->features & NETIF_F_RXFCS)) { 670 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 671 *buf = val; 672 } 673 674 if (sz < 0) { 675 err = sz; 676 break; 677 } 678 679 if (ocelot->ptp) { 680 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 681 682 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 683 if ((tod_in_ns & 0xffffffff) < info.timestamp) 684 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 685 info.timestamp; 686 else 687 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 688 info.timestamp; 689 690 shhwtstamps = skb_hwtstamps(skb); 691 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 692 shhwtstamps->hwtstamp = full_ts_in_ns; 693 } 694 695 /* Everything we see on an interface that is in the HW bridge 696 * has already been forwarded. 697 */ 698 if (ocelot->bridge_mask & BIT(info.port)) 699 skb->offload_fwd_mark = 1; 700 701 skb->protocol = eth_type_trans(skb, dev); 702 if (!skb_defer_rx_timestamp(skb)) 703 netif_rx(skb); 704 dev->stats.rx_bytes += len; 705 dev->stats.rx_packets++; 706 } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)); 707 708 if (err) 709 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 710 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 711 712 return IRQ_HANDLED; 713} 714 715static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 716{ 717 struct ocelot *ocelot = arg; 718 719 ocelot_get_txtstamp(ocelot); 720 721 return IRQ_HANDLED; 722} 723 724static const struct of_device_id mscc_ocelot_match[] = { 725 { .compatible = "mscc,vsc7514-switch" }, 726 { } 727}; 728MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 729 730static int ocelot_reset(struct ocelot *ocelot) 731{ 732 int retries = 100; 733 u32 val; 734 735 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 736 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 737 738 do { 739 msleep(1); 740 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 741 &val); 742 } while (val && --retries); 743 744 if (!retries) 745 return -ETIMEDOUT; 746 747 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 748 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 749 750 return 0; 751} 752 753/* Watermark encode 754 * Bit 8: Unit; 0:1, 1:16 755 * Bit 7-0: Value to be multiplied with unit 756 */ 757static u16 ocelot_wm_enc(u16 value) 758{ 759 WARN_ON(value >= 16 * BIT(8)); 760 761 if (value >= BIT(8)) 762 return BIT(8) | (value / 16); 763 764 return value; 765} 766 767static const struct ocelot_ops ocelot_ops = { 768 .reset = ocelot_reset, 769 .wm_enc = ocelot_wm_enc, 770 .port_to_netdev = ocelot_port_to_netdev, 771 .netdev_to_port = ocelot_netdev_to_port, 772}; 773 774static const struct vcap_field vsc7514_vcap_es0_keys[] = { 775 [VCAP_ES0_EGR_PORT] = { 0, 4}, 776 [VCAP_ES0_IGR_PORT] = { 4, 4}, 777 [VCAP_ES0_RSV] = { 8, 2}, 778 [VCAP_ES0_L2_MC] = { 10, 1}, 779 [VCAP_ES0_L2_BC] = { 11, 1}, 780 [VCAP_ES0_VID] = { 12, 12}, 781 [VCAP_ES0_DP] = { 24, 1}, 782 [VCAP_ES0_PCP] = { 25, 3}, 783}; 784 785static const struct vcap_field vsc7514_vcap_es0_actions[] = { 786 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 787 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 788 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 789 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 790 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 791 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 792 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 793 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 794 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 795 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 796 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 797 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 798 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 799 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 800 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 801 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 802 [VCAP_ES0_ACT_RSV] = { 49, 24}, 803 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1}, 804}; 805 806static const struct vcap_field vsc7514_vcap_is1_keys[] = { 807 [VCAP_IS1_HK_TYPE] = { 0, 1}, 808 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 809 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12}, 810 [VCAP_IS1_HK_RSV] = { 15, 9}, 811 [VCAP_IS1_HK_OAM_Y1731] = { 24, 1}, 812 [VCAP_IS1_HK_L2_MC] = { 25, 1}, 813 [VCAP_IS1_HK_L2_BC] = { 26, 1}, 814 [VCAP_IS1_HK_IP_MC] = { 27, 1}, 815 [VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1}, 816 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1}, 817 [VCAP_IS1_HK_TPID] = { 30, 1}, 818 [VCAP_IS1_HK_VID] = { 31, 12}, 819 [VCAP_IS1_HK_DEI] = { 43, 1}, 820 [VCAP_IS1_HK_PCP] = { 44, 3}, 821 /* Specific Fields for IS1 Half Key S1_NORMAL */ 822 [VCAP_IS1_HK_L2_SMAC] = { 47, 48}, 823 [VCAP_IS1_HK_ETYPE_LEN] = { 95, 1}, 824 [VCAP_IS1_HK_ETYPE] = { 96, 16}, 825 [VCAP_IS1_HK_IP_SNAP] = {112, 1}, 826 [VCAP_IS1_HK_IP4] = {113, 1}, 827 /* Layer-3 Information */ 828 [VCAP_IS1_HK_L3_FRAGMENT] = {114, 1}, 829 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {115, 1}, 830 [VCAP_IS1_HK_L3_OPTIONS] = {116, 1}, 831 [VCAP_IS1_HK_L3_DSCP] = {117, 6}, 832 [VCAP_IS1_HK_L3_IP4_SIP] = {123, 32}, 833 /* Layer-4 Information */ 834 [VCAP_IS1_HK_TCP_UDP] = {155, 1}, 835 [VCAP_IS1_HK_TCP] = {156, 1}, 836 [VCAP_IS1_HK_L4_SPORT] = {157, 16}, 837 [VCAP_IS1_HK_L4_RNG] = {173, 8}, 838 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 839 [VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1}, 840 [VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12}, 841 [VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1}, 842 [VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3}, 843 [VCAP_IS1_HK_IP4_IP4] = { 64, 1}, 844 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1}, 845 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1}, 846 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1}, 847 [VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6}, 848 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32}, 849 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {106, 32}, 850 [VCAP_IS1_HK_IP4_L3_PROTO] = {138, 8}, 851 [VCAP_IS1_HK_IP4_TCP_UDP] = {146, 1}, 852 [VCAP_IS1_HK_IP4_TCP] = {147, 1}, 853 [VCAP_IS1_HK_IP4_L4_RNG] = {148, 8}, 854 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {156, 32}, 855}; 856 857static const struct vcap_field vsc7514_vcap_is1_actions[] = { 858 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 859 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 860 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 861 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 862 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 863 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 864 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 865 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 866 [VCAP_IS1_ACT_RSV] = { 29, 9}, 867 /* The fields below are incorrectly shifted by 2 in the manual */ 868 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 869 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 870 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 871 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 872 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 873 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 874 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 875 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 876 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 877 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 878 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 879}; 880 881static const struct vcap_field vsc7514_vcap_is2_keys[] = { 882 /* Common: 46 bits */ 883 [VCAP_IS2_TYPE] = { 0, 4}, 884 [VCAP_IS2_HK_FIRST] = { 4, 1}, 885 [VCAP_IS2_HK_PAG] = { 5, 8}, 886 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 887 [VCAP_IS2_HK_RSV2] = { 25, 1}, 888 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 889 [VCAP_IS2_HK_L2_MC] = { 27, 1}, 890 [VCAP_IS2_HK_L2_BC] = { 28, 1}, 891 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 892 [VCAP_IS2_HK_VID] = { 30, 12}, 893 [VCAP_IS2_HK_DEI] = { 42, 1}, 894 [VCAP_IS2_HK_PCP] = { 43, 3}, 895 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 896 [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 897 [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 898 /* MAC_ETYPE (TYPE=000) */ 899 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 900 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 901 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 902 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 903 /* MAC_LLC (TYPE=001) */ 904 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 905 /* MAC_SNAP (TYPE=010) */ 906 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 907 /* MAC_ARP (TYPE=011) */ 908 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 909 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 910 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 911 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 912 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 913 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 914 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 915 [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 916 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 917 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 918 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 919 /* IP4_TCP_UDP / IP4_OTHER common */ 920 [VCAP_IS2_HK_IP4] = { 46, 1}, 921 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 922 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 923 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 924 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 925 [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 926 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 927 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 928 [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 929 /* IP4_TCP_UDP (TYPE=100) */ 930 [VCAP_IS2_HK_TCP] = {124, 1}, 931 [VCAP_IS2_HK_L4_DPORT] = {125, 16}, 932 [VCAP_IS2_HK_L4_SPORT] = {141, 16}, 933 [VCAP_IS2_HK_L4_RNG] = {157, 8}, 934 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 935 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 936 [VCAP_IS2_HK_L4_FIN] = {167, 1}, 937 [VCAP_IS2_HK_L4_SYN] = {168, 1}, 938 [VCAP_IS2_HK_L4_RST] = {169, 1}, 939 [VCAP_IS2_HK_L4_PSH] = {170, 1}, 940 [VCAP_IS2_HK_L4_ACK] = {171, 1}, 941 [VCAP_IS2_HK_L4_URG] = {172, 1}, 942 [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 943 [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 944 /* IP4_OTHER (TYPE=101) */ 945 [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 946 [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 947 /* IP6_STD (TYPE=110) */ 948 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 949 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 950 [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 951 /* OAM (TYPE=111) */ 952 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 953 [VCAP_IS2_HK_OAM_VER] = {149, 5}, 954 [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 955 [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 956 [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 957 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 958 [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 959}; 960 961static const struct vcap_field vsc7514_vcap_is2_actions[] = { 962 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 963 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 964 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 965 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 966 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 967 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 968 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 969 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 970 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 971 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 972 [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 973 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 974 [VCAP_IS2_ACT_RSV] = { 41, 2}, 975 [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 976 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 977}; 978 979static struct vcap_props vsc7514_vcap_props[] = { 980 [VCAP_ES0] = { 981 .action_type_width = 0, 982 .action_table = { 983 [ES0_ACTION_TYPE_NORMAL] = { 984 .width = 73, /* HIT_STICKY not included */ 985 .count = 1, 986 }, 987 }, 988 .target = S0, 989 .keys = vsc7514_vcap_es0_keys, 990 .actions = vsc7514_vcap_es0_actions, 991 }, 992 [VCAP_IS1] = { 993 .action_type_width = 0, 994 .action_table = { 995 [IS1_ACTION_TYPE_NORMAL] = { 996 .width = 78, /* HIT_STICKY not included */ 997 .count = 4, 998 }, 999 }, 1000 .target = S1, 1001 .keys = vsc7514_vcap_is1_keys, 1002 .actions = vsc7514_vcap_is1_actions, 1003 }, 1004 [VCAP_IS2] = { 1005 .action_type_width = 1, 1006 .action_table = { 1007 [IS2_ACTION_TYPE_NORMAL] = { 1008 .width = 49, 1009 .count = 2 1010 }, 1011 [IS2_ACTION_TYPE_SMAC_SIP] = { 1012 .width = 6, 1013 .count = 4 1014 }, 1015 }, 1016 .target = S2, 1017 .keys = vsc7514_vcap_is2_keys, 1018 .actions = vsc7514_vcap_is2_actions, 1019 }, 1020}; 1021 1022static struct ptp_clock_info ocelot_ptp_clock_info = { 1023 .owner = THIS_MODULE, 1024 .name = "ocelot ptp", 1025 .max_adj = 0x7fffffff, 1026 .n_alarm = 0, 1027 .n_ext_ts = 0, 1028 .n_per_out = OCELOT_PTP_PINS_NUM, 1029 .n_pins = OCELOT_PTP_PINS_NUM, 1030 .pps = 0, 1031 .gettime64 = ocelot_ptp_gettime64, 1032 .settime64 = ocelot_ptp_settime64, 1033 .adjtime = ocelot_ptp_adjtime, 1034 .adjfine = ocelot_ptp_adjfine, 1035 .verify = ocelot_ptp_verify, 1036 .enable = ocelot_ptp_enable, 1037}; 1038 1039static void mscc_ocelot_release_ports(struct ocelot *ocelot) 1040{ 1041 int port; 1042 1043 for (port = 0; port < ocelot->num_phys_ports; port++) { 1044 struct ocelot_port_private *priv; 1045 struct ocelot_port *ocelot_port; 1046 1047 ocelot_port = ocelot->ports[port]; 1048 if (!ocelot_port) 1049 continue; 1050 1051 ocelot_deinit_port(ocelot, port); 1052 1053 priv = container_of(ocelot_port, struct ocelot_port_private, 1054 port); 1055 1056 unregister_netdev(priv->dev); 1057 free_netdev(priv->dev); 1058 } 1059} 1060 1061static int mscc_ocelot_init_ports(struct platform_device *pdev, 1062 struct device_node *ports) 1063{ 1064 struct ocelot *ocelot = platform_get_drvdata(pdev); 1065 struct device_node *portnp; 1066 int err; 1067 1068 ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1069 sizeof(struct ocelot_port *), GFP_KERNEL); 1070 if (!ocelot->ports) 1071 return -ENOMEM; 1072 1073 for_each_available_child_of_node(ports, portnp) { 1074 struct ocelot_port_private *priv; 1075 struct ocelot_port *ocelot_port; 1076 struct device_node *phy_node; 1077 phy_interface_t phy_mode; 1078 struct phy_device *phy; 1079 struct regmap *target; 1080 struct resource *res; 1081 struct phy *serdes; 1082 char res_name[8]; 1083 u32 port; 1084 1085 if (of_property_read_u32(portnp, "reg", &port)) 1086 continue; 1087 1088 snprintf(res_name, sizeof(res_name), "port%d", port); 1089 1090 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1091 res_name); 1092 target = ocelot_regmap_init(ocelot, res); 1093 if (IS_ERR(target)) 1094 continue; 1095 1096 phy_node = of_parse_phandle(portnp, "phy-handle", 0); 1097 if (!phy_node) 1098 continue; 1099 1100 phy = of_phy_find_device(phy_node); 1101 of_node_put(phy_node); 1102 if (!phy) 1103 continue; 1104 1105 err = ocelot_probe_port(ocelot, port, target, phy); 1106 if (err) { 1107 of_node_put(portnp); 1108 return err; 1109 } 1110 1111 ocelot_port = ocelot->ports[port]; 1112 priv = container_of(ocelot_port, struct ocelot_port_private, 1113 port); 1114 1115 of_get_phy_mode(portnp, &phy_mode); 1116 1117 ocelot_port->phy_mode = phy_mode; 1118 1119 switch (ocelot_port->phy_mode) { 1120 case PHY_INTERFACE_MODE_NA: 1121 continue; 1122 case PHY_INTERFACE_MODE_SGMII: 1123 break; 1124 case PHY_INTERFACE_MODE_QSGMII: 1125 /* Ensure clock signals and speed is set on all 1126 * QSGMII links 1127 */ 1128 ocelot_port_writel(ocelot_port, 1129 DEV_CLOCK_CFG_LINK_SPEED 1130 (OCELOT_SPEED_1000), 1131 DEV_CLOCK_CFG); 1132 break; 1133 default: 1134 dev_err(ocelot->dev, 1135 "invalid phy mode for port%d, (Q)SGMII only\n", 1136 port); 1137 of_node_put(portnp); 1138 return -EINVAL; 1139 } 1140 1141 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); 1142 if (IS_ERR(serdes)) { 1143 err = PTR_ERR(serdes); 1144 if (err == -EPROBE_DEFER) 1145 dev_dbg(ocelot->dev, "deferring probe\n"); 1146 else 1147 dev_err(ocelot->dev, 1148 "missing SerDes phys for port%d\n", 1149 port); 1150 1151 of_node_put(portnp); 1152 return err; 1153 } 1154 1155 priv->serdes = serdes; 1156 } 1157 1158 return 0; 1159} 1160 1161static int mscc_ocelot_probe(struct platform_device *pdev) 1162{ 1163 struct device_node *np = pdev->dev.of_node; 1164 int err, irq_xtr, irq_ptp_rdy; 1165 struct device_node *ports; 1166 struct ocelot *ocelot; 1167 struct regmap *hsio; 1168 unsigned int i; 1169 1170 struct { 1171 enum ocelot_target id; 1172 char *name; 1173 u8 optional:1; 1174 } io_target[] = { 1175 { SYS, "sys" }, 1176 { REW, "rew" }, 1177 { QSYS, "qsys" }, 1178 { ANA, "ana" }, 1179 { QS, "qs" }, 1180 { S0, "s0" }, 1181 { S1, "s1" }, 1182 { S2, "s2" }, 1183 { PTP, "ptp", 1 }, 1184 }; 1185 1186 if (!np && !pdev->dev.platform_data) 1187 return -ENODEV; 1188 1189 ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL); 1190 if (!ocelot) 1191 return -ENOMEM; 1192 1193 platform_set_drvdata(pdev, ocelot); 1194 ocelot->dev = &pdev->dev; 1195 1196 for (i = 0; i < ARRAY_SIZE(io_target); i++) { 1197 struct regmap *target; 1198 struct resource *res; 1199 1200 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1201 io_target[i].name); 1202 1203 target = ocelot_regmap_init(ocelot, res); 1204 if (IS_ERR(target)) { 1205 if (io_target[i].optional) { 1206 ocelot->targets[io_target[i].id] = NULL; 1207 continue; 1208 } 1209 return PTR_ERR(target); 1210 } 1211 1212 ocelot->targets[io_target[i].id] = target; 1213 } 1214 1215 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 1216 if (IS_ERR(hsio)) { 1217 dev_err(&pdev->dev, "missing hsio syscon\n"); 1218 return PTR_ERR(hsio); 1219 } 1220 1221 ocelot->targets[HSIO] = hsio; 1222 1223 err = ocelot_chip_init(ocelot, &ocelot_ops); 1224 if (err) 1225 return err; 1226 1227 irq_xtr = platform_get_irq_byname(pdev, "xtr"); 1228 if (irq_xtr < 0) 1229 return -ENODEV; 1230 1231 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 1232 ocelot_xtr_irq_handler, IRQF_ONESHOT, 1233 "frame extraction", ocelot); 1234 if (err) 1235 return err; 1236 1237 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 1238 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 1239 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 1240 ocelot_ptp_rdy_irq_handler, 1241 IRQF_ONESHOT, "ptp ready", 1242 ocelot); 1243 if (err) 1244 return err; 1245 1246 /* Both the PTP interrupt and the PTP bank are available */ 1247 ocelot->ptp = 1; 1248 } 1249 1250 ports = of_get_child_by_name(np, "ethernet-ports"); 1251 if (!ports) { 1252 dev_err(ocelot->dev, "no ethernet-ports child node found\n"); 1253 return -ENODEV; 1254 } 1255 1256 ocelot->num_phys_ports = of_get_child_count(ports); 1257 ocelot->num_flooding_pgids = 1; 1258 1259 ocelot->vcap = vsc7514_vcap_props; 1260 ocelot->inj_prefix = OCELOT_TAG_PREFIX_NONE; 1261 ocelot->xtr_prefix = OCELOT_TAG_PREFIX_NONE; 1262 ocelot->npi = -1; 1263 1264 err = ocelot_init(ocelot); 1265 if (err) 1266 goto out_put_ports; 1267 1268 err = mscc_ocelot_init_ports(pdev, ports); 1269 if (err) 1270 goto out_ocelot_deinit; 1271 1272 if (ocelot->ptp) { 1273 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 1274 if (err) { 1275 dev_err(ocelot->dev, 1276 "Timestamp initialization failed\n"); 1277 ocelot->ptp = 0; 1278 } 1279 } 1280 1281 register_netdevice_notifier(&ocelot_netdevice_nb); 1282 register_switchdev_notifier(&ocelot_switchdev_nb); 1283 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1284 1285 of_node_put(ports); 1286 1287 dev_info(&pdev->dev, "Ocelot switch probed\n"); 1288 1289 return 0; 1290 1291out_ocelot_deinit: 1292 ocelot_deinit(ocelot); 1293out_put_ports: 1294 of_node_put(ports); 1295 return err; 1296} 1297 1298static int mscc_ocelot_remove(struct platform_device *pdev) 1299{ 1300 struct ocelot *ocelot = platform_get_drvdata(pdev); 1301 1302 ocelot_deinit_timestamp(ocelot); 1303 mscc_ocelot_release_ports(ocelot); 1304 ocelot_deinit(ocelot); 1305 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1306 unregister_switchdev_notifier(&ocelot_switchdev_nb); 1307 unregister_netdevice_notifier(&ocelot_netdevice_nb); 1308 1309 return 0; 1310} 1311 1312static struct platform_driver mscc_ocelot_driver = { 1313 .probe = mscc_ocelot_probe, 1314 .remove = mscc_ocelot_remove, 1315 .driver = { 1316 .name = "ocelot-switch", 1317 .of_match_table = mscc_ocelot_match, 1318 }, 1319}; 1320 1321module_platform_driver(mscc_ocelot_driver); 1322 1323MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1324MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1325MODULE_LICENSE("Dual MIT/GPL"); 1326