1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7#include <linux/if_bridge.h> 8#include <soc/mscc/ocelot_vcap.h> 9#include "ocelot.h" 10#include "ocelot_vcap.h" 11 12#define TABLE_UPDATE_SLEEP_US 10 13#define TABLE_UPDATE_TIMEOUT_US 100000 14 15struct ocelot_mact_entry { 16 u8 mac[ETH_ALEN]; 17 u16 vid; 18 enum macaccess_entry_type type; 19}; 20 21static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 22{ 23 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 24} 25 26static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 27{ 28 u32 val; 29 30 return readx_poll_timeout(ocelot_mact_read_macaccess, 31 ocelot, val, 32 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 33 MACACCESS_CMD_IDLE, 34 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 35} 36 37static void ocelot_mact_select(struct ocelot *ocelot, 38 const unsigned char mac[ETH_ALEN], 39 unsigned int vid) 40{ 41 u32 macl = 0, mach = 0; 42 43 /* Set the MAC address to handle and the vlan associated in a format 44 * understood by the hardware. 45 */ 46 mach |= vid << 16; 47 mach |= mac[0] << 8; 48 mach |= mac[1] << 0; 49 macl |= mac[2] << 24; 50 macl |= mac[3] << 16; 51 macl |= mac[4] << 8; 52 macl |= mac[5] << 0; 53 54 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 55 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 56 57} 58 59int ocelot_mact_learn(struct ocelot *ocelot, int port, 60 const unsigned char mac[ETH_ALEN], 61 unsigned int vid, enum macaccess_entry_type type) 62{ 63 u32 cmd = ANA_TABLES_MACACCESS_VALID | 64 ANA_TABLES_MACACCESS_DEST_IDX(port) | 65 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 66 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 67 unsigned int mc_ports; 68 69 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 70 if (type == ENTRYTYPE_MACv4) 71 mc_ports = (mac[1] << 8) | mac[2]; 72 else if (type == ENTRYTYPE_MACv6) 73 mc_ports = (mac[0] << 8) | mac[1]; 74 else 75 mc_ports = 0; 76 77 if (mc_ports & BIT(ocelot->num_phys_ports)) 78 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 79 80 ocelot_mact_select(ocelot, mac, vid); 81 82 /* Issue a write command */ 83 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 84 85 return ocelot_mact_wait_for_completion(ocelot); 86} 87EXPORT_SYMBOL(ocelot_mact_learn); 88 89int ocelot_mact_forget(struct ocelot *ocelot, 90 const unsigned char mac[ETH_ALEN], unsigned int vid) 91{ 92 ocelot_mact_select(ocelot, mac, vid); 93 94 /* Issue a forget command */ 95 ocelot_write(ocelot, 96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 97 ANA_TABLES_MACACCESS); 98 99 return ocelot_mact_wait_for_completion(ocelot); 100} 101EXPORT_SYMBOL(ocelot_mact_forget); 102 103static void ocelot_mact_init(struct ocelot *ocelot) 104{ 105 /* Configure the learning mode entries attributes: 106 * - Do not copy the frame to the CPU extraction queues. 107 * - Use the vlan and mac_cpoy for dmac lookup. 108 */ 109 ocelot_rmw(ocelot, 0, 110 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 111 | ANA_AGENCTRL_LEARN_FWD_KILL 112 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 113 ANA_AGENCTRL); 114 115 /* Clear the MAC table */ 116 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 117} 118 119static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 120{ 121 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 122 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 123 ANA_PORT_VCAP_S2_CFG, port); 124 125 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 126 ANA_PORT_VCAP_CFG, port); 127 128 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 129 REW_PORT_CFG_ES0_EN, 130 REW_PORT_CFG, port); 131} 132 133static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 134{ 135 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 136} 137 138static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 139{ 140 u32 val; 141 142 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 143 ocelot, 144 val, 145 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 146 ANA_TABLES_VLANACCESS_CMD_IDLE, 147 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 148} 149 150static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 151{ 152 /* Select the VID to configure */ 153 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 154 ANA_TABLES_VLANTIDX); 155 /* Set the vlan port members mask and issue a write command */ 156 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 157 ANA_TABLES_VLANACCESS_CMD_WRITE, 158 ANA_TABLES_VLANACCESS); 159 160 return ocelot_vlant_wait_for_completion(ocelot); 161} 162 163static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 164 u16 vid) 165{ 166 struct ocelot_port *ocelot_port = ocelot->ports[port]; 167 u32 val = 0; 168 169 if (ocelot_port->vid != vid) { 170 /* Always permit deleting the native VLAN (vid = 0) */ 171 if (ocelot_port->vid && vid) { 172 dev_err(ocelot->dev, 173 "Port already has a native VLAN: %d\n", 174 ocelot_port->vid); 175 return -EBUSY; 176 } 177 ocelot_port->vid = vid; 178 } 179 180 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 181 REW_PORT_VLAN_CFG_PORT_VID_M, 182 REW_PORT_VLAN_CFG, port); 183 184 if (ocelot_port->vlan_aware && !ocelot_port->vid) 185 /* If port is vlan-aware and tagged, drop untagged and priority 186 * tagged frames. 187 */ 188 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 189 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 190 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 191 ocelot_rmw_gix(ocelot, val, 192 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 193 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 194 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 195 ANA_PORT_DROP_CFG, port); 196 197 if (ocelot_port->vlan_aware) { 198 if (ocelot_port->vid) 199 /* Tag all frames except when VID == DEFAULT_VLAN */ 200 val = REW_TAG_CFG_TAG_CFG(1); 201 else 202 /* Tag all frames */ 203 val = REW_TAG_CFG_TAG_CFG(3); 204 } else { 205 /* Port tagging disabled. */ 206 val = REW_TAG_CFG_TAG_CFG(0); 207 } 208 ocelot_rmw_gix(ocelot, val, 209 REW_TAG_CFG_TAG_CFG_M, 210 REW_TAG_CFG, port); 211 212 return 0; 213} 214 215int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 216 bool vlan_aware, struct switchdev_trans *trans) 217{ 218 struct ocelot_port *ocelot_port = ocelot->ports[port]; 219 u32 val; 220 221 if (switchdev_trans_ph_prepare(trans)) { 222 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 223 struct ocelot_vcap_filter *filter; 224 225 list_for_each_entry(filter, &block->rules, list) { 226 if (filter->ingress_port_mask & BIT(port) && 227 filter->action.vid_replace_ena) { 228 dev_err(ocelot->dev, 229 "Cannot change VLAN state with vlan modify rules active\n"); 230 return -EBUSY; 231 } 232 } 233 234 return 0; 235 } 236 237 ocelot_port->vlan_aware = vlan_aware; 238 239 if (vlan_aware) 240 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 241 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 242 else 243 val = 0; 244 ocelot_rmw_gix(ocelot, val, 245 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 246 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 247 ANA_PORT_VLAN_CFG, port); 248 249 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 250 251 return 0; 252} 253EXPORT_SYMBOL(ocelot_port_vlan_filtering); 254 255/* Default vlan to clasify for untagged frames (may be zero) */ 256static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 257{ 258 struct ocelot_port *ocelot_port = ocelot->ports[port]; 259 260 ocelot_rmw_gix(ocelot, 261 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 262 ANA_PORT_VLAN_CFG_VLAN_VID_M, 263 ANA_PORT_VLAN_CFG, port); 264 265 ocelot_port->pvid = pvid; 266} 267 268int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 269 bool untagged) 270{ 271 int ret; 272 273 /* Make the port a member of the VLAN */ 274 ocelot->vlan_mask[vid] |= BIT(port); 275 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 276 if (ret) 277 return ret; 278 279 /* Default ingress vlan classification */ 280 if (pvid) 281 ocelot_port_set_pvid(ocelot, port, vid); 282 283 /* Untagged egress vlan clasification */ 284 if (untagged) { 285 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 286 if (ret) 287 return ret; 288 } 289 290 return 0; 291} 292EXPORT_SYMBOL(ocelot_vlan_add); 293 294int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 295{ 296 struct ocelot_port *ocelot_port = ocelot->ports[port]; 297 int ret; 298 299 /* Stop the port from being a member of the vlan */ 300 ocelot->vlan_mask[vid] &= ~BIT(port); 301 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 302 if (ret) 303 return ret; 304 305 /* Ingress */ 306 if (ocelot_port->pvid == vid) 307 ocelot_port_set_pvid(ocelot, port, 0); 308 309 /* Egress */ 310 if (ocelot_port->vid == vid) 311 ocelot_port_set_native_vlan(ocelot, port, 0); 312 313 return 0; 314} 315EXPORT_SYMBOL(ocelot_vlan_del); 316 317static void ocelot_vlan_init(struct ocelot *ocelot) 318{ 319 u16 port, vid; 320 321 /* Clear VLAN table, by default all ports are members of all VLANs */ 322 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 323 ANA_TABLES_VLANACCESS); 324 ocelot_vlant_wait_for_completion(ocelot); 325 326 /* Configure the port VLAN memberships */ 327 for (vid = 1; vid < VLAN_N_VID; vid++) { 328 ocelot->vlan_mask[vid] = 0; 329 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 330 } 331 332 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 333 * traffic. It is added automatically if 8021q module is loaded, but 334 * we can't rely on it since module may be not loaded. 335 */ 336 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 337 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 338 339 /* Set vlan ingress filter mask to all ports but the CPU port by 340 * default. 341 */ 342 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 343 ANA_VLANMASK); 344 345 for (port = 0; port < ocelot->num_phys_ports; port++) { 346 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 347 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 348 } 349} 350 351static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 352{ 353 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 354} 355 356int ocelot_port_flush(struct ocelot *ocelot, int port) 357{ 358 unsigned int pause_ena; 359 int err, val; 360 361 /* Disable dequeuing from the egress queues */ 362 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 363 QSYS_PORT_MODE_DEQUEUE_DIS, 364 QSYS_PORT_MODE, port); 365 366 /* Disable flow control */ 367 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 368 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 369 370 /* Disable priority flow control */ 371 ocelot_fields_write(ocelot, port, 372 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 373 374 /* Wait at least the time it takes to receive a frame of maximum length 375 * at the port. 376 * Worst-case delays for 10 kilobyte jumbo frames are: 377 * 8 ms on a 10M port 378 * 800 μs on a 100M port 379 * 80 μs on a 1G port 380 * 32 μs on a 2.5G port 381 */ 382 usleep_range(8000, 10000); 383 384 /* Disable half duplex backpressure. */ 385 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 386 SYS_FRONT_PORT_MODE, port); 387 388 /* Flush the queues associated with the port. */ 389 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 390 REW_PORT_CFG, port); 391 392 /* Enable dequeuing from the egress queues. */ 393 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 394 port); 395 396 /* Wait until flushing is complete. */ 397 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 398 100, 2000000, false, ocelot, port); 399 400 /* Clear flushing again. */ 401 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 402 403 /* Re-enable flow control */ 404 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 405 406 return err; 407} 408EXPORT_SYMBOL(ocelot_port_flush); 409 410void ocelot_adjust_link(struct ocelot *ocelot, int port, 411 struct phy_device *phydev) 412{ 413 struct ocelot_port *ocelot_port = ocelot->ports[port]; 414 int speed, mode = 0; 415 416 switch (phydev->speed) { 417 case SPEED_10: 418 speed = OCELOT_SPEED_10; 419 break; 420 case SPEED_100: 421 speed = OCELOT_SPEED_100; 422 break; 423 case SPEED_1000: 424 speed = OCELOT_SPEED_1000; 425 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 426 break; 427 case SPEED_2500: 428 speed = OCELOT_SPEED_2500; 429 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 430 break; 431 default: 432 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 433 port, phydev->speed); 434 return; 435 } 436 437 phy_print_status(phydev); 438 439 if (!phydev->link) 440 return; 441 442 /* Only full duplex supported for now */ 443 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 444 mode, DEV_MAC_MODE_CFG); 445 446 /* Disable HDX fast control */ 447 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 448 DEV_PORT_MISC); 449 450 /* SGMII only for now */ 451 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 452 PCS1G_MODE_CFG); 453 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 454 455 /* Enable PCS */ 456 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 457 458 /* No aneg on SGMII */ 459 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 460 461 /* No loopback */ 462 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 463 464 /* Enable MAC module */ 465 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 466 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 467 468 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 469 * reset */ 470 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 471 DEV_CLOCK_CFG); 472 473 /* No PFC */ 474 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 475 ANA_PFC_PFC_CFG, port); 476 477 /* Core: Enable port for frame transfer */ 478 ocelot_fields_write(ocelot, port, 479 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 480 481 /* Flow control */ 482 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 483 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 484 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 485 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 486 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 487 SYS_MAC_FC_CFG, port); 488 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 489} 490EXPORT_SYMBOL(ocelot_adjust_link); 491 492void ocelot_port_enable(struct ocelot *ocelot, int port, 493 struct phy_device *phy) 494{ 495 /* Enable receiving frames on the port, and activate auto-learning of 496 * MAC addresses. 497 */ 498 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 499 ANA_PORT_PORT_CFG_RECV_ENA | 500 ANA_PORT_PORT_CFG_PORTID_VAL(port), 501 ANA_PORT_PORT_CFG, port); 502} 503EXPORT_SYMBOL(ocelot_port_enable); 504 505void ocelot_port_disable(struct ocelot *ocelot, int port) 506{ 507 struct ocelot_port *ocelot_port = ocelot->ports[port]; 508 509 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 510 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 511} 512EXPORT_SYMBOL(ocelot_port_disable); 513 514void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 515 struct sk_buff *clone) 516{ 517 struct ocelot_port *ocelot_port = ocelot->ports[port]; 518 519 spin_lock(&ocelot_port->ts_id_lock); 520 521 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 522 /* Store timestamp ID in cb[0] of sk_buff */ 523 clone->cb[0] = ocelot_port->ts_id; 524 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 525 skb_queue_tail(&ocelot_port->tx_skbs, clone); 526 527 spin_unlock(&ocelot_port->ts_id_lock); 528} 529EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 530 531static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 532 struct timespec64 *ts) 533{ 534 unsigned long flags; 535 u32 val; 536 537 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 538 539 /* Read current PTP time to get seconds */ 540 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 541 542 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 543 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 544 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 545 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 546 547 /* Read packet HW timestamp from FIFO */ 548 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 549 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 550 551 /* Sec has incremented since the ts was registered */ 552 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 553 ts->tv_sec--; 554 555 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 556} 557 558void ocelot_get_txtstamp(struct ocelot *ocelot) 559{ 560 int budget = OCELOT_PTP_QUEUE_SZ; 561 562 while (budget--) { 563 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 564 struct skb_shared_hwtstamps shhwtstamps; 565 struct ocelot_port *port; 566 struct timespec64 ts; 567 unsigned long flags; 568 u32 val, id, txport; 569 570 val = ocelot_read(ocelot, SYS_PTP_STATUS); 571 572 /* Check if a timestamp can be retrieved */ 573 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 574 break; 575 576 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 577 578 /* Retrieve the ts ID and Tx port */ 579 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 580 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 581 582 /* Retrieve its associated skb */ 583 port = ocelot->ports[txport]; 584 585 spin_lock_irqsave(&port->tx_skbs.lock, flags); 586 587 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 588 if (skb->cb[0] != id) 589 continue; 590 __skb_unlink(skb, &port->tx_skbs); 591 skb_match = skb; 592 break; 593 } 594 595 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 596 597 if (WARN_ON(!skb_match)) 598 continue; 599 600 /* Get the h/w timestamp */ 601 ocelot_get_hwtimestamp(ocelot, &ts); 602 603 /* Set the timestamp into the skb */ 604 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 605 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 606 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 607 608 /* Next ts */ 609 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 610 } 611} 612EXPORT_SYMBOL(ocelot_get_txtstamp); 613 614int ocelot_fdb_add(struct ocelot *ocelot, int port, 615 const unsigned char *addr, u16 vid) 616{ 617 struct ocelot_port *ocelot_port = ocelot->ports[port]; 618 int pgid = port; 619 620 if (port == ocelot->npi) 621 pgid = PGID_CPU; 622 623 if (!vid) { 624 if (!ocelot_port->vlan_aware) 625 /* If the bridge is not VLAN aware and no VID was 626 * provided, set it to pvid to ensure the MAC entry 627 * matches incoming untagged packets 628 */ 629 vid = ocelot_port->pvid; 630 else 631 /* If the bridge is VLAN aware a VID must be provided as 632 * otherwise the learnt entry wouldn't match any frame. 633 */ 634 return -EINVAL; 635 } 636 637 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 638} 639EXPORT_SYMBOL(ocelot_fdb_add); 640 641int ocelot_fdb_del(struct ocelot *ocelot, int port, 642 const unsigned char *addr, u16 vid) 643{ 644 return ocelot_mact_forget(ocelot, addr, vid); 645} 646EXPORT_SYMBOL(ocelot_fdb_del); 647 648int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 649 bool is_static, void *data) 650{ 651 struct ocelot_dump_ctx *dump = data; 652 u32 portid = NETLINK_CB(dump->cb->skb).portid; 653 u32 seq = dump->cb->nlh->nlmsg_seq; 654 struct nlmsghdr *nlh; 655 struct ndmsg *ndm; 656 657 if (dump->idx < dump->cb->args[2]) 658 goto skip; 659 660 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 661 sizeof(*ndm), NLM_F_MULTI); 662 if (!nlh) 663 return -EMSGSIZE; 664 665 ndm = nlmsg_data(nlh); 666 ndm->ndm_family = AF_BRIDGE; 667 ndm->ndm_pad1 = 0; 668 ndm->ndm_pad2 = 0; 669 ndm->ndm_flags = NTF_SELF; 670 ndm->ndm_type = 0; 671 ndm->ndm_ifindex = dump->dev->ifindex; 672 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 673 674 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 675 goto nla_put_failure; 676 677 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 678 goto nla_put_failure; 679 680 nlmsg_end(dump->skb, nlh); 681 682skip: 683 dump->idx++; 684 return 0; 685 686nla_put_failure: 687 nlmsg_cancel(dump->skb, nlh); 688 return -EMSGSIZE; 689} 690EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 691 692static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 693 struct ocelot_mact_entry *entry) 694{ 695 u32 val, dst, macl, mach; 696 char mac[ETH_ALEN]; 697 698 /* Set row and column to read from */ 699 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 700 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 701 702 /* Issue a read command */ 703 ocelot_write(ocelot, 704 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 705 ANA_TABLES_MACACCESS); 706 707 if (ocelot_mact_wait_for_completion(ocelot)) 708 return -ETIMEDOUT; 709 710 /* Read the entry flags */ 711 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 712 if (!(val & ANA_TABLES_MACACCESS_VALID)) 713 return -EINVAL; 714 715 /* If the entry read has another port configured as its destination, 716 * do not report it. 717 */ 718 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 719 if (dst != port) 720 return -EINVAL; 721 722 /* Get the entry's MAC address and VLAN id */ 723 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 724 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 725 726 mac[0] = (mach >> 8) & 0xff; 727 mac[1] = (mach >> 0) & 0xff; 728 mac[2] = (macl >> 24) & 0xff; 729 mac[3] = (macl >> 16) & 0xff; 730 mac[4] = (macl >> 8) & 0xff; 731 mac[5] = (macl >> 0) & 0xff; 732 733 entry->vid = (mach >> 16) & 0xfff; 734 ether_addr_copy(entry->mac, mac); 735 736 return 0; 737} 738 739int ocelot_fdb_dump(struct ocelot *ocelot, int port, 740 dsa_fdb_dump_cb_t *cb, void *data) 741{ 742 int i, j; 743 744 /* Loop through all the mac tables entries. */ 745 for (i = 0; i < ocelot->num_mact_rows; i++) { 746 for (j = 0; j < 4; j++) { 747 struct ocelot_mact_entry entry; 748 bool is_static; 749 int ret; 750 751 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 752 /* If the entry is invalid (wrong port, invalid...), 753 * skip it. 754 */ 755 if (ret == -EINVAL) 756 continue; 757 else if (ret) 758 return ret; 759 760 is_static = (entry.type == ENTRYTYPE_LOCKED); 761 762 ret = cb(entry.mac, entry.vid, is_static, data); 763 if (ret) 764 return ret; 765 } 766 } 767 768 return 0; 769} 770EXPORT_SYMBOL(ocelot_fdb_dump); 771 772int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 773{ 774 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 775 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 776} 777EXPORT_SYMBOL(ocelot_hwstamp_get); 778 779int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 780{ 781 struct ocelot_port *ocelot_port = ocelot->ports[port]; 782 struct hwtstamp_config cfg; 783 784 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 785 return -EFAULT; 786 787 /* reserved for future extensions */ 788 if (cfg.flags) 789 return -EINVAL; 790 791 /* Tx type sanity check */ 792 switch (cfg.tx_type) { 793 case HWTSTAMP_TX_ON: 794 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 795 break; 796 case HWTSTAMP_TX_ONESTEP_SYNC: 797 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 798 * need to update the origin time. 799 */ 800 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 801 break; 802 case HWTSTAMP_TX_OFF: 803 ocelot_port->ptp_cmd = 0; 804 break; 805 default: 806 return -ERANGE; 807 } 808 809 mutex_lock(&ocelot->ptp_lock); 810 811 switch (cfg.rx_filter) { 812 case HWTSTAMP_FILTER_NONE: 813 break; 814 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 815 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 816 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 817 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 818 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 819 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 820 case HWTSTAMP_FILTER_PTP_V2_EVENT: 821 case HWTSTAMP_FILTER_PTP_V2_SYNC: 822 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 823 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 824 break; 825 default: 826 mutex_unlock(&ocelot->ptp_lock); 827 return -ERANGE; 828 } 829 830 /* Commit back the result & save it */ 831 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 832 mutex_unlock(&ocelot->ptp_lock); 833 834 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 835} 836EXPORT_SYMBOL(ocelot_hwstamp_set); 837 838void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 839{ 840 int i; 841 842 if (sset != ETH_SS_STATS) 843 return; 844 845 for (i = 0; i < ocelot->num_stats; i++) 846 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 847 ETH_GSTRING_LEN); 848} 849EXPORT_SYMBOL(ocelot_get_strings); 850 851static void ocelot_update_stats(struct ocelot *ocelot) 852{ 853 int i, j; 854 855 mutex_lock(&ocelot->stats_lock); 856 857 for (i = 0; i < ocelot->num_phys_ports; i++) { 858 /* Configure the port to read the stats from */ 859 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 860 861 for (j = 0; j < ocelot->num_stats; j++) { 862 u32 val; 863 unsigned int idx = i * ocelot->num_stats + j; 864 865 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 866 ocelot->stats_layout[j].offset); 867 868 if (val < (ocelot->stats[idx] & U32_MAX)) 869 ocelot->stats[idx] += (u64)1 << 32; 870 871 ocelot->stats[idx] = (ocelot->stats[idx] & 872 ~(u64)U32_MAX) + val; 873 } 874 } 875 876 mutex_unlock(&ocelot->stats_lock); 877} 878 879static void ocelot_check_stats_work(struct work_struct *work) 880{ 881 struct delayed_work *del_work = to_delayed_work(work); 882 struct ocelot *ocelot = container_of(del_work, struct ocelot, 883 stats_work); 884 885 ocelot_update_stats(ocelot); 886 887 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 888 OCELOT_STATS_CHECK_DELAY); 889} 890 891void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 892{ 893 int i; 894 895 /* check and update now */ 896 ocelot_update_stats(ocelot); 897 898 /* Copy all counters */ 899 for (i = 0; i < ocelot->num_stats; i++) 900 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 901} 902EXPORT_SYMBOL(ocelot_get_ethtool_stats); 903 904int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 905{ 906 if (sset != ETH_SS_STATS) 907 return -EOPNOTSUPP; 908 909 return ocelot->num_stats; 910} 911EXPORT_SYMBOL(ocelot_get_sset_count); 912 913int ocelot_get_ts_info(struct ocelot *ocelot, int port, 914 struct ethtool_ts_info *info) 915{ 916 info->phc_index = ocelot->ptp_clock ? 917 ptp_clock_index(ocelot->ptp_clock) : -1; 918 if (info->phc_index == -1) { 919 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 920 SOF_TIMESTAMPING_RX_SOFTWARE | 921 SOF_TIMESTAMPING_SOFTWARE; 922 return 0; 923 } 924 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 925 SOF_TIMESTAMPING_RX_SOFTWARE | 926 SOF_TIMESTAMPING_SOFTWARE | 927 SOF_TIMESTAMPING_TX_HARDWARE | 928 SOF_TIMESTAMPING_RX_HARDWARE | 929 SOF_TIMESTAMPING_RAW_HARDWARE; 930 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 931 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 932 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 933 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 934 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 935 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 936 937 return 0; 938} 939EXPORT_SYMBOL(ocelot_get_ts_info); 940 941void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 942{ 943 u32 port_cfg; 944 int p, i; 945 946 if (!(BIT(port) & ocelot->bridge_mask)) 947 return; 948 949 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 950 951 switch (state) { 952 case BR_STATE_FORWARDING: 953 ocelot->bridge_fwd_mask |= BIT(port); 954 fallthrough; 955 case BR_STATE_LEARNING: 956 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 957 break; 958 959 default: 960 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 961 ocelot->bridge_fwd_mask &= ~BIT(port); 962 break; 963 } 964 965 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 966 967 /* Apply FWD mask. The loop is needed to add/remove the current port as 968 * a source for the other ports. 969 */ 970 for (p = 0; p < ocelot->num_phys_ports; p++) { 971 if (ocelot->bridge_fwd_mask & BIT(p)) { 972 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 973 974 for (i = 0; i < ocelot->num_phys_ports; i++) { 975 unsigned long bond_mask = ocelot->lags[i]; 976 977 if (!bond_mask) 978 continue; 979 980 if (bond_mask & BIT(p)) { 981 mask &= ~bond_mask; 982 break; 983 } 984 } 985 986 ocelot_write_rix(ocelot, mask, 987 ANA_PGID_PGID, PGID_SRC + p); 988 } else { 989 ocelot_write_rix(ocelot, 0, 990 ANA_PGID_PGID, PGID_SRC + p); 991 } 992 } 993} 994EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 995 996void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 997{ 998 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 999 1000 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1001 * which is clearly not what our intention is. So avoid that. 1002 */ 1003 if (!age_period) 1004 age_period = 1; 1005 1006 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1007} 1008EXPORT_SYMBOL(ocelot_set_ageing_time); 1009 1010static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1011 const unsigned char *addr, 1012 u16 vid) 1013{ 1014 struct ocelot_multicast *mc; 1015 1016 list_for_each_entry(mc, &ocelot->multicast, list) { 1017 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1018 return mc; 1019 } 1020 1021 return NULL; 1022} 1023 1024static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1025{ 1026 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1027 return ENTRYTYPE_MACv4; 1028 if (addr[0] == 0x33 && addr[1] == 0x33) 1029 return ENTRYTYPE_MACv6; 1030 return ENTRYTYPE_NORMAL; 1031} 1032 1033static int ocelot_mdb_get_pgid(struct ocelot *ocelot, 1034 enum macaccess_entry_type entry_type) 1035{ 1036 int pgid; 1037 1038 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1039 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1040 * destination mask table (PGID), the destination set is programmed as 1041 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1042 */ 1043 if (entry_type == ENTRYTYPE_MACv4 || 1044 entry_type == ENTRYTYPE_MACv6) 1045 return 0; 1046 1047 for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) { 1048 struct ocelot_multicast *mc; 1049 bool used = false; 1050 1051 list_for_each_entry(mc, &ocelot->multicast, list) { 1052 if (mc->pgid == pgid) { 1053 used = true; 1054 break; 1055 } 1056 } 1057 1058 if (!used) 1059 return pgid; 1060 } 1061 1062 return -1; 1063} 1064 1065static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1066 struct ocelot_multicast *mc, 1067 enum macaccess_entry_type entry_type) 1068{ 1069 memcpy(addr, mc->addr, ETH_ALEN); 1070 1071 if (entry_type == ENTRYTYPE_MACv4) { 1072 addr[0] = 0; 1073 addr[1] = mc->ports >> 8; 1074 addr[2] = mc->ports & 0xff; 1075 } else if (entry_type == ENTRYTYPE_MACv6) { 1076 addr[0] = mc->ports >> 8; 1077 addr[1] = mc->ports & 0xff; 1078 } 1079} 1080 1081int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1082 const struct switchdev_obj_port_mdb *mdb) 1083{ 1084 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1085 enum macaccess_entry_type entry_type; 1086 unsigned char addr[ETH_ALEN]; 1087 struct ocelot_multicast *mc; 1088 u16 vid = mdb->vid; 1089 bool new = false; 1090 1091 if (port == ocelot->npi) 1092 port = ocelot->num_phys_ports; 1093 1094 if (!vid) 1095 vid = ocelot_port->pvid; 1096 1097 entry_type = ocelot_classify_mdb(mdb->addr); 1098 1099 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1100 if (!mc) { 1101 int pgid = ocelot_mdb_get_pgid(ocelot, entry_type); 1102 1103 if (pgid < 0) { 1104 dev_err(ocelot->dev, 1105 "No more PGIDs available for mdb %pM vid %d\n", 1106 mdb->addr, vid); 1107 return -ENOSPC; 1108 } 1109 1110 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1111 if (!mc) 1112 return -ENOMEM; 1113 1114 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1115 mc->vid = vid; 1116 mc->pgid = pgid; 1117 1118 list_add_tail(&mc->list, &ocelot->multicast); 1119 new = true; 1120 } 1121 1122 if (!new) { 1123 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1124 ocelot_mact_forget(ocelot, addr, vid); 1125 } 1126 1127 mc->ports |= BIT(port); 1128 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1129 1130 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1131} 1132EXPORT_SYMBOL(ocelot_port_mdb_add); 1133 1134int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1135 const struct switchdev_obj_port_mdb *mdb) 1136{ 1137 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1138 enum macaccess_entry_type entry_type; 1139 unsigned char addr[ETH_ALEN]; 1140 struct ocelot_multicast *mc; 1141 u16 vid = mdb->vid; 1142 1143 if (port == ocelot->npi) 1144 port = ocelot->num_phys_ports; 1145 1146 if (!vid) 1147 vid = ocelot_port->pvid; 1148 1149 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1150 if (!mc) 1151 return -ENOENT; 1152 1153 entry_type = ocelot_classify_mdb(mdb->addr); 1154 1155 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1156 ocelot_mact_forget(ocelot, addr, vid); 1157 1158 mc->ports &= ~BIT(port); 1159 if (!mc->ports) { 1160 list_del(&mc->list); 1161 devm_kfree(ocelot->dev, mc); 1162 return 0; 1163 } 1164 1165 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1166 1167 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1168} 1169EXPORT_SYMBOL(ocelot_port_mdb_del); 1170 1171int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1172 struct net_device *bridge) 1173{ 1174 if (!ocelot->bridge_mask) { 1175 ocelot->hw_bridge_dev = bridge; 1176 } else { 1177 if (ocelot->hw_bridge_dev != bridge) 1178 /* This is adding the port to a second bridge, this is 1179 * unsupported */ 1180 return -ENODEV; 1181 } 1182 1183 ocelot->bridge_mask |= BIT(port); 1184 1185 return 0; 1186} 1187EXPORT_SYMBOL(ocelot_port_bridge_join); 1188 1189int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1190 struct net_device *bridge) 1191{ 1192 struct switchdev_trans trans; 1193 int ret; 1194 1195 ocelot->bridge_mask &= ~BIT(port); 1196 1197 if (!ocelot->bridge_mask) 1198 ocelot->hw_bridge_dev = NULL; 1199 1200 trans.ph_prepare = true; 1201 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1202 if (ret) 1203 return ret; 1204 1205 trans.ph_prepare = false; 1206 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1207 if (ret) 1208 return ret; 1209 1210 ocelot_port_set_pvid(ocelot, port, 0); 1211 return ocelot_port_set_native_vlan(ocelot, port, 0); 1212} 1213EXPORT_SYMBOL(ocelot_port_bridge_leave); 1214 1215static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1216{ 1217 int i, port, lag; 1218 1219 /* Reset destination and aggregation PGIDS */ 1220 for_each_unicast_dest_pgid(ocelot, port) 1221 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1222 1223 for_each_aggr_pgid(ocelot, i) 1224 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1225 ANA_PGID_PGID, i); 1226 1227 /* Now, set PGIDs for each LAG */ 1228 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1229 unsigned long bond_mask; 1230 int aggr_count = 0; 1231 u8 aggr_idx[16]; 1232 1233 bond_mask = ocelot->lags[lag]; 1234 if (!bond_mask) 1235 continue; 1236 1237 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1238 // Destination mask 1239 ocelot_write_rix(ocelot, bond_mask, 1240 ANA_PGID_PGID, port); 1241 aggr_idx[aggr_count] = port; 1242 aggr_count++; 1243 } 1244 1245 for_each_aggr_pgid(ocelot, i) { 1246 u32 ac; 1247 1248 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1249 ac &= ~bond_mask; 1250 ac |= BIT(aggr_idx[i % aggr_count]); 1251 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1252 } 1253 } 1254} 1255 1256static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1257{ 1258 unsigned long bond_mask = ocelot->lags[lag]; 1259 unsigned int p; 1260 1261 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1262 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1263 1264 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1265 1266 /* Use lag port as logical port for port i */ 1267 ocelot_write_gix(ocelot, port_cfg | 1268 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1269 ANA_PORT_PORT_CFG, p); 1270 } 1271} 1272 1273int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1274 struct net_device *bond) 1275{ 1276 struct net_device *ndev; 1277 u32 bond_mask = 0; 1278 int lag, lp; 1279 1280 rcu_read_lock(); 1281 for_each_netdev_in_bond_rcu(bond, ndev) { 1282 struct ocelot_port_private *priv = netdev_priv(ndev); 1283 1284 bond_mask |= BIT(priv->chip_port); 1285 } 1286 rcu_read_unlock(); 1287 1288 lp = __ffs(bond_mask); 1289 1290 /* If the new port is the lowest one, use it as the logical port from 1291 * now on 1292 */ 1293 if (port == lp) { 1294 lag = port; 1295 ocelot->lags[port] = bond_mask; 1296 bond_mask &= ~BIT(port); 1297 if (bond_mask) { 1298 lp = __ffs(bond_mask); 1299 ocelot->lags[lp] = 0; 1300 } 1301 } else { 1302 lag = lp; 1303 ocelot->lags[lp] |= BIT(port); 1304 } 1305 1306 ocelot_setup_lag(ocelot, lag); 1307 ocelot_set_aggr_pgids(ocelot); 1308 1309 return 0; 1310} 1311EXPORT_SYMBOL(ocelot_port_lag_join); 1312 1313void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1314 struct net_device *bond) 1315{ 1316 u32 port_cfg; 1317 int i; 1318 1319 /* Remove port from any lag */ 1320 for (i = 0; i < ocelot->num_phys_ports; i++) 1321 ocelot->lags[i] &= ~BIT(port); 1322 1323 /* if it was the logical port of the lag, move the lag config to the 1324 * next port 1325 */ 1326 if (ocelot->lags[port]) { 1327 int n = __ffs(ocelot->lags[port]); 1328 1329 ocelot->lags[n] = ocelot->lags[port]; 1330 ocelot->lags[port] = 0; 1331 1332 ocelot_setup_lag(ocelot, n); 1333 } 1334 1335 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1336 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1337 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1338 ANA_PORT_PORT_CFG, port); 1339 1340 ocelot_set_aggr_pgids(ocelot); 1341} 1342EXPORT_SYMBOL(ocelot_port_lag_leave); 1343 1344/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1345 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1346 * In the special case that it's the NPI port that we're configuring, the 1347 * length of the tag and optional prefix needs to be accounted for privately, 1348 * in order to be able to sustain communication at the requested @sdu. 1349 */ 1350void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1351{ 1352 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1353 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1354 int pause_start, pause_stop; 1355 int atop, atop_tot; 1356 1357 if (port == ocelot->npi) { 1358 maxlen += OCELOT_TAG_LEN; 1359 1360 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1361 maxlen += OCELOT_SHORT_PREFIX_LEN; 1362 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1363 maxlen += OCELOT_LONG_PREFIX_LEN; 1364 } 1365 1366 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1367 1368 /* Set Pause watermark hysteresis */ 1369 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1370 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1371 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1372 pause_start); 1373 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1374 pause_stop); 1375 1376 /* Tail dropping watermarks */ 1377 atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) / 1378 OCELOT_BUFFER_CELL_SZ; 1379 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1380 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1381 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1382} 1383EXPORT_SYMBOL(ocelot_port_set_maxlen); 1384 1385int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1386{ 1387 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1388 1389 if (port == ocelot->npi) { 1390 max_mtu -= OCELOT_TAG_LEN; 1391 1392 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1393 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1394 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1395 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1396 } 1397 1398 return max_mtu; 1399} 1400EXPORT_SYMBOL(ocelot_get_max_mtu); 1401 1402void ocelot_init_port(struct ocelot *ocelot, int port) 1403{ 1404 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1405 1406 skb_queue_head_init(&ocelot_port->tx_skbs); 1407 spin_lock_init(&ocelot_port->ts_id_lock); 1408 1409 /* Basic L2 initialization */ 1410 1411 /* Set MAC IFG Gaps 1412 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1413 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1414 */ 1415 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1416 DEV_MAC_IFG_CFG); 1417 1418 /* Load seed (0) and set MAC HDX late collision */ 1419 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1420 DEV_MAC_HDX_CFG_SEED_LOAD, 1421 DEV_MAC_HDX_CFG); 1422 mdelay(1); 1423 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1424 DEV_MAC_HDX_CFG); 1425 1426 /* Set Max Length and maximum tags allowed */ 1427 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1428 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1429 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1430 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1431 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1432 DEV_MAC_TAGS_CFG); 1433 1434 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1435 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1436 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1437 1438 /* Enable transmission of pause frames */ 1439 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1440 1441 /* Drop frames with multicast source address */ 1442 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1443 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1444 ANA_PORT_DROP_CFG, port); 1445 1446 /* Set default VLAN and tag type to 8021Q. */ 1447 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1448 REW_PORT_VLAN_CFG_PORT_TPID_M, 1449 REW_PORT_VLAN_CFG, port); 1450 1451 /* Enable vcap lookups */ 1452 ocelot_vcap_enable(ocelot, port); 1453} 1454EXPORT_SYMBOL(ocelot_init_port); 1455 1456/* Configure and enable the CPU port module, which is a set of queues 1457 * accessible through register MMIO, frame DMA or Ethernet (in case 1458 * NPI mode is used). 1459 */ 1460static void ocelot_cpu_port_init(struct ocelot *ocelot) 1461{ 1462 int cpu = ocelot->num_phys_ports; 1463 1464 /* The unicast destination PGID for the CPU port module is unused */ 1465 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1466 /* Instead set up a multicast destination PGID for traffic copied to 1467 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1468 * addresses will be copied to the CPU via this PGID. 1469 */ 1470 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1471 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1472 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1473 ANA_PORT_PORT_CFG, cpu); 1474 1475 /* Enable CPU port module */ 1476 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1477 /* CPU port Injection/Extraction configuration */ 1478 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1479 ocelot->xtr_prefix); 1480 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1481 ocelot->inj_prefix); 1482 1483 /* Configure the CPU port to be VLAN aware */ 1484 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1485 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1486 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1487 ANA_PORT_VLAN_CFG, cpu); 1488} 1489 1490int ocelot_init(struct ocelot *ocelot) 1491{ 1492 char queue_name[32]; 1493 int i, ret; 1494 u32 port; 1495 1496 if (ocelot->ops->reset) { 1497 ret = ocelot->ops->reset(ocelot); 1498 if (ret) { 1499 dev_err(ocelot->dev, "Switch reset failed\n"); 1500 return ret; 1501 } 1502 } 1503 1504 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1505 sizeof(u32), GFP_KERNEL); 1506 if (!ocelot->lags) 1507 return -ENOMEM; 1508 1509 ocelot->stats = devm_kcalloc(ocelot->dev, 1510 ocelot->num_phys_ports * ocelot->num_stats, 1511 sizeof(u64), GFP_KERNEL); 1512 if (!ocelot->stats) 1513 return -ENOMEM; 1514 1515 mutex_init(&ocelot->stats_lock); 1516 mutex_init(&ocelot->ptp_lock); 1517 spin_lock_init(&ocelot->ptp_clock_lock); 1518 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1519 dev_name(ocelot->dev)); 1520 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1521 if (!ocelot->stats_queue) 1522 return -ENOMEM; 1523 1524 INIT_LIST_HEAD(&ocelot->multicast); 1525 ocelot_mact_init(ocelot); 1526 ocelot_vlan_init(ocelot); 1527 ocelot_vcap_init(ocelot); 1528 ocelot_cpu_port_init(ocelot); 1529 1530 for (port = 0; port < ocelot->num_phys_ports; port++) { 1531 /* Clear all counters (5 groups) */ 1532 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1533 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1534 SYS_STAT_CFG); 1535 } 1536 1537 /* Only use S-Tag */ 1538 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1539 1540 /* Aggregation mode */ 1541 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1542 ANA_AGGR_CFG_AC_DMAC_ENA | 1543 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1544 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1545 1546 /* Set MAC age time to default value. The entry is aged after 1547 * 2*AGE_PERIOD 1548 */ 1549 ocelot_write(ocelot, 1550 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1551 ANA_AUTOAGE); 1552 1553 /* Disable learning for frames discarded by VLAN ingress filtering */ 1554 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1555 1556 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1557 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1558 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1559 1560 /* Setup flooding PGIDs */ 1561 for (i = 0; i < ocelot->num_flooding_pgids; i++) 1562 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1563 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1564 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1565 ANA_FLOODING, i); 1566 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1567 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1568 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1569 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1570 ANA_FLOODING_IPMC); 1571 1572 for (port = 0; port < ocelot->num_phys_ports; port++) { 1573 /* Transmit the frame to the local port. */ 1574 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1575 /* Do not forward BPDU frames to the front ports. */ 1576 ocelot_write_gix(ocelot, 1577 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1578 ANA_PORT_CPU_FWD_BPDU_CFG, 1579 port); 1580 /* Ensure bridging is disabled */ 1581 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1582 } 1583 1584 /* Allow broadcast MAC frames. */ 1585 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1586 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1587 1588 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1589 } 1590 ocelot_write_rix(ocelot, 1591 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1592 ANA_PGID_PGID, PGID_MC); 1593 ocelot_write_rix(ocelot, 1594 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1595 ANA_PGID_PGID, PGID_MCIPV4); 1596 ocelot_write_rix(ocelot, 1597 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1598 ANA_PGID_PGID, PGID_MCIPV6); 1599 1600 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1601 * registers endianness. 1602 */ 1603 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1604 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1605 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1606 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1607 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1608 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1609 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1610 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1611 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1612 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1613 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1614 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1615 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1616 for (i = 0; i < 16; i++) 1617 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1618 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1619 ANA_CPUQ_8021_CFG, i); 1620 1621 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1622 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1623 OCELOT_STATS_CHECK_DELAY); 1624 1625 return 0; 1626} 1627EXPORT_SYMBOL(ocelot_init); 1628 1629void ocelot_deinit(struct ocelot *ocelot) 1630{ 1631 cancel_delayed_work(&ocelot->stats_work); 1632 destroy_workqueue(ocelot->stats_queue); 1633 mutex_destroy(&ocelot->stats_lock); 1634} 1635EXPORT_SYMBOL(ocelot_deinit); 1636 1637void ocelot_deinit_port(struct ocelot *ocelot, int port) 1638{ 1639 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1640 1641 skb_queue_purge(&ocelot_port->tx_skbs); 1642} 1643EXPORT_SYMBOL(ocelot_deinit_port); 1644 1645MODULE_LICENSE("Dual MIT/GPL"); 1646