1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4#ifndef _MLXSW_REG_H 5#define _MLXSW_REG_H 6 7#include <linux/kernel.h> 8#include <linux/string.h> 9#include <linux/bitops.h> 10#include <linux/if_vlan.h> 11 12#include "item.h" 13#include "port.h" 14 15struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19}; 20 21#define MLXSW_REG_DEFINE(_name, _id, _len) \ 22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26} 27 28#define MLXSW_REG(type) (&mlxsw_reg_##type) 29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32/* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36#define MLXSW_REG_SGCR_ID 0x2000 37#define MLXSW_REG_SGCR_LEN 0x10 38 39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41/* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50{ 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53} 54 55/* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59#define MLXSW_REG_SPAD_ID 0x2002 60#define MLXSW_REG_SPAD_LEN 0x10 61 62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64/* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72/* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78#define MLXSW_REG_SMID_ID 0x2007 79#define MLXSW_REG_SMID_LEN 0x240 80 81MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83/* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89/* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96/* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102/* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110{ 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116} 117 118/* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122#define MLXSW_REG_SSPR_ID 0x2008 123#define MLXSW_REG_SSPR_LEN 0x8 124 125MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127/* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139/* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146/* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154/* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165{ 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171} 172 173/* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178#define MLXSW_REG_SFDAT_ID 0x2009 179#define MLXSW_REG_SFDAT_LEN 0x8 180 181MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183/* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189/* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199{ 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203} 204 205/* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212#define MLXSW_REG_SFD_ID 0x200A 213#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215#define MLXSW_REG_SFD_REC_MAX_COUNT 64 216#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221/* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253}; 254 255/* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261/* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270/* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281{ 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285} 286 287/* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299}; 300 301/* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317}; 318 319/* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326/* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335/* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352}; 353 354/* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362/* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371/* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384/* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395{ 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404} 405 406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411{ 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418} 419 420static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423{ 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427} 428 429/* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437/* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450/* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457/* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464static inline void 465mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470{ 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479} 480 481static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484{ 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488} 489 490/* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500/* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508/* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517static inline void 518mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521{ 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527} 528 529/* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538/* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548}; 549 550/* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557/* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567static inline void 568mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573{ 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582} 583 584/* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589#define MLXSW_REG_SFN_ID 0x200B 590#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592#define MLXSW_REG_SFN_REC_MAX_COUNT 64 593#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598/* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604/* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610/* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620static inline void mlxsw_reg_sfn_pack(char *payload) 621{ 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 0); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626} 627 628/* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648}; 649 650/* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657/* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664/* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672/* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679/* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689{ 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693} 694 695/* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705{ 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709} 710 711/* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723}; 724 725/* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732/* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746}; 747 748/* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756static inline void 757mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760{ 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769} 770 771/* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775#define MLXSW_REG_SPMS_ID 0x200D 776#define MLXSW_REG_SPMS_LEN 0x404 777 778MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780/* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791}; 792 793/* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804{ 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807} 808 809static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811{ 812 mlxsw_reg_spms_state_set(payload, vid, state); 813} 814 815/* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819#define MLXSW_REG_SPVID_ID 0x200E 820#define MLXSW_REG_SPVID_LEN 0x08 821 822MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824/* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830/* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837/* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844{ 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848} 849 850/* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856#define MLXSW_REG_SPVM_ID 0x200F 857#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859#define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865/* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873/* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880/* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886/* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893/* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899/* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907/* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915/* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924/* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935{ 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949} 950 951/* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956#define MLXSW_REG_SPAFT_ID 0x2010 957#define MLXSW_REG_SPAFT_LEN 0x08 958 959MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961/* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969/* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976/* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982/* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988/* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996{ 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002} 1003 1004/* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009#define MLXSW_REG_SFGC_ID 0x2011 1010#define MLXSW_REG_SFGC_LEN 0x10 1011 1012MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024}; 1025 1026/* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035}; 1036 1037/* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050}; 1051 1052/* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060/* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067/* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073/* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079/* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085static inline void 1086mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090{ 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097} 1098 1099/* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104#define MLXSW_REG_SFTR_ID 0x2012 1105#define MLXSW_REG_SFTR_LEN 0x420 1106 1107MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109/* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115/* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122/* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129/* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135/* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141/* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147/* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158{ 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167} 1168 1169/* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174#define MLXSW_REG_SFDF_ID 0x2013 1175#define MLXSW_REG_SFDF_LEN 0x14 1176 1177MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179/* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194}; 1195 1196/* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212/* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222{ 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226} 1227 1228/* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234/* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240/* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246/* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252/* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258/* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264#define MLXSW_REG_SLDR_ID 0x2014 1265#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277}; 1278 1279/* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285/* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292{ 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296} 1297 1298static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299{ 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303} 1304 1305/* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313/* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321{ 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327} 1328 1329static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331{ 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337} 1338 1339/* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344#define MLXSW_REG_SLCR_ID 0x2015 1345#define MLXSW_REG_SLCR_LEN 0x10 1346 1347MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354}; 1355 1356/* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363/* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376}; 1377 1378/* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384/* Ingress port */ 1385#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386/* SMAC - for IPv4 and IPv6 packets */ 1387#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388/* SMAC - for non-IP packets */ 1389#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390#define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393/* DMAC - for IPv4 and IPv6 packets */ 1394#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395/* DMAC - for non-IP packets */ 1396#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397#define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400/* Ethertype - for IPv4 and IPv6 packets */ 1401#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402/* Ethertype - for non-IP packets */ 1403#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407/* VLAN ID - for IPv4 and IPv6 packets */ 1408#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409/* VLAN ID - for non-IP packets */ 1410#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411#define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414/* Source IP address (can be IPv4 or IPv6) */ 1415#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416/* Destination IP address (can be IPv4 or IPv6) */ 1417#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418/* TCP/UDP source port */ 1419#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420/* TCP/UDP destination port*/ 1421#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422/* IPv4 Protocol/IPv6 Next Header */ 1423#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424/* IPv6 Flow label */ 1425#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426/* SID - FCoE source ID */ 1427#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428/* DID - FCoE destination ID */ 1429#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430/* OXID - FCoE originator exchange ID */ 1431#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432/* Destination QP number - for RoCE packets */ 1433#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435/* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444/* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451{ 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457} 1458 1459/* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464#define MLXSW_REG_SLCOR_ID 0x2016 1465#define MLXSW_REG_SLCOR_LEN 0x10 1466 1467MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475}; 1476 1477/* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483/* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490/* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496/* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506{ 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511} 1512 1513static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516{ 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520} 1521 1522static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524{ 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527} 1528 1529static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531{ 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534} 1535 1536static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538{ 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541} 1542 1543/* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547#define MLXSW_REG_SPMLR_ID 0x2018 1548#define MLXSW_REG_SPMLR_LEN 0x8 1549 1550MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552/* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558/* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569}; 1570 1571/* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586{ 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591} 1592 1593/* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598#define MLXSW_REG_SVFA_ID 0x201C 1599#define MLXSW_REG_SVFA_LEN 0x10 1600 1601MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603/* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609/* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620}; 1621 1622/* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632/* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641/* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647/* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653/* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661/* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672{ 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681} 1682 1683/* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687#define MLXSW_REG_SVPE_ID 0x201E 1688#define MLXSW_REG_SVPE_LEN 0x4 1689 1690MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692/* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700/* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710{ 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714} 1715 1716/* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720#define MLXSW_REG_SFMR_ID 0x201F 1721#define MLXSW_REG_SFMR_LEN 0x18 1722 1723MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728}; 1729 1730/* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738/* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744/* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752/* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761/* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769/* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778/* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789{ 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796} 1797 1798/* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802#define MLXSW_REG_SPVMLR_ID 0x2020 1803#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812/* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820/* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826/* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834/* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844{ 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858} 1859 1860/* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864#define MLXSW_REG_CWTP_ID 0x2802 1865#define MLXSW_REG_CWTP_BASE_LEN 0x28 1866#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867#define MLXSW_REG_CWTP_LEN 0x40 1868 1869MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871/* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878/* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884/* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891/* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899/* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906#define MLXSW_REG_CWTP_MIN_VALUE 64 1907#define MLXSW_REG_CWTP_MAX_PROFILE 2 1908#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912{ 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925} 1926 1927#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929static inline void 1930mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932{ 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938} 1939 1940/* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944#define MLXSW_REG_CWTPM_ID 0x2803 1945#define MLXSW_REG_CWTPM_LEN 0x44 1946 1947MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949/* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956/* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962/* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970/* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978/* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986/* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994/* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002/* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010/* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018/* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026#define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031{ 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043} 2044 2045/* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049#define MLXSW_REG_PGCR_ID 0x3001 2050#define MLXSW_REG_PGCR_LEN 0x20 2051 2052MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054/* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062{ 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065} 2066 2067/* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071#define MLXSW_REG_PPBT_ID 0x3002 2072#define MLXSW_REG_PPBT_LEN 0x14 2073 2074MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079}; 2080 2081/* reg_ppbt_e 2082 * Access: Index 2083 */ 2084MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089}; 2090 2091/* reg_ppbt_op 2092 * Access: RW 2093 */ 2094MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096/* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102/* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110/* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120{ 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127} 2128 2129/* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133#define MLXSW_REG_PACL_ID 0x3004 2134#define MLXSW_REG_PACL_LEN 0x70 2135 2136MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138/* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145/* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154/* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164{ 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169} 2170 2171/* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175#define MLXSW_REG_PAGT_ID 0x3005 2176#define MLXSW_REG_PAGT_BASE_LEN 0x30 2177#define MLXSW_REG_PAGT_ACL_LEN 4 2178#define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184/* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195/* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202/* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210/* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217{ 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220} 2221 2222static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224{ 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231} 2232 2233/* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238#define MLXSW_REG_PTAR_ID 0x3006 2239#define MLXSW_REG_PTAR_BASE_LEN 0x20 2240#define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256}; 2257 2258/* reg_ptar_op 2259 * Access: OP 2260 */ 2261MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263/* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273}; 2274 2275/* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281/* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291/* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298/* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307/* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322{ 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330} 2331 2332static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334{ 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336} 2337 2338static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339{ 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341} 2342 2343/* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347#define MLXSW_REG_PPBS_ID 0x300C 2348#define MLXSW_REG_PPBS_LEN 0x14 2349 2350MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352/* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359/* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367{ 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371} 2372 2373/* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377#define MLXSW_REG_PRCR_ID 0x300D 2378#define MLXSW_REG_PRCR_LEN 0x40 2379 2380MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393}; 2394 2395/* reg_prcr_op 2396 * Access: OP 2397 */ 2398MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400/* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406/* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412/* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419/* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425/* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437{ 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447} 2448 2449/* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454#define MLXSW_REG_PEFA_ID 0x300F 2455#define MLXSW_REG_PEFA_LEN 0xB0 2456 2457MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459/* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465/* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474/* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484/* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493{ 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500} 2501 2502static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503{ 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505} 2506 2507/* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513#define MLXSW_REG_PEMRBT_ID 0x3014 2514#define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521}; 2522 2523/* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528/* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535static inline void 2536mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538{ 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542} 2543 2544/* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551#define MLXSW_REG_PTCE2_ID 0x3017 2552#define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556/* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562/* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585}; 2586 2587/* reg_ptce2_op 2588 * Access: OP 2589 */ 2590MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592/* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597/* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606/* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615/* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622/* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631/* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642{ 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649} 2650 2651/* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655#define MLXSW_REG_PERPT_ID 0x3021 2656#define MLXSW_REG_PERPT_LEN 0x80 2657 2658MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660/* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667/* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679}; 2680 2681/* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686/* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695/* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701/* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708/* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715/* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721/* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727/* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738{ 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743} 2744 2745static inline void 2746mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750{ 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761} 2762 2763/* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768#define MLXSW_REG_PERAR_ID 0x3026 2769#define MLXSW_REG_PERAR_LEN 0x08 2770 2771MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773/* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780static inline unsigned int 2781mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782{ 2783 return DIV_ROUND_UP(block_num, 4); 2784} 2785 2786/* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798{ 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802} 2803 2804/* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809#define MLXSW_REG_PTCE3_ID 0x3027 2810#define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814/* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831}; 2832 2833/* reg_ptce3_op 2834 * Access: OP 2835 */ 2836MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838/* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846/* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853/* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861/* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867/* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874/* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885/* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892/* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904/* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912/* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925/* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935/* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950{ 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964} 2965 2966/* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971#define MLXSW_REG_PERCR_ID 0x302A 2972#define MLXSW_REG_PERCR_LEN 0x80 2973 2974MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976/* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983/* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989/* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995/* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004/* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013{ 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019} 3020 3021/* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026#define MLXSW_REG_PERERP_ID 0x302B 3027#define MLXSW_REG_PERERP_LEN 0x1C 3028 3029MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031/* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038/* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044/* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050/* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057/* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066/* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075/* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086{ 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091} 3092 3093static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097{ 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105} 3106 3107/* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111#define MLXSW_REG_PEABFE_ID 0x3022 3112#define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121/* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128/* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138/* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147/* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156static inline void mlxsw_reg_peabfe_pack(char *payload) 3157{ 3158 MLXSW_REG_ZERO(peabfe, payload); 3159} 3160 3161static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163{ 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171} 3172 3173/* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179#define MLXSW_REG_IEDR_ID 0x3804 3180#define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181#define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182#define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189/* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195/* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202/* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209/* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216static inline void mlxsw_reg_iedr_pack(char *payload) 3217{ 3218 MLXSW_REG_ZERO(iedr, payload); 3219} 3220 3221static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224{ 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232} 3233 3234/* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239#define MLXSW_REG_QPTS_ID 0x4002 3240#define MLXSW_REG_QPTS_LEN 0x8 3241 3242MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244/* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255}; 3256 3257/* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265{ 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270} 3271 3272/* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277#define MLXSW_REG_QPCR_ID 0x4004 3278#define MLXSW_REG_QPCR_LEN 0x28 3279 3280MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285}; 3286 3287/* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293/* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299/* reg_qpcr_clear_counter 3300 * Clear counters. 3301 * Access: OP 3302 */ 3303MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3304 3305/* reg_qpcr_color_aware 3306 * Is the policer aware of colors. 3307 * Must be 0 (unaware) for cpu port. 3308 * Access: RW for unbounded policer. RO for bounded policer. 3309 */ 3310MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3311 3312/* reg_qpcr_bytes 3313 * Is policer limit is for bytes per sec or packets per sec. 3314 * 0 - packets 3315 * 1 - bytes 3316 * Access: RW for unbounded policer. RO for bounded policer. 3317 */ 3318MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3319 3320enum mlxsw_reg_qpcr_ir_units { 3321 MLXSW_REG_QPCR_IR_UNITS_M, 3322 MLXSW_REG_QPCR_IR_UNITS_K, 3323}; 3324 3325/* reg_qpcr_ir_units 3326 * Policer's units for cir and eir fields (for bytes limits only) 3327 * 1 - 10^3 3328 * 0 - 10^6 3329 * Access: OP 3330 */ 3331MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3332 3333enum mlxsw_reg_qpcr_rate_type { 3334 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3335 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3336}; 3337 3338/* reg_qpcr_rate_type 3339 * Policer can have one limit (single rate) or 2 limits with specific operation 3340 * for packets that exceed the lower rate but not the upper one. 3341 * (For cpu port must be single rate) 3342 * Access: RW for unbounded policer. RO for bounded policer. 3343 */ 3344MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3345 3346/* reg_qpc_cbs 3347 * Policer's committed burst size. 3348 * The policer is working with time slices of 50 nano sec. By default every 3349 * slice is granted the proportionate share of the committed rate. If we want to 3350 * allow a slice to exceed that share (while still keeping the rate per sec) we 3351 * can allow burst. The burst size is between the default proportionate share 3352 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3353 * committed rate will result in exceeding the rate). The burst size must be a 3354 * log of 2 and will be determined by 2^cbs. 3355 * Access: RW 3356 */ 3357MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3358 3359/* reg_qpcr_cir 3360 * Policer's committed rate. 3361 * The rate used for sungle rate, the lower rate for double rate. 3362 * For bytes limits, the rate will be this value * the unit from ir_units. 3363 * (Resolution error is up to 1%). 3364 * Access: RW 3365 */ 3366MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3367 3368/* reg_qpcr_eir 3369 * Policer's exceed rate. 3370 * The higher rate for double rate, reserved for single rate. 3371 * Lower rate for double rate policer. 3372 * For bytes limits, the rate will be this value * the unit from ir_units. 3373 * (Resolution error is up to 1%). 3374 * Access: RW 3375 */ 3376MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3377 3378#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3379 3380/* reg_qpcr_exceed_action. 3381 * What to do with packets between the 2 limits for double rate. 3382 * Access: RW for unbounded policer. RO for bounded policer. 3383 */ 3384MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3385 3386enum mlxsw_reg_qpcr_action { 3387 /* Discard */ 3388 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3389 /* Forward and set color to red. 3390 * If the packet is intended to cpu port, it will be dropped. 3391 */ 3392 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3393}; 3394 3395/* reg_qpcr_violate_action 3396 * What to do with packets that cross the cir limit (for single rate) or the eir 3397 * limit (for double rate). 3398 * Access: RW for unbounded policer. RO for bounded policer. 3399 */ 3400MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3401 3402/* reg_qpcr_violate_count 3403 * Counts the number of times violate_action happened on this PID. 3404 * Access: RW 3405 */ 3406MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3407 3408/* Packets */ 3409#define MLXSW_REG_QPCR_LOWEST_CIR 1 3410#define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3411#define MLXSW_REG_QPCR_LOWEST_CBS 4 3412#define MLXSW_REG_QPCR_HIGHEST_CBS 24 3413 3414/* Bandwidth */ 3415#define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3416#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3417#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3418#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3419#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3420#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3421 3422static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3423 enum mlxsw_reg_qpcr_ir_units ir_units, 3424 bool bytes, u32 cir, u16 cbs) 3425{ 3426 MLXSW_REG_ZERO(qpcr, payload); 3427 mlxsw_reg_qpcr_pid_set(payload, pid); 3428 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3429 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3430 mlxsw_reg_qpcr_violate_action_set(payload, 3431 MLXSW_REG_QPCR_ACTION_DISCARD); 3432 mlxsw_reg_qpcr_cir_set(payload, cir); 3433 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3434 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3435 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3436} 3437 3438/* QTCT - QoS Switch Traffic Class Table 3439 * ------------------------------------- 3440 * Configures the mapping between the packet switch priority and the 3441 * traffic class on the transmit port. 3442 */ 3443#define MLXSW_REG_QTCT_ID 0x400A 3444#define MLXSW_REG_QTCT_LEN 0x08 3445 3446MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3447 3448/* reg_qtct_local_port 3449 * Local port number. 3450 * Access: Index 3451 * 3452 * Note: CPU port is not supported. 3453 */ 3454MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3455 3456/* reg_qtct_sub_port 3457 * Virtual port within the physical port. 3458 * Should be set to 0 when virtual ports are not enabled on the port. 3459 * Access: Index 3460 */ 3461MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3462 3463/* reg_qtct_switch_prio 3464 * Switch priority. 3465 * Access: Index 3466 */ 3467MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3468 3469/* reg_qtct_tclass 3470 * Traffic class. 3471 * Default values: 3472 * switch_prio 0 : tclass 1 3473 * switch_prio 1 : tclass 0 3474 * switch_prio i : tclass i, for i > 1 3475 * Access: RW 3476 */ 3477MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3478 3479static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3480 u8 switch_prio, u8 tclass) 3481{ 3482 MLXSW_REG_ZERO(qtct, payload); 3483 mlxsw_reg_qtct_local_port_set(payload, local_port); 3484 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3485 mlxsw_reg_qtct_tclass_set(payload, tclass); 3486} 3487 3488/* QEEC - QoS ETS Element Configuration Register 3489 * --------------------------------------------- 3490 * Configures the ETS elements. 3491 */ 3492#define MLXSW_REG_QEEC_ID 0x400D 3493#define MLXSW_REG_QEEC_LEN 0x20 3494 3495MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3496 3497/* reg_qeec_local_port 3498 * Local port number. 3499 * Access: Index 3500 * 3501 * Note: CPU port is supported. 3502 */ 3503MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3504 3505enum mlxsw_reg_qeec_hr { 3506 MLXSW_REG_QEEC_HR_PORT, 3507 MLXSW_REG_QEEC_HR_GROUP, 3508 MLXSW_REG_QEEC_HR_SUBGROUP, 3509 MLXSW_REG_QEEC_HR_TC, 3510}; 3511 3512/* reg_qeec_element_hierarchy 3513 * 0 - Port 3514 * 1 - Group 3515 * 2 - Subgroup 3516 * 3 - Traffic Class 3517 * Access: Index 3518 */ 3519MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3520 3521/* reg_qeec_element_index 3522 * The index of the element in the hierarchy. 3523 * Access: Index 3524 */ 3525MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3526 3527/* reg_qeec_next_element_index 3528 * The index of the next (lower) element in the hierarchy. 3529 * Access: RW 3530 * 3531 * Note: Reserved for element_hierarchy 0. 3532 */ 3533MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3534 3535/* reg_qeec_mise 3536 * Min shaper configuration enable. Enables configuration of the min 3537 * shaper on this ETS element 3538 * 0 - Disable 3539 * 1 - Enable 3540 * Access: RW 3541 */ 3542MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3543 3544/* reg_qeec_ptps 3545 * PTP shaper 3546 * 0: regular shaper mode 3547 * 1: PTP oriented shaper 3548 * Allowed only for hierarchy 0 3549 * Not supported for CPU port 3550 * Note that ptps mode may affect the shaper rates of all hierarchies 3551 * Supported only on Spectrum-1 3552 * Access: RW 3553 */ 3554MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3555 3556enum { 3557 MLXSW_REG_QEEC_BYTES_MODE, 3558 MLXSW_REG_QEEC_PACKETS_MODE, 3559}; 3560 3561/* reg_qeec_pb 3562 * Packets or bytes mode. 3563 * 0 - Bytes mode 3564 * 1 - Packets mode 3565 * Access: RW 3566 * 3567 * Note: Used for max shaper configuration. For Spectrum, packets mode 3568 * is supported only for traffic classes of CPU port. 3569 */ 3570MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3571 3572/* The smallest permitted min shaper rate. */ 3573#define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3574 3575/* reg_qeec_min_shaper_rate 3576 * Min shaper information rate. 3577 * For CPU port, can only be configured for port hierarchy. 3578 * When in bytes mode, value is specified in units of 1000bps. 3579 * Access: RW 3580 */ 3581MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3582 3583/* reg_qeec_mase 3584 * Max shaper configuration enable. Enables configuration of the max 3585 * shaper on this ETS element. 3586 * 0 - Disable 3587 * 1 - Enable 3588 * Access: RW 3589 */ 3590MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3591 3592/* The largest max shaper value possible to disable the shaper. */ 3593#define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3594 3595/* reg_qeec_max_shaper_rate 3596 * Max shaper information rate. 3597 * For CPU port, can only be configured for port hierarchy. 3598 * When in bytes mode, value is specified in units of 1000bps. 3599 * Access: RW 3600 */ 3601MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3602 3603/* reg_qeec_de 3604 * DWRR configuration enable. Enables configuration of the dwrr and 3605 * dwrr_weight. 3606 * 0 - Disable 3607 * 1 - Enable 3608 * Access: RW 3609 */ 3610MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3611 3612/* reg_qeec_dwrr 3613 * Transmission selection algorithm to use on the link going down from 3614 * the ETS element. 3615 * 0 - Strict priority 3616 * 1 - DWRR 3617 * Access: RW 3618 */ 3619MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3620 3621/* reg_qeec_dwrr_weight 3622 * DWRR weight on the link going down from the ETS element. The 3623 * percentage of bandwidth guaranteed to an ETS element within 3624 * its hierarchy. The sum of all weights across all ETS elements 3625 * within one hierarchy should be equal to 100. Reserved when 3626 * transmission selection algorithm is strict priority. 3627 * Access: RW 3628 */ 3629MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3630 3631/* reg_qeec_max_shaper_bs 3632 * Max shaper burst size 3633 * Burst size is 2^max_shaper_bs * 512 bits 3634 * For Spectrum-1: Range is: 5..25 3635 * For Spectrum-2: Range is: 11..25 3636 * Reserved when ptps = 1 3637 * Access: RW 3638 */ 3639MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3640 3641#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3642#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3643#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3644#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 3645 3646static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3647 enum mlxsw_reg_qeec_hr hr, u8 index, 3648 u8 next_index) 3649{ 3650 MLXSW_REG_ZERO(qeec, payload); 3651 mlxsw_reg_qeec_local_port_set(payload, local_port); 3652 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3653 mlxsw_reg_qeec_element_index_set(payload, index); 3654 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3655} 3656 3657static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3658 bool ptps) 3659{ 3660 MLXSW_REG_ZERO(qeec, payload); 3661 mlxsw_reg_qeec_local_port_set(payload, local_port); 3662 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3663 mlxsw_reg_qeec_ptps_set(payload, ptps); 3664} 3665 3666/* QRWE - QoS ReWrite Enable 3667 * ------------------------- 3668 * This register configures the rewrite enable per receive port. 3669 */ 3670#define MLXSW_REG_QRWE_ID 0x400F 3671#define MLXSW_REG_QRWE_LEN 0x08 3672 3673MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3674 3675/* reg_qrwe_local_port 3676 * Local port number. 3677 * Access: Index 3678 * 3679 * Note: CPU port is supported. No support for router port. 3680 */ 3681MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3682 3683/* reg_qrwe_dscp 3684 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3685 * Access: RW 3686 */ 3687MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3688 3689/* reg_qrwe_pcp 3690 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3691 * Access: RW 3692 */ 3693MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3694 3695static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3696 bool rewrite_pcp, bool rewrite_dscp) 3697{ 3698 MLXSW_REG_ZERO(qrwe, payload); 3699 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3700 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3701 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3702} 3703 3704/* QPDSM - QoS Priority to DSCP Mapping 3705 * ------------------------------------ 3706 * QoS Priority to DSCP Mapping Register 3707 */ 3708#define MLXSW_REG_QPDSM_ID 0x4011 3709#define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3710#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3711#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3712#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3713 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3714 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3715 3716MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3717 3718/* reg_qpdsm_local_port 3719 * Local Port. Supported for data packets from CPU port. 3720 * Access: Index 3721 */ 3722MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3723 3724/* reg_qpdsm_prio_entry_color0_e 3725 * Enable update of the entry for color 0 and a given port. 3726 * Access: WO 3727 */ 3728MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3729 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3730 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3731 3732/* reg_qpdsm_prio_entry_color0_dscp 3733 * DSCP field in the outer label of the packet for color 0 and a given port. 3734 * Reserved when e=0. 3735 * Access: RW 3736 */ 3737MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3738 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3739 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3740 3741/* reg_qpdsm_prio_entry_color1_e 3742 * Enable update of the entry for color 1 and a given port. 3743 * Access: WO 3744 */ 3745MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3746 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3747 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3748 3749/* reg_qpdsm_prio_entry_color1_dscp 3750 * DSCP field in the outer label of the packet for color 1 and a given port. 3751 * Reserved when e=0. 3752 * Access: RW 3753 */ 3754MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3755 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3756 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3757 3758/* reg_qpdsm_prio_entry_color2_e 3759 * Enable update of the entry for color 2 and a given port. 3760 * Access: WO 3761 */ 3762MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3763 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3764 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3765 3766/* reg_qpdsm_prio_entry_color2_dscp 3767 * DSCP field in the outer label of the packet for color 2 and a given port. 3768 * Reserved when e=0. 3769 * Access: RW 3770 */ 3771MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3772 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3773 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3774 3775static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3776{ 3777 MLXSW_REG_ZERO(qpdsm, payload); 3778 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3779} 3780 3781static inline void 3782mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3783{ 3784 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3785 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3786 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3787 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3788 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3789 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3790} 3791 3792/* QPDP - QoS Port DSCP to Priority Mapping Register 3793 * ------------------------------------------------- 3794 * This register controls the port default Switch Priority and Color. The 3795 * default Switch Priority and Color are used for frames where the trust state 3796 * uses default values. All member ports of a LAG should be configured with the 3797 * same default values. 3798 */ 3799#define MLXSW_REG_QPDP_ID 0x4007 3800#define MLXSW_REG_QPDP_LEN 0x8 3801 3802MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 3803 3804/* reg_qpdp_local_port 3805 * Local Port. Supported for data packets from CPU port. 3806 * Access: Index 3807 */ 3808MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 3809 3810/* reg_qpdp_switch_prio 3811 * Default port Switch Priority (default 0) 3812 * Access: RW 3813 */ 3814MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 3815 3816static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 3817 u8 switch_prio) 3818{ 3819 MLXSW_REG_ZERO(qpdp, payload); 3820 mlxsw_reg_qpdp_local_port_set(payload, local_port); 3821 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 3822} 3823 3824/* QPDPM - QoS Port DSCP to Priority Mapping Register 3825 * -------------------------------------------------- 3826 * This register controls the mapping from DSCP field to 3827 * Switch Priority for IP packets. 3828 */ 3829#define MLXSW_REG_QPDPM_ID 0x4013 3830#define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3831#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3832#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3833#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3834 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3835 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3836 3837MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3838 3839/* reg_qpdpm_local_port 3840 * Local Port. Supported for data packets from CPU port. 3841 * Access: Index 3842 */ 3843MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3844 3845/* reg_qpdpm_dscp_e 3846 * Enable update of the specific entry. When cleared, the switch_prio and color 3847 * fields are ignored and the previous switch_prio and color values are 3848 * preserved. 3849 * Access: WO 3850 */ 3851MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3852 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3853 3854/* reg_qpdpm_dscp_prio 3855 * The new Switch Priority value for the relevant DSCP value. 3856 * Access: RW 3857 */ 3858MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3859 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3860 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3861 3862static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3863{ 3864 MLXSW_REG_ZERO(qpdpm, payload); 3865 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3866} 3867 3868static inline void 3869mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3870{ 3871 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3872 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3873} 3874 3875/* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3876 * ------------------------------------------------------------------ 3877 * This register configures if the Switch Priority to Traffic Class mapping is 3878 * based on Multicast packet indication. If so, then multicast packets will get 3879 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3880 * QTCT. 3881 * By default, Switch Priority to Traffic Class mapping is not based on 3882 * Multicast packet indication. 3883 */ 3884#define MLXSW_REG_QTCTM_ID 0x401A 3885#define MLXSW_REG_QTCTM_LEN 0x08 3886 3887MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3888 3889/* reg_qtctm_local_port 3890 * Local port number. 3891 * No support for CPU port. 3892 * Access: Index 3893 */ 3894MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3895 3896/* reg_qtctm_mc 3897 * Multicast Mode 3898 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3899 * indication (default is 0, not based on Multicast packet indication). 3900 */ 3901MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3902 3903static inline void 3904mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3905{ 3906 MLXSW_REG_ZERO(qtctm, payload); 3907 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3908 mlxsw_reg_qtctm_mc_set(payload, mc); 3909} 3910 3911/* QPSC - QoS PTP Shaper Configuration Register 3912 * -------------------------------------------- 3913 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 3914 * Supported only on Spectrum-1. 3915 */ 3916#define MLXSW_REG_QPSC_ID 0x401B 3917#define MLXSW_REG_QPSC_LEN 0x28 3918 3919MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 3920 3921enum mlxsw_reg_qpsc_port_speed { 3922 MLXSW_REG_QPSC_PORT_SPEED_100M, 3923 MLXSW_REG_QPSC_PORT_SPEED_1G, 3924 MLXSW_REG_QPSC_PORT_SPEED_10G, 3925 MLXSW_REG_QPSC_PORT_SPEED_25G, 3926}; 3927 3928/* reg_qpsc_port_speed 3929 * Port speed. 3930 * Access: Index 3931 */ 3932MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 3933 3934/* reg_qpsc_shaper_time_exp 3935 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3936 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3937 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3938 * Access: RW 3939 */ 3940MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 3941 3942/* reg_qpsc_shaper_time_mantissa 3943 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3944 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3945 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3946 * Access: RW 3947 */ 3948MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 3949 3950/* reg_qpsc_shaper_inc 3951 * Number of tokens added to shaper on each update. 3952 * Units of 8B. 3953 * Access: RW 3954 */ 3955MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 3956 3957/* reg_qpsc_shaper_bs 3958 * Max shaper Burst size. 3959 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 3960 * Range is: 5..25 (from 2KB..2GB) 3961 * Access: RW 3962 */ 3963MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 3964 3965/* reg_qpsc_ptsc_we 3966 * Write enable to port_to_shaper_credits. 3967 * Access: WO 3968 */ 3969MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 3970 3971/* reg_qpsc_port_to_shaper_credits 3972 * For split ports: range 1..57 3973 * For non-split ports: range 1..112 3974 * Written only when ptsc_we is set. 3975 * Access: RW 3976 */ 3977MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 3978 3979/* reg_qpsc_ing_timestamp_inc 3980 * Ingress timestamp increment. 3981 * 2's complement. 3982 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 3983 * value for all ports. 3984 * Same units as used by MTPPTR. 3985 * Access: RW 3986 */ 3987MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 3988 3989/* reg_qpsc_egr_timestamp_inc 3990 * Egress timestamp increment. 3991 * 2's complement. 3992 * The timestamp of MTPPTR at egress will be incremented by this value. Global 3993 * value for all ports. 3994 * Same units as used by MTPPTR. 3995 * Access: RW 3996 */ 3997MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 3998 3999static inline void 4000mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4001 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4002 u8 shaper_bs, u8 port_to_shaper_credits, 4003 int ing_timestamp_inc, int egr_timestamp_inc) 4004{ 4005 MLXSW_REG_ZERO(qpsc, payload); 4006 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4007 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4008 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4009 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4010 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4011 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4012 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4013 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4014 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4015} 4016 4017/* PMLP - Ports Module to Local Port Register 4018 * ------------------------------------------ 4019 * Configures the assignment of modules to local ports. 4020 */ 4021#define MLXSW_REG_PMLP_ID 0x5002 4022#define MLXSW_REG_PMLP_LEN 0x40 4023 4024MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4025 4026/* reg_pmlp_rxtx 4027 * 0 - Tx value is used for both Tx and Rx. 4028 * 1 - Rx value is taken from a separte field. 4029 * Access: RW 4030 */ 4031MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4032 4033/* reg_pmlp_local_port 4034 * Local port number. 4035 * Access: Index 4036 */ 4037MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4038 4039/* reg_pmlp_width 4040 * 0 - Unmap local port. 4041 * 1 - Lane 0 is used. 4042 * 2 - Lanes 0 and 1 are used. 4043 * 4 - Lanes 0, 1, 2 and 3 are used. 4044 * 8 - Lanes 0-7 are used. 4045 * Access: RW 4046 */ 4047MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4048 4049/* reg_pmlp_module 4050 * Module number. 4051 * Access: RW 4052 */ 4053MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4054 4055/* reg_pmlp_tx_lane 4056 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4057 * Access: RW 4058 */ 4059MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4060 4061/* reg_pmlp_rx_lane 4062 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4063 * equal to Tx lane. 4064 * Access: RW 4065 */ 4066MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4067 4068static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4069{ 4070 MLXSW_REG_ZERO(pmlp, payload); 4071 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4072} 4073 4074/* PMTU - Port MTU Register 4075 * ------------------------ 4076 * Configures and reports the port MTU. 4077 */ 4078#define MLXSW_REG_PMTU_ID 0x5003 4079#define MLXSW_REG_PMTU_LEN 0x10 4080 4081MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4082 4083/* reg_pmtu_local_port 4084 * Local port number. 4085 * Access: Index 4086 */ 4087MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4088 4089/* reg_pmtu_max_mtu 4090 * Maximum MTU. 4091 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4092 * reported, otherwise the minimum between the max_mtu of the different 4093 * types is reported. 4094 * Access: RO 4095 */ 4096MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4097 4098/* reg_pmtu_admin_mtu 4099 * MTU value to set port to. Must be smaller or equal to max_mtu. 4100 * Note: If port type is Infiniband, then port must be disabled, when its 4101 * MTU is set. 4102 * Access: RW 4103 */ 4104MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4105 4106/* reg_pmtu_oper_mtu 4107 * The actual MTU configured on the port. Packets exceeding this size 4108 * will be dropped. 4109 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4110 * oper_mtu might be smaller than admin_mtu. 4111 * Access: RO 4112 */ 4113MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4114 4115static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4116 u16 new_mtu) 4117{ 4118 MLXSW_REG_ZERO(pmtu, payload); 4119 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4120 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4121 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4122 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4123} 4124 4125/* PTYS - Port Type and Speed Register 4126 * ----------------------------------- 4127 * Configures and reports the port speed type. 4128 * 4129 * Note: When set while the link is up, the changes will not take effect 4130 * until the port transitions from down to up state. 4131 */ 4132#define MLXSW_REG_PTYS_ID 0x5004 4133#define MLXSW_REG_PTYS_LEN 0x40 4134 4135MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4136 4137/* an_disable_admin 4138 * Auto negotiation disable administrative configuration 4139 * 0 - Device doesn't support AN disable. 4140 * 1 - Device supports AN disable. 4141 * Access: RW 4142 */ 4143MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4144 4145/* reg_ptys_local_port 4146 * Local port number. 4147 * Access: Index 4148 */ 4149MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4150 4151#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4152#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4153 4154/* reg_ptys_proto_mask 4155 * Protocol mask. Indicates which protocol is used. 4156 * 0 - Infiniband. 4157 * 1 - Fibre Channel. 4158 * 2 - Ethernet. 4159 * Access: Index 4160 */ 4161MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4162 4163enum { 4164 MLXSW_REG_PTYS_AN_STATUS_NA, 4165 MLXSW_REG_PTYS_AN_STATUS_OK, 4166 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4167}; 4168 4169/* reg_ptys_an_status 4170 * Autonegotiation status. 4171 * Access: RO 4172 */ 4173MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4174 4175#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4176#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4177#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4178#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4179#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4180#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4181#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4182#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4183#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4184#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4185#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4186#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4187 4188/* reg_ptys_ext_eth_proto_cap 4189 * Extended Ethernet port supported speeds and protocols. 4190 * Access: RO 4191 */ 4192MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4193 4194#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4195#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4196#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4197#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4198#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4199#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4200#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4201#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4202#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4203#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4204#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4205#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4206#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4207#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4208#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4209#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4210#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4211#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4212#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4213#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4214#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4215#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4216#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4217 4218/* reg_ptys_eth_proto_cap 4219 * Ethernet port supported speeds and protocols. 4220 * Access: RO 4221 */ 4222MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4223 4224/* reg_ptys_ib_link_width_cap 4225 * IB port supported widths. 4226 * Access: RO 4227 */ 4228MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4229 4230#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4231#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4232#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4233#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4234#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4235#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4236 4237/* reg_ptys_ib_proto_cap 4238 * IB port supported speeds and protocols. 4239 * Access: RO 4240 */ 4241MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4242 4243/* reg_ptys_ext_eth_proto_admin 4244 * Extended speed and protocol to set port to. 4245 * Access: RW 4246 */ 4247MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4248 4249/* reg_ptys_eth_proto_admin 4250 * Speed and protocol to set port to. 4251 * Access: RW 4252 */ 4253MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4254 4255/* reg_ptys_ib_link_width_admin 4256 * IB width to set port to. 4257 * Access: RW 4258 */ 4259MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4260 4261/* reg_ptys_ib_proto_admin 4262 * IB speeds and protocols to set port to. 4263 * Access: RW 4264 */ 4265MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4266 4267/* reg_ptys_ext_eth_proto_oper 4268 * The extended current speed and protocol configured for the port. 4269 * Access: RO 4270 */ 4271MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4272 4273/* reg_ptys_eth_proto_oper 4274 * The current speed and protocol configured for the port. 4275 * Access: RO 4276 */ 4277MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4278 4279/* reg_ptys_ib_link_width_oper 4280 * The current IB width to set port to. 4281 * Access: RO 4282 */ 4283MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4284 4285/* reg_ptys_ib_proto_oper 4286 * The current IB speed and protocol. 4287 * Access: RO 4288 */ 4289MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4290 4291enum mlxsw_reg_ptys_connector_type { 4292 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4293 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4294 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4295 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4296 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4297 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4298 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4299 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4300 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4301}; 4302 4303/* reg_ptys_connector_type 4304 * Connector type indication. 4305 * Access: RO 4306 */ 4307MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4308 4309static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4310 u32 proto_admin, bool autoneg) 4311{ 4312 MLXSW_REG_ZERO(ptys, payload); 4313 mlxsw_reg_ptys_local_port_set(payload, local_port); 4314 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4315 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4316 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4317} 4318 4319static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4320 u32 proto_admin, bool autoneg) 4321{ 4322 MLXSW_REG_ZERO(ptys, payload); 4323 mlxsw_reg_ptys_local_port_set(payload, local_port); 4324 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4325 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4326 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4327} 4328 4329static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4330 u32 *p_eth_proto_cap, 4331 u32 *p_eth_proto_admin, 4332 u32 *p_eth_proto_oper) 4333{ 4334 if (p_eth_proto_cap) 4335 *p_eth_proto_cap = 4336 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4337 if (p_eth_proto_admin) 4338 *p_eth_proto_admin = 4339 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4340 if (p_eth_proto_oper) 4341 *p_eth_proto_oper = 4342 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4343} 4344 4345static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4346 u32 *p_eth_proto_cap, 4347 u32 *p_eth_proto_admin, 4348 u32 *p_eth_proto_oper) 4349{ 4350 if (p_eth_proto_cap) 4351 *p_eth_proto_cap = 4352 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4353 if (p_eth_proto_admin) 4354 *p_eth_proto_admin = 4355 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4356 if (p_eth_proto_oper) 4357 *p_eth_proto_oper = 4358 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4359} 4360 4361static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4362 u16 proto_admin, u16 link_width) 4363{ 4364 MLXSW_REG_ZERO(ptys, payload); 4365 mlxsw_reg_ptys_local_port_set(payload, local_port); 4366 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4367 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4368 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4369} 4370 4371static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4372 u16 *p_ib_link_width_cap, 4373 u16 *p_ib_proto_oper, 4374 u16 *p_ib_link_width_oper) 4375{ 4376 if (p_ib_proto_cap) 4377 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4378 if (p_ib_link_width_cap) 4379 *p_ib_link_width_cap = 4380 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4381 if (p_ib_proto_oper) 4382 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4383 if (p_ib_link_width_oper) 4384 *p_ib_link_width_oper = 4385 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4386} 4387 4388/* PPAD - Port Physical Address Register 4389 * ------------------------------------- 4390 * The PPAD register configures the per port physical MAC address. 4391 */ 4392#define MLXSW_REG_PPAD_ID 0x5005 4393#define MLXSW_REG_PPAD_LEN 0x10 4394 4395MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4396 4397/* reg_ppad_single_base_mac 4398 * 0: base_mac, local port should be 0 and mac[7:0] is 4399 * reserved. HW will set incremental 4400 * 1: single_mac - mac of the local_port 4401 * Access: RW 4402 */ 4403MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4404 4405/* reg_ppad_local_port 4406 * port number, if single_base_mac = 0 then local_port is reserved 4407 * Access: RW 4408 */ 4409MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4410 4411/* reg_ppad_mac 4412 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4413 * If single_base_mac = 1 - the per port MAC address 4414 * Access: RW 4415 */ 4416MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4417 4418static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4419 u8 local_port) 4420{ 4421 MLXSW_REG_ZERO(ppad, payload); 4422 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4423 mlxsw_reg_ppad_local_port_set(payload, local_port); 4424} 4425 4426/* PAOS - Ports Administrative and Operational Status Register 4427 * ----------------------------------------------------------- 4428 * Configures and retrieves per port administrative and operational status. 4429 */ 4430#define MLXSW_REG_PAOS_ID 0x5006 4431#define MLXSW_REG_PAOS_LEN 0x10 4432 4433MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4434 4435/* reg_paos_swid 4436 * Switch partition ID with which to associate the port. 4437 * Note: while external ports uses unique local port numbers (and thus swid is 4438 * redundant), router ports use the same local port number where swid is the 4439 * only indication for the relevant port. 4440 * Access: Index 4441 */ 4442MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4443 4444/* reg_paos_local_port 4445 * Local port number. 4446 * Access: Index 4447 */ 4448MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4449 4450/* reg_paos_admin_status 4451 * Port administrative state (the desired state of the port): 4452 * 1 - Up. 4453 * 2 - Down. 4454 * 3 - Up once. This means that in case of link failure, the port won't go 4455 * into polling mode, but will wait to be re-enabled by software. 4456 * 4 - Disabled by system. Can only be set by hardware. 4457 * Access: RW 4458 */ 4459MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4460 4461/* reg_paos_oper_status 4462 * Port operational state (the current state): 4463 * 1 - Up. 4464 * 2 - Down. 4465 * 3 - Down by port failure. This means that the device will not let the 4466 * port up again until explicitly specified by software. 4467 * Access: RO 4468 */ 4469MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4470 4471/* reg_paos_ase 4472 * Admin state update enabled. 4473 * Access: WO 4474 */ 4475MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4476 4477/* reg_paos_ee 4478 * Event update enable. If this bit is set, event generation will be 4479 * updated based on the e field. 4480 * Access: WO 4481 */ 4482MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4483 4484/* reg_paos_e 4485 * Event generation on operational state change: 4486 * 0 - Do not generate event. 4487 * 1 - Generate Event. 4488 * 2 - Generate Single Event. 4489 * Access: RW 4490 */ 4491MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4492 4493static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4494 enum mlxsw_port_admin_status status) 4495{ 4496 MLXSW_REG_ZERO(paos, payload); 4497 mlxsw_reg_paos_swid_set(payload, 0); 4498 mlxsw_reg_paos_local_port_set(payload, local_port); 4499 mlxsw_reg_paos_admin_status_set(payload, status); 4500 mlxsw_reg_paos_oper_status_set(payload, 0); 4501 mlxsw_reg_paos_ase_set(payload, 1); 4502 mlxsw_reg_paos_ee_set(payload, 1); 4503 mlxsw_reg_paos_e_set(payload, 1); 4504} 4505 4506/* PFCC - Ports Flow Control Configuration Register 4507 * ------------------------------------------------ 4508 * Configures and retrieves the per port flow control configuration. 4509 */ 4510#define MLXSW_REG_PFCC_ID 0x5007 4511#define MLXSW_REG_PFCC_LEN 0x20 4512 4513MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4514 4515/* reg_pfcc_local_port 4516 * Local port number. 4517 * Access: Index 4518 */ 4519MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4520 4521/* reg_pfcc_pnat 4522 * Port number access type. Determines the way local_port is interpreted: 4523 * 0 - Local port number. 4524 * 1 - IB / label port number. 4525 * Access: Index 4526 */ 4527MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4528 4529/* reg_pfcc_shl_cap 4530 * Send to higher layers capabilities: 4531 * 0 - No capability of sending Pause and PFC frames to higher layers. 4532 * 1 - Device has capability of sending Pause and PFC frames to higher 4533 * layers. 4534 * Access: RO 4535 */ 4536MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4537 4538/* reg_pfcc_shl_opr 4539 * Send to higher layers operation: 4540 * 0 - Pause and PFC frames are handled by the port (default). 4541 * 1 - Pause and PFC frames are handled by the port and also sent to 4542 * higher layers. Only valid if shl_cap = 1. 4543 * Access: RW 4544 */ 4545MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4546 4547/* reg_pfcc_ppan 4548 * Pause policy auto negotiation. 4549 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4550 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4551 * based on the auto-negotiation resolution. 4552 * Access: RW 4553 * 4554 * Note: The auto-negotiation advertisement is set according to pptx and 4555 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4556 */ 4557MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4558 4559/* reg_pfcc_prio_mask_tx 4560 * Bit per priority indicating if Tx flow control policy should be 4561 * updated based on bit pfctx. 4562 * Access: WO 4563 */ 4564MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4565 4566/* reg_pfcc_prio_mask_rx 4567 * Bit per priority indicating if Rx flow control policy should be 4568 * updated based on bit pfcrx. 4569 * Access: WO 4570 */ 4571MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4572 4573/* reg_pfcc_pptx 4574 * Admin Pause policy on Tx. 4575 * 0 - Never generate Pause frames (default). 4576 * 1 - Generate Pause frames according to Rx buffer threshold. 4577 * Access: RW 4578 */ 4579MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4580 4581/* reg_pfcc_aptx 4582 * Active (operational) Pause policy on Tx. 4583 * 0 - Never generate Pause frames. 4584 * 1 - Generate Pause frames according to Rx buffer threshold. 4585 * Access: RO 4586 */ 4587MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4588 4589/* reg_pfcc_pfctx 4590 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4591 * 0 - Never generate priority Pause frames on the specified priority 4592 * (default). 4593 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4594 * the specified priority. 4595 * Access: RW 4596 * 4597 * Note: pfctx and pptx must be mutually exclusive. 4598 */ 4599MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4600 4601/* reg_pfcc_pprx 4602 * Admin Pause policy on Rx. 4603 * 0 - Ignore received Pause frames (default). 4604 * 1 - Respect received Pause frames. 4605 * Access: RW 4606 */ 4607MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4608 4609/* reg_pfcc_aprx 4610 * Active (operational) Pause policy on Rx. 4611 * 0 - Ignore received Pause frames. 4612 * 1 - Respect received Pause frames. 4613 * Access: RO 4614 */ 4615MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4616 4617/* reg_pfcc_pfcrx 4618 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4619 * 0 - Ignore incoming priority Pause frames on the specified priority 4620 * (default). 4621 * 1 - Respect incoming priority Pause frames on the specified priority. 4622 * Access: RW 4623 */ 4624MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4625 4626#define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4627 4628static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4629{ 4630 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4631 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4632 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4633 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4634} 4635 4636static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4637{ 4638 MLXSW_REG_ZERO(pfcc, payload); 4639 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4640} 4641 4642/* PPCNT - Ports Performance Counters Register 4643 * ------------------------------------------- 4644 * The PPCNT register retrieves per port performance counters. 4645 */ 4646#define MLXSW_REG_PPCNT_ID 0x5008 4647#define MLXSW_REG_PPCNT_LEN 0x100 4648#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4649 4650MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4651 4652/* reg_ppcnt_swid 4653 * For HCA: must be always 0. 4654 * Switch partition ID to associate port with. 4655 * Switch partitions are numbered from 0 to 7 inclusively. 4656 * Switch partition 254 indicates stacking ports. 4657 * Switch partition 255 indicates all switch partitions. 4658 * Only valid on Set() operation with local_port=255. 4659 * Access: Index 4660 */ 4661MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4662 4663/* reg_ppcnt_local_port 4664 * Local port number. 4665 * 255 indicates all ports on the device, and is only allowed 4666 * for Set() operation. 4667 * Access: Index 4668 */ 4669MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4670 4671/* reg_ppcnt_pnat 4672 * Port number access type: 4673 * 0 - Local port number 4674 * 1 - IB port number 4675 * Access: Index 4676 */ 4677MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4678 4679enum mlxsw_reg_ppcnt_grp { 4680 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4681 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4682 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4683 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4684 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4685 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4686 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4687 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4688 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4689}; 4690 4691/* reg_ppcnt_grp 4692 * Performance counter group. 4693 * Group 63 indicates all groups. Only valid on Set() operation with 4694 * clr bit set. 4695 * 0x0: IEEE 802.3 Counters 4696 * 0x1: RFC 2863 Counters 4697 * 0x2: RFC 2819 Counters 4698 * 0x3: RFC 3635 Counters 4699 * 0x5: Ethernet Extended Counters 4700 * 0x6: Ethernet Discard Counters 4701 * 0x8: Link Level Retransmission Counters 4702 * 0x10: Per Priority Counters 4703 * 0x11: Per Traffic Class Counters 4704 * 0x12: Physical Layer Counters 4705 * 0x13: Per Traffic Class Congestion Counters 4706 * Access: Index 4707 */ 4708MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4709 4710/* reg_ppcnt_clr 4711 * Clear counters. Setting the clr bit will reset the counter value 4712 * for all counters in the counter group. This bit can be set 4713 * for both Set() and Get() operation. 4714 * Access: OP 4715 */ 4716MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4717 4718/* reg_ppcnt_prio_tc 4719 * Priority for counter set that support per priority, valid values: 0-7. 4720 * Traffic class for counter set that support per traffic class, 4721 * valid values: 0- cap_max_tclass-1 . 4722 * For HCA: cap_max_tclass is always 8. 4723 * Otherwise must be 0. 4724 * Access: Index 4725 */ 4726MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4727 4728/* Ethernet IEEE 802.3 Counter Group */ 4729 4730/* reg_ppcnt_a_frames_transmitted_ok 4731 * Access: RO 4732 */ 4733MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4734 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4735 4736/* reg_ppcnt_a_frames_received_ok 4737 * Access: RO 4738 */ 4739MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4740 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4741 4742/* reg_ppcnt_a_frame_check_sequence_errors 4743 * Access: RO 4744 */ 4745MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4746 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4747 4748/* reg_ppcnt_a_alignment_errors 4749 * Access: RO 4750 */ 4751MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4752 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4753 4754/* reg_ppcnt_a_octets_transmitted_ok 4755 * Access: RO 4756 */ 4757MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4758 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4759 4760/* reg_ppcnt_a_octets_received_ok 4761 * Access: RO 4762 */ 4763MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4764 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4765 4766/* reg_ppcnt_a_multicast_frames_xmitted_ok 4767 * Access: RO 4768 */ 4769MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4770 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4771 4772/* reg_ppcnt_a_broadcast_frames_xmitted_ok 4773 * Access: RO 4774 */ 4775MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4776 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4777 4778/* reg_ppcnt_a_multicast_frames_received_ok 4779 * Access: RO 4780 */ 4781MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4782 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4783 4784/* reg_ppcnt_a_broadcast_frames_received_ok 4785 * Access: RO 4786 */ 4787MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4788 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4789 4790/* reg_ppcnt_a_in_range_length_errors 4791 * Access: RO 4792 */ 4793MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4794 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4795 4796/* reg_ppcnt_a_out_of_range_length_field 4797 * Access: RO 4798 */ 4799MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4800 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4801 4802/* reg_ppcnt_a_frame_too_long_errors 4803 * Access: RO 4804 */ 4805MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4806 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4807 4808/* reg_ppcnt_a_symbol_error_during_carrier 4809 * Access: RO 4810 */ 4811MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4812 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4813 4814/* reg_ppcnt_a_mac_control_frames_transmitted 4815 * Access: RO 4816 */ 4817MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4818 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4819 4820/* reg_ppcnt_a_mac_control_frames_received 4821 * Access: RO 4822 */ 4823MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4824 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4825 4826/* reg_ppcnt_a_unsupported_opcodes_received 4827 * Access: RO 4828 */ 4829MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4830 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4831 4832/* reg_ppcnt_a_pause_mac_ctrl_frames_received 4833 * Access: RO 4834 */ 4835MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4836 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4837 4838/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4839 * Access: RO 4840 */ 4841MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4842 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4843 4844/* Ethernet RFC 2863 Counter Group */ 4845 4846/* reg_ppcnt_if_in_discards 4847 * Access: RO 4848 */ 4849MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4850 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4851 4852/* reg_ppcnt_if_out_discards 4853 * Access: RO 4854 */ 4855MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4856 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4857 4858/* reg_ppcnt_if_out_errors 4859 * Access: RO 4860 */ 4861MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4862 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4863 4864/* Ethernet RFC 2819 Counter Group */ 4865 4866/* reg_ppcnt_ether_stats_undersize_pkts 4867 * Access: RO 4868 */ 4869MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4870 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4871 4872/* reg_ppcnt_ether_stats_oversize_pkts 4873 * Access: RO 4874 */ 4875MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4876 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4877 4878/* reg_ppcnt_ether_stats_fragments 4879 * Access: RO 4880 */ 4881MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4882 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4883 4884/* reg_ppcnt_ether_stats_pkts64octets 4885 * Access: RO 4886 */ 4887MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4888 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4889 4890/* reg_ppcnt_ether_stats_pkts65to127octets 4891 * Access: RO 4892 */ 4893MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4894 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4895 4896/* reg_ppcnt_ether_stats_pkts128to255octets 4897 * Access: RO 4898 */ 4899MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4900 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4901 4902/* reg_ppcnt_ether_stats_pkts256to511octets 4903 * Access: RO 4904 */ 4905MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4906 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4907 4908/* reg_ppcnt_ether_stats_pkts512to1023octets 4909 * Access: RO 4910 */ 4911MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4912 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4913 4914/* reg_ppcnt_ether_stats_pkts1024to1518octets 4915 * Access: RO 4916 */ 4917MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4918 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4919 4920/* reg_ppcnt_ether_stats_pkts1519to2047octets 4921 * Access: RO 4922 */ 4923MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4924 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4925 4926/* reg_ppcnt_ether_stats_pkts2048to4095octets 4927 * Access: RO 4928 */ 4929MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4930 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4931 4932/* reg_ppcnt_ether_stats_pkts4096to8191octets 4933 * Access: RO 4934 */ 4935MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4936 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4937 4938/* reg_ppcnt_ether_stats_pkts8192to10239octets 4939 * Access: RO 4940 */ 4941MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4942 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4943 4944/* Ethernet RFC 3635 Counter Group */ 4945 4946/* reg_ppcnt_dot3stats_fcs_errors 4947 * Access: RO 4948 */ 4949MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4950 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4951 4952/* reg_ppcnt_dot3stats_symbol_errors 4953 * Access: RO 4954 */ 4955MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4956 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4957 4958/* reg_ppcnt_dot3control_in_unknown_opcodes 4959 * Access: RO 4960 */ 4961MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4962 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4963 4964/* reg_ppcnt_dot3in_pause_frames 4965 * Access: RO 4966 */ 4967MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4968 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4969 4970/* Ethernet Extended Counter Group Counters */ 4971 4972/* reg_ppcnt_ecn_marked 4973 * Access: RO 4974 */ 4975MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4976 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4977 4978/* Ethernet Discard Counter Group Counters */ 4979 4980/* reg_ppcnt_ingress_general 4981 * Access: RO 4982 */ 4983MLXSW_ITEM64(reg, ppcnt, ingress_general, 4984 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4985 4986/* reg_ppcnt_ingress_policy_engine 4987 * Access: RO 4988 */ 4989MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4990 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4991 4992/* reg_ppcnt_ingress_vlan_membership 4993 * Access: RO 4994 */ 4995MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4996 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4997 4998/* reg_ppcnt_ingress_tag_frame_type 4999 * Access: RO 5000 */ 5001MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5002 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5003 5004/* reg_ppcnt_egress_vlan_membership 5005 * Access: RO 5006 */ 5007MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5008 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5009 5010/* reg_ppcnt_loopback_filter 5011 * Access: RO 5012 */ 5013MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5014 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5015 5016/* reg_ppcnt_egress_general 5017 * Access: RO 5018 */ 5019MLXSW_ITEM64(reg, ppcnt, egress_general, 5020 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5021 5022/* reg_ppcnt_egress_hoq 5023 * Access: RO 5024 */ 5025MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5026 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5027 5028/* reg_ppcnt_egress_policy_engine 5029 * Access: RO 5030 */ 5031MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5032 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5033 5034/* reg_ppcnt_ingress_tx_link_down 5035 * Access: RO 5036 */ 5037MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5038 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5039 5040/* reg_ppcnt_egress_stp_filter 5041 * Access: RO 5042 */ 5043MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5044 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5045 5046/* reg_ppcnt_egress_sll 5047 * Access: RO 5048 */ 5049MLXSW_ITEM64(reg, ppcnt, egress_sll, 5050 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5051 5052/* Ethernet Per Priority Group Counters */ 5053 5054/* reg_ppcnt_rx_octets 5055 * Access: RO 5056 */ 5057MLXSW_ITEM64(reg, ppcnt, rx_octets, 5058 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5059 5060/* reg_ppcnt_rx_frames 5061 * Access: RO 5062 */ 5063MLXSW_ITEM64(reg, ppcnt, rx_frames, 5064 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5065 5066/* reg_ppcnt_tx_octets 5067 * Access: RO 5068 */ 5069MLXSW_ITEM64(reg, ppcnt, tx_octets, 5070 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5071 5072/* reg_ppcnt_tx_frames 5073 * Access: RO 5074 */ 5075MLXSW_ITEM64(reg, ppcnt, tx_frames, 5076 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5077 5078/* reg_ppcnt_rx_pause 5079 * Access: RO 5080 */ 5081MLXSW_ITEM64(reg, ppcnt, rx_pause, 5082 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5083 5084/* reg_ppcnt_rx_pause_duration 5085 * Access: RO 5086 */ 5087MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5088 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5089 5090/* reg_ppcnt_tx_pause 5091 * Access: RO 5092 */ 5093MLXSW_ITEM64(reg, ppcnt, tx_pause, 5094 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5095 5096/* reg_ppcnt_tx_pause_duration 5097 * Access: RO 5098 */ 5099MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5100 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5101 5102/* reg_ppcnt_rx_pause_transition 5103 * Access: RO 5104 */ 5105MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5106 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5107 5108/* Ethernet Per Traffic Group Counters */ 5109 5110/* reg_ppcnt_tc_transmit_queue 5111 * Contains the transmit queue depth in cells of traffic class 5112 * selected by prio_tc and the port selected by local_port. 5113 * The field cannot be cleared. 5114 * Access: RO 5115 */ 5116MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5117 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5118 5119/* reg_ppcnt_tc_no_buffer_discard_uc 5120 * The number of unicast packets dropped due to lack of shared 5121 * buffer resources. 5122 * Access: RO 5123 */ 5124MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5125 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5126 5127/* Ethernet Per Traffic Class Congestion Group Counters */ 5128 5129/* reg_ppcnt_wred_discard 5130 * Access: RO 5131 */ 5132MLXSW_ITEM64(reg, ppcnt, wred_discard, 5133 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5134 5135static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5136 enum mlxsw_reg_ppcnt_grp grp, 5137 u8 prio_tc) 5138{ 5139 MLXSW_REG_ZERO(ppcnt, payload); 5140 mlxsw_reg_ppcnt_swid_set(payload, 0); 5141 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5142 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5143 mlxsw_reg_ppcnt_grp_set(payload, grp); 5144 mlxsw_reg_ppcnt_clr_set(payload, 0); 5145 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5146} 5147 5148/* PLIB - Port Local to InfiniBand Port 5149 * ------------------------------------ 5150 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5151 */ 5152#define MLXSW_REG_PLIB_ID 0x500A 5153#define MLXSW_REG_PLIB_LEN 0x10 5154 5155MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5156 5157/* reg_plib_local_port 5158 * Local port number. 5159 * Access: Index 5160 */ 5161MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5162 5163/* reg_plib_ib_port 5164 * InfiniBand port remapping for local_port. 5165 * Access: RW 5166 */ 5167MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5168 5169/* PPTB - Port Prio To Buffer Register 5170 * ----------------------------------- 5171 * Configures the switch priority to buffer table. 5172 */ 5173#define MLXSW_REG_PPTB_ID 0x500B 5174#define MLXSW_REG_PPTB_LEN 0x10 5175 5176MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5177 5178enum { 5179 MLXSW_REG_PPTB_MM_UM, 5180 MLXSW_REG_PPTB_MM_UNICAST, 5181 MLXSW_REG_PPTB_MM_MULTICAST, 5182}; 5183 5184/* reg_pptb_mm 5185 * Mapping mode. 5186 * 0 - Map both unicast and multicast packets to the same buffer. 5187 * 1 - Map only unicast packets. 5188 * 2 - Map only multicast packets. 5189 * Access: Index 5190 * 5191 * Note: SwitchX-2 only supports the first option. 5192 */ 5193MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5194 5195/* reg_pptb_local_port 5196 * Local port number. 5197 * Access: Index 5198 */ 5199MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5200 5201/* reg_pptb_um 5202 * Enables the update of the untagged_buf field. 5203 * Access: RW 5204 */ 5205MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5206 5207/* reg_pptb_pm 5208 * Enables the update of the prio_to_buff field. 5209 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5210 * Access: RW 5211 */ 5212MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5213 5214/* reg_pptb_prio_to_buff 5215 * Mapping of switch priority <i> to one of the allocated receive port 5216 * buffers. 5217 * Access: RW 5218 */ 5219MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5220 5221/* reg_pptb_pm_msb 5222 * Enables the update of the prio_to_buff field. 5223 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5224 * Access: RW 5225 */ 5226MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5227 5228/* reg_pptb_untagged_buff 5229 * Mapping of untagged frames to one of the allocated receive port buffers. 5230 * Access: RW 5231 * 5232 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5233 * Spectrum, as it maps untagged packets based on the default switch priority. 5234 */ 5235MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5236 5237/* reg_pptb_prio_to_buff_msb 5238 * Mapping of switch priority <i+8> to one of the allocated receive port 5239 * buffers. 5240 * Access: RW 5241 */ 5242MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5243 5244#define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5245 5246static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5247{ 5248 MLXSW_REG_ZERO(pptb, payload); 5249 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5250 mlxsw_reg_pptb_local_port_set(payload, local_port); 5251 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5252 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5253} 5254 5255static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5256 u8 buff) 5257{ 5258 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5259 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5260} 5261 5262/* PBMC - Port Buffer Management Control Register 5263 * ---------------------------------------------- 5264 * The PBMC register configures and retrieves the port packet buffer 5265 * allocation for different Prios, and the Pause threshold management. 5266 */ 5267#define MLXSW_REG_PBMC_ID 0x500C 5268#define MLXSW_REG_PBMC_LEN 0x6C 5269 5270MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5271 5272/* reg_pbmc_local_port 5273 * Local port number. 5274 * Access: Index 5275 */ 5276MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5277 5278/* reg_pbmc_xoff_timer_value 5279 * When device generates a pause frame, it uses this value as the pause 5280 * timer (time for the peer port to pause in quota-512 bit time). 5281 * Access: RW 5282 */ 5283MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5284 5285/* reg_pbmc_xoff_refresh 5286 * The time before a new pause frame should be sent to refresh the pause RW 5287 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5288 * time). 5289 * Access: RW 5290 */ 5291MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5292 5293#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5294 5295/* reg_pbmc_buf_lossy 5296 * The field indicates if the buffer is lossy. 5297 * 0 - Lossless 5298 * 1 - Lossy 5299 * Access: RW 5300 */ 5301MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5302 5303/* reg_pbmc_buf_epsb 5304 * Eligible for Port Shared buffer. 5305 * If epsb is set, packets assigned to buffer are allowed to insert the port 5306 * shared buffer. 5307 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5308 * Access: RW 5309 */ 5310MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5311 5312/* reg_pbmc_buf_size 5313 * The part of the packet buffer array is allocated for the specific buffer. 5314 * Units are represented in cells. 5315 * Access: RW 5316 */ 5317MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5318 5319/* reg_pbmc_buf_xoff_threshold 5320 * Once the amount of data in the buffer goes above this value, device 5321 * starts sending PFC frames for all priorities associated with the 5322 * buffer. Units are represented in cells. Reserved in case of lossy 5323 * buffer. 5324 * Access: RW 5325 * 5326 * Note: In Spectrum, reserved for buffer[9]. 5327 */ 5328MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5329 0x08, 0x04, false); 5330 5331/* reg_pbmc_buf_xon_threshold 5332 * When the amount of data in the buffer goes below this value, device 5333 * stops sending PFC frames for the priorities associated with the 5334 * buffer. Units are represented in cells. Reserved in case of lossy 5335 * buffer. 5336 * Access: RW 5337 * 5338 * Note: In Spectrum, reserved for buffer[9]. 5339 */ 5340MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5341 0x08, 0x04, false); 5342 5343static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5344 u16 xoff_timer_value, u16 xoff_refresh) 5345{ 5346 MLXSW_REG_ZERO(pbmc, payload); 5347 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5348 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5349 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5350} 5351 5352static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5353 int buf_index, 5354 u16 size) 5355{ 5356 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5357 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5358 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5359} 5360 5361static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5362 int buf_index, u16 size, 5363 u16 threshold) 5364{ 5365 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5366 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5367 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5368 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5369 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5370} 5371 5372/* PSPA - Port Switch Partition Allocation 5373 * --------------------------------------- 5374 * Controls the association of a port with a switch partition and enables 5375 * configuring ports as stacking ports. 5376 */ 5377#define MLXSW_REG_PSPA_ID 0x500D 5378#define MLXSW_REG_PSPA_LEN 0x8 5379 5380MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5381 5382/* reg_pspa_swid 5383 * Switch partition ID. 5384 * Access: RW 5385 */ 5386MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5387 5388/* reg_pspa_local_port 5389 * Local port number. 5390 * Access: Index 5391 */ 5392MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5393 5394/* reg_pspa_sub_port 5395 * Virtual port within the local port. Set to 0 when virtual ports are 5396 * disabled on the local port. 5397 * Access: Index 5398 */ 5399MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5400 5401static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5402{ 5403 MLXSW_REG_ZERO(pspa, payload); 5404 mlxsw_reg_pspa_swid_set(payload, swid); 5405 mlxsw_reg_pspa_local_port_set(payload, local_port); 5406 mlxsw_reg_pspa_sub_port_set(payload, 0); 5407} 5408 5409/* PMAOS - Ports Module Administrative and Operational Status 5410 * ---------------------------------------------------------- 5411 * This register configures and retrieves the per module status. 5412 */ 5413#define MLXSW_REG_PMAOS_ID 0x5012 5414#define MLXSW_REG_PMAOS_LEN 0x10 5415 5416MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5417 5418/* reg_slot_index 5419 * Slot index. 5420 * Access: Index 5421 */ 5422MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5423 5424/* reg_pmaos_module 5425 * Module number. 5426 * Access: Index 5427 */ 5428MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5429 5430/* reg_pmaos_ase 5431 * Admin state update enable. 5432 * If this bit is set, admin state will be updated based on admin_state field. 5433 * Only relevant on Set() operations. 5434 * Access: WO 5435 */ 5436MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5437 5438/* reg_pmaos_ee 5439 * Event update enable. 5440 * If this bit is set, event generation will be updated based on the e field. 5441 * Only relevant on Set operations. 5442 * Access: WO 5443 */ 5444MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5445 5446enum mlxsw_reg_pmaos_e { 5447 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5448 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5449 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5450}; 5451 5452/* reg_pmaos_e 5453 * Event Generation on operational state change. 5454 * Access: RW 5455 */ 5456MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5457 5458static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module, 5459 enum mlxsw_reg_pmaos_e e) 5460{ 5461 MLXSW_REG_ZERO(pmaos, payload); 5462 mlxsw_reg_pmaos_module_set(payload, module); 5463 mlxsw_reg_pmaos_e_set(payload, e); 5464 mlxsw_reg_pmaos_ee_set(payload, true); 5465} 5466 5467/* PPLR - Port Physical Loopback Register 5468 * -------------------------------------- 5469 * This register allows configuration of the port's loopback mode. 5470 */ 5471#define MLXSW_REG_PPLR_ID 0x5018 5472#define MLXSW_REG_PPLR_LEN 0x8 5473 5474MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5475 5476/* reg_pplr_local_port 5477 * Local port number. 5478 * Access: Index 5479 */ 5480MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5481 5482/* Phy local loopback. When set the port's egress traffic is looped back 5483 * to the receiver and the port transmitter is disabled. 5484 */ 5485#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5486 5487/* reg_pplr_lb_en 5488 * Loopback enable. 5489 * Access: RW 5490 */ 5491MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5492 5493static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5494 bool phy_local) 5495{ 5496 MLXSW_REG_ZERO(pplr, payload); 5497 mlxsw_reg_pplr_local_port_set(payload, local_port); 5498 mlxsw_reg_pplr_lb_en_set(payload, 5499 phy_local ? 5500 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5501} 5502 5503/* PMPE - Port Module Plug/Unplug Event Register 5504 * --------------------------------------------- 5505 * This register reports any operational status change of a module. 5506 * A change in the module’s state will generate an event only if the change 5507 * happens after arming the event mechanism. Any changes to the module state 5508 * while the event mechanism is not armed will not be reported. Software can 5509 * query the PMPE register for module status. 5510 */ 5511#define MLXSW_REG_PMPE_ID 0x5024 5512#define MLXSW_REG_PMPE_LEN 0x10 5513 5514MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 5515 5516/* reg_pmpe_slot_index 5517 * Slot index. 5518 * Access: Index 5519 */ 5520MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 5521 5522/* reg_pmpe_module 5523 * Module number. 5524 * Access: Index 5525 */ 5526MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 5527 5528enum mlxsw_reg_pmpe_module_status { 5529 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 5530 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 5531 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 5532 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 5533}; 5534 5535/* reg_pmpe_module_status 5536 * Module status. 5537 * Access: RO 5538 */ 5539MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 5540 5541/* reg_pmpe_error_type 5542 * Module error details. 5543 * Access: RO 5544 */ 5545MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 5546 5547/* PDDR - Port Diagnostics Database Register 5548 * ----------------------------------------- 5549 * The PDDR enables to read the Phy debug database 5550 */ 5551#define MLXSW_REG_PDDR_ID 0x5031 5552#define MLXSW_REG_PDDR_LEN 0x100 5553 5554MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5555 5556/* reg_pddr_local_port 5557 * Local port number. 5558 * Access: Index 5559 */ 5560MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8); 5561 5562enum mlxsw_reg_pddr_page_select { 5563 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5564}; 5565 5566/* reg_pddr_page_select 5567 * Page select index. 5568 * Access: Index 5569 */ 5570MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5571 5572enum mlxsw_reg_pddr_trblsh_group_opcode { 5573 /* Monitor opcodes */ 5574 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5575}; 5576 5577/* reg_pddr_group_opcode 5578 * Group selector. 5579 * Access: Index 5580 */ 5581MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5582 5583/* reg_pddr_status_opcode 5584 * Group selector. 5585 * Access: RO 5586 */ 5587MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5588 5589static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port, 5590 u8 page_select) 5591{ 5592 MLXSW_REG_ZERO(pddr, payload); 5593 mlxsw_reg_pddr_local_port_set(payload, local_port); 5594 mlxsw_reg_pddr_page_select_set(payload, page_select); 5595} 5596 5597/* PMTM - Port Module Type Mapping Register 5598 * ---------------------------------------- 5599 * The PMTM allows query or configuration of module types. 5600 */ 5601#define MLXSW_REG_PMTM_ID 0x5067 5602#define MLXSW_REG_PMTM_LEN 0x10 5603 5604MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5605 5606/* reg_pmtm_module 5607 * Module number. 5608 * Access: Index 5609 */ 5610MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5611 5612enum mlxsw_reg_pmtm_module_type { 5613 /* Backplane with 4 lanes */ 5614 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5615 /* QSFP */ 5616 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5617 /* SFP */ 5618 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5619 /* Backplane with single lane */ 5620 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5621 /* Backplane with two lane */ 5622 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5623 /* Chip2Chip4x */ 5624 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5625 /* Chip2Chip2x */ 5626 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5627 /* Chip2Chip1x */ 5628 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5629 /* QSFP-DD */ 5630 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5631 /* OSFP */ 5632 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5633 /* SFP-DD */ 5634 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5635 /* DSFP */ 5636 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5637 /* Chip2Chip8x */ 5638 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5639}; 5640 5641/* reg_pmtm_module_type 5642 * Module type. 5643 * Access: RW 5644 */ 5645MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5646 5647static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5648{ 5649 MLXSW_REG_ZERO(pmtm, payload); 5650 mlxsw_reg_pmtm_module_set(payload, module); 5651} 5652 5653static inline void 5654mlxsw_reg_pmtm_unpack(char *payload, 5655 enum mlxsw_reg_pmtm_module_type *module_type) 5656{ 5657 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5658} 5659 5660/* HTGT - Host Trap Group Table 5661 * ---------------------------- 5662 * Configures the properties for forwarding to CPU. 5663 */ 5664#define MLXSW_REG_HTGT_ID 0x7002 5665#define MLXSW_REG_HTGT_LEN 0x20 5666 5667MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5668 5669/* reg_htgt_swid 5670 * Switch partition ID. 5671 * Access: Index 5672 */ 5673MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5674 5675#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5676 5677/* reg_htgt_type 5678 * CPU path type. 5679 * Access: RW 5680 */ 5681MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5682 5683enum mlxsw_reg_htgt_trap_group { 5684 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5685 MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 5686 MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 5687 MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 5688 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5689 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5690 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5691 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5692 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5693 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5694 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5695 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5696 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5697 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5698 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5699 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5700 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5701 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5702 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5703 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5704 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5705 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5706 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5707 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5708 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5709 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5710 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5711 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5712 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5713 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5714 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5715 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5716 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5717 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 5718 5719 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5720 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5721}; 5722 5723/* reg_htgt_trap_group 5724 * Trap group number. User defined number specifying which trap groups 5725 * should be forwarded to the CPU. The mapping between trap IDs and trap 5726 * groups is configured using HPKT register. 5727 * Access: Index 5728 */ 5729MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5730 5731enum { 5732 MLXSW_REG_HTGT_POLICER_DISABLE, 5733 MLXSW_REG_HTGT_POLICER_ENABLE, 5734}; 5735 5736/* reg_htgt_pide 5737 * Enable policer ID specified using 'pid' field. 5738 * Access: RW 5739 */ 5740MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5741 5742#define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5743 5744/* reg_htgt_pid 5745 * Policer ID for the trap group. 5746 * Access: RW 5747 */ 5748MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5749 5750#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5751 5752/* reg_htgt_mirror_action 5753 * Mirror action to use. 5754 * 0 - Trap to CPU. 5755 * 1 - Trap to CPU and mirror to a mirroring agent. 5756 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5757 * Access: RW 5758 * 5759 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5760 */ 5761MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5762 5763/* reg_htgt_mirroring_agent 5764 * Mirroring agent. 5765 * Access: RW 5766 */ 5767MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5768 5769#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5770 5771/* reg_htgt_priority 5772 * Trap group priority. 5773 * In case a packet matches multiple classification rules, the packet will 5774 * only be trapped once, based on the trap ID associated with the group (via 5775 * register HPKT) with the highest priority. 5776 * Supported values are 0-7, with 7 represnting the highest priority. 5777 * Access: RW 5778 * 5779 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5780 * by the 'trap_group' field. 5781 */ 5782MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5783 5784#define MLXSW_REG_HTGT_DEFAULT_TC 7 5785 5786/* reg_htgt_local_path_cpu_tclass 5787 * CPU ingress traffic class for the trap group. 5788 * Access: RW 5789 */ 5790MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5791 5792enum mlxsw_reg_htgt_local_path_rdq { 5793 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5794 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5795 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5796 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5797}; 5798/* reg_htgt_local_path_rdq 5799 * Receive descriptor queue (RDQ) to use for the trap group. 5800 * Access: RW 5801 */ 5802MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5803 5804static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5805 u8 priority, u8 tc) 5806{ 5807 MLXSW_REG_ZERO(htgt, payload); 5808 5809 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5810 mlxsw_reg_htgt_pide_set(payload, 5811 MLXSW_REG_HTGT_POLICER_DISABLE); 5812 } else { 5813 mlxsw_reg_htgt_pide_set(payload, 5814 MLXSW_REG_HTGT_POLICER_ENABLE); 5815 mlxsw_reg_htgt_pid_set(payload, policer_id); 5816 } 5817 5818 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5819 mlxsw_reg_htgt_trap_group_set(payload, group); 5820 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5821 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5822 mlxsw_reg_htgt_priority_set(payload, priority); 5823 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5824 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5825} 5826 5827/* HPKT - Host Packet Trap 5828 * ----------------------- 5829 * Configures trap IDs inside trap groups. 5830 */ 5831#define MLXSW_REG_HPKT_ID 0x7003 5832#define MLXSW_REG_HPKT_LEN 0x10 5833 5834MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5835 5836enum { 5837 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5838 MLXSW_REG_HPKT_ACK_REQUIRED, 5839}; 5840 5841/* reg_hpkt_ack 5842 * Require acknowledgements from the host for events. 5843 * If set, then the device will wait for the event it sent to be acknowledged 5844 * by the host. This option is only relevant for event trap IDs. 5845 * Access: RW 5846 * 5847 * Note: Currently not supported by firmware. 5848 */ 5849MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5850 5851enum mlxsw_reg_hpkt_action { 5852 MLXSW_REG_HPKT_ACTION_FORWARD, 5853 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5854 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5855 MLXSW_REG_HPKT_ACTION_DISCARD, 5856 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5857 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5858 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5859 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5860}; 5861 5862/* reg_hpkt_action 5863 * Action to perform on packet when trapped. 5864 * 0 - No action. Forward to CPU based on switching rules. 5865 * 1 - Trap to CPU (CPU receives sole copy). 5866 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5867 * 3 - Discard. 5868 * 4 - Soft discard (allow other traps to act on the packet). 5869 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5870 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5871 * 15 - Restore the firmware's default action. 5872 * Access: RW 5873 * 5874 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5875 * addressed to the CPU. 5876 */ 5877MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5878 5879/* reg_hpkt_trap_group 5880 * Trap group to associate the trap with. 5881 * Access: RW 5882 */ 5883MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5884 5885/* reg_hpkt_trap_id 5886 * Trap ID. 5887 * Access: Index 5888 * 5889 * Note: A trap ID can only be associated with a single trap group. The device 5890 * will associate the trap ID with the last trap group configured. 5891 */ 5892MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 5893 5894enum { 5895 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5896 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5897 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5898}; 5899 5900/* reg_hpkt_ctrl 5901 * Configure dedicated buffer resources for control packets. 5902 * Ignored by SwitchX-2. 5903 * 0 - Keep factory defaults. 5904 * 1 - Do not use control buffer for this trap ID. 5905 * 2 - Use control buffer for this trap ID. 5906 * Access: RW 5907 */ 5908MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5909 5910static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5911 enum mlxsw_reg_htgt_trap_group trap_group, 5912 bool is_ctrl) 5913{ 5914 MLXSW_REG_ZERO(hpkt, payload); 5915 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5916 mlxsw_reg_hpkt_action_set(payload, action); 5917 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5918 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5919 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5920 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5921 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5922} 5923 5924/* RGCR - Router General Configuration Register 5925 * -------------------------------------------- 5926 * The register is used for setting up the router configuration. 5927 */ 5928#define MLXSW_REG_RGCR_ID 0x8001 5929#define MLXSW_REG_RGCR_LEN 0x28 5930 5931MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5932 5933/* reg_rgcr_ipv4_en 5934 * IPv4 router enable. 5935 * Access: RW 5936 */ 5937MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5938 5939/* reg_rgcr_ipv6_en 5940 * IPv6 router enable. 5941 * Access: RW 5942 */ 5943MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5944 5945/* reg_rgcr_max_router_interfaces 5946 * Defines the maximum number of active router interfaces for all virtual 5947 * routers. 5948 * Access: RW 5949 */ 5950MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5951 5952/* reg_rgcr_usp 5953 * Update switch priority and packet color. 5954 * 0 - Preserve the value of Switch Priority and packet color. 5955 * 1 - Recalculate the value of Switch Priority and packet color. 5956 * Access: RW 5957 * 5958 * Note: Not supported by SwitchX and SwitchX-2. 5959 */ 5960MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5961 5962/* reg_rgcr_pcp_rw 5963 * Indicates how to handle the pcp_rewrite_en value: 5964 * 0 - Preserve the value of pcp_rewrite_en. 5965 * 2 - Disable PCP rewrite. 5966 * 3 - Enable PCP rewrite. 5967 * Access: RW 5968 * 5969 * Note: Not supported by SwitchX and SwitchX-2. 5970 */ 5971MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5972 5973/* reg_rgcr_activity_dis 5974 * Activity disable: 5975 * 0 - Activity will be set when an entry is hit (default). 5976 * 1 - Activity will not be set when an entry is hit. 5977 * 5978 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5979 * (RALUE). 5980 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5981 * Entry (RAUHT). 5982 * Bits 2:7 are reserved. 5983 * Access: RW 5984 * 5985 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5986 */ 5987MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5988 5989static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5990 bool ipv6_en) 5991{ 5992 MLXSW_REG_ZERO(rgcr, payload); 5993 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5994 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5995} 5996 5997/* RITR - Router Interface Table Register 5998 * -------------------------------------- 5999 * The register is used to configure the router interface table. 6000 */ 6001#define MLXSW_REG_RITR_ID 0x8002 6002#define MLXSW_REG_RITR_LEN 0x40 6003 6004MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6005 6006/* reg_ritr_enable 6007 * Enables routing on the router interface. 6008 * Access: RW 6009 */ 6010MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6011 6012/* reg_ritr_ipv4 6013 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6014 * interface. 6015 * Access: RW 6016 */ 6017MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6018 6019/* reg_ritr_ipv6 6020 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6021 * interface. 6022 * Access: RW 6023 */ 6024MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6025 6026/* reg_ritr_ipv4_mc 6027 * IPv4 multicast routing enable. 6028 * Access: RW 6029 */ 6030MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6031 6032/* reg_ritr_ipv6_mc 6033 * IPv6 multicast routing enable. 6034 * Access: RW 6035 */ 6036MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6037 6038enum mlxsw_reg_ritr_if_type { 6039 /* VLAN interface. */ 6040 MLXSW_REG_RITR_VLAN_IF, 6041 /* FID interface. */ 6042 MLXSW_REG_RITR_FID_IF, 6043 /* Sub-port interface. */ 6044 MLXSW_REG_RITR_SP_IF, 6045 /* Loopback Interface. */ 6046 MLXSW_REG_RITR_LOOPBACK_IF, 6047}; 6048 6049/* reg_ritr_type 6050 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6051 * Access: RW 6052 */ 6053MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6054 6055enum { 6056 MLXSW_REG_RITR_RIF_CREATE, 6057 MLXSW_REG_RITR_RIF_DEL, 6058}; 6059 6060/* reg_ritr_op 6061 * Opcode: 6062 * 0 - Create or edit RIF. 6063 * 1 - Delete RIF. 6064 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6065 * is not supported. An interface must be deleted and re-created in order 6066 * to update properties. 6067 * Access: WO 6068 */ 6069MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6070 6071/* reg_ritr_rif 6072 * Router interface index. A pointer to the Router Interface Table. 6073 * Access: Index 6074 */ 6075MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6076 6077/* reg_ritr_ipv4_fe 6078 * IPv4 Forwarding Enable. 6079 * Enables routing of IPv4 traffic on the router interface. When disabled, 6080 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6081 * Not supported in SwitchX-2. 6082 * Access: RW 6083 */ 6084MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6085 6086/* reg_ritr_ipv6_fe 6087 * IPv6 Forwarding Enable. 6088 * Enables routing of IPv6 traffic on the router interface. When disabled, 6089 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6090 * Not supported in SwitchX-2. 6091 * Access: RW 6092 */ 6093MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6094 6095/* reg_ritr_ipv4_mc_fe 6096 * IPv4 Multicast Forwarding Enable. 6097 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6098 * will be enabled. 6099 * Access: RW 6100 */ 6101MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6102 6103/* reg_ritr_ipv6_mc_fe 6104 * IPv6 Multicast Forwarding Enable. 6105 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6106 * will be enabled. 6107 * Access: RW 6108 */ 6109MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6110 6111/* reg_ritr_lb_en 6112 * Loop-back filter enable for unicast packets. 6113 * If the flag is set then loop-back filter for unicast packets is 6114 * implemented on the RIF. Multicast packets are always subject to 6115 * loop-back filtering. 6116 * Access: RW 6117 */ 6118MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6119 6120/* reg_ritr_virtual_router 6121 * Virtual router ID associated with the router interface. 6122 * Access: RW 6123 */ 6124MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6125 6126/* reg_ritr_mtu 6127 * Router interface MTU. 6128 * Access: RW 6129 */ 6130MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6131 6132/* reg_ritr_if_swid 6133 * Switch partition ID. 6134 * Access: RW 6135 */ 6136MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6137 6138/* reg_ritr_if_mac 6139 * Router interface MAC address. 6140 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6141 * Access: RW 6142 */ 6143MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6144 6145/* reg_ritr_if_vrrp_id_ipv6 6146 * VRRP ID for IPv6 6147 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6148 * Access: RW 6149 */ 6150MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6151 6152/* reg_ritr_if_vrrp_id_ipv4 6153 * VRRP ID for IPv4 6154 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6155 * Access: RW 6156 */ 6157MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6158 6159/* VLAN Interface */ 6160 6161/* reg_ritr_vlan_if_vid 6162 * VLAN ID. 6163 * Access: RW 6164 */ 6165MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6166 6167/* FID Interface */ 6168 6169/* reg_ritr_fid_if_fid 6170 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6171 * the vFID range are supported. 6172 * Access: RW 6173 */ 6174MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6175 6176static inline void mlxsw_reg_ritr_fid_set(char *payload, 6177 enum mlxsw_reg_ritr_if_type rif_type, 6178 u16 fid) 6179{ 6180 if (rif_type == MLXSW_REG_RITR_FID_IF) 6181 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6182 else 6183 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6184} 6185 6186/* Sub-port Interface */ 6187 6188/* reg_ritr_sp_if_lag 6189 * LAG indication. When this bit is set the system_port field holds the 6190 * LAG identifier. 6191 * Access: RW 6192 */ 6193MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6194 6195/* reg_ritr_sp_system_port 6196 * Port unique indentifier. When lag bit is set, this field holds the 6197 * lag_id in bits 0:9. 6198 * Access: RW 6199 */ 6200MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6201 6202/* reg_ritr_sp_if_vid 6203 * VLAN ID. 6204 * Access: RW 6205 */ 6206MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6207 6208/* Loopback Interface */ 6209 6210enum mlxsw_reg_ritr_loopback_protocol { 6211 /* IPinIP IPv4 underlay Unicast */ 6212 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6213 /* IPinIP IPv6 underlay Unicast */ 6214 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6215 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6216 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6217}; 6218 6219/* reg_ritr_loopback_protocol 6220 * Access: RW 6221 */ 6222MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6223 6224enum mlxsw_reg_ritr_loopback_ipip_type { 6225 /* Tunnel is IPinIP. */ 6226 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6227 /* Tunnel is GRE, no key. */ 6228 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6229 /* Tunnel is GRE, with a key. */ 6230 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6231}; 6232 6233/* reg_ritr_loopback_ipip_type 6234 * Encapsulation type. 6235 * Access: RW 6236 */ 6237MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6238 6239enum mlxsw_reg_ritr_loopback_ipip_options { 6240 /* The key is defined by gre_key. */ 6241 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6242}; 6243 6244/* reg_ritr_loopback_ipip_options 6245 * Access: RW 6246 */ 6247MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6248 6249/* reg_ritr_loopback_ipip_uvr 6250 * Underlay Virtual Router ID. 6251 * Range is 0..cap_max_virtual_routers-1. 6252 * Reserved for Spectrum-2. 6253 * Access: RW 6254 */ 6255MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6256 6257/* reg_ritr_loopback_ipip_underlay_rif 6258 * Underlay ingress router interface. 6259 * Reserved for Spectrum. 6260 * Access: RW 6261 */ 6262MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6263 6264/* reg_ritr_loopback_ipip_usip* 6265 * Encapsulation Underlay source IP. 6266 * Access: RW 6267 */ 6268MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6269MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6270 6271/* reg_ritr_loopback_ipip_gre_key 6272 * GRE Key. 6273 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6274 * Access: RW 6275 */ 6276MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6277 6278/* Shared between ingress/egress */ 6279enum mlxsw_reg_ritr_counter_set_type { 6280 /* No Count. */ 6281 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6282 /* Basic. Used for router interfaces, counting the following: 6283 * - Error and Discard counters. 6284 * - Unicast, Multicast and Broadcast counters. Sharing the 6285 * same set of counters for the different type of traffic 6286 * (IPv4, IPv6 and mpls). 6287 */ 6288 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6289}; 6290 6291/* reg_ritr_ingress_counter_index 6292 * Counter Index for flow counter. 6293 * Access: RW 6294 */ 6295MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6296 6297/* reg_ritr_ingress_counter_set_type 6298 * Igress Counter Set Type for router interface counter. 6299 * Access: RW 6300 */ 6301MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6302 6303/* reg_ritr_egress_counter_index 6304 * Counter Index for flow counter. 6305 * Access: RW 6306 */ 6307MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6308 6309/* reg_ritr_egress_counter_set_type 6310 * Egress Counter Set Type for router interface counter. 6311 * Access: RW 6312 */ 6313MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6314 6315static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6316 bool enable, bool egress) 6317{ 6318 enum mlxsw_reg_ritr_counter_set_type set_type; 6319 6320 if (enable) 6321 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6322 else 6323 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6324 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6325 6326 if (egress) 6327 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6328 else 6329 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6330} 6331 6332static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6333{ 6334 MLXSW_REG_ZERO(ritr, payload); 6335 mlxsw_reg_ritr_rif_set(payload, rif); 6336} 6337 6338static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6339 u16 system_port, u16 vid) 6340{ 6341 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6342 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6343 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6344} 6345 6346static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6347 enum mlxsw_reg_ritr_if_type type, 6348 u16 rif, u16 vr_id, u16 mtu) 6349{ 6350 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6351 6352 MLXSW_REG_ZERO(ritr, payload); 6353 mlxsw_reg_ritr_enable_set(payload, enable); 6354 mlxsw_reg_ritr_ipv4_set(payload, 1); 6355 mlxsw_reg_ritr_ipv6_set(payload, 1); 6356 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6357 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6358 mlxsw_reg_ritr_type_set(payload, type); 6359 mlxsw_reg_ritr_op_set(payload, op); 6360 mlxsw_reg_ritr_rif_set(payload, rif); 6361 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6362 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6363 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6364 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6365 mlxsw_reg_ritr_lb_en_set(payload, 1); 6366 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6367 mlxsw_reg_ritr_mtu_set(payload, mtu); 6368} 6369 6370static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6371{ 6372 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6373} 6374 6375static inline void 6376mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6377 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6378 enum mlxsw_reg_ritr_loopback_ipip_options options, 6379 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6380{ 6381 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6382 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6383 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6384 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6385 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6386} 6387 6388static inline void 6389mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6390 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6391 enum mlxsw_reg_ritr_loopback_ipip_options options, 6392 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6393{ 6394 mlxsw_reg_ritr_loopback_protocol_set(payload, 6395 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6396 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6397 uvr_id, underlay_rif, gre_key); 6398 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6399} 6400 6401/* RTAR - Router TCAM Allocation Register 6402 * -------------------------------------- 6403 * This register is used for allocation of regions in the TCAM table. 6404 */ 6405#define MLXSW_REG_RTAR_ID 0x8004 6406#define MLXSW_REG_RTAR_LEN 0x20 6407 6408MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6409 6410enum mlxsw_reg_rtar_op { 6411 MLXSW_REG_RTAR_OP_ALLOCATE, 6412 MLXSW_REG_RTAR_OP_RESIZE, 6413 MLXSW_REG_RTAR_OP_DEALLOCATE, 6414}; 6415 6416/* reg_rtar_op 6417 * Access: WO 6418 */ 6419MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6420 6421enum mlxsw_reg_rtar_key_type { 6422 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6423 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6424}; 6425 6426/* reg_rtar_key_type 6427 * TCAM key type for the region. 6428 * Access: WO 6429 */ 6430MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6431 6432/* reg_rtar_region_size 6433 * TCAM region size. When allocating/resizing this is the requested 6434 * size, the response is the actual size. 6435 * Note: Actual size may be larger than requested. 6436 * Reserved for op = Deallocate 6437 * Access: WO 6438 */ 6439MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6440 6441static inline void mlxsw_reg_rtar_pack(char *payload, 6442 enum mlxsw_reg_rtar_op op, 6443 enum mlxsw_reg_rtar_key_type key_type, 6444 u16 region_size) 6445{ 6446 MLXSW_REG_ZERO(rtar, payload); 6447 mlxsw_reg_rtar_op_set(payload, op); 6448 mlxsw_reg_rtar_key_type_set(payload, key_type); 6449 mlxsw_reg_rtar_region_size_set(payload, region_size); 6450} 6451 6452/* RATR - Router Adjacency Table Register 6453 * -------------------------------------- 6454 * The RATR register is used to configure the Router Adjacency (next-hop) 6455 * Table. 6456 */ 6457#define MLXSW_REG_RATR_ID 0x8008 6458#define MLXSW_REG_RATR_LEN 0x2C 6459 6460MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6461 6462enum mlxsw_reg_ratr_op { 6463 /* Read */ 6464 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6465 /* Read and clear activity */ 6466 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6467 /* Write Adjacency entry */ 6468 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6469 /* Write Adjacency entry only if the activity is cleared. 6470 * The write may not succeed if the activity is set. There is not 6471 * direct feedback if the write has succeeded or not, however 6472 * the get will reveal the actual entry (SW can compare the get 6473 * response to the set command). 6474 */ 6475 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6476}; 6477 6478/* reg_ratr_op 6479 * Note that Write operation may also be used for updating 6480 * counter_set_type and counter_index. In this case all other 6481 * fields must not be updated. 6482 * Access: OP 6483 */ 6484MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6485 6486/* reg_ratr_v 6487 * Valid bit. Indicates if the adjacency entry is valid. 6488 * Note: the device may need some time before reusing an invalidated 6489 * entry. During this time the entry can not be reused. It is 6490 * recommended to use another entry before reusing an invalidated 6491 * entry (e.g. software can put it at the end of the list for 6492 * reusing). Trying to access an invalidated entry not yet cleared 6493 * by the device results with failure indicating "Try Again" status. 6494 * When valid is '0' then egress_router_interface,trap_action, 6495 * adjacency_parameters and counters are reserved 6496 * Access: RW 6497 */ 6498MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6499 6500/* reg_ratr_a 6501 * Activity. Set for new entries. Set if a packet lookup has hit on 6502 * the specific entry. To clear the a bit, use "clear activity". 6503 * Access: RO 6504 */ 6505MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6506 6507enum mlxsw_reg_ratr_type { 6508 /* Ethernet */ 6509 MLXSW_REG_RATR_TYPE_ETHERNET, 6510 /* IPoIB Unicast without GRH. 6511 * Reserved for Spectrum. 6512 */ 6513 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6514 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6515 * adjacency). 6516 * Reserved for Spectrum. 6517 */ 6518 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6519 /* IPoIB Multicast. 6520 * Reserved for Spectrum. 6521 */ 6522 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6523 /* MPLS. 6524 * Reserved for SwitchX/-2. 6525 */ 6526 MLXSW_REG_RATR_TYPE_MPLS, 6527 /* IPinIP Encap. 6528 * Reserved for SwitchX/-2. 6529 */ 6530 MLXSW_REG_RATR_TYPE_IPIP, 6531}; 6532 6533/* reg_ratr_type 6534 * Adjacency entry type. 6535 * Access: RW 6536 */ 6537MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6538 6539/* reg_ratr_adjacency_index_low 6540 * Bits 15:0 of index into the adjacency table. 6541 * For SwitchX and SwitchX-2, the adjacency table is linear and 6542 * used for adjacency entries only. 6543 * For Spectrum, the index is to the KVD linear. 6544 * Access: Index 6545 */ 6546MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6547 6548/* reg_ratr_egress_router_interface 6549 * Range is 0 .. cap_max_router_interfaces - 1 6550 * Access: RW 6551 */ 6552MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6553 6554enum mlxsw_reg_ratr_trap_action { 6555 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6556 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6557 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6558 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6559 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6560}; 6561 6562/* reg_ratr_trap_action 6563 * see mlxsw_reg_ratr_trap_action 6564 * Access: RW 6565 */ 6566MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6567 6568/* reg_ratr_adjacency_index_high 6569 * Bits 23:16 of the adjacency_index. 6570 * Access: Index 6571 */ 6572MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6573 6574enum mlxsw_reg_ratr_trap_id { 6575 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6576 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6577}; 6578 6579/* reg_ratr_trap_id 6580 * Trap ID to be reported to CPU. 6581 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6582 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6583 * Access: RW 6584 */ 6585MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6586 6587/* reg_ratr_eth_destination_mac 6588 * MAC address of the destination next-hop. 6589 * Access: RW 6590 */ 6591MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6592 6593enum mlxsw_reg_ratr_ipip_type { 6594 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6595 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6596 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6597 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6598}; 6599 6600/* reg_ratr_ipip_type 6601 * Underlay destination ip type. 6602 * Note: the type field must match the protocol of the router interface. 6603 * Access: RW 6604 */ 6605MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6606 6607/* reg_ratr_ipip_ipv4_udip 6608 * Underlay ipv4 dip. 6609 * Reserved when ipip_type is IPv6. 6610 * Access: RW 6611 */ 6612MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6613 6614/* reg_ratr_ipip_ipv6_ptr 6615 * Pointer to IPv6 underlay destination ip address. 6616 * For Spectrum: Pointer to KVD linear space. 6617 * Access: RW 6618 */ 6619MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6620 6621enum mlxsw_reg_flow_counter_set_type { 6622 /* No count */ 6623 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6624 /* Count packets and bytes */ 6625 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6626 /* Count only packets */ 6627 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6628}; 6629 6630/* reg_ratr_counter_set_type 6631 * Counter set type for flow counters 6632 * Access: RW 6633 */ 6634MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6635 6636/* reg_ratr_counter_index 6637 * Counter index for flow counters 6638 * Access: RW 6639 */ 6640MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6641 6642static inline void 6643mlxsw_reg_ratr_pack(char *payload, 6644 enum mlxsw_reg_ratr_op op, bool valid, 6645 enum mlxsw_reg_ratr_type type, 6646 u32 adjacency_index, u16 egress_rif) 6647{ 6648 MLXSW_REG_ZERO(ratr, payload); 6649 mlxsw_reg_ratr_op_set(payload, op); 6650 mlxsw_reg_ratr_v_set(payload, valid); 6651 mlxsw_reg_ratr_type_set(payload, type); 6652 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6653 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6654 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6655} 6656 6657static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6658 const char *dest_mac) 6659{ 6660 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6661} 6662 6663static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6664{ 6665 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6666 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6667} 6668 6669static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6670 bool counter_enable) 6671{ 6672 enum mlxsw_reg_flow_counter_set_type set_type; 6673 6674 if (counter_enable) 6675 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6676 else 6677 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6678 6679 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6680 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6681} 6682 6683/* RDPM - Router DSCP to Priority Mapping 6684 * -------------------------------------- 6685 * Controls the mapping from DSCP field to switch priority on routed packets 6686 */ 6687#define MLXSW_REG_RDPM_ID 0x8009 6688#define MLXSW_REG_RDPM_BASE_LEN 0x00 6689#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6690#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6691#define MLXSW_REG_RDPM_LEN 0x40 6692#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6693 MLXSW_REG_RDPM_LEN - \ 6694 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6695 6696MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6697 6698/* reg_dscp_entry_e 6699 * Enable update of the specific entry 6700 * Access: Index 6701 */ 6702MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6703 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6704 6705/* reg_dscp_entry_prio 6706 * Switch Priority 6707 * Access: RW 6708 */ 6709MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6710 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6711 6712static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6713 u8 prio) 6714{ 6715 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6716 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6717} 6718 6719/* RICNT - Router Interface Counter Register 6720 * ----------------------------------------- 6721 * The RICNT register retrieves per port performance counters 6722 */ 6723#define MLXSW_REG_RICNT_ID 0x800B 6724#define MLXSW_REG_RICNT_LEN 0x100 6725 6726MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6727 6728/* reg_ricnt_counter_index 6729 * Counter index 6730 * Access: RW 6731 */ 6732MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6733 6734enum mlxsw_reg_ricnt_counter_set_type { 6735 /* No Count. */ 6736 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6737 /* Basic. Used for router interfaces, counting the following: 6738 * - Error and Discard counters. 6739 * - Unicast, Multicast and Broadcast counters. Sharing the 6740 * same set of counters for the different type of traffic 6741 * (IPv4, IPv6 and mpls). 6742 */ 6743 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6744}; 6745 6746/* reg_ricnt_counter_set_type 6747 * Counter Set Type for router interface counter 6748 * Access: RW 6749 */ 6750MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6751 6752enum mlxsw_reg_ricnt_opcode { 6753 /* Nop. Supported only for read access*/ 6754 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6755 /* Clear. Setting the clr bit will reset the counter value for 6756 * all counters of the specified Router Interface. 6757 */ 6758 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6759}; 6760 6761/* reg_ricnt_opcode 6762 * Opcode 6763 * Access: RW 6764 */ 6765MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6766 6767/* reg_ricnt_good_unicast_packets 6768 * good unicast packets. 6769 * Access: RW 6770 */ 6771MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6772 6773/* reg_ricnt_good_multicast_packets 6774 * good multicast packets. 6775 * Access: RW 6776 */ 6777MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6778 6779/* reg_ricnt_good_broadcast_packets 6780 * good broadcast packets 6781 * Access: RW 6782 */ 6783MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6784 6785/* reg_ricnt_good_unicast_bytes 6786 * A count of L3 data and padding octets not including L2 headers 6787 * for good unicast frames. 6788 * Access: RW 6789 */ 6790MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6791 6792/* reg_ricnt_good_multicast_bytes 6793 * A count of L3 data and padding octets not including L2 headers 6794 * for good multicast frames. 6795 * Access: RW 6796 */ 6797MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6798 6799/* reg_ritr_good_broadcast_bytes 6800 * A count of L3 data and padding octets not including L2 headers 6801 * for good broadcast frames. 6802 * Access: RW 6803 */ 6804MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6805 6806/* reg_ricnt_error_packets 6807 * A count of errored frames that do not pass the router checks. 6808 * Access: RW 6809 */ 6810MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6811 6812/* reg_ricnt_discrad_packets 6813 * A count of non-errored frames that do not pass the router checks. 6814 * Access: RW 6815 */ 6816MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6817 6818/* reg_ricnt_error_bytes 6819 * A count of L3 data and padding octets not including L2 headers 6820 * for errored frames. 6821 * Access: RW 6822 */ 6823MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6824 6825/* reg_ricnt_discard_bytes 6826 * A count of L3 data and padding octets not including L2 headers 6827 * for non-errored frames that do not pass the router checks. 6828 * Access: RW 6829 */ 6830MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6831 6832static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6833 enum mlxsw_reg_ricnt_opcode op) 6834{ 6835 MLXSW_REG_ZERO(ricnt, payload); 6836 mlxsw_reg_ricnt_op_set(payload, op); 6837 mlxsw_reg_ricnt_counter_index_set(payload, index); 6838 mlxsw_reg_ricnt_counter_set_type_set(payload, 6839 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6840} 6841 6842/* RRCR - Router Rules Copy Register Layout 6843 * ---------------------------------------- 6844 * This register is used for moving and copying route entry rules. 6845 */ 6846#define MLXSW_REG_RRCR_ID 0x800F 6847#define MLXSW_REG_RRCR_LEN 0x24 6848 6849MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6850 6851enum mlxsw_reg_rrcr_op { 6852 /* Move rules */ 6853 MLXSW_REG_RRCR_OP_MOVE, 6854 /* Copy rules */ 6855 MLXSW_REG_RRCR_OP_COPY, 6856}; 6857 6858/* reg_rrcr_op 6859 * Access: WO 6860 */ 6861MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6862 6863/* reg_rrcr_offset 6864 * Offset within the region from which to copy/move. 6865 * Access: Index 6866 */ 6867MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6868 6869/* reg_rrcr_size 6870 * The number of rules to copy/move. 6871 * Access: WO 6872 */ 6873MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6874 6875/* reg_rrcr_table_id 6876 * Identifier of the table on which to perform the operation. Encoding is the 6877 * same as in RTAR.key_type 6878 * Access: Index 6879 */ 6880MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6881 6882/* reg_rrcr_dest_offset 6883 * Offset within the region to which to copy/move 6884 * Access: Index 6885 */ 6886MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6887 6888static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6889 u16 offset, u16 size, 6890 enum mlxsw_reg_rtar_key_type table_id, 6891 u16 dest_offset) 6892{ 6893 MLXSW_REG_ZERO(rrcr, payload); 6894 mlxsw_reg_rrcr_op_set(payload, op); 6895 mlxsw_reg_rrcr_offset_set(payload, offset); 6896 mlxsw_reg_rrcr_size_set(payload, size); 6897 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6898 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6899} 6900 6901/* RALTA - Router Algorithmic LPM Tree Allocation Register 6902 * ------------------------------------------------------- 6903 * RALTA is used to allocate the LPM trees of the SHSPM method. 6904 */ 6905#define MLXSW_REG_RALTA_ID 0x8010 6906#define MLXSW_REG_RALTA_LEN 0x04 6907 6908MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6909 6910/* reg_ralta_op 6911 * opcode (valid for Write, must be 0 on Read) 6912 * 0 - allocate a tree 6913 * 1 - deallocate a tree 6914 * Access: OP 6915 */ 6916MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6917 6918enum mlxsw_reg_ralxx_protocol { 6919 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6920 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6921}; 6922 6923/* reg_ralta_protocol 6924 * Protocol. 6925 * Deallocation opcode: Reserved. 6926 * Access: RW 6927 */ 6928MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6929 6930/* reg_ralta_tree_id 6931 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6932 * the tree identifier (managed by software). 6933 * Note that tree_id 0 is allocated for a default-route tree. 6934 * Access: Index 6935 */ 6936MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6937 6938static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6939 enum mlxsw_reg_ralxx_protocol protocol, 6940 u8 tree_id) 6941{ 6942 MLXSW_REG_ZERO(ralta, payload); 6943 mlxsw_reg_ralta_op_set(payload, !alloc); 6944 mlxsw_reg_ralta_protocol_set(payload, protocol); 6945 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6946} 6947 6948/* RALST - Router Algorithmic LPM Structure Tree Register 6949 * ------------------------------------------------------ 6950 * RALST is used to set and query the structure of an LPM tree. 6951 * The structure of the tree must be sorted as a sorted binary tree, while 6952 * each node is a bin that is tagged as the length of the prefixes the lookup 6953 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6954 * of X bits to match with the destination address. The bin 0 indicates 6955 * the default action, when there is no match of any prefix. 6956 */ 6957#define MLXSW_REG_RALST_ID 0x8011 6958#define MLXSW_REG_RALST_LEN 0x104 6959 6960MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6961 6962/* reg_ralst_root_bin 6963 * The bin number of the root bin. 6964 * 0<root_bin=<(length of IP address) 6965 * For a default-route tree configure 0xff 6966 * Access: RW 6967 */ 6968MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6969 6970/* reg_ralst_tree_id 6971 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6972 * Access: Index 6973 */ 6974MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6975 6976#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6977#define MLXSW_REG_RALST_BIN_OFFSET 0x04 6978#define MLXSW_REG_RALST_BIN_COUNT 128 6979 6980/* reg_ralst_left_child_bin 6981 * Holding the children of the bin according to the stored tree's structure. 6982 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6983 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6984 * Access: RW 6985 */ 6986MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6987 6988/* reg_ralst_right_child_bin 6989 * Holding the children of the bin according to the stored tree's structure. 6990 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6991 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6992 * Access: RW 6993 */ 6994MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6995 false); 6996 6997static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6998{ 6999 MLXSW_REG_ZERO(ralst, payload); 7000 7001 /* Initialize all bins to have no left or right child */ 7002 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7003 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7004 7005 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7006 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7007} 7008 7009static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7010 u8 left_child_bin, 7011 u8 right_child_bin) 7012{ 7013 int bin_index = bin_number - 1; 7014 7015 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7016 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7017 right_child_bin); 7018} 7019 7020/* RALTB - Router Algorithmic LPM Tree Binding Register 7021 * ---------------------------------------------------- 7022 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7023 */ 7024#define MLXSW_REG_RALTB_ID 0x8012 7025#define MLXSW_REG_RALTB_LEN 0x04 7026 7027MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7028 7029/* reg_raltb_virtual_router 7030 * Virtual Router ID 7031 * Range is 0..cap_max_virtual_routers-1 7032 * Access: Index 7033 */ 7034MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7035 7036/* reg_raltb_protocol 7037 * Protocol. 7038 * Access: Index 7039 */ 7040MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7041 7042/* reg_raltb_tree_id 7043 * Tree to be used for the {virtual_router, protocol} 7044 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7045 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7046 * Access: RW 7047 */ 7048MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7049 7050static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7051 enum mlxsw_reg_ralxx_protocol protocol, 7052 u8 tree_id) 7053{ 7054 MLXSW_REG_ZERO(raltb, payload); 7055 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7056 mlxsw_reg_raltb_protocol_set(payload, protocol); 7057 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7058} 7059 7060/* RALUE - Router Algorithmic LPM Unicast Entry Register 7061 * ----------------------------------------------------- 7062 * RALUE is used to configure and query LPM entries that serve 7063 * the Unicast protocols. 7064 */ 7065#define MLXSW_REG_RALUE_ID 0x8013 7066#define MLXSW_REG_RALUE_LEN 0x38 7067 7068MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7069 7070/* reg_ralue_protocol 7071 * Protocol. 7072 * Access: Index 7073 */ 7074MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7075 7076enum mlxsw_reg_ralue_op { 7077 /* Read operation. If entry doesn't exist, the operation fails. */ 7078 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7079 /* Clear on read operation. Used to read entry and 7080 * clear Activity bit. 7081 */ 7082 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7083 /* Write operation. Used to write a new entry to the table. All RW 7084 * fields are written for new entry. Activity bit is set 7085 * for new entries. 7086 */ 7087 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7088 /* Update operation. Used to update an existing route entry and 7089 * only update the RW fields that are detailed in the field 7090 * op_u_mask. If entry doesn't exist, the operation fails. 7091 */ 7092 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7093 /* Clear activity. The Activity bit (the field a) is cleared 7094 * for the entry. 7095 */ 7096 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7097 /* Delete operation. Used to delete an existing entry. If entry 7098 * doesn't exist, the operation fails. 7099 */ 7100 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7101}; 7102 7103/* reg_ralue_op 7104 * Operation. 7105 * Access: OP 7106 */ 7107MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7108 7109/* reg_ralue_a 7110 * Activity. Set for new entries. Set if a packet lookup has hit on the 7111 * specific entry, only if the entry is a route. To clear the a bit, use 7112 * "clear activity" op. 7113 * Enabled by activity_dis in RGCR 7114 * Access: RO 7115 */ 7116MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7117 7118/* reg_ralue_virtual_router 7119 * Virtual Router ID 7120 * Range is 0..cap_max_virtual_routers-1 7121 * Access: Index 7122 */ 7123MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7124 7125#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7126#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7127#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7128 7129/* reg_ralue_op_u_mask 7130 * opcode update mask. 7131 * On read operation, this field is reserved. 7132 * This field is valid for update opcode, otherwise - reserved. 7133 * This field is a bitmask of the fields that should be updated. 7134 * Access: WO 7135 */ 7136MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7137 7138/* reg_ralue_prefix_len 7139 * Number of bits in the prefix of the LPM route. 7140 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7141 * two entries in the physical HW table. 7142 * Access: Index 7143 */ 7144MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7145 7146/* reg_ralue_dip* 7147 * The prefix of the route or of the marker that the object of the LPM 7148 * is compared with. The most significant bits of the dip are the prefix. 7149 * The least significant bits must be '0' if the prefix_len is smaller 7150 * than 128 for IPv6 or smaller than 32 for IPv4. 7151 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7152 * Access: Index 7153 */ 7154MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7155MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7156 7157enum mlxsw_reg_ralue_entry_type { 7158 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7159 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7160 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7161}; 7162 7163/* reg_ralue_entry_type 7164 * Entry type. 7165 * Note - for Marker entries, the action_type and action fields are reserved. 7166 * Access: RW 7167 */ 7168MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7169 7170/* reg_ralue_bmp_len 7171 * The best match prefix length in the case that there is no match for 7172 * longer prefixes. 7173 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7174 * Note for any update operation with entry_type modification this 7175 * field must be set. 7176 * Access: RW 7177 */ 7178MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7179 7180enum mlxsw_reg_ralue_action_type { 7181 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7182 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7183 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7184}; 7185 7186/* reg_ralue_action_type 7187 * Action Type 7188 * Indicates how the IP address is connected. 7189 * It can be connected to a local subnet through local_erif or can be 7190 * on a remote subnet connected through a next-hop router, 7191 * or transmitted to the CPU. 7192 * Reserved when entry_type = MARKER_ENTRY 7193 * Access: RW 7194 */ 7195MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7196 7197enum mlxsw_reg_ralue_trap_action { 7198 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7199 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7200 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7201 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7202 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7203}; 7204 7205/* reg_ralue_trap_action 7206 * Trap action. 7207 * For IP2ME action, only NOP and MIRROR are possible. 7208 * Access: RW 7209 */ 7210MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7211 7212/* reg_ralue_trap_id 7213 * Trap ID to be reported to CPU. 7214 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7215 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7216 * Access: RW 7217 */ 7218MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7219 7220/* reg_ralue_adjacency_index 7221 * Points to the first entry of the group-based ECMP. 7222 * Only relevant in case of REMOTE action. 7223 * Access: RW 7224 */ 7225MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7226 7227/* reg_ralue_ecmp_size 7228 * Amount of sequential entries starting 7229 * from the adjacency_index (the number of ECMPs). 7230 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7231 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7232 * Only relevant in case of REMOTE action. 7233 * Access: RW 7234 */ 7235MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7236 7237/* reg_ralue_local_erif 7238 * Egress Router Interface. 7239 * Only relevant in case of LOCAL action. 7240 * Access: RW 7241 */ 7242MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7243 7244/* reg_ralue_ip2me_v 7245 * Valid bit for the tunnel_ptr field. 7246 * If valid = 0 then trap to CPU as IP2ME trap ID. 7247 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7248 * decapsulation then tunnel decapsulation is done. 7249 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7250 * decapsulation then trap as IP2ME trap ID. 7251 * Only relevant in case of IP2ME action. 7252 * Access: RW 7253 */ 7254MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7255 7256/* reg_ralue_ip2me_tunnel_ptr 7257 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7258 * For Spectrum, pointer to KVD Linear. 7259 * Only relevant in case of IP2ME action. 7260 * Access: RW 7261 */ 7262MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7263 7264static inline void mlxsw_reg_ralue_pack(char *payload, 7265 enum mlxsw_reg_ralxx_protocol protocol, 7266 enum mlxsw_reg_ralue_op op, 7267 u16 virtual_router, u8 prefix_len) 7268{ 7269 MLXSW_REG_ZERO(ralue, payload); 7270 mlxsw_reg_ralue_protocol_set(payload, protocol); 7271 mlxsw_reg_ralue_op_set(payload, op); 7272 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7273 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7274 mlxsw_reg_ralue_entry_type_set(payload, 7275 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7276 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7277} 7278 7279static inline void mlxsw_reg_ralue_pack4(char *payload, 7280 enum mlxsw_reg_ralxx_protocol protocol, 7281 enum mlxsw_reg_ralue_op op, 7282 u16 virtual_router, u8 prefix_len, 7283 u32 dip) 7284{ 7285 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7286 mlxsw_reg_ralue_dip4_set(payload, dip); 7287} 7288 7289static inline void mlxsw_reg_ralue_pack6(char *payload, 7290 enum mlxsw_reg_ralxx_protocol protocol, 7291 enum mlxsw_reg_ralue_op op, 7292 u16 virtual_router, u8 prefix_len, 7293 const void *dip) 7294{ 7295 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7296 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7297} 7298 7299static inline void 7300mlxsw_reg_ralue_act_remote_pack(char *payload, 7301 enum mlxsw_reg_ralue_trap_action trap_action, 7302 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7303{ 7304 mlxsw_reg_ralue_action_type_set(payload, 7305 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7306 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7307 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7308 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7309 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7310} 7311 7312static inline void 7313mlxsw_reg_ralue_act_local_pack(char *payload, 7314 enum mlxsw_reg_ralue_trap_action trap_action, 7315 u16 trap_id, u16 local_erif) 7316{ 7317 mlxsw_reg_ralue_action_type_set(payload, 7318 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7319 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7320 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7321 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7322} 7323 7324static inline void 7325mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7326{ 7327 mlxsw_reg_ralue_action_type_set(payload, 7328 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7329} 7330 7331static inline void 7332mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7333{ 7334 mlxsw_reg_ralue_action_type_set(payload, 7335 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7336 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7337 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7338} 7339 7340/* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7341 * ---------------------------------------------------------- 7342 * The RAUHT register is used to configure and query the Unicast Host table in 7343 * devices that implement the Algorithmic LPM. 7344 */ 7345#define MLXSW_REG_RAUHT_ID 0x8014 7346#define MLXSW_REG_RAUHT_LEN 0x74 7347 7348MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7349 7350enum mlxsw_reg_rauht_type { 7351 MLXSW_REG_RAUHT_TYPE_IPV4, 7352 MLXSW_REG_RAUHT_TYPE_IPV6, 7353}; 7354 7355/* reg_rauht_type 7356 * Access: Index 7357 */ 7358MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7359 7360enum mlxsw_reg_rauht_op { 7361 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7362 /* Read operation */ 7363 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7364 /* Clear on read operation. Used to read entry and clear 7365 * activity bit. 7366 */ 7367 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7368 /* Add. Used to write a new entry to the table. All R/W fields are 7369 * relevant for new entry. Activity bit is set for new entries. 7370 */ 7371 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7372 /* Update action. Used to update an existing route entry and 7373 * only update the following fields: 7374 * trap_action, trap_id, mac, counter_set_type, counter_index 7375 */ 7376 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7377 /* Clear activity. A bit is cleared for the entry. */ 7378 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7379 /* Delete entry */ 7380 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7381 /* Delete all host entries on a RIF. In this command, dip 7382 * field is reserved. 7383 */ 7384}; 7385 7386/* reg_rauht_op 7387 * Access: OP 7388 */ 7389MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7390 7391/* reg_rauht_a 7392 * Activity. Set for new entries. Set if a packet lookup has hit on 7393 * the specific entry. 7394 * To clear the a bit, use "clear activity" op. 7395 * Enabled by activity_dis in RGCR 7396 * Access: RO 7397 */ 7398MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7399 7400/* reg_rauht_rif 7401 * Router Interface 7402 * Access: Index 7403 */ 7404MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7405 7406/* reg_rauht_dip* 7407 * Destination address. 7408 * Access: Index 7409 */ 7410MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7411MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7412 7413enum mlxsw_reg_rauht_trap_action { 7414 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7415 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7416 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7417 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7418 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7419}; 7420 7421/* reg_rauht_trap_action 7422 * Access: RW 7423 */ 7424MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7425 7426enum mlxsw_reg_rauht_trap_id { 7427 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7428 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7429}; 7430 7431/* reg_rauht_trap_id 7432 * Trap ID to be reported to CPU. 7433 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7434 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7435 * trap_id is reserved. 7436 * Access: RW 7437 */ 7438MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7439 7440/* reg_rauht_counter_set_type 7441 * Counter set type for flow counters 7442 * Access: RW 7443 */ 7444MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7445 7446/* reg_rauht_counter_index 7447 * Counter index for flow counters 7448 * Access: RW 7449 */ 7450MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7451 7452/* reg_rauht_mac 7453 * MAC address. 7454 * Access: RW 7455 */ 7456MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7457 7458static inline void mlxsw_reg_rauht_pack(char *payload, 7459 enum mlxsw_reg_rauht_op op, u16 rif, 7460 const char *mac) 7461{ 7462 MLXSW_REG_ZERO(rauht, payload); 7463 mlxsw_reg_rauht_op_set(payload, op); 7464 mlxsw_reg_rauht_rif_set(payload, rif); 7465 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7466} 7467 7468static inline void mlxsw_reg_rauht_pack4(char *payload, 7469 enum mlxsw_reg_rauht_op op, u16 rif, 7470 const char *mac, u32 dip) 7471{ 7472 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7473 mlxsw_reg_rauht_dip4_set(payload, dip); 7474} 7475 7476static inline void mlxsw_reg_rauht_pack6(char *payload, 7477 enum mlxsw_reg_rauht_op op, u16 rif, 7478 const char *mac, const char *dip) 7479{ 7480 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7481 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7482 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7483} 7484 7485static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7486 u64 counter_index) 7487{ 7488 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7489 mlxsw_reg_rauht_counter_set_type_set(payload, 7490 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7491} 7492 7493/* RALEU - Router Algorithmic LPM ECMP Update Register 7494 * --------------------------------------------------- 7495 * The register enables updating the ECMP section in the action for multiple 7496 * LPM Unicast entries in a single operation. The update is executed to 7497 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7498 */ 7499#define MLXSW_REG_RALEU_ID 0x8015 7500#define MLXSW_REG_RALEU_LEN 0x28 7501 7502MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7503 7504/* reg_raleu_protocol 7505 * Protocol. 7506 * Access: Index 7507 */ 7508MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7509 7510/* reg_raleu_virtual_router 7511 * Virtual Router ID 7512 * Range is 0..cap_max_virtual_routers-1 7513 * Access: Index 7514 */ 7515MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7516 7517/* reg_raleu_adjacency_index 7518 * Adjacency Index used for matching on the existing entries. 7519 * Access: Index 7520 */ 7521MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7522 7523/* reg_raleu_ecmp_size 7524 * ECMP Size used for matching on the existing entries. 7525 * Access: Index 7526 */ 7527MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7528 7529/* reg_raleu_new_adjacency_index 7530 * New Adjacency Index. 7531 * Access: WO 7532 */ 7533MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7534 7535/* reg_raleu_new_ecmp_size 7536 * New ECMP Size. 7537 * Access: WO 7538 */ 7539MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7540 7541static inline void mlxsw_reg_raleu_pack(char *payload, 7542 enum mlxsw_reg_ralxx_protocol protocol, 7543 u16 virtual_router, 7544 u32 adjacency_index, u16 ecmp_size, 7545 u32 new_adjacency_index, 7546 u16 new_ecmp_size) 7547{ 7548 MLXSW_REG_ZERO(raleu, payload); 7549 mlxsw_reg_raleu_protocol_set(payload, protocol); 7550 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7551 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7552 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7553 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7554 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7555} 7556 7557/* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7558 * ---------------------------------------------------------------- 7559 * The RAUHTD register allows dumping entries from the Router Unicast Host 7560 * Table. For a given session an entry is dumped no more than one time. The 7561 * first RAUHTD access after reset is a new session. A session ends when the 7562 * num_rec response is smaller than num_rec request or for IPv4 when the 7563 * num_entries is smaller than 4. The clear activity affect the current session 7564 * or the last session if a new session has not started. 7565 */ 7566#define MLXSW_REG_RAUHTD_ID 0x8018 7567#define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7568#define MLXSW_REG_RAUHTD_REC_LEN 0x20 7569#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7570#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7571 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7572#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7573 7574MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7575 7576#define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7577#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7578 7579/* reg_rauhtd_filter_fields 7580 * if a bit is '0' then the relevant field is ignored and dump is done 7581 * regardless of the field value 7582 * Bit0 - filter by activity: entry_a 7583 * Bit3 - filter by entry rip: entry_rif 7584 * Access: Index 7585 */ 7586MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7587 7588enum mlxsw_reg_rauhtd_op { 7589 MLXSW_REG_RAUHTD_OP_DUMP, 7590 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7591}; 7592 7593/* reg_rauhtd_op 7594 * Access: OP 7595 */ 7596MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7597 7598/* reg_rauhtd_num_rec 7599 * At request: number of records requested 7600 * At response: number of records dumped 7601 * For IPv4, each record has 4 entries at request and up to 4 entries 7602 * at response 7603 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7604 * Access: Index 7605 */ 7606MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7607 7608/* reg_rauhtd_entry_a 7609 * Dump only if activity has value of entry_a 7610 * Reserved if filter_fields bit0 is '0' 7611 * Access: Index 7612 */ 7613MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7614 7615enum mlxsw_reg_rauhtd_type { 7616 MLXSW_REG_RAUHTD_TYPE_IPV4, 7617 MLXSW_REG_RAUHTD_TYPE_IPV6, 7618}; 7619 7620/* reg_rauhtd_type 7621 * Dump only if record type is: 7622 * 0 - IPv4 7623 * 1 - IPv6 7624 * Access: Index 7625 */ 7626MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7627 7628/* reg_rauhtd_entry_rif 7629 * Dump only if RIF has value of entry_rif 7630 * Reserved if filter_fields bit3 is '0' 7631 * Access: Index 7632 */ 7633MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7634 7635static inline void mlxsw_reg_rauhtd_pack(char *payload, 7636 enum mlxsw_reg_rauhtd_type type) 7637{ 7638 MLXSW_REG_ZERO(rauhtd, payload); 7639 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7640 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7641 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7642 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7643 mlxsw_reg_rauhtd_type_set(payload, type); 7644} 7645 7646/* reg_rauhtd_ipv4_rec_num_entries 7647 * Number of valid entries in this record: 7648 * 0 - 1 valid entry 7649 * 1 - 2 valid entries 7650 * 2 - 3 valid entries 7651 * 3 - 4 valid entries 7652 * Access: RO 7653 */ 7654MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7655 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7656 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7657 7658/* reg_rauhtd_rec_type 7659 * Record type. 7660 * 0 - IPv4 7661 * 1 - IPv6 7662 * Access: RO 7663 */ 7664MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7665 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7666 7667#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7668 7669/* reg_rauhtd_ipv4_ent_a 7670 * Activity. Set for new entries. Set if a packet lookup has hit on the 7671 * specific entry. 7672 * Access: RO 7673 */ 7674MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7675 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7676 7677/* reg_rauhtd_ipv4_ent_rif 7678 * Router interface. 7679 * Access: RO 7680 */ 7681MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7682 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7683 7684/* reg_rauhtd_ipv4_ent_dip 7685 * Destination IPv4 address. 7686 * Access: RO 7687 */ 7688MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7689 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7690 7691#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7692 7693/* reg_rauhtd_ipv6_ent_a 7694 * Activity. Set for new entries. Set if a packet lookup has hit on the 7695 * specific entry. 7696 * Access: RO 7697 */ 7698MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7699 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7700 7701/* reg_rauhtd_ipv6_ent_rif 7702 * Router interface. 7703 * Access: RO 7704 */ 7705MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7706 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7707 7708/* reg_rauhtd_ipv6_ent_dip 7709 * Destination IPv6 address. 7710 * Access: RO 7711 */ 7712MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7713 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7714 7715static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7716 int ent_index, u16 *p_rif, 7717 u32 *p_dip) 7718{ 7719 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7720 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7721} 7722 7723static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7724 int rec_index, u16 *p_rif, 7725 char *p_dip) 7726{ 7727 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7728 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7729} 7730 7731/* RTDP - Routing Tunnel Decap Properties Register 7732 * ----------------------------------------------- 7733 * The RTDP register is used for configuring the tunnel decap properties of NVE 7734 * and IPinIP. 7735 */ 7736#define MLXSW_REG_RTDP_ID 0x8020 7737#define MLXSW_REG_RTDP_LEN 0x44 7738 7739MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7740 7741enum mlxsw_reg_rtdp_type { 7742 MLXSW_REG_RTDP_TYPE_NVE, 7743 MLXSW_REG_RTDP_TYPE_IPIP, 7744}; 7745 7746/* reg_rtdp_type 7747 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7748 * Access: RW 7749 */ 7750MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7751 7752/* reg_rtdp_tunnel_index 7753 * Index to the Decap entry. 7754 * For Spectrum, Index to KVD Linear. 7755 * Access: Index 7756 */ 7757MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7758 7759/* reg_rtdp_egress_router_interface 7760 * Underlay egress router interface. 7761 * Valid range is from 0 to cap_max_router_interfaces - 1 7762 * Access: RW 7763 */ 7764MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7765 7766/* IPinIP */ 7767 7768/* reg_rtdp_ipip_irif 7769 * Ingress Router Interface for the overlay router 7770 * Access: RW 7771 */ 7772MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7773 7774enum mlxsw_reg_rtdp_ipip_sip_check { 7775 /* No sip checks. */ 7776 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7777 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7778 * equal ipv4_usip. 7779 */ 7780 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7781 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7782 * equal ipv6_usip. 7783 */ 7784 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7785}; 7786 7787/* reg_rtdp_ipip_sip_check 7788 * SIP check to perform. If decapsulation failed due to these configurations 7789 * then trap_id is IPIP_DECAP_ERROR. 7790 * Access: RW 7791 */ 7792MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7793 7794/* If set, allow decapsulation of IPinIP (without GRE). */ 7795#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7796/* If set, allow decapsulation of IPinGREinIP without a key. */ 7797#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7798/* If set, allow decapsulation of IPinGREinIP with a key. */ 7799#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7800 7801/* reg_rtdp_ipip_type_check 7802 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7803 * these configurations then trap_id is IPIP_DECAP_ERROR. 7804 * Access: RW 7805 */ 7806MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7807 7808/* reg_rtdp_ipip_gre_key_check 7809 * Whether GRE key should be checked. When check is enabled: 7810 * - A packet received as IPinIP (without GRE) will always pass. 7811 * - A packet received as IPinGREinIP without a key will not pass the check. 7812 * - A packet received as IPinGREinIP with a key will pass the check only if the 7813 * key in the packet is equal to expected_gre_key. 7814 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7815 * Access: RW 7816 */ 7817MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7818 7819/* reg_rtdp_ipip_ipv4_usip 7820 * Underlay IPv4 address for ipv4 source address check. 7821 * Reserved when sip_check is not '1'. 7822 * Access: RW 7823 */ 7824MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7825 7826/* reg_rtdp_ipip_ipv6_usip_ptr 7827 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7828 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7829 * is to the KVD linear. 7830 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7831 * Access: RW 7832 */ 7833MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7834 7835/* reg_rtdp_ipip_expected_gre_key 7836 * GRE key for checking. 7837 * Reserved when gre_key_check is '0'. 7838 * Access: RW 7839 */ 7840MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7841 7842static inline void mlxsw_reg_rtdp_pack(char *payload, 7843 enum mlxsw_reg_rtdp_type type, 7844 u32 tunnel_index) 7845{ 7846 MLXSW_REG_ZERO(rtdp, payload); 7847 mlxsw_reg_rtdp_type_set(payload, type); 7848 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7849} 7850 7851static inline void 7852mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7853 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7854 unsigned int type_check, bool gre_key_check, 7855 u32 ipv4_usip, u32 expected_gre_key) 7856{ 7857 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7858 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7859 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7860 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7861 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7862 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7863} 7864 7865/* RIGR-V2 - Router Interface Group Register Version 2 7866 * --------------------------------------------------- 7867 * The RIGR_V2 register is used to add, remove and query egress interface list 7868 * of a multicast forwarding entry. 7869 */ 7870#define MLXSW_REG_RIGR2_ID 0x8023 7871#define MLXSW_REG_RIGR2_LEN 0xB0 7872 7873#define MLXSW_REG_RIGR2_MAX_ERIFS 32 7874 7875MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7876 7877/* reg_rigr2_rigr_index 7878 * KVD Linear index. 7879 * Access: Index 7880 */ 7881MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7882 7883/* reg_rigr2_vnext 7884 * Next RIGR Index is valid. 7885 * Access: RW 7886 */ 7887MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7888 7889/* reg_rigr2_next_rigr_index 7890 * Next RIGR Index. The index is to the KVD linear. 7891 * Reserved when vnxet = '0'. 7892 * Access: RW 7893 */ 7894MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7895 7896/* reg_rigr2_vrmid 7897 * RMID Index is valid. 7898 * Access: RW 7899 */ 7900MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7901 7902/* reg_rigr2_rmid_index 7903 * RMID Index. 7904 * Range 0 .. max_mid - 1 7905 * Reserved when vrmid = '0'. 7906 * The index is to the Port Group Table (PGT) 7907 * Access: RW 7908 */ 7909MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7910 7911/* reg_rigr2_erif_entry_v 7912 * Egress Router Interface is valid. 7913 * Note that low-entries must be set if high-entries are set. For 7914 * example: if erif_entry[2].v is set then erif_entry[1].v and 7915 * erif_entry[0].v must be set. 7916 * Index can be from 0 to cap_mc_erif_list_entries-1 7917 * Access: RW 7918 */ 7919MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7920 7921/* reg_rigr2_erif_entry_erif 7922 * Egress Router Interface. 7923 * Valid range is from 0 to cap_max_router_interfaces - 1 7924 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7925 * Access: RW 7926 */ 7927MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7928 7929static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7930 bool vnext, u32 next_rigr_index) 7931{ 7932 MLXSW_REG_ZERO(rigr2, payload); 7933 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7934 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7935 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7936 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7937 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7938} 7939 7940static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7941 bool v, u16 erif) 7942{ 7943 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7944 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7945} 7946 7947/* RECR-V2 - Router ECMP Configuration Version 2 Register 7948 * ------------------------------------------------------ 7949 */ 7950#define MLXSW_REG_RECR2_ID 0x8025 7951#define MLXSW_REG_RECR2_LEN 0x38 7952 7953MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7954 7955/* reg_recr2_pp 7956 * Per-port configuration 7957 * Access: Index 7958 */ 7959MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7960 7961/* reg_recr2_sh 7962 * Symmetric hash 7963 * Access: RW 7964 */ 7965MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7966 7967/* reg_recr2_seed 7968 * Seed 7969 * Access: RW 7970 */ 7971MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7972 7973enum { 7974 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7975 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7976 /* Enable IPv4 fields if packet is TCP or UDP */ 7977 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7978 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7979 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7980 /* Enable IPv6 fields if packet is TCP or UDP */ 7981 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7982 /* Enable TCP/UDP header fields if packet is IPv4 */ 7983 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7984 /* Enable TCP/UDP header fields if packet is IPv6 */ 7985 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7986}; 7987 7988/* reg_recr2_outer_header_enables 7989 * Bit mask where each bit enables a specific layer to be included in 7990 * the hash calculation. 7991 * Access: RW 7992 */ 7993MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7994 7995enum { 7996 /* IPv4 Source IP */ 7997 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7998 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7999 /* IPv4 Destination IP */ 8000 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8001 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8002 /* IP Protocol */ 8003 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8004 /* IPv6 Source IP */ 8005 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8006 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8007 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8008 /* IPv6 Destination IP */ 8009 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8010 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8011 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8012 /* IPv6 Next Header */ 8013 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8014 /* IPv6 Flow Label */ 8015 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8016 /* TCP/UDP Source Port */ 8017 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8018 /* TCP/UDP Destination Port */ 8019 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8020}; 8021 8022/* reg_recr2_outer_header_fields_enable 8023 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8024 * Access: RW 8025 */ 8026MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8027 8028static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 8029{ 8030 int i; 8031 8032 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 8033 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8034 true); 8035} 8036 8037static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 8038{ 8039 int i; 8040 8041 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 8042 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8043 true); 8044} 8045 8046static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 8047{ 8048 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 8049 8050 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8051 8052 i = MLXSW_REG_RECR2_IPV6_SIP8; 8053 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 8054 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8055 true); 8056} 8057 8058static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 8059{ 8060 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 8061 8062 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8063 8064 i = MLXSW_REG_RECR2_IPV6_DIP8; 8065 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 8066 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8067 true); 8068} 8069 8070static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8071{ 8072 MLXSW_REG_ZERO(recr2, payload); 8073 mlxsw_reg_recr2_pp_set(payload, false); 8074 mlxsw_reg_recr2_sh_set(payload, true); 8075 mlxsw_reg_recr2_seed_set(payload, seed); 8076} 8077 8078/* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8079 * -------------------------------------------------------------- 8080 * The RMFT_V2 register is used to configure and query the multicast table. 8081 */ 8082#define MLXSW_REG_RMFT2_ID 0x8027 8083#define MLXSW_REG_RMFT2_LEN 0x174 8084 8085MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8086 8087/* reg_rmft2_v 8088 * Valid 8089 * Access: RW 8090 */ 8091MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8092 8093enum mlxsw_reg_rmft2_type { 8094 MLXSW_REG_RMFT2_TYPE_IPV4, 8095 MLXSW_REG_RMFT2_TYPE_IPV6 8096}; 8097 8098/* reg_rmft2_type 8099 * Access: Index 8100 */ 8101MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8102 8103enum mlxsw_sp_reg_rmft2_op { 8104 /* For Write: 8105 * Write operation. Used to write a new entry to the table. All RW 8106 * fields are relevant for new entry. Activity bit is set for new 8107 * entries - Note write with v (Valid) 0 will delete the entry. 8108 * For Query: 8109 * Read operation 8110 */ 8111 MLXSW_REG_RMFT2_OP_READ_WRITE, 8112}; 8113 8114/* reg_rmft2_op 8115 * Operation. 8116 * Access: OP 8117 */ 8118MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8119 8120/* reg_rmft2_a 8121 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8122 * entry. 8123 * Access: RO 8124 */ 8125MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8126 8127/* reg_rmft2_offset 8128 * Offset within the multicast forwarding table to write to. 8129 * Access: Index 8130 */ 8131MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8132 8133/* reg_rmft2_virtual_router 8134 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8135 * Access: RW 8136 */ 8137MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8138 8139enum mlxsw_reg_rmft2_irif_mask { 8140 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8141 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8142}; 8143 8144/* reg_rmft2_irif_mask 8145 * Ingress RIF mask. 8146 * Access: RW 8147 */ 8148MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8149 8150/* reg_rmft2_irif 8151 * Ingress RIF index. 8152 * Access: RW 8153 */ 8154MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8155 8156/* reg_rmft2_dip{4,6} 8157 * Destination IPv4/6 address 8158 * Access: RW 8159 */ 8160MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8161MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8162 8163/* reg_rmft2_dip{4,6}_mask 8164 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8165 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8166 * Access: RW 8167 */ 8168MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8169MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8170 8171/* reg_rmft2_sip{4,6} 8172 * Source IPv4/6 address 8173 * Access: RW 8174 */ 8175MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8176MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8177 8178/* reg_rmft2_sip{4,6}_mask 8179 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8180 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8181 * Access: RW 8182 */ 8183MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8184MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8185 8186/* reg_rmft2_flexible_action_set 8187 * ACL action set. The only supported action types in this field and in any 8188 * action-set pointed from here are as follows: 8189 * 00h: ACTION_NULL 8190 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8191 * 03h: ACTION_TRAP 8192 * 06h: ACTION_QOS 8193 * 08h: ACTION_POLICING_MONITORING 8194 * 10h: ACTION_ROUTER_MC 8195 * Access: RW 8196 */ 8197MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8198 MLXSW_REG_FLEX_ACTION_SET_LEN); 8199 8200static inline void 8201mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8202 u16 virtual_router, 8203 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8204 const char *flex_action_set) 8205{ 8206 MLXSW_REG_ZERO(rmft2, payload); 8207 mlxsw_reg_rmft2_v_set(payload, v); 8208 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8209 mlxsw_reg_rmft2_offset_set(payload, offset); 8210 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8211 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8212 mlxsw_reg_rmft2_irif_set(payload, irif); 8213 if (flex_action_set) 8214 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8215 flex_action_set); 8216} 8217 8218static inline void 8219mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8220 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8221 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8222 const char *flexible_action_set) 8223{ 8224 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8225 irif_mask, irif, flexible_action_set); 8226 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8227 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8228 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8229 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8230 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8231} 8232 8233static inline void 8234mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8235 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8236 struct in6_addr dip6, struct in6_addr dip6_mask, 8237 struct in6_addr sip6, struct in6_addr sip6_mask, 8238 const char *flexible_action_set) 8239{ 8240 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8241 irif_mask, irif, flexible_action_set); 8242 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8243 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8244 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8245 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8246 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8247} 8248 8249/* MFCR - Management Fan Control Register 8250 * -------------------------------------- 8251 * This register controls the settings of the Fan Speed PWM mechanism. 8252 */ 8253#define MLXSW_REG_MFCR_ID 0x9001 8254#define MLXSW_REG_MFCR_LEN 0x08 8255 8256MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8257 8258enum mlxsw_reg_mfcr_pwm_frequency { 8259 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8260 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8261 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8262 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8263 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8264 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8265 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8266 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8267}; 8268 8269/* reg_mfcr_pwm_frequency 8270 * Controls the frequency of the PWM signal. 8271 * Access: RW 8272 */ 8273MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8274 8275#define MLXSW_MFCR_TACHOS_MAX 10 8276 8277/* reg_mfcr_tacho_active 8278 * Indicates which of the tachometer is active (bit per tachometer). 8279 * Access: RO 8280 */ 8281MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8282 8283#define MLXSW_MFCR_PWMS_MAX 5 8284 8285/* reg_mfcr_pwm_active 8286 * Indicates which of the PWM control is active (bit per PWM). 8287 * Access: RO 8288 */ 8289MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8290 8291static inline void 8292mlxsw_reg_mfcr_pack(char *payload, 8293 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8294{ 8295 MLXSW_REG_ZERO(mfcr, payload); 8296 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8297} 8298 8299static inline void 8300mlxsw_reg_mfcr_unpack(char *payload, 8301 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8302 u16 *p_tacho_active, u8 *p_pwm_active) 8303{ 8304 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8305 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8306 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8307} 8308 8309/* MFSC - Management Fan Speed Control Register 8310 * -------------------------------------------- 8311 * This register controls the settings of the Fan Speed PWM mechanism. 8312 */ 8313#define MLXSW_REG_MFSC_ID 0x9002 8314#define MLXSW_REG_MFSC_LEN 0x08 8315 8316MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8317 8318/* reg_mfsc_pwm 8319 * Fan pwm to control / monitor. 8320 * Access: Index 8321 */ 8322MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8323 8324/* reg_mfsc_pwm_duty_cycle 8325 * Controls the duty cycle of the PWM. Value range from 0..255 to 8326 * represent duty cycle of 0%...100%. 8327 * Access: RW 8328 */ 8329MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8330 8331static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8332 u8 pwm_duty_cycle) 8333{ 8334 MLXSW_REG_ZERO(mfsc, payload); 8335 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8336 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8337} 8338 8339/* MFSM - Management Fan Speed Measurement 8340 * --------------------------------------- 8341 * This register controls the settings of the Tacho measurements and 8342 * enables reading the Tachometer measurements. 8343 */ 8344#define MLXSW_REG_MFSM_ID 0x9003 8345#define MLXSW_REG_MFSM_LEN 0x08 8346 8347MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8348 8349/* reg_mfsm_tacho 8350 * Fan tachometer index. 8351 * Access: Index 8352 */ 8353MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8354 8355/* reg_mfsm_rpm 8356 * Fan speed (round per minute). 8357 * Access: RO 8358 */ 8359MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8360 8361static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8362{ 8363 MLXSW_REG_ZERO(mfsm, payload); 8364 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8365} 8366 8367/* MFSL - Management Fan Speed Limit Register 8368 * ------------------------------------------ 8369 * The Fan Speed Limit register is used to configure the fan speed 8370 * event / interrupt notification mechanism. Fan speed threshold are 8371 * defined for both under-speed and over-speed. 8372 */ 8373#define MLXSW_REG_MFSL_ID 0x9004 8374#define MLXSW_REG_MFSL_LEN 0x0C 8375 8376MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8377 8378/* reg_mfsl_tacho 8379 * Fan tachometer index. 8380 * Access: Index 8381 */ 8382MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8383 8384/* reg_mfsl_tach_min 8385 * Tachometer minimum value (minimum RPM). 8386 * Access: RW 8387 */ 8388MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8389 8390/* reg_mfsl_tach_max 8391 * Tachometer maximum value (maximum RPM). 8392 * Access: RW 8393 */ 8394MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8395 8396static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8397 u16 tach_min, u16 tach_max) 8398{ 8399 MLXSW_REG_ZERO(mfsl, payload); 8400 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8401 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8402 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8403} 8404 8405static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8406 u16 *p_tach_min, u16 *p_tach_max) 8407{ 8408 if (p_tach_min) 8409 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8410 8411 if (p_tach_max) 8412 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8413} 8414 8415/* FORE - Fan Out of Range Event Register 8416 * -------------------------------------- 8417 * This register reports the status of the controlled fans compared to the 8418 * range defined by the MFSL register. 8419 */ 8420#define MLXSW_REG_FORE_ID 0x9007 8421#define MLXSW_REG_FORE_LEN 0x0C 8422 8423MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8424 8425/* fan_under_limit 8426 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8427 * to a single tachometer and indicates the specific tachometer reading is 8428 * below the threshold. 8429 * Access: RO 8430 */ 8431MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8432 8433static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8434 bool *fault) 8435{ 8436 u16 limit; 8437 8438 if (fault) { 8439 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8440 *fault = limit & BIT(tacho); 8441 } 8442} 8443 8444/* MTCAP - Management Temperature Capabilities 8445 * ------------------------------------------- 8446 * This register exposes the capabilities of the device and 8447 * system temperature sensing. 8448 */ 8449#define MLXSW_REG_MTCAP_ID 0x9009 8450#define MLXSW_REG_MTCAP_LEN 0x08 8451 8452MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8453 8454/* reg_mtcap_sensor_count 8455 * Number of sensors supported by the device. 8456 * This includes the QSFP module sensors (if exists in the QSFP module). 8457 * Access: RO 8458 */ 8459MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8460 8461/* MTMP - Management Temperature 8462 * ----------------------------- 8463 * This register controls the settings of the temperature measurements 8464 * and enables reading the temperature measurements. Note that temperature 8465 * is in 0.125 degrees Celsius. 8466 */ 8467#define MLXSW_REG_MTMP_ID 0x900A 8468#define MLXSW_REG_MTMP_LEN 0x20 8469 8470MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8471 8472#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8473#define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8474/* reg_mtmp_sensor_index 8475 * Sensors index to access. 8476 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8477 * (module 0 is mapped to sensor_index 64). 8478 * Access: Index 8479 */ 8480MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8481 8482/* Convert to milli degrees Celsius */ 8483#define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8484 ((v_) >= 0) ? ((v_) * 125) : \ 8485 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8486 * 125)); }) 8487 8488/* reg_mtmp_temperature 8489 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8490 * degrees units. 8491 * Access: RO 8492 */ 8493MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8494 8495/* reg_mtmp_mte 8496 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8497 * Access: RW 8498 */ 8499MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8500 8501/* reg_mtmp_mtr 8502 * Max Temperature Reset - clears the value of the max temperature register. 8503 * Access: WO 8504 */ 8505MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8506 8507/* reg_mtmp_max_temperature 8508 * The highest measured temperature from the sensor. 8509 * When the bit mte is cleared, the field max_temperature is reserved. 8510 * Access: RO 8511 */ 8512MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8513 8514/* reg_mtmp_tee 8515 * Temperature Event Enable. 8516 * 0 - Do not generate event 8517 * 1 - Generate event 8518 * 2 - Generate single event 8519 * Access: RW 8520 */ 8521 8522enum mlxsw_reg_mtmp_tee { 8523 MLXSW_REG_MTMP_TEE_NO_EVENT, 8524 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 8525 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 8526}; 8527 8528MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8529 8530#define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8531 8532/* reg_mtmp_temperature_threshold_hi 8533 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8534 * Access: RW 8535 */ 8536MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8537 8538#define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 8539/* reg_mtmp_temperature_threshold_lo 8540 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8541 * Access: RW 8542 */ 8543MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8544 8545#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8546 8547/* reg_mtmp_sensor_name 8548 * Sensor Name 8549 * Access: RO 8550 */ 8551MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8552 8553static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8554 bool max_temp_enable, 8555 bool max_temp_reset) 8556{ 8557 MLXSW_REG_ZERO(mtmp, payload); 8558 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8559 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8560 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8561 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8562 MLXSW_REG_MTMP_THRESH_HI); 8563} 8564 8565static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8566 int *p_max_temp, char *sensor_name) 8567{ 8568 s16 temp; 8569 8570 if (p_temp) { 8571 temp = mlxsw_reg_mtmp_temperature_get(payload); 8572 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8573 } 8574 if (p_max_temp) { 8575 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8576 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8577 } 8578 if (sensor_name) 8579 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8580} 8581 8582/* MTWE - Management Temperature Warning Event 8583 * ------------------------------------------- 8584 * This register is used for over temperature warning. 8585 */ 8586#define MLXSW_REG_MTWE_ID 0x900B 8587#define MLXSW_REG_MTWE_LEN 0x10 8588 8589MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 8590 8591/* reg_mtwe_sensor_warning 8592 * Bit vector indicating which of the sensor reading is above threshold. 8593 * Address 00h bit31 is sensor_warning[127]. 8594 * Address 0Ch bit0 is sensor_warning[0]. 8595 * Access: RO 8596 */ 8597MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 8598 8599/* MTBR - Management Temperature Bulk Register 8600 * ------------------------------------------- 8601 * This register is used for bulk temperature reading. 8602 */ 8603#define MLXSW_REG_MTBR_ID 0x900F 8604#define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8605#define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8606#define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8607#define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8608 MLXSW_REG_MTBR_REC_LEN * \ 8609 MLXSW_REG_MTBR_REC_MAX_COUNT) 8610 8611MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8612 8613/* reg_mtbr_base_sensor_index 8614 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8615 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8616 * Access: Index 8617 */ 8618MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8619 8620/* reg_mtbr_num_rec 8621 * Request: Number of records to read 8622 * Response: Number of records read 8623 * See above description for more details. 8624 * Range 1..255 8625 * Access: RW 8626 */ 8627MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8628 8629/* reg_mtbr_rec_max_temp 8630 * The highest measured temperature from the sensor. 8631 * When the bit mte is cleared, the field max_temperature is reserved. 8632 * Access: RO 8633 */ 8634MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8635 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8636 8637/* reg_mtbr_rec_temp 8638 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8639 * degrees units. 8640 * Access: RO 8641 */ 8642MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8643 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8644 8645static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8646 u8 num_rec) 8647{ 8648 MLXSW_REG_ZERO(mtbr, payload); 8649 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8650 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8651} 8652 8653/* Error codes from temperatute reading */ 8654enum mlxsw_reg_mtbr_temp_status { 8655 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8656 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8657 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8658 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8659}; 8660 8661/* Base index for reading modules temperature */ 8662#define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8663 8664static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8665 u16 *p_temp, u16 *p_max_temp) 8666{ 8667 if (p_temp) 8668 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8669 if (p_max_temp) 8670 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8671} 8672 8673/* MCIA - Management Cable Info Access 8674 * ----------------------------------- 8675 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8676 */ 8677 8678#define MLXSW_REG_MCIA_ID 0x9014 8679#define MLXSW_REG_MCIA_LEN 0x40 8680 8681MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8682 8683/* reg_mcia_l 8684 * Lock bit. Setting this bit will lock the access to the specific 8685 * cable. Used for updating a full page in a cable EPROM. Any access 8686 * other then subsequence writes will fail while the port is locked. 8687 * Access: RW 8688 */ 8689MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8690 8691/* reg_mcia_module 8692 * Module number. 8693 * Access: Index 8694 */ 8695MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8696 8697/* reg_mcia_status 8698 * Module status. 8699 * Access: RO 8700 */ 8701MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8702 8703/* reg_mcia_i2c_device_address 8704 * I2C device address. 8705 * Access: RW 8706 */ 8707MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8708 8709/* reg_mcia_page_number 8710 * Page number. 8711 * Access: RW 8712 */ 8713MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8714 8715/* reg_mcia_device_address 8716 * Device address. 8717 * Access: RW 8718 */ 8719MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8720 8721/* reg_mcia_size 8722 * Number of bytes to read/write (up to 48 bytes). 8723 * Access: RW 8724 */ 8725MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8726 8727#define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8728#define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8729#define MLXSW_REG_MCIA_EEPROM_SIZE 48 8730#define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8731#define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8732#define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8733#define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8734#define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8735#define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 8736#define MLXSW_REG_MCIA_PAGE0_LO 0 8737#define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8738#define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 8739 8740enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8741 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8742 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8743 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8744}; 8745 8746enum mlxsw_reg_mcia_eeprom_module_info_id { 8747 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8748 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8749 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8750 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8751 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8752}; 8753 8754enum mlxsw_reg_mcia_eeprom_module_info { 8755 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8756 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8757 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 8758 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8759}; 8760 8761/* reg_mcia_eeprom 8762 * Bytes to read/write. 8763 * Access: RW 8764 */ 8765MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8766 8767/* This is used to access the optional upper pages (1-3) in the QSFP+ 8768 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8769 * on offset 384 through 511, page 3 - on offset 512 through 639. 8770 */ 8771#define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8772 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8773 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8774 8775static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8776 u8 page_number, u16 device_addr, 8777 u8 size, u8 i2c_device_addr) 8778{ 8779 MLXSW_REG_ZERO(mcia, payload); 8780 mlxsw_reg_mcia_module_set(payload, module); 8781 mlxsw_reg_mcia_l_set(payload, lock); 8782 mlxsw_reg_mcia_page_number_set(payload, page_number); 8783 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8784 mlxsw_reg_mcia_size_set(payload, size); 8785 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8786} 8787 8788/* MPAT - Monitoring Port Analyzer Table 8789 * ------------------------------------- 8790 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8791 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8792 */ 8793#define MLXSW_REG_MPAT_ID 0x901A 8794#define MLXSW_REG_MPAT_LEN 0x78 8795 8796MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8797 8798/* reg_mpat_pa_id 8799 * Port Analyzer ID. 8800 * Access: Index 8801 */ 8802MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8803 8804/* reg_mpat_session_id 8805 * Mirror Session ID. 8806 * Used for MIRROR_SESSION<i> trap. 8807 * Access: RW 8808 */ 8809MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 8810 8811/* reg_mpat_system_port 8812 * A unique port identifier for the final destination of the packet. 8813 * Access: RW 8814 */ 8815MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8816 8817/* reg_mpat_e 8818 * Enable. Indicating the Port Analyzer is enabled. 8819 * Access: RW 8820 */ 8821MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8822 8823/* reg_mpat_qos 8824 * Quality Of Service Mode. 8825 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8826 * PCP, DEI, DSCP or VL) are configured. 8827 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8828 * same as in the original packet that has triggered the mirroring. For 8829 * SPAN also the pcp,dei are maintained. 8830 * Access: RW 8831 */ 8832MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8833 8834/* reg_mpat_be 8835 * Best effort mode. Indicates mirroring traffic should not cause packet 8836 * drop or back pressure, but will discard the mirrored packets. Mirrored 8837 * packets will be forwarded on a best effort manner. 8838 * 0: Do not discard mirrored packets 8839 * 1: Discard mirrored packets if causing congestion 8840 * Access: RW 8841 */ 8842MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8843 8844enum mlxsw_reg_mpat_span_type { 8845 /* Local SPAN Ethernet. 8846 * The original packet is not encapsulated. 8847 */ 8848 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8849 8850 /* Remote SPAN Ethernet VLAN. 8851 * The packet is forwarded to the monitoring port on the monitoring 8852 * VLAN. 8853 */ 8854 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8855 8856 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8857 * The packet is encapsulated with GRE header. 8858 */ 8859 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8860}; 8861 8862/* reg_mpat_span_type 8863 * SPAN type. 8864 * Access: RW 8865 */ 8866MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8867 8868/* reg_mpat_pide 8869 * Policer enable. 8870 * Access: RW 8871 */ 8872MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 8873 8874/* reg_mpat_pid 8875 * Policer ID. 8876 * Access: RW 8877 */ 8878MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 8879 8880/* Remote SPAN - Ethernet VLAN 8881 * - - - - - - - - - - - - - - 8882 */ 8883 8884/* reg_mpat_eth_rspan_vid 8885 * Encapsulation header VLAN ID. 8886 * Access: RW 8887 */ 8888MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8889 8890/* Encapsulated Remote SPAN - Ethernet L2 8891 * - - - - - - - - - - - - - - - - - - - 8892 */ 8893 8894enum mlxsw_reg_mpat_eth_rspan_version { 8895 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8896}; 8897 8898/* reg_mpat_eth_rspan_version 8899 * RSPAN mirror header version. 8900 * Access: RW 8901 */ 8902MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8903 8904/* reg_mpat_eth_rspan_mac 8905 * Destination MAC address. 8906 * Access: RW 8907 */ 8908MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8909 8910/* reg_mpat_eth_rspan_tp 8911 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8912 * Access: RW 8913 */ 8914MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8915 8916/* Encapsulated Remote SPAN - Ethernet L3 8917 * - - - - - - - - - - - - - - - - - - - 8918 */ 8919 8920enum mlxsw_reg_mpat_eth_rspan_protocol { 8921 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8922 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8923}; 8924 8925/* reg_mpat_eth_rspan_protocol 8926 * SPAN encapsulation protocol. 8927 * Access: RW 8928 */ 8929MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8930 8931/* reg_mpat_eth_rspan_ttl 8932 * Encapsulation header Time-to-Live/HopLimit. 8933 * Access: RW 8934 */ 8935MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8936 8937/* reg_mpat_eth_rspan_smac 8938 * Source MAC address 8939 * Access: RW 8940 */ 8941MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8942 8943/* reg_mpat_eth_rspan_dip* 8944 * Destination IP address. The IP version is configured by protocol. 8945 * Access: RW 8946 */ 8947MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8948MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8949 8950/* reg_mpat_eth_rspan_sip* 8951 * Source IP address. The IP version is configured by protocol. 8952 * Access: RW 8953 */ 8954MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8955MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8956 8957static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8958 u16 system_port, bool e, 8959 enum mlxsw_reg_mpat_span_type span_type) 8960{ 8961 MLXSW_REG_ZERO(mpat, payload); 8962 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8963 mlxsw_reg_mpat_system_port_set(payload, system_port); 8964 mlxsw_reg_mpat_e_set(payload, e); 8965 mlxsw_reg_mpat_qos_set(payload, 1); 8966 mlxsw_reg_mpat_be_set(payload, 1); 8967 mlxsw_reg_mpat_span_type_set(payload, span_type); 8968} 8969 8970static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8971{ 8972 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8973} 8974 8975static inline void 8976mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8977 enum mlxsw_reg_mpat_eth_rspan_version version, 8978 const char *mac, 8979 bool tp) 8980{ 8981 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8982 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8983 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8984} 8985 8986static inline void 8987mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8988 const char *smac, 8989 u32 sip, u32 dip) 8990{ 8991 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8992 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8993 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8994 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8995 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8996 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8997} 8998 8999static inline void 9000mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9001 const char *smac, 9002 struct in6_addr sip, struct in6_addr dip) 9003{ 9004 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9005 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9006 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9007 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9008 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9009 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9010} 9011 9012/* MPAR - Monitoring Port Analyzer Register 9013 * ---------------------------------------- 9014 * MPAR register is used to query and configure the port analyzer port mirroring 9015 * properties. 9016 */ 9017#define MLXSW_REG_MPAR_ID 0x901B 9018#define MLXSW_REG_MPAR_LEN 0x0C 9019 9020MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9021 9022/* reg_mpar_local_port 9023 * The local port to mirror the packets from. 9024 * Access: Index 9025 */ 9026MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 9027 9028enum mlxsw_reg_mpar_i_e { 9029 MLXSW_REG_MPAR_TYPE_EGRESS, 9030 MLXSW_REG_MPAR_TYPE_INGRESS, 9031}; 9032 9033/* reg_mpar_i_e 9034 * Ingress/Egress 9035 * Access: Index 9036 */ 9037MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9038 9039/* reg_mpar_enable 9040 * Enable mirroring 9041 * By default, port mirroring is disabled for all ports. 9042 * Access: RW 9043 */ 9044MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9045 9046/* reg_mpar_pa_id 9047 * Port Analyzer ID. 9048 * Access: RW 9049 */ 9050MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9051 9052static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 9053 enum mlxsw_reg_mpar_i_e i_e, 9054 bool enable, u8 pa_id) 9055{ 9056 MLXSW_REG_ZERO(mpar, payload); 9057 mlxsw_reg_mpar_local_port_set(payload, local_port); 9058 mlxsw_reg_mpar_enable_set(payload, enable); 9059 mlxsw_reg_mpar_i_e_set(payload, i_e); 9060 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9061} 9062 9063/* MGIR - Management General Information Register 9064 * ---------------------------------------------- 9065 * MGIR register allows software to query the hardware and firmware general 9066 * information. 9067 */ 9068#define MLXSW_REG_MGIR_ID 0x9020 9069#define MLXSW_REG_MGIR_LEN 0x9C 9070 9071MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9072 9073/* reg_mgir_hw_info_device_hw_revision 9074 * Access: RO 9075 */ 9076MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 9077 9078#define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 9079 9080/* reg_mgir_fw_info_psid 9081 * PSID (ASCII string). 9082 * Access: RO 9083 */ 9084MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 9085 9086/* reg_mgir_fw_info_extended_major 9087 * Access: RO 9088 */ 9089MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 9090 9091/* reg_mgir_fw_info_extended_minor 9092 * Access: RO 9093 */ 9094MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 9095 9096/* reg_mgir_fw_info_extended_sub_minor 9097 * Access: RO 9098 */ 9099MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 9100 9101static inline void mlxsw_reg_mgir_pack(char *payload) 9102{ 9103 MLXSW_REG_ZERO(mgir, payload); 9104} 9105 9106static inline void 9107mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 9108 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 9109{ 9110 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 9111 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 9112 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 9113 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 9114 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 9115} 9116 9117/* MRSR - Management Reset and Shutdown Register 9118 * --------------------------------------------- 9119 * MRSR register is used to reset or shutdown the switch or 9120 * the entire system (when applicable). 9121 */ 9122#define MLXSW_REG_MRSR_ID 0x9023 9123#define MLXSW_REG_MRSR_LEN 0x08 9124 9125MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 9126 9127/* reg_mrsr_command 9128 * Reset/shutdown command 9129 * 0 - do nothing 9130 * 1 - software reset 9131 * Access: WO 9132 */ 9133MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 9134 9135static inline void mlxsw_reg_mrsr_pack(char *payload) 9136{ 9137 MLXSW_REG_ZERO(mrsr, payload); 9138 mlxsw_reg_mrsr_command_set(payload, 1); 9139} 9140 9141/* MLCR - Management LED Control Register 9142 * -------------------------------------- 9143 * Controls the system LEDs. 9144 */ 9145#define MLXSW_REG_MLCR_ID 0x902B 9146#define MLXSW_REG_MLCR_LEN 0x0C 9147 9148MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 9149 9150/* reg_mlcr_local_port 9151 * Local port number. 9152 * Access: RW 9153 */ 9154MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 9155 9156#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 9157 9158/* reg_mlcr_beacon_duration 9159 * Duration of the beacon to be active, in seconds. 9160 * 0x0 - Will turn off the beacon. 9161 * 0xFFFF - Will turn on the beacon until explicitly turned off. 9162 * Access: RW 9163 */ 9164MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 9165 9166/* reg_mlcr_beacon_remain 9167 * Remaining duration of the beacon, in seconds. 9168 * 0xFFFF indicates an infinite amount of time. 9169 * Access: RO 9170 */ 9171MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 9172 9173static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 9174 bool active) 9175{ 9176 MLXSW_REG_ZERO(mlcr, payload); 9177 mlxsw_reg_mlcr_local_port_set(payload, local_port); 9178 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 9179 MLXSW_REG_MLCR_DURATION_MAX : 0); 9180} 9181 9182/* MTPPS - Management Pulse Per Second Register 9183 * -------------------------------------------- 9184 * This register provides the device PPS capabilities, configure the PPS in and 9185 * out modules and holds the PPS in time stamp. 9186 */ 9187#define MLXSW_REG_MTPPS_ID 0x9053 9188#define MLXSW_REG_MTPPS_LEN 0x3C 9189 9190MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 9191 9192/* reg_mtpps_enable 9193 * Enables the PPS functionality the specific pin. 9194 * A boolean variable. 9195 * Access: RW 9196 */ 9197MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 9198 9199enum mlxsw_reg_mtpps_pin_mode { 9200 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 9201}; 9202 9203/* reg_mtpps_pin_mode 9204 * Pin mode to be used. The mode must comply with the supported modes of the 9205 * requested pin. 9206 * Access: RW 9207 */ 9208MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 9209 9210#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 9211 9212/* reg_mtpps_pin 9213 * Pin to be configured or queried out of the supported pins. 9214 * Access: Index 9215 */ 9216MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 9217 9218/* reg_mtpps_time_stamp 9219 * When pin_mode = pps_in, the latched device time when it was triggered from 9220 * the external GPIO pin. 9221 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9222 * time to generate next output signal. 9223 * Time is in units of device clock. 9224 * Access: RW 9225 */ 9226MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9227 9228static inline void 9229mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9230{ 9231 MLXSW_REG_ZERO(mtpps, payload); 9232 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9233 mlxsw_reg_mtpps_pin_mode_set(payload, 9234 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9235 mlxsw_reg_mtpps_enable_set(payload, true); 9236 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9237} 9238 9239/* MTUTC - Management UTC Register 9240 * ------------------------------- 9241 * Configures the HW UTC counter. 9242 */ 9243#define MLXSW_REG_MTUTC_ID 0x9055 9244#define MLXSW_REG_MTUTC_LEN 0x1C 9245 9246MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9247 9248enum mlxsw_reg_mtutc_operation { 9249 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9250 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9251}; 9252 9253/* reg_mtutc_operation 9254 * Operation. 9255 * Access: OP 9256 */ 9257MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9258 9259/* reg_mtutc_freq_adjustment 9260 * Frequency adjustment: Every PPS the HW frequency will be 9261 * adjusted by this value. Units of HW clock, where HW counts 9262 * 10^9 HW clocks for 1 HW second. 9263 * Access: RW 9264 */ 9265MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9266 9267/* reg_mtutc_utc_sec 9268 * UTC seconds. 9269 * Access: WO 9270 */ 9271MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9272 9273static inline void 9274mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9275 u32 freq_adj, u32 utc_sec) 9276{ 9277 MLXSW_REG_ZERO(mtutc, payload); 9278 mlxsw_reg_mtutc_operation_set(payload, oper); 9279 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9280 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9281} 9282 9283/* MCQI - Management Component Query Information 9284 * --------------------------------------------- 9285 * This register allows querying information about firmware components. 9286 */ 9287#define MLXSW_REG_MCQI_ID 0x9061 9288#define MLXSW_REG_MCQI_BASE_LEN 0x18 9289#define MLXSW_REG_MCQI_CAP_LEN 0x14 9290#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9291 9292MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9293 9294/* reg_mcqi_component_index 9295 * Index of the accessed component. 9296 * Access: Index 9297 */ 9298MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9299 9300enum mlxfw_reg_mcqi_info_type { 9301 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9302}; 9303 9304/* reg_mcqi_info_type 9305 * Component properties set. 9306 * Access: RW 9307 */ 9308MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9309 9310/* reg_mcqi_offset 9311 * The requested/returned data offset from the section start, given in bytes. 9312 * Must be DWORD aligned. 9313 * Access: RW 9314 */ 9315MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9316 9317/* reg_mcqi_data_size 9318 * The requested/returned data size, given in bytes. If data_size is not DWORD 9319 * aligned, the last bytes are zero padded. 9320 * Access: RW 9321 */ 9322MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9323 9324/* reg_mcqi_cap_max_component_size 9325 * Maximum size for this component, given in bytes. 9326 * Access: RO 9327 */ 9328MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9329 9330/* reg_mcqi_cap_log_mcda_word_size 9331 * Log 2 of the access word size in bytes. Read and write access must be aligned 9332 * to the word size. Write access must be done for an integer number of words. 9333 * Access: RO 9334 */ 9335MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9336 9337/* reg_mcqi_cap_mcda_max_write_size 9338 * Maximal write size for MCDA register 9339 * Access: RO 9340 */ 9341MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9342 9343static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9344{ 9345 MLXSW_REG_ZERO(mcqi, payload); 9346 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9347 mlxsw_reg_mcqi_info_type_set(payload, 9348 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9349 mlxsw_reg_mcqi_offset_set(payload, 0); 9350 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9351} 9352 9353static inline void mlxsw_reg_mcqi_unpack(char *payload, 9354 u32 *p_cap_max_component_size, 9355 u8 *p_cap_log_mcda_word_size, 9356 u16 *p_cap_mcda_max_write_size) 9357{ 9358 *p_cap_max_component_size = 9359 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9360 *p_cap_log_mcda_word_size = 9361 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9362 *p_cap_mcda_max_write_size = 9363 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9364} 9365 9366/* MCC - Management Component Control 9367 * ---------------------------------- 9368 * Controls the firmware component and updates the FSM. 9369 */ 9370#define MLXSW_REG_MCC_ID 0x9062 9371#define MLXSW_REG_MCC_LEN 0x1C 9372 9373MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9374 9375enum mlxsw_reg_mcc_instruction { 9376 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9377 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9378 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9379 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9380 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9381 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9382}; 9383 9384/* reg_mcc_instruction 9385 * Command to be executed by the FSM. 9386 * Applicable for write operation only. 9387 * Access: RW 9388 */ 9389MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9390 9391/* reg_mcc_component_index 9392 * Index of the accessed component. Applicable only for commands that 9393 * refer to components. Otherwise, this field is reserved. 9394 * Access: Index 9395 */ 9396MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9397 9398/* reg_mcc_update_handle 9399 * Token representing the current flow executed by the FSM. 9400 * Access: WO 9401 */ 9402MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9403 9404/* reg_mcc_error_code 9405 * Indicates the successful completion of the instruction, or the reason it 9406 * failed 9407 * Access: RO 9408 */ 9409MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9410 9411/* reg_mcc_control_state 9412 * Current FSM state 9413 * Access: RO 9414 */ 9415MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9416 9417/* reg_mcc_component_size 9418 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9419 * the size may shorten the update time. Value 0x0 means that size is 9420 * unspecified. 9421 * Access: WO 9422 */ 9423MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9424 9425static inline void mlxsw_reg_mcc_pack(char *payload, 9426 enum mlxsw_reg_mcc_instruction instr, 9427 u16 component_index, u32 update_handle, 9428 u32 component_size) 9429{ 9430 MLXSW_REG_ZERO(mcc, payload); 9431 mlxsw_reg_mcc_instruction_set(payload, instr); 9432 mlxsw_reg_mcc_component_index_set(payload, component_index); 9433 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9434 mlxsw_reg_mcc_component_size_set(payload, component_size); 9435} 9436 9437static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9438 u8 *p_error_code, u8 *p_control_state) 9439{ 9440 if (p_update_handle) 9441 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9442 if (p_error_code) 9443 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9444 if (p_control_state) 9445 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9446} 9447 9448/* MCDA - Management Component Data Access 9449 * --------------------------------------- 9450 * This register allows reading and writing a firmware component. 9451 */ 9452#define MLXSW_REG_MCDA_ID 0x9063 9453#define MLXSW_REG_MCDA_BASE_LEN 0x10 9454#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9455#define MLXSW_REG_MCDA_LEN \ 9456 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9457 9458MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9459 9460/* reg_mcda_update_handle 9461 * Token representing the current flow executed by the FSM. 9462 * Access: RW 9463 */ 9464MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9465 9466/* reg_mcda_offset 9467 * Offset of accessed address relative to component start. Accesses must be in 9468 * accordance to log_mcda_word_size in MCQI reg. 9469 * Access: RW 9470 */ 9471MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9472 9473/* reg_mcda_size 9474 * Size of the data accessed, given in bytes. 9475 * Access: RW 9476 */ 9477MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9478 9479/* reg_mcda_data 9480 * Data block accessed. 9481 * Access: RW 9482 */ 9483MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9484 9485static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9486 u32 offset, u16 size, u8 *data) 9487{ 9488 int i; 9489 9490 MLXSW_REG_ZERO(mcda, payload); 9491 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9492 mlxsw_reg_mcda_offset_set(payload, offset); 9493 mlxsw_reg_mcda_size_set(payload, size); 9494 9495 for (i = 0; i < size / 4; i++) 9496 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9497} 9498 9499/* MPSC - Monitoring Packet Sampling Configuration Register 9500 * -------------------------------------------------------- 9501 * MPSC Register is used to configure the Packet Sampling mechanism. 9502 */ 9503#define MLXSW_REG_MPSC_ID 0x9080 9504#define MLXSW_REG_MPSC_LEN 0x1C 9505 9506MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9507 9508/* reg_mpsc_local_port 9509 * Local port number 9510 * Not supported for CPU port 9511 * Access: Index 9512 */ 9513MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9514 9515/* reg_mpsc_e 9516 * Enable sampling on port local_port 9517 * Access: RW 9518 */ 9519MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9520 9521#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9522 9523/* reg_mpsc_rate 9524 * Sampling rate = 1 out of rate packets (with randomization around 9525 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9526 * Access: RW 9527 */ 9528MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9529 9530static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9531 u32 rate) 9532{ 9533 MLXSW_REG_ZERO(mpsc, payload); 9534 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9535 mlxsw_reg_mpsc_e_set(payload, e); 9536 mlxsw_reg_mpsc_rate_set(payload, rate); 9537} 9538 9539/* MGPC - Monitoring General Purpose Counter Set Register 9540 * The MGPC register retrieves and sets the General Purpose Counter Set. 9541 */ 9542#define MLXSW_REG_MGPC_ID 0x9081 9543#define MLXSW_REG_MGPC_LEN 0x18 9544 9545MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9546 9547/* reg_mgpc_counter_set_type 9548 * Counter set type. 9549 * Access: OP 9550 */ 9551MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9552 9553/* reg_mgpc_counter_index 9554 * Counter index. 9555 * Access: Index 9556 */ 9557MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9558 9559enum mlxsw_reg_mgpc_opcode { 9560 /* Nop */ 9561 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9562 /* Clear counters */ 9563 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9564}; 9565 9566/* reg_mgpc_opcode 9567 * Opcode. 9568 * Access: OP 9569 */ 9570MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9571 9572/* reg_mgpc_byte_counter 9573 * Byte counter value. 9574 * Access: RW 9575 */ 9576MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9577 9578/* reg_mgpc_packet_counter 9579 * Packet counter value. 9580 * Access: RW 9581 */ 9582MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9583 9584static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9585 enum mlxsw_reg_mgpc_opcode opcode, 9586 enum mlxsw_reg_flow_counter_set_type set_type) 9587{ 9588 MLXSW_REG_ZERO(mgpc, payload); 9589 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9590 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9591 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9592} 9593 9594/* MPRS - Monitoring Parsing State Register 9595 * ---------------------------------------- 9596 * The MPRS register is used for setting up the parsing for hash, 9597 * policy-engine and routing. 9598 */ 9599#define MLXSW_REG_MPRS_ID 0x9083 9600#define MLXSW_REG_MPRS_LEN 0x14 9601 9602MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9603 9604/* reg_mprs_parsing_depth 9605 * Minimum parsing depth. 9606 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9607 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9608 * Access: RW 9609 */ 9610MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9611 9612/* reg_mprs_parsing_en 9613 * Parsing enable. 9614 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9615 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9616 * Access: RW 9617 */ 9618MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9619 9620/* reg_mprs_vxlan_udp_dport 9621 * VxLAN UDP destination port. 9622 * Used for identifying VxLAN packets and for dport field in 9623 * encapsulation. Default is 4789. 9624 * Access: RW 9625 */ 9626MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9627 9628static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9629 u16 vxlan_udp_dport) 9630{ 9631 MLXSW_REG_ZERO(mprs, payload); 9632 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9633 mlxsw_reg_mprs_parsing_en_set(payload, true); 9634 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9635} 9636 9637/* MOGCR - Monitoring Global Configuration Register 9638 * ------------------------------------------------ 9639 */ 9640#define MLXSW_REG_MOGCR_ID 0x9086 9641#define MLXSW_REG_MOGCR_LEN 0x20 9642 9643MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9644 9645/* reg_mogcr_ptp_iftc 9646 * PTP Ingress FIFO Trap Clear 9647 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9648 * to this value. Default 0. 9649 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9650 * Access: RW 9651 */ 9652MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9653 9654/* reg_mogcr_ptp_eftc 9655 * PTP Egress FIFO Trap Clear 9656 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9657 * to this value. Default 0. 9658 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9659 * Access: RW 9660 */ 9661MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9662 9663/* reg_mogcr_mirroring_pid_base 9664 * Base policer id for mirroring policers. 9665 * Must have an even value (e.g. 1000, not 1001). 9666 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 9667 * Access: RW 9668 */ 9669MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 9670 9671/* MPAGR - Monitoring Port Analyzer Global Register 9672 * ------------------------------------------------ 9673 * This register is used for global port analyzer configurations. 9674 * Note: This register is not supported by current FW versions for Spectrum-1. 9675 */ 9676#define MLXSW_REG_MPAGR_ID 0x9089 9677#define MLXSW_REG_MPAGR_LEN 0x0C 9678 9679MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 9680 9681enum mlxsw_reg_mpagr_trigger { 9682 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 9683 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 9684 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 9685 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 9686 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 9687 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 9688 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 9689 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 9690}; 9691 9692/* reg_mpagr_trigger 9693 * Mirror trigger. 9694 * Access: Index 9695 */ 9696MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 9697 9698/* reg_mpagr_pa_id 9699 * Port analyzer ID. 9700 * Access: RW 9701 */ 9702MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 9703 9704/* reg_mpagr_probability_rate 9705 * Sampling rate. 9706 * Valid values are: 1 to 3.5*10^9 9707 * Value of 1 means "sample all". Default is 1. 9708 * Access: RW 9709 */ 9710MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 9711 9712static inline void mlxsw_reg_mpagr_pack(char *payload, 9713 enum mlxsw_reg_mpagr_trigger trigger, 9714 u8 pa_id, u32 probability_rate) 9715{ 9716 MLXSW_REG_ZERO(mpagr, payload); 9717 mlxsw_reg_mpagr_trigger_set(payload, trigger); 9718 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 9719 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 9720} 9721 9722/* MOMTE - Monitoring Mirror Trigger Enable Register 9723 * ------------------------------------------------- 9724 * This register is used to configure the mirror enable for different mirror 9725 * reasons. 9726 */ 9727#define MLXSW_REG_MOMTE_ID 0x908D 9728#define MLXSW_REG_MOMTE_LEN 0x10 9729 9730MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 9731 9732/* reg_momte_local_port 9733 * Local port number. 9734 * Access: Index 9735 */ 9736MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8); 9737 9738enum mlxsw_reg_momte_type { 9739 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 9740 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 9741 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 9742 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 9743 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 9744 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 9745 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 9746 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 9747}; 9748 9749/* reg_momte_type 9750 * Type of mirroring. 9751 * Access: Index 9752 */ 9753MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 9754 9755/* reg_momte_tclass_en 9756 * TClass/PG mirror enable. Each bit represents corresponding tclass. 9757 * 0: disable (default) 9758 * 1: enable 9759 * Access: RW 9760 */ 9761MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 9762 9763static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port, 9764 enum mlxsw_reg_momte_type type) 9765{ 9766 MLXSW_REG_ZERO(momte, payload); 9767 mlxsw_reg_momte_local_port_set(payload, local_port); 9768 mlxsw_reg_momte_type_set(payload, type); 9769} 9770 9771/* MTPPPC - Time Precision Packet Port Configuration 9772 * ------------------------------------------------- 9773 * This register serves for configuration of which PTP messages should be 9774 * timestamped. This is a global configuration, despite the register name. 9775 * 9776 * Reserved when Spectrum-2. 9777 */ 9778#define MLXSW_REG_MTPPPC_ID 0x9090 9779#define MLXSW_REG_MTPPPC_LEN 0x28 9780 9781MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9782 9783/* reg_mtpppc_ing_timestamp_message_type 9784 * Bitwise vector of PTP message types to timestamp at ingress. 9785 * MessageType field as defined by IEEE 1588 9786 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9787 * Default all 0 9788 * Access: RW 9789 */ 9790MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9791 9792/* reg_mtpppc_egr_timestamp_message_type 9793 * Bitwise vector of PTP message types to timestamp at egress. 9794 * MessageType field as defined by IEEE 1588 9795 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9796 * Default all 0 9797 * Access: RW 9798 */ 9799MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9800 9801static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9802{ 9803 MLXSW_REG_ZERO(mtpppc, payload); 9804 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9805 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9806} 9807 9808/* MTPPTR - Time Precision Packet Timestamping Reading 9809 * --------------------------------------------------- 9810 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 9811 * There is a trap for packets which are latched to the timestamp FIFO, thus the 9812 * SW knows which FIFO to read. Note that packets enter the FIFO before been 9813 * trapped. The sequence number is used to synchronize the timestamp FIFO 9814 * entries and the trapped packets. 9815 * Reserved when Spectrum-2. 9816 */ 9817 9818#define MLXSW_REG_MTPPTR_ID 0x9091 9819#define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 9820#define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 9821#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 9822#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 9823 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 9824 9825MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 9826 9827/* reg_mtpptr_local_port 9828 * Not supported for CPU port. 9829 * Access: Index 9830 */ 9831MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 9832 9833enum mlxsw_reg_mtpptr_dir { 9834 MLXSW_REG_MTPPTR_DIR_INGRESS, 9835 MLXSW_REG_MTPPTR_DIR_EGRESS, 9836}; 9837 9838/* reg_mtpptr_dir 9839 * Direction. 9840 * Access: Index 9841 */ 9842MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 9843 9844/* reg_mtpptr_clr 9845 * Clear the records. 9846 * Access: OP 9847 */ 9848MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 9849 9850/* reg_mtpptr_num_rec 9851 * Number of valid records in the response 9852 * Range 0.. cap_ptp_timestamp_fifo 9853 * Access: RO 9854 */ 9855MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 9856 9857/* reg_mtpptr_rec_message_type 9858 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 9859 * (e.g. Bit0: Sync, Bit1: Delay_Req) 9860 * Access: RO 9861 */ 9862MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 9863 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 9864 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9865 9866/* reg_mtpptr_rec_domain_number 9867 * DomainNumber field as defined by IEEE 1588 9868 * Access: RO 9869 */ 9870MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 9871 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 9872 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9873 9874/* reg_mtpptr_rec_sequence_id 9875 * SequenceId field as defined by IEEE 1588 9876 * Access: RO 9877 */ 9878MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 9879 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 9880 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 9881 9882/* reg_mtpptr_rec_timestamp_high 9883 * Timestamp of when the PTP packet has passed through the port Units of PLL 9884 * clock time. 9885 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 9886 * Access: RO 9887 */ 9888MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 9889 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9890 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 9891 9892/* reg_mtpptr_rec_timestamp_low 9893 * See rec_timestamp_high. 9894 * Access: RO 9895 */ 9896MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 9897 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9898 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 9899 9900static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 9901 unsigned int rec, 9902 u8 *p_message_type, 9903 u8 *p_domain_number, 9904 u16 *p_sequence_id, 9905 u64 *p_timestamp) 9906{ 9907 u32 timestamp_high, timestamp_low; 9908 9909 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 9910 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 9911 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 9912 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 9913 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 9914 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 9915} 9916 9917/* MTPTPT - Monitoring Precision Time Protocol Trap Register 9918 * --------------------------------------------------------- 9919 * This register is used for configuring under which trap to deliver PTP 9920 * packets depending on type of the packet. 9921 */ 9922#define MLXSW_REG_MTPTPT_ID 0x9092 9923#define MLXSW_REG_MTPTPT_LEN 0x08 9924 9925MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 9926 9927enum mlxsw_reg_mtptpt_trap_id { 9928 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 9929 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 9930}; 9931 9932/* reg_mtptpt_trap_id 9933 * Trap id. 9934 * Access: Index 9935 */ 9936MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 9937 9938/* reg_mtptpt_message_type 9939 * Bitwise vector of PTP message types to trap. This is a necessary but 9940 * non-sufficient condition since need to enable also per port. See MTPPPC. 9941 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 9942 * Bit0: Sync, Bit1: Delay_Req) 9943 */ 9944MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 9945 9946static inline void mlxsw_reg_mtptptp_pack(char *payload, 9947 enum mlxsw_reg_mtptpt_trap_id trap_id, 9948 u16 message_type) 9949{ 9950 MLXSW_REG_ZERO(mtptpt, payload); 9951 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 9952 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 9953} 9954 9955/* MFGD - Monitoring FW General Debug Register 9956 * ------------------------------------------- 9957 */ 9958#define MLXSW_REG_MFGD_ID 0x90F0 9959#define MLXSW_REG_MFGD_LEN 0x0C 9960 9961MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 9962 9963/* reg_mfgd_fw_fatal_event_mode 9964 * 0 - don't check FW fatal (default) 9965 * 1 - check FW fatal - enable MFDE trap 9966 * Access: RW 9967 */ 9968MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 9969 9970/* reg_mfgd_trigger_test 9971 * Access: WO 9972 */ 9973MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 9974 9975/* MGPIR - Management General Peripheral Information Register 9976 * ---------------------------------------------------------- 9977 * MGPIR register allows software to query the hardware and 9978 * firmware general information of peripheral entities. 9979 */ 9980#define MLXSW_REG_MGPIR_ID 0x9100 9981#define MLXSW_REG_MGPIR_LEN 0xA0 9982 9983MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 9984 9985enum mlxsw_reg_mgpir_device_type { 9986 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 9987 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 9988}; 9989 9990/* device_type 9991 * Access: RO 9992 */ 9993MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 9994 9995/* devices_per_flash 9996 * Number of devices of device_type per flash (can be shared by few devices). 9997 * Access: RO 9998 */ 9999MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 10000 10001/* num_of_devices 10002 * Number of devices of device_type. 10003 * Access: RO 10004 */ 10005MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 10006 10007/* num_of_modules 10008 * Number of modules. 10009 * Access: RO 10010 */ 10011MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 10012 10013static inline void mlxsw_reg_mgpir_pack(char *payload) 10014{ 10015 MLXSW_REG_ZERO(mgpir, payload); 10016} 10017 10018static inline void 10019mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 10020 enum mlxsw_reg_mgpir_device_type *device_type, 10021 u8 *devices_per_flash, u8 *num_of_modules) 10022{ 10023 if (num_of_devices) 10024 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 10025 if (device_type) 10026 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 10027 if (devices_per_flash) 10028 *devices_per_flash = 10029 mlxsw_reg_mgpir_devices_per_flash_get(payload); 10030 if (num_of_modules) 10031 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 10032} 10033 10034/* MFDE - Monitoring FW Debug Register 10035 * ----------------------------------- 10036 */ 10037#define MLXSW_REG_MFDE_ID 0x9200 10038#define MLXSW_REG_MFDE_LEN 0x18 10039 10040MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 10041 10042/* reg_mfde_irisc_id 10043 * Which irisc triggered the event 10044 * Access: RO 10045 */ 10046MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 8, 4); 10047 10048enum mlxsw_reg_mfde_event_id { 10049 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 10050 /* KVD insertion machine stopped */ 10051 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 10052}; 10053 10054/* reg_mfde_event_id 10055 * Access: RO 10056 */ 10057MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 8); 10058 10059enum mlxsw_reg_mfde_method { 10060 MLXSW_REG_MFDE_METHOD_QUERY, 10061 MLXSW_REG_MFDE_METHOD_WRITE, 10062}; 10063 10064/* reg_mfde_method 10065 * Access: RO 10066 */ 10067MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 10068 10069/* reg_mfde_long_process 10070 * Indicates if the command is in long_process mode. 10071 * Access: RO 10072 */ 10073MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 10074 10075enum mlxsw_reg_mfde_command_type { 10076 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 10077 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 10078 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 10079}; 10080 10081/* reg_mfde_command_type 10082 * Access: RO 10083 */ 10084MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 10085 10086/* reg_mfde_reg_attr_id 10087 * EMAD - register id, MAD - attibute id 10088 * Access: RO 10089 */ 10090MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 10091 10092/* reg_mfde_log_address 10093 * crspace address accessed, which resulted in timeout. 10094 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10095 * Access: RO 10096 */ 10097MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32); 10098 10099/* reg_mfde_log_id 10100 * Which irisc triggered the timeout. 10101 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10102 * Access: RO 10103 */ 10104MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4); 10105 10106/* reg_mfde_pipes_mask 10107 * Bit per kvh pipe. 10108 * Access: RO 10109 */ 10110MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16); 10111 10112/* TNGCR - Tunneling NVE General Configuration Register 10113 * ---------------------------------------------------- 10114 * The TNGCR register is used for setting up the NVE Tunneling configuration. 10115 */ 10116#define MLXSW_REG_TNGCR_ID 0xA001 10117#define MLXSW_REG_TNGCR_LEN 0x44 10118 10119MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 10120 10121enum mlxsw_reg_tngcr_type { 10122 MLXSW_REG_TNGCR_TYPE_VXLAN, 10123 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 10124 MLXSW_REG_TNGCR_TYPE_GENEVE, 10125 MLXSW_REG_TNGCR_TYPE_NVGRE, 10126}; 10127 10128/* reg_tngcr_type 10129 * Tunnel type for encapsulation and decapsulation. The types are mutually 10130 * exclusive. 10131 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 10132 * Access: RW 10133 */ 10134MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 10135 10136/* reg_tngcr_nve_valid 10137 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 10138 * Access: RW 10139 */ 10140MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 10141 10142/* reg_tngcr_nve_ttl_uc 10143 * The TTL for NVE tunnel encapsulation underlay unicast packets. 10144 * Access: RW 10145 */ 10146MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 10147 10148/* reg_tngcr_nve_ttl_mc 10149 * The TTL for NVE tunnel encapsulation underlay multicast packets. 10150 * Access: RW 10151 */ 10152MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 10153 10154enum { 10155 /* Do not copy flow label. Calculate flow label using nve_flh. */ 10156 MLXSW_REG_TNGCR_FL_NO_COPY, 10157 /* Copy flow label from inner packet if packet is IPv6 and 10158 * encapsulation is by IPv6. Otherwise, calculate flow label using 10159 * nve_flh. 10160 */ 10161 MLXSW_REG_TNGCR_FL_COPY, 10162}; 10163 10164/* reg_tngcr_nve_flc 10165 * For NVE tunnel encapsulation: Flow label copy from inner packet. 10166 * Access: RW 10167 */ 10168MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 10169 10170enum { 10171 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 10172 * uses {nve_fl_prefix, nve_fl_suffix}. 10173 */ 10174 MLXSW_REG_TNGCR_FL_NO_HASH, 10175 /* 8 LSBs of the flow label are calculated from ECMP hash of the 10176 * inner packet. 12 MSBs are configured by nve_fl_prefix. 10177 */ 10178 MLXSW_REG_TNGCR_FL_HASH, 10179}; 10180 10181/* reg_tngcr_nve_flh 10182 * NVE flow label hash. 10183 * Access: RW 10184 */ 10185MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 10186 10187/* reg_tngcr_nve_fl_prefix 10188 * NVE flow label prefix. Constant 12 MSBs of the flow label. 10189 * Access: RW 10190 */ 10191MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 10192 10193/* reg_tngcr_nve_fl_suffix 10194 * NVE flow label suffix. Constant 8 LSBs of the flow label. 10195 * Reserved when nve_flh=1 and for Spectrum. 10196 * Access: RW 10197 */ 10198MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 10199 10200enum { 10201 /* Source UDP port is fixed (default '0') */ 10202 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 10203 /* Source UDP port is calculated based on hash */ 10204 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 10205}; 10206 10207/* reg_tngcr_nve_udp_sport_type 10208 * NVE UDP source port type. 10209 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 10210 * When the source UDP port is calculated based on hash, then the 8 LSBs 10211 * are calculated from hash the 8 MSBs are configured by 10212 * nve_udp_sport_prefix. 10213 * Access: RW 10214 */ 10215MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 10216 10217/* reg_tngcr_nve_udp_sport_prefix 10218 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 10219 * Reserved when NVE type is NVGRE. 10220 * Access: RW 10221 */ 10222MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 10223 10224/* reg_tngcr_nve_group_size_mc 10225 * The amount of sequential linked lists of MC entries. The first linked 10226 * list is configured by SFD.underlay_mc_ptr. 10227 * Valid values: 1, 2, 4, 8, 16, 32, 64 10228 * The linked list are configured by TNUMT. 10229 * The hash is set by LAG hash. 10230 * Access: RW 10231 */ 10232MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 10233 10234/* reg_tngcr_nve_group_size_flood 10235 * The amount of sequential linked lists of flooding entries. The first 10236 * linked list is configured by SFMR.nve_tunnel_flood_ptr 10237 * Valid values: 1, 2, 4, 8, 16, 32, 64 10238 * The linked list are configured by TNUMT. 10239 * The hash is set by LAG hash. 10240 * Access: RW 10241 */ 10242MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 10243 10244/* reg_tngcr_learn_enable 10245 * During decapsulation, whether to learn from NVE port. 10246 * Reserved when Spectrum-2. See TNPC. 10247 * Access: RW 10248 */ 10249MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 10250 10251/* reg_tngcr_underlay_virtual_router 10252 * Underlay virtual router. 10253 * Reserved when Spectrum-2. 10254 * Access: RW 10255 */ 10256MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 10257 10258/* reg_tngcr_underlay_rif 10259 * Underlay ingress router interface. RIF type should be loopback generic. 10260 * Reserved when Spectrum. 10261 * Access: RW 10262 */ 10263MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 10264 10265/* reg_tngcr_usipv4 10266 * Underlay source IPv4 address of the NVE. 10267 * Access: RW 10268 */ 10269MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 10270 10271/* reg_tngcr_usipv6 10272 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 10273 * modified under traffic of NVE tunneling encapsulation. 10274 * Access: RW 10275 */ 10276MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 10277 10278static inline void mlxsw_reg_tngcr_pack(char *payload, 10279 enum mlxsw_reg_tngcr_type type, 10280 bool valid, u8 ttl) 10281{ 10282 MLXSW_REG_ZERO(tngcr, payload); 10283 mlxsw_reg_tngcr_type_set(payload, type); 10284 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 10285 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 10286 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 10287 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 10288 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 10289 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 10290 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 10291 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 10292 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 10293 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 10294} 10295 10296/* TNUMT - Tunneling NVE Underlay Multicast Table Register 10297 * ------------------------------------------------------- 10298 * The TNUMT register is for building the underlay MC table. It is used 10299 * for MC, flooding and BC traffic into the NVE tunnel. 10300 */ 10301#define MLXSW_REG_TNUMT_ID 0xA003 10302#define MLXSW_REG_TNUMT_LEN 0x20 10303 10304MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 10305 10306enum mlxsw_reg_tnumt_record_type { 10307 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 10308 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 10309 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 10310}; 10311 10312/* reg_tnumt_record_type 10313 * Record type. 10314 * Access: RW 10315 */ 10316MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 10317 10318enum mlxsw_reg_tnumt_tunnel_port { 10319 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 10320 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 10321 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 10322 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 10323}; 10324 10325/* reg_tnumt_tunnel_port 10326 * Tunnel port. 10327 * Access: RW 10328 */ 10329MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 10330 10331/* reg_tnumt_underlay_mc_ptr 10332 * Index to the underlay multicast table. 10333 * For Spectrum the index is to the KVD linear. 10334 * Access: Index 10335 */ 10336MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 10337 10338/* reg_tnumt_vnext 10339 * The next_underlay_mc_ptr is valid. 10340 * Access: RW 10341 */ 10342MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 10343 10344/* reg_tnumt_next_underlay_mc_ptr 10345 * The next index to the underlay multicast table. 10346 * Access: RW 10347 */ 10348MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 10349 10350/* reg_tnumt_record_size 10351 * Number of IP addresses in the record. 10352 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 10353 * Access: RW 10354 */ 10355MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 10356 10357/* reg_tnumt_udip 10358 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 10359 * Access: RW 10360 */ 10361MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 10362 10363/* reg_tnumt_udip_ptr 10364 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 10365 * i >= size. The IPv6 addresses are configured by RIPS. 10366 * Access: RW 10367 */ 10368MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 10369 10370static inline void mlxsw_reg_tnumt_pack(char *payload, 10371 enum mlxsw_reg_tnumt_record_type type, 10372 enum mlxsw_reg_tnumt_tunnel_port tport, 10373 u32 underlay_mc_ptr, bool vnext, 10374 u32 next_underlay_mc_ptr, 10375 u8 record_size) 10376{ 10377 MLXSW_REG_ZERO(tnumt, payload); 10378 mlxsw_reg_tnumt_record_type_set(payload, type); 10379 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 10380 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 10381 mlxsw_reg_tnumt_vnext_set(payload, vnext); 10382 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 10383 mlxsw_reg_tnumt_record_size_set(payload, record_size); 10384} 10385 10386/* TNQCR - Tunneling NVE QoS Configuration Register 10387 * ------------------------------------------------ 10388 * The TNQCR register configures how QoS is set in encapsulation into the 10389 * underlay network. 10390 */ 10391#define MLXSW_REG_TNQCR_ID 0xA010 10392#define MLXSW_REG_TNQCR_LEN 0x0C 10393 10394MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 10395 10396/* reg_tnqcr_enc_set_dscp 10397 * For encapsulation: How to set DSCP field: 10398 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 10399 * (outer) IP header. If there is no IP header, use TNQDR.dscp 10400 * 1 - Set the DSCP field as TNQDR.dscp 10401 * Access: RW 10402 */ 10403MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 10404 10405static inline void mlxsw_reg_tnqcr_pack(char *payload) 10406{ 10407 MLXSW_REG_ZERO(tnqcr, payload); 10408 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 10409} 10410 10411/* TNQDR - Tunneling NVE QoS Default Register 10412 * ------------------------------------------ 10413 * The TNQDR register configures the default QoS settings for NVE 10414 * encapsulation. 10415 */ 10416#define MLXSW_REG_TNQDR_ID 0xA011 10417#define MLXSW_REG_TNQDR_LEN 0x08 10418 10419MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 10420 10421/* reg_tnqdr_local_port 10422 * Local port number (receive port). CPU port is supported. 10423 * Access: Index 10424 */ 10425MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10426 10427/* reg_tnqdr_dscp 10428 * For encapsulation, the default DSCP. 10429 * Access: RW 10430 */ 10431MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10432 10433static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10434{ 10435 MLXSW_REG_ZERO(tnqdr, payload); 10436 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10437 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10438} 10439 10440/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10441 * -------------------------------------------------------- 10442 * The TNEEM register maps ECN of the IP header at the ingress to the 10443 * encapsulation to the ECN of the underlay network. 10444 */ 10445#define MLXSW_REG_TNEEM_ID 0xA012 10446#define MLXSW_REG_TNEEM_LEN 0x0C 10447 10448MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10449 10450/* reg_tneem_overlay_ecn 10451 * ECN of the IP header in the overlay network. 10452 * Access: Index 10453 */ 10454MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10455 10456/* reg_tneem_underlay_ecn 10457 * ECN of the IP header in the underlay network. 10458 * Access: RW 10459 */ 10460MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10461 10462static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10463 u8 underlay_ecn) 10464{ 10465 MLXSW_REG_ZERO(tneem, payload); 10466 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10467 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10468} 10469 10470/* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10471 * -------------------------------------------------------- 10472 * The TNDEM register configures the actions that are done in the 10473 * decapsulation. 10474 */ 10475#define MLXSW_REG_TNDEM_ID 0xA013 10476#define MLXSW_REG_TNDEM_LEN 0x0C 10477 10478MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10479 10480/* reg_tndem_underlay_ecn 10481 * ECN field of the IP header in the underlay network. 10482 * Access: Index 10483 */ 10484MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10485 10486/* reg_tndem_overlay_ecn 10487 * ECN field of the IP header in the overlay network. 10488 * Access: Index 10489 */ 10490MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10491 10492/* reg_tndem_eip_ecn 10493 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10494 * from the decapsulation. 10495 * Access: RW 10496 */ 10497MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10498 10499/* reg_tndem_trap_en 10500 * Trap enable: 10501 * 0 - No trap due to decap ECN 10502 * 1 - Trap enable with trap_id 10503 * Access: RW 10504 */ 10505MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10506 10507/* reg_tndem_trap_id 10508 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10509 * Reserved when trap_en is '0'. 10510 * Access: RW 10511 */ 10512MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10513 10514static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10515 u8 overlay_ecn, u8 ecn, bool trap_en, 10516 u16 trap_id) 10517{ 10518 MLXSW_REG_ZERO(tndem, payload); 10519 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10520 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10521 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10522 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10523 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10524} 10525 10526/* TNPC - Tunnel Port Configuration Register 10527 * ----------------------------------------- 10528 * The TNPC register is used for tunnel port configuration. 10529 * Reserved when Spectrum. 10530 */ 10531#define MLXSW_REG_TNPC_ID 0xA020 10532#define MLXSW_REG_TNPC_LEN 0x18 10533 10534MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10535 10536enum mlxsw_reg_tnpc_tunnel_port { 10537 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10538 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10539 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10540 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10541}; 10542 10543/* reg_tnpc_tunnel_port 10544 * Tunnel port. 10545 * Access: Index 10546 */ 10547MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10548 10549/* reg_tnpc_learn_enable_v6 10550 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10551 * Access: RW 10552 */ 10553MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10554 10555/* reg_tnpc_learn_enable_v4 10556 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10557 * Access: RW 10558 */ 10559MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10560 10561static inline void mlxsw_reg_tnpc_pack(char *payload, 10562 enum mlxsw_reg_tnpc_tunnel_port tport, 10563 bool learn_enable) 10564{ 10565 MLXSW_REG_ZERO(tnpc, payload); 10566 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10567 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10568 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10569} 10570 10571/* TIGCR - Tunneling IPinIP General Configuration Register 10572 * ------------------------------------------------------- 10573 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10574 */ 10575#define MLXSW_REG_TIGCR_ID 0xA801 10576#define MLXSW_REG_TIGCR_LEN 0x10 10577 10578MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10579 10580/* reg_tigcr_ipip_ttlc 10581 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10582 * header. 10583 * Access: RW 10584 */ 10585MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10586 10587/* reg_tigcr_ipip_ttl_uc 10588 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10589 * reg_tigcr_ipip_ttlc is unset. 10590 * Access: RW 10591 */ 10592MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10593 10594static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10595{ 10596 MLXSW_REG_ZERO(tigcr, payload); 10597 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10598 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10599} 10600 10601/* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10602 * ----------------------------------------------------------- 10603 * The TIEEM register maps ECN of the IP header at the ingress to the 10604 * encapsulation to the ECN of the underlay network. 10605 */ 10606#define MLXSW_REG_TIEEM_ID 0xA812 10607#define MLXSW_REG_TIEEM_LEN 0x0C 10608 10609MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10610 10611/* reg_tieem_overlay_ecn 10612 * ECN of the IP header in the overlay network. 10613 * Access: Index 10614 */ 10615MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10616 10617/* reg_tineem_underlay_ecn 10618 * ECN of the IP header in the underlay network. 10619 * Access: RW 10620 */ 10621MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10622 10623static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10624 u8 underlay_ecn) 10625{ 10626 MLXSW_REG_ZERO(tieem, payload); 10627 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10628 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10629} 10630 10631/* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10632 * ----------------------------------------------------------- 10633 * The TIDEM register configures the actions that are done in the 10634 * decapsulation. 10635 */ 10636#define MLXSW_REG_TIDEM_ID 0xA813 10637#define MLXSW_REG_TIDEM_LEN 0x0C 10638 10639MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10640 10641/* reg_tidem_underlay_ecn 10642 * ECN field of the IP header in the underlay network. 10643 * Access: Index 10644 */ 10645MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10646 10647/* reg_tidem_overlay_ecn 10648 * ECN field of the IP header in the overlay network. 10649 * Access: Index 10650 */ 10651MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10652 10653/* reg_tidem_eip_ecn 10654 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10655 * from the decapsulation. 10656 * Access: RW 10657 */ 10658MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10659 10660/* reg_tidem_trap_en 10661 * Trap enable: 10662 * 0 - No trap due to decap ECN 10663 * 1 - Trap enable with trap_id 10664 * Access: RW 10665 */ 10666MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10667 10668/* reg_tidem_trap_id 10669 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10670 * Reserved when trap_en is '0'. 10671 * Access: RW 10672 */ 10673MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10674 10675static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10676 u8 overlay_ecn, u8 eip_ecn, 10677 bool trap_en, u16 trap_id) 10678{ 10679 MLXSW_REG_ZERO(tidem, payload); 10680 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10681 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10682 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10683 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10684 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10685} 10686 10687/* SBPR - Shared Buffer Pools Register 10688 * ----------------------------------- 10689 * The SBPR configures and retrieves the shared buffer pools and configuration. 10690 */ 10691#define MLXSW_REG_SBPR_ID 0xB001 10692#define MLXSW_REG_SBPR_LEN 0x14 10693 10694MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10695 10696/* shared direstion enum for SBPR, SBCM, SBPM */ 10697enum mlxsw_reg_sbxx_dir { 10698 MLXSW_REG_SBXX_DIR_INGRESS, 10699 MLXSW_REG_SBXX_DIR_EGRESS, 10700}; 10701 10702/* reg_sbpr_dir 10703 * Direction. 10704 * Access: Index 10705 */ 10706MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10707 10708/* reg_sbpr_pool 10709 * Pool index. 10710 * Access: Index 10711 */ 10712MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10713 10714/* reg_sbpr_infi_size 10715 * Size is infinite. 10716 * Access: RW 10717 */ 10718MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10719 10720/* reg_sbpr_size 10721 * Pool size in buffer cells. 10722 * Reserved when infi_size = 1. 10723 * Access: RW 10724 */ 10725MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10726 10727enum mlxsw_reg_sbpr_mode { 10728 MLXSW_REG_SBPR_MODE_STATIC, 10729 MLXSW_REG_SBPR_MODE_DYNAMIC, 10730}; 10731 10732/* reg_sbpr_mode 10733 * Pool quota calculation mode. 10734 * Access: RW 10735 */ 10736MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10737 10738static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10739 enum mlxsw_reg_sbxx_dir dir, 10740 enum mlxsw_reg_sbpr_mode mode, u32 size, 10741 bool infi_size) 10742{ 10743 MLXSW_REG_ZERO(sbpr, payload); 10744 mlxsw_reg_sbpr_pool_set(payload, pool); 10745 mlxsw_reg_sbpr_dir_set(payload, dir); 10746 mlxsw_reg_sbpr_mode_set(payload, mode); 10747 mlxsw_reg_sbpr_size_set(payload, size); 10748 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10749} 10750 10751/* SBCM - Shared Buffer Class Management Register 10752 * ---------------------------------------------- 10753 * The SBCM register configures and retrieves the shared buffer allocation 10754 * and configuration according to Port-PG, including the binding to pool 10755 * and definition of the associated quota. 10756 */ 10757#define MLXSW_REG_SBCM_ID 0xB002 10758#define MLXSW_REG_SBCM_LEN 0x28 10759 10760MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10761 10762/* reg_sbcm_local_port 10763 * Local port number. 10764 * For Ingress: excludes CPU port and Router port 10765 * For Egress: excludes IP Router 10766 * Access: Index 10767 */ 10768MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10769 10770/* reg_sbcm_pg_buff 10771 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10772 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10773 * For traffic class: range is 0..cap_max_tclass - 1 10774 * Note that when traffic class is in MC aware mode then the traffic 10775 * classes which are MC aware cannot be configured. 10776 * Access: Index 10777 */ 10778MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10779 10780/* reg_sbcm_dir 10781 * Direction. 10782 * Access: Index 10783 */ 10784MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10785 10786/* reg_sbcm_min_buff 10787 * Minimum buffer size for the limiter, in cells. 10788 * Access: RW 10789 */ 10790MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10791 10792/* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10793#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10794#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10795 10796/* reg_sbcm_infi_max 10797 * Max buffer is infinite. 10798 * Access: RW 10799 */ 10800MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10801 10802/* reg_sbcm_max_buff 10803 * When the pool associated to the port-pg/tclass is configured to 10804 * static, Maximum buffer size for the limiter configured in cells. 10805 * When the pool associated to the port-pg/tclass is configured to 10806 * dynamic, the max_buff holds the "alpha" parameter, supporting 10807 * the following values: 10808 * 0: 0 10809 * i: (1/128)*2^(i-1), for i=1..14 10810 * 0xFF: Infinity 10811 * Reserved when infi_max = 1. 10812 * Access: RW 10813 */ 10814MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 10815 10816/* reg_sbcm_pool 10817 * Association of the port-priority to a pool. 10818 * Access: RW 10819 */ 10820MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 10821 10822static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 10823 enum mlxsw_reg_sbxx_dir dir, 10824 u32 min_buff, u32 max_buff, 10825 bool infi_max, u8 pool) 10826{ 10827 MLXSW_REG_ZERO(sbcm, payload); 10828 mlxsw_reg_sbcm_local_port_set(payload, local_port); 10829 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 10830 mlxsw_reg_sbcm_dir_set(payload, dir); 10831 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 10832 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 10833 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 10834 mlxsw_reg_sbcm_pool_set(payload, pool); 10835} 10836 10837/* SBPM - Shared Buffer Port Management Register 10838 * --------------------------------------------- 10839 * The SBPM register configures and retrieves the shared buffer allocation 10840 * and configuration according to Port-Pool, including the definition 10841 * of the associated quota. 10842 */ 10843#define MLXSW_REG_SBPM_ID 0xB003 10844#define MLXSW_REG_SBPM_LEN 0x28 10845 10846MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 10847 10848/* reg_sbpm_local_port 10849 * Local port number. 10850 * For Ingress: excludes CPU port and Router port 10851 * For Egress: excludes IP Router 10852 * Access: Index 10853 */ 10854MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 10855 10856/* reg_sbpm_pool 10857 * The pool associated to quota counting on the local_port. 10858 * Access: Index 10859 */ 10860MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 10861 10862/* reg_sbpm_dir 10863 * Direction. 10864 * Access: Index 10865 */ 10866MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 10867 10868/* reg_sbpm_buff_occupancy 10869 * Current buffer occupancy in cells. 10870 * Access: RO 10871 */ 10872MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 10873 10874/* reg_sbpm_clr 10875 * Clear Max Buffer Occupancy 10876 * When this bit is set, max_buff_occupancy field is cleared (and a 10877 * new max value is tracked from the time the clear was performed). 10878 * Access: OP 10879 */ 10880MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 10881 10882/* reg_sbpm_max_buff_occupancy 10883 * Maximum value of buffer occupancy in cells monitored. Cleared by 10884 * writing to the clr field. 10885 * Access: RO 10886 */ 10887MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 10888 10889/* reg_sbpm_min_buff 10890 * Minimum buffer size for the limiter, in cells. 10891 * Access: RW 10892 */ 10893MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 10894 10895/* reg_sbpm_max_buff 10896 * When the pool associated to the port-pg/tclass is configured to 10897 * static, Maximum buffer size for the limiter configured in cells. 10898 * When the pool associated to the port-pg/tclass is configured to 10899 * dynamic, the max_buff holds the "alpha" parameter, supporting 10900 * the following values: 10901 * 0: 0 10902 * i: (1/128)*2^(i-1), for i=1..14 10903 * 0xFF: Infinity 10904 * Access: RW 10905 */ 10906MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 10907 10908static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 10909 enum mlxsw_reg_sbxx_dir dir, bool clr, 10910 u32 min_buff, u32 max_buff) 10911{ 10912 MLXSW_REG_ZERO(sbpm, payload); 10913 mlxsw_reg_sbpm_local_port_set(payload, local_port); 10914 mlxsw_reg_sbpm_pool_set(payload, pool); 10915 mlxsw_reg_sbpm_dir_set(payload, dir); 10916 mlxsw_reg_sbpm_clr_set(payload, clr); 10917 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 10918 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 10919} 10920 10921static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 10922 u32 *p_max_buff_occupancy) 10923{ 10924 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 10925 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 10926} 10927 10928/* SBMM - Shared Buffer Multicast Management Register 10929 * -------------------------------------------------- 10930 * The SBMM register configures and retrieves the shared buffer allocation 10931 * and configuration for MC packets according to Switch-Priority, including 10932 * the binding to pool and definition of the associated quota. 10933 */ 10934#define MLXSW_REG_SBMM_ID 0xB004 10935#define MLXSW_REG_SBMM_LEN 0x28 10936 10937MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 10938 10939/* reg_sbmm_prio 10940 * Switch Priority. 10941 * Access: Index 10942 */ 10943MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 10944 10945/* reg_sbmm_min_buff 10946 * Minimum buffer size for the limiter, in cells. 10947 * Access: RW 10948 */ 10949MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 10950 10951/* reg_sbmm_max_buff 10952 * When the pool associated to the port-pg/tclass is configured to 10953 * static, Maximum buffer size for the limiter configured in cells. 10954 * When the pool associated to the port-pg/tclass is configured to 10955 * dynamic, the max_buff holds the "alpha" parameter, supporting 10956 * the following values: 10957 * 0: 0 10958 * i: (1/128)*2^(i-1), for i=1..14 10959 * 0xFF: Infinity 10960 * Access: RW 10961 */ 10962MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 10963 10964/* reg_sbmm_pool 10965 * Association of the port-priority to a pool. 10966 * Access: RW 10967 */ 10968MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 10969 10970static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 10971 u32 max_buff, u8 pool) 10972{ 10973 MLXSW_REG_ZERO(sbmm, payload); 10974 mlxsw_reg_sbmm_prio_set(payload, prio); 10975 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 10976 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 10977 mlxsw_reg_sbmm_pool_set(payload, pool); 10978} 10979 10980/* SBSR - Shared Buffer Status Register 10981 * ------------------------------------ 10982 * The SBSR register retrieves the shared buffer occupancy according to 10983 * Port-Pool. Note that this register enables reading a large amount of data. 10984 * It is the user's responsibility to limit the amount of data to ensure the 10985 * response can match the maximum transfer unit. In case the response exceeds 10986 * the maximum transport unit, it will be truncated with no special notice. 10987 */ 10988#define MLXSW_REG_SBSR_ID 0xB005 10989#define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 10990#define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 10991#define MLXSW_REG_SBSR_REC_MAX_COUNT 120 10992#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 10993 MLXSW_REG_SBSR_REC_LEN * \ 10994 MLXSW_REG_SBSR_REC_MAX_COUNT) 10995 10996MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 10997 10998/* reg_sbsr_clr 10999 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 11000 * field is cleared (and a new max value is tracked from the time the clear 11001 * was performed). 11002 * Access: OP 11003 */ 11004MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 11005 11006/* reg_sbsr_ingress_port_mask 11007 * Bit vector for all ingress network ports. 11008 * Indicates which of the ports (for which the relevant bit is set) 11009 * are affected by the set operation. Configuration of any other port 11010 * does not change. 11011 * Access: Index 11012 */ 11013MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 11014 11015/* reg_sbsr_pg_buff_mask 11016 * Bit vector for all switch priority groups. 11017 * Indicates which of the priorities (for which the relevant bit is set) 11018 * are affected by the set operation. Configuration of any other priority 11019 * does not change. 11020 * Range is 0..cap_max_pg_buffers - 1 11021 * Access: Index 11022 */ 11023MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 11024 11025/* reg_sbsr_egress_port_mask 11026 * Bit vector for all egress network ports. 11027 * Indicates which of the ports (for which the relevant bit is set) 11028 * are affected by the set operation. Configuration of any other port 11029 * does not change. 11030 * Access: Index 11031 */ 11032MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 11033 11034/* reg_sbsr_tclass_mask 11035 * Bit vector for all traffic classes. 11036 * Indicates which of the traffic classes (for which the relevant bit is 11037 * set) are affected by the set operation. Configuration of any other 11038 * traffic class does not change. 11039 * Range is 0..cap_max_tclass - 1 11040 * Access: Index 11041 */ 11042MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 11043 11044static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 11045{ 11046 MLXSW_REG_ZERO(sbsr, payload); 11047 mlxsw_reg_sbsr_clr_set(payload, clr); 11048} 11049 11050/* reg_sbsr_rec_buff_occupancy 11051 * Current buffer occupancy in cells. 11052 * Access: RO 11053 */ 11054MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11055 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 11056 11057/* reg_sbsr_rec_max_buff_occupancy 11058 * Maximum value of buffer occupancy in cells monitored. Cleared by 11059 * writing to the clr field. 11060 * Access: RO 11061 */ 11062MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11063 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 11064 11065static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 11066 u32 *p_buff_occupancy, 11067 u32 *p_max_buff_occupancy) 11068{ 11069 *p_buff_occupancy = 11070 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 11071 *p_max_buff_occupancy = 11072 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 11073} 11074 11075/* SBIB - Shared Buffer Internal Buffer Register 11076 * --------------------------------------------- 11077 * The SBIB register configures per port buffers for internal use. The internal 11078 * buffers consume memory on the port buffers (note that the port buffers are 11079 * used also by PBMC). 11080 * 11081 * For Spectrum this is used for egress mirroring. 11082 */ 11083#define MLXSW_REG_SBIB_ID 0xB006 11084#define MLXSW_REG_SBIB_LEN 0x10 11085 11086MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 11087 11088/* reg_sbib_local_port 11089 * Local port number 11090 * Not supported for CPU port and router port 11091 * Access: Index 11092 */ 11093MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 11094 11095/* reg_sbib_buff_size 11096 * Units represented in cells 11097 * Allowed range is 0 to (cap_max_headroom_size - 1) 11098 * Default is 0 11099 * Access: RW 11100 */ 11101MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 11102 11103static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 11104 u32 buff_size) 11105{ 11106 MLXSW_REG_ZERO(sbib, payload); 11107 mlxsw_reg_sbib_local_port_set(payload, local_port); 11108 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 11109} 11110 11111static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 11112 MLXSW_REG(sgcr), 11113 MLXSW_REG(spad), 11114 MLXSW_REG(smid), 11115 MLXSW_REG(sspr), 11116 MLXSW_REG(sfdat), 11117 MLXSW_REG(sfd), 11118 MLXSW_REG(sfn), 11119 MLXSW_REG(spms), 11120 MLXSW_REG(spvid), 11121 MLXSW_REG(spvm), 11122 MLXSW_REG(spaft), 11123 MLXSW_REG(sfgc), 11124 MLXSW_REG(sftr), 11125 MLXSW_REG(sfdf), 11126 MLXSW_REG(sldr), 11127 MLXSW_REG(slcr), 11128 MLXSW_REG(slcor), 11129 MLXSW_REG(spmlr), 11130 MLXSW_REG(svfa), 11131 MLXSW_REG(svpe), 11132 MLXSW_REG(sfmr), 11133 MLXSW_REG(spvmlr), 11134 MLXSW_REG(cwtp), 11135 MLXSW_REG(cwtpm), 11136 MLXSW_REG(pgcr), 11137 MLXSW_REG(ppbt), 11138 MLXSW_REG(pacl), 11139 MLXSW_REG(pagt), 11140 MLXSW_REG(ptar), 11141 MLXSW_REG(ppbs), 11142 MLXSW_REG(prcr), 11143 MLXSW_REG(pefa), 11144 MLXSW_REG(pemrbt), 11145 MLXSW_REG(ptce2), 11146 MLXSW_REG(perpt), 11147 MLXSW_REG(peabfe), 11148 MLXSW_REG(perar), 11149 MLXSW_REG(ptce3), 11150 MLXSW_REG(percr), 11151 MLXSW_REG(pererp), 11152 MLXSW_REG(iedr), 11153 MLXSW_REG(qpts), 11154 MLXSW_REG(qpcr), 11155 MLXSW_REG(qtct), 11156 MLXSW_REG(qeec), 11157 MLXSW_REG(qrwe), 11158 MLXSW_REG(qpdsm), 11159 MLXSW_REG(qpdp), 11160 MLXSW_REG(qpdpm), 11161 MLXSW_REG(qtctm), 11162 MLXSW_REG(qpsc), 11163 MLXSW_REG(pmlp), 11164 MLXSW_REG(pmtu), 11165 MLXSW_REG(ptys), 11166 MLXSW_REG(ppad), 11167 MLXSW_REG(paos), 11168 MLXSW_REG(pfcc), 11169 MLXSW_REG(ppcnt), 11170 MLXSW_REG(plib), 11171 MLXSW_REG(pptb), 11172 MLXSW_REG(pbmc), 11173 MLXSW_REG(pspa), 11174 MLXSW_REG(pmaos), 11175 MLXSW_REG(pplr), 11176 MLXSW_REG(pmpe), 11177 MLXSW_REG(pddr), 11178 MLXSW_REG(pmtm), 11179 MLXSW_REG(htgt), 11180 MLXSW_REG(hpkt), 11181 MLXSW_REG(rgcr), 11182 MLXSW_REG(ritr), 11183 MLXSW_REG(rtar), 11184 MLXSW_REG(ratr), 11185 MLXSW_REG(rtdp), 11186 MLXSW_REG(rdpm), 11187 MLXSW_REG(ricnt), 11188 MLXSW_REG(rrcr), 11189 MLXSW_REG(ralta), 11190 MLXSW_REG(ralst), 11191 MLXSW_REG(raltb), 11192 MLXSW_REG(ralue), 11193 MLXSW_REG(rauht), 11194 MLXSW_REG(raleu), 11195 MLXSW_REG(rauhtd), 11196 MLXSW_REG(rigr2), 11197 MLXSW_REG(recr2), 11198 MLXSW_REG(rmft2), 11199 MLXSW_REG(mfcr), 11200 MLXSW_REG(mfsc), 11201 MLXSW_REG(mfsm), 11202 MLXSW_REG(mfsl), 11203 MLXSW_REG(fore), 11204 MLXSW_REG(mtcap), 11205 MLXSW_REG(mtmp), 11206 MLXSW_REG(mtwe), 11207 MLXSW_REG(mtbr), 11208 MLXSW_REG(mcia), 11209 MLXSW_REG(mpat), 11210 MLXSW_REG(mpar), 11211 MLXSW_REG(mgir), 11212 MLXSW_REG(mrsr), 11213 MLXSW_REG(mlcr), 11214 MLXSW_REG(mtpps), 11215 MLXSW_REG(mtutc), 11216 MLXSW_REG(mpsc), 11217 MLXSW_REG(mcqi), 11218 MLXSW_REG(mcc), 11219 MLXSW_REG(mcda), 11220 MLXSW_REG(mgpc), 11221 MLXSW_REG(mprs), 11222 MLXSW_REG(mogcr), 11223 MLXSW_REG(mpagr), 11224 MLXSW_REG(momte), 11225 MLXSW_REG(mtpppc), 11226 MLXSW_REG(mtpptr), 11227 MLXSW_REG(mtptpt), 11228 MLXSW_REG(mfgd), 11229 MLXSW_REG(mgpir), 11230 MLXSW_REG(mfde), 11231 MLXSW_REG(tngcr), 11232 MLXSW_REG(tnumt), 11233 MLXSW_REG(tnqcr), 11234 MLXSW_REG(tnqdr), 11235 MLXSW_REG(tneem), 11236 MLXSW_REG(tndem), 11237 MLXSW_REG(tnpc), 11238 MLXSW_REG(tigcr), 11239 MLXSW_REG(tieem), 11240 MLXSW_REG(tidem), 11241 MLXSW_REG(sbpr), 11242 MLXSW_REG(sbcm), 11243 MLXSW_REG(sbpm), 11244 MLXSW_REG(sbmm), 11245 MLXSW_REG(sbsr), 11246 MLXSW_REG(sbib), 11247}; 11248 11249static inline const char *mlxsw_reg_id_str(u16 reg_id) 11250{ 11251 const struct mlxsw_reg_info *reg_info; 11252 int i; 11253 11254 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 11255 reg_info = mlxsw_reg_infos[i]; 11256 if (reg_info->id == reg_id) 11257 return reg_info->name; 11258 } 11259 return "*UNKNOWN*"; 11260} 11261 11262/* PUDE - Port Up / Down Event 11263 * --------------------------- 11264 * Reports the operational state change of a port. 11265 */ 11266#define MLXSW_REG_PUDE_LEN 0x10 11267 11268/* reg_pude_swid 11269 * Switch partition ID with which to associate the port. 11270 * Access: Index 11271 */ 11272MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 11273 11274/* reg_pude_local_port 11275 * Local port number. 11276 * Access: Index 11277 */ 11278MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 11279 11280/* reg_pude_admin_status 11281 * Port administrative state (the desired state). 11282 * 1 - Up. 11283 * 2 - Down. 11284 * 3 - Up once. This means that in case of link failure, the port won't go 11285 * into polling mode, but will wait to be re-enabled by software. 11286 * 4 - Disabled by system. Can only be set by hardware. 11287 * Access: RO 11288 */ 11289MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 11290 11291/* reg_pude_oper_status 11292 * Port operatioanl state. 11293 * 1 - Up. 11294 * 2 - Down. 11295 * 3 - Down by port failure. This means that the device will not let the 11296 * port up again until explicitly specified by software. 11297 * Access: RO 11298 */ 11299MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 11300 11301#endif 11302